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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=amdgcn -mcpu=gfx90a < %s | FileCheck -check-prefix=GFX90A %s3 4define amdgpu_ps void @atomic_swap_1d_agpr(<8 x i32> inreg %rsrc, i32 %s) {5; GFX90A-LABEL: atomic_swap_1d_agpr:6; GFX90A: ; %bb.0:7; GFX90A-NEXT: ;;#ASMSTART8; GFX90A-NEXT: ; def a09; GFX90A-NEXT: ;;#ASMEND10; GFX90A-NEXT: image_atomic_swap a0, v0, s[0:7] dmask:0x1 unorm glc11; GFX90A-NEXT: s_endpgm12 %data = call i32 asm "; def $0", "=a"()13 %v = call i32 @llvm.amdgcn.image.atomic.swap.1d.i32.i32(i32 %data, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)14 call void asm "; use $0", "a"(i32 %v)15 ret void16}17 18define amdgpu_ps void @atomic_add_2d_agpr(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {19; GFX90A-LABEL: atomic_add_2d_agpr:20; GFX90A: ; %bb.0:21; GFX90A-NEXT: ;;#ASMSTART22; GFX90A-NEXT: ; def a023; GFX90A-NEXT: ;;#ASMEND24; GFX90A-NEXT: image_atomic_add a0, v[0:1], s[0:7] dmask:0x1 unorm glc25; GFX90A-NEXT: s_endpgm26 %data = call i32 asm "; def $0", "=a"()27 %v = call i32 @llvm.amdgcn.image.atomic.add.2d.i32.i32(i32 %data, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)28 call void asm "; use $0", "a"(i32 %v)29 ret void30}31 32; FIXME: This should directly use the AGPRs33define amdgpu_ps void @atomic_cmpswap_1d_agpr(<8 x i32> inreg %rsrc, i32 %s) {34; GFX90A-LABEL: atomic_cmpswap_1d_agpr:35; GFX90A: ; %bb.0:36; GFX90A-NEXT: ;;#ASMSTART37; GFX90A-NEXT: ; def a038; GFX90A-NEXT: ;;#ASMEND39; GFX90A-NEXT: ;;#ASMSTART40; GFX90A-NEXT: ; def a141; GFX90A-NEXT: ;;#ASMEND42; GFX90A-NEXT: image_atomic_cmpswap a[0:1], v0, s[0:7] dmask:0x3 unorm glc43; GFX90A-NEXT: s_endpgm44 %cmp = call i32 asm "; def $0", "=a"()45 %swap = call i32 asm "; def $0", "=a"()46 %v = call i32 @llvm.amdgcn.image.atomic.cmpswap.1d.i32.i32(i32 %cmp, i32 %swap, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)47 call void asm "; use $0", "a"(i32 %v)48 ret void49}50 51define amdgpu_ps void @atomic_swap_1d_i64_agpr(<8 x i32> inreg %rsrc, i32 %s) {52; GFX90A-LABEL: atomic_swap_1d_i64_agpr:53; GFX90A: ; %bb.0:54; GFX90A-NEXT: ;;#ASMSTART55; GFX90A-NEXT: ; def a[0:1]56; GFX90A-NEXT: ;;#ASMEND57; GFX90A-NEXT: image_atomic_swap a[0:1], v0, s[0:7] dmask:0x3 unorm glc58; GFX90A-NEXT: s_endpgm59 %data = call i64 asm "; def $0", "=a"()60 %v = call i64 @llvm.amdgcn.image.atomic.swap.1d.i64.i32(i64 %data, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)61 call void asm "; use $0", "a"(i64 %v)62 ret void63}64 65define amdgpu_ps void @atomic_cmpswap_1d_64_agpr(<8 x i32> inreg %rsrc, i32 %s) {66; GFX90A-LABEL: atomic_cmpswap_1d_64_agpr:67; GFX90A: ; %bb.0:68; GFX90A-NEXT: ;;#ASMSTART69; GFX90A-NEXT: ; def a[0:1]70; GFX90A-NEXT: ;;#ASMEND71; GFX90A-NEXT: ;;#ASMSTART72; GFX90A-NEXT: ; def a[2:3]73; GFX90A-NEXT: ;;#ASMEND74; GFX90A-NEXT: image_atomic_cmpswap a[0:3], v0, s[0:7] dmask:0xf unorm glc75; GFX90A-NEXT: s_endpgm76 %cmp = call i64 asm "; def $0", "=a"()77 %swap = call i64 asm "; def $0", "=a"()78 %v = call i64 @llvm.amdgcn.image.atomic.cmpswap.1d.i64.i32(i64 %cmp, i64 %swap, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)79 call void asm "; use $0", "a"(i64 %v)80 ret void81}82 83define amdgpu_ps void @atomic_swap_1d_agpr_noret(<8 x i32> inreg %rsrc, i32 %s) {84; GFX90A-LABEL: atomic_swap_1d_agpr_noret:85; GFX90A: ; %bb.0:86; GFX90A-NEXT: ;;#ASMSTART87; GFX90A-NEXT: ; def a088; GFX90A-NEXT: ;;#ASMEND89; GFX90A-NEXT: image_atomic_swap a0, v0, s[0:7] dmask:0x1 unorm90; GFX90A-NEXT: s_endpgm91 %data = call i32 asm "; def $0", "=a"()92 %unused = call i32 @llvm.amdgcn.image.atomic.swap.1d.i32.i32(i32 %data, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)93 ret void94}95 96define amdgpu_ps void @atomic_add_2d_agpr_noret(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {97; GFX90A-LABEL: atomic_add_2d_agpr_noret:98; GFX90A: ; %bb.0:99; GFX90A-NEXT: ;;#ASMSTART100; GFX90A-NEXT: ; def a0101; GFX90A-NEXT: ;;#ASMEND102; GFX90A-NEXT: image_atomic_add a0, v[0:1], s[0:7] dmask:0x1 unorm103; GFX90A-NEXT: s_endpgm104 %data = call i32 asm "; def $0", "=a"()105 %unused = call i32 @llvm.amdgcn.image.atomic.add.2d.i32.i32(i32 %data, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)106 ret void107}108 109define amdgpu_ps void @atomic_cmpswap_1d_agpr_noret(<8 x i32> inreg %rsrc, i32 %s) {110; GFX90A-LABEL: atomic_cmpswap_1d_agpr_noret:111; GFX90A: ; %bb.0:112; GFX90A-NEXT: ;;#ASMSTART113; GFX90A-NEXT: ; def a0114; GFX90A-NEXT: ;;#ASMEND115; GFX90A-NEXT: ;;#ASMSTART116; GFX90A-NEXT: ; def a1117; GFX90A-NEXT: ;;#ASMEND118; GFX90A-NEXT: image_atomic_cmpswap a[0:1], v0, s[0:7] dmask:0x3 unorm119; GFX90A-NEXT: s_endpgm120 %cmp = call i32 asm "; def $0", "=a"()121 %swap = call i32 asm "; def $0", "=a"()122 %unused = call i32 @llvm.amdgcn.image.atomic.cmpswap.1d.i32.i32(i32 %cmp, i32 %swap, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)123 ret void124}125 126define amdgpu_ps void @atomic_swap_1d_i64_agpr_noret(<8 x i32> inreg %rsrc, i32 %s) {127; GFX90A-LABEL: atomic_swap_1d_i64_agpr_noret:128; GFX90A: ; %bb.0:129; GFX90A-NEXT: ;;#ASMSTART130; GFX90A-NEXT: ; def a[0:1]131; GFX90A-NEXT: ;;#ASMEND132; GFX90A-NEXT: image_atomic_swap a[0:1], v0, s[0:7] dmask:0x3 unorm133; GFX90A-NEXT: s_endpgm134 %data = call i64 asm "; def $0", "=a"()135 %unused = call i64 @llvm.amdgcn.image.atomic.swap.1d.i64.i32(i64 %data, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)136 ret void137}138 139define amdgpu_ps void @atomic_cmpswap_1d_64_agpr_noret(<8 x i32> inreg %rsrc, i32 %s) {140; GFX90A-LABEL: atomic_cmpswap_1d_64_agpr_noret:141; GFX90A: ; %bb.0:142; GFX90A-NEXT: ;;#ASMSTART143; GFX90A-NEXT: ; def a[0:1]144; GFX90A-NEXT: ;;#ASMEND145; GFX90A-NEXT: ;;#ASMSTART146; GFX90A-NEXT: ; def a[2:3]147; GFX90A-NEXT: ;;#ASMEND148; GFX90A-NEXT: image_atomic_cmpswap a[0:3], v0, s[0:7] dmask:0xf unorm149; GFX90A-NEXT: s_endpgm150 %cmp = call i64 asm "; def $0", "=a"()151 %swap = call i64 asm "; def $0", "=a"()152 %unused = call i64 @llvm.amdgcn.image.atomic.cmpswap.1d.i64.i32(i64 %cmp, i64 %swap, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)153 ret void154}155