582 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX10PLUS-GISE %s3; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX10PLUS %s4; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GFX12-GISE %s5; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GFX12 %s6 7define amdgpu_ps void @atomic_swap_1d(<8 x i32> inreg %rsrc, i32 %data, i32 %s) {8; GFX10PLUS-GISE-LABEL: atomic_swap_1d:9; GFX10PLUS-GISE: ; %bb.0:10; GFX10PLUS-GISE-NEXT: image_atomic_swap v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm11; GFX10PLUS-GISE-NEXT: s_endpgm12;13; GFX10PLUS-LABEL: atomic_swap_1d:14; GFX10PLUS: ; %bb.0:15; GFX10PLUS-NEXT: image_atomic_swap v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm16; GFX10PLUS-NEXT: s_endpgm17;18; GFX12-GISE-LABEL: atomic_swap_1d:19; GFX12-GISE: ; %bb.0:20; GFX12-GISE-NEXT: image_atomic_swap v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D21; GFX12-GISE-NEXT: s_endpgm22;23; GFX12-LABEL: atomic_swap_1d:24; GFX12: ; %bb.0:25; GFX12-NEXT: image_atomic_swap v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D26; GFX12-NEXT: s_endpgm27 %v = call i32 @llvm.amdgcn.image.atomic.swap.1d.i32.i32(i32 %data, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)28 ret void29}30 31define amdgpu_ps void @atomic_swap_1d_i64(<8 x i32> inreg %rsrc, i64 %data, i32 %s) {32; GFX10PLUS-GISE-LABEL: atomic_swap_1d_i64:33; GFX10PLUS-GISE: ; %bb.0:34; GFX10PLUS-GISE-NEXT: image_atomic_swap v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm35; GFX10PLUS-GISE-NEXT: s_endpgm36;37; GFX10PLUS-LABEL: atomic_swap_1d_i64:38; GFX10PLUS: ; %bb.0:39; GFX10PLUS-NEXT: image_atomic_swap v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm40; GFX10PLUS-NEXT: s_endpgm41;42; GFX12-GISE-LABEL: atomic_swap_1d_i64:43; GFX12-GISE: ; %bb.0:44; GFX12-GISE-NEXT: image_atomic_swap v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D45; GFX12-GISE-NEXT: s_endpgm46;47; GFX12-LABEL: atomic_swap_1d_i64:48; GFX12: ; %bb.0:49; GFX12-NEXT: image_atomic_swap v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D50; GFX12-NEXT: s_endpgm51 %v = call i64 @llvm.amdgcn.image.atomic.swap.1d.i64.i32(i64 %data, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)52 ret void53}54 55define amdgpu_ps void @atomic_swap_1d_float(<8 x i32> inreg %rsrc, float %data, i32 %s) {56; GFX10PLUS-GISE-LABEL: atomic_swap_1d_float:57; GFX10PLUS-GISE: ; %bb.0:58; GFX10PLUS-GISE-NEXT: image_atomic_swap v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm59; GFX10PLUS-GISE-NEXT: s_endpgm60;61; GFX10PLUS-LABEL: atomic_swap_1d_float:62; GFX10PLUS: ; %bb.0:63; GFX10PLUS-NEXT: image_atomic_swap v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm64; GFX10PLUS-NEXT: s_endpgm65;66; GFX12-GISE-LABEL: atomic_swap_1d_float:67; GFX12-GISE: ; %bb.0:68; GFX12-GISE-NEXT: image_atomic_swap v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D69; GFX12-GISE-NEXT: s_endpgm70;71; GFX12-LABEL: atomic_swap_1d_float:72; GFX12: ; %bb.0:73; GFX12-NEXT: image_atomic_swap v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D74; GFX12-NEXT: s_endpgm75 %v = call float @llvm.amdgcn.image.atomic.swap.1d.f32.i32(float %data, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)76 ret void77}78 79define amdgpu_ps void @atomic_add_1d(<8 x i32> inreg %rsrc, i32 %data, i32 %s) {80; GFX10PLUS-GISE-LABEL: atomic_add_1d:81; GFX10PLUS-GISE: ; %bb.0:82; GFX10PLUS-GISE-NEXT: image_atomic_add v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm83; GFX10PLUS-GISE-NEXT: s_endpgm84;85; GFX10PLUS-LABEL: atomic_add_1d:86; GFX10PLUS: ; %bb.0:87; GFX10PLUS-NEXT: image_atomic_add v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm88; GFX10PLUS-NEXT: s_endpgm89;90; GFX12-GISE-LABEL: atomic_add_1d:91; GFX12-GISE: ; %bb.0:92; GFX12-GISE-NEXT: image_atomic_add_uint v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D93; GFX12-GISE-NEXT: s_endpgm94;95; GFX12-LABEL: atomic_add_1d:96; GFX12: ; %bb.0:97; GFX12-NEXT: image_atomic_add_uint v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D98; GFX12-NEXT: s_endpgm99 %v = call i32 @llvm.amdgcn.image.atomic.add.1d.i32.i32(i32 %data, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)100 ret void101}102 103define amdgpu_ps void @atomic_sub_1d(<8 x i32> inreg %rsrc, i32 %data, i32 %s) {104; GFX10PLUS-GISE-LABEL: atomic_sub_1d:105; GFX10PLUS-GISE: ; %bb.0:106; GFX10PLUS-GISE-NEXT: image_atomic_sub v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm107; GFX10PLUS-GISE-NEXT: s_endpgm108;109; GFX10PLUS-LABEL: atomic_sub_1d:110; GFX10PLUS: ; %bb.0:111; GFX10PLUS-NEXT: image_atomic_sub v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm112; GFX10PLUS-NEXT: s_endpgm113;114; GFX12-GISE-LABEL: atomic_sub_1d:115; GFX12-GISE: ; %bb.0:116; GFX12-GISE-NEXT: image_atomic_sub_uint v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D117; GFX12-GISE-NEXT: s_endpgm118;119; GFX12-LABEL: atomic_sub_1d:120; GFX12: ; %bb.0:121; GFX12-NEXT: image_atomic_sub_uint v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D122; GFX12-NEXT: s_endpgm123 %v = call i32 @llvm.amdgcn.image.atomic.sub.1d.i32.i32(i32 %data, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)124 ret void125}126 127define amdgpu_ps void @atomic_smin_1d(<8 x i32> inreg %rsrc, i32 %data, i32 %s) {128; GFX10PLUS-GISE-LABEL: atomic_smin_1d:129; GFX10PLUS-GISE: ; %bb.0:130; GFX10PLUS-GISE-NEXT: image_atomic_smin v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm131; GFX10PLUS-GISE-NEXT: s_endpgm132;133; GFX10PLUS-LABEL: atomic_smin_1d:134; GFX10PLUS: ; %bb.0:135; GFX10PLUS-NEXT: image_atomic_smin v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm136; GFX10PLUS-NEXT: s_endpgm137;138; GFX12-GISE-LABEL: atomic_smin_1d:139; GFX12-GISE: ; %bb.0:140; GFX12-GISE-NEXT: image_atomic_min_int v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D141; GFX12-GISE-NEXT: s_endpgm142;143; GFX12-LABEL: atomic_smin_1d:144; GFX12: ; %bb.0:145; GFX12-NEXT: image_atomic_min_int v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D146; GFX12-NEXT: s_endpgm147 %v = call i32 @llvm.amdgcn.image.atomic.smin.1d.i32.i32(i32 %data, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)148 ret void149}150 151define amdgpu_ps void @atomic_umin_1d(<8 x i32> inreg %rsrc, i32 %data, i32 %s) {152; GFX10PLUS-GISE-LABEL: atomic_umin_1d:153; GFX10PLUS-GISE: ; %bb.0:154; GFX10PLUS-GISE-NEXT: image_atomic_umin v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm155; GFX10PLUS-GISE-NEXT: s_endpgm156;157; GFX10PLUS-LABEL: atomic_umin_1d:158; GFX10PLUS: ; %bb.0:159; GFX10PLUS-NEXT: image_atomic_umin v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm160; GFX10PLUS-NEXT: s_endpgm161;162; GFX12-GISE-LABEL: atomic_umin_1d:163; GFX12-GISE: ; %bb.0:164; GFX12-GISE-NEXT: image_atomic_min_uint v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D165; GFX12-GISE-NEXT: s_endpgm166;167; GFX12-LABEL: atomic_umin_1d:168; GFX12: ; %bb.0:169; GFX12-NEXT: image_atomic_min_uint v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D170; GFX12-NEXT: s_endpgm171 %v = call i32 @llvm.amdgcn.image.atomic.umin.1d.i32.i32(i32 %data, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)172 ret void173}174 175define amdgpu_ps void @atomic_smax_1d(<8 x i32> inreg %rsrc, i32 %data, i32 %s) {176; GFX10PLUS-GISE-LABEL: atomic_smax_1d:177; GFX10PLUS-GISE: ; %bb.0:178; GFX10PLUS-GISE-NEXT: image_atomic_smax v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm179; GFX10PLUS-GISE-NEXT: s_endpgm180;181; GFX10PLUS-LABEL: atomic_smax_1d:182; GFX10PLUS: ; %bb.0:183; GFX10PLUS-NEXT: image_atomic_smax v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm184; GFX10PLUS-NEXT: s_endpgm185;186; GFX12-GISE-LABEL: atomic_smax_1d:187; GFX12-GISE: ; %bb.0:188; GFX12-GISE-NEXT: image_atomic_max_int v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D189; GFX12-GISE-NEXT: s_endpgm190;191; GFX12-LABEL: atomic_smax_1d:192; GFX12: ; %bb.0:193; GFX12-NEXT: image_atomic_max_int v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D194; GFX12-NEXT: s_endpgm195 %v = call i32 @llvm.amdgcn.image.atomic.smax.1d.i32.i32(i32 %data, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)196 ret void197}198 199define amdgpu_ps void @atomic_umax_1d(<8 x i32> inreg %rsrc, i32 %data, i32 %s) {200; GFX10PLUS-GISE-LABEL: atomic_umax_1d:201; GFX10PLUS-GISE: ; %bb.0:202; GFX10PLUS-GISE-NEXT: image_atomic_umax v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm203; GFX10PLUS-GISE-NEXT: s_endpgm204;205; GFX10PLUS-LABEL: atomic_umax_1d:206; GFX10PLUS: ; %bb.0:207; GFX10PLUS-NEXT: image_atomic_umax v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm208; GFX10PLUS-NEXT: s_endpgm209;210; GFX12-GISE-LABEL: atomic_umax_1d:211; GFX12-GISE: ; %bb.0:212; GFX12-GISE-NEXT: image_atomic_max_uint v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D213; GFX12-GISE-NEXT: s_endpgm214;215; GFX12-LABEL: atomic_umax_1d:216; GFX12: ; %bb.0:217; GFX12-NEXT: image_atomic_max_uint v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D218; GFX12-NEXT: s_endpgm219 %v = call i32 @llvm.amdgcn.image.atomic.umax.1d.i32.i32(i32 %data, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)220 ret void221}222 223define amdgpu_ps void @atomic_and_1d(<8 x i32> inreg %rsrc, i32 %data, i32 %s) {224; GFX10PLUS-GISE-LABEL: atomic_and_1d:225; GFX10PLUS-GISE: ; %bb.0:226; GFX10PLUS-GISE-NEXT: image_atomic_and v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm227; GFX10PLUS-GISE-NEXT: s_endpgm228;229; GFX10PLUS-LABEL: atomic_and_1d:230; GFX10PLUS: ; %bb.0:231; GFX10PLUS-NEXT: image_atomic_and v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm232; GFX10PLUS-NEXT: s_endpgm233;234; GFX12-GISE-LABEL: atomic_and_1d:235; GFX12-GISE: ; %bb.0:236; GFX12-GISE-NEXT: image_atomic_and v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D237; GFX12-GISE-NEXT: s_endpgm238;239; GFX12-LABEL: atomic_and_1d:240; GFX12: ; %bb.0:241; GFX12-NEXT: image_atomic_and v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D242; GFX12-NEXT: s_endpgm243 %v = call i32 @llvm.amdgcn.image.atomic.and.1d.i32.i32(i32 %data, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)244 ret void245}246 247define amdgpu_ps void @atomic_or_1d(<8 x i32> inreg %rsrc, i32 %data, i32 %s) {248; GFX10PLUS-GISE-LABEL: atomic_or_1d:249; GFX10PLUS-GISE: ; %bb.0:250; GFX10PLUS-GISE-NEXT: image_atomic_or v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm251; GFX10PLUS-GISE-NEXT: s_endpgm252;253; GFX10PLUS-LABEL: atomic_or_1d:254; GFX10PLUS: ; %bb.0:255; GFX10PLUS-NEXT: image_atomic_or v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm256; GFX10PLUS-NEXT: s_endpgm257;258; GFX12-GISE-LABEL: atomic_or_1d:259; GFX12-GISE: ; %bb.0:260; GFX12-GISE-NEXT: image_atomic_or v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D261; GFX12-GISE-NEXT: s_endpgm262;263; GFX12-LABEL: atomic_or_1d:264; GFX12: ; %bb.0:265; GFX12-NEXT: image_atomic_or v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D266; GFX12-NEXT: s_endpgm267 %v = call i32 @llvm.amdgcn.image.atomic.or.1d.i32.i32(i32 %data, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)268 ret void269}270 271define amdgpu_ps void @atomic_xor_1d(<8 x i32> inreg %rsrc, i32 %data, i32 %s) {272; GFX10PLUS-GISE-LABEL: atomic_xor_1d:273; GFX10PLUS-GISE: ; %bb.0:274; GFX10PLUS-GISE-NEXT: image_atomic_xor v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm275; GFX10PLUS-GISE-NEXT: s_endpgm276;277; GFX10PLUS-LABEL: atomic_xor_1d:278; GFX10PLUS: ; %bb.0:279; GFX10PLUS-NEXT: image_atomic_xor v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm280; GFX10PLUS-NEXT: s_endpgm281;282; GFX12-GISE-LABEL: atomic_xor_1d:283; GFX12-GISE: ; %bb.0:284; GFX12-GISE-NEXT: image_atomic_xor v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D285; GFX12-GISE-NEXT: s_endpgm286;287; GFX12-LABEL: atomic_xor_1d:288; GFX12: ; %bb.0:289; GFX12-NEXT: image_atomic_xor v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D290; GFX12-NEXT: s_endpgm291 %v = call i32 @llvm.amdgcn.image.atomic.xor.1d.i32.i32(i32 %data, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)292 ret void293}294 295define amdgpu_ps void @atomic_inc_1d(<8 x i32> inreg %rsrc, i32 %data, i32 %s) {296; GFX10PLUS-GISE-LABEL: atomic_inc_1d:297; GFX10PLUS-GISE: ; %bb.0:298; GFX10PLUS-GISE-NEXT: image_atomic_inc v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm299; GFX10PLUS-GISE-NEXT: s_endpgm300;301; GFX10PLUS-LABEL: atomic_inc_1d:302; GFX10PLUS: ; %bb.0:303; GFX10PLUS-NEXT: image_atomic_inc v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm304; GFX10PLUS-NEXT: s_endpgm305;306; GFX12-GISE-LABEL: atomic_inc_1d:307; GFX12-GISE: ; %bb.0:308; GFX12-GISE-NEXT: image_atomic_inc_uint v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D309; GFX12-GISE-NEXT: s_endpgm310;311; GFX12-LABEL: atomic_inc_1d:312; GFX12: ; %bb.0:313; GFX12-NEXT: image_atomic_inc_uint v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D314; GFX12-NEXT: s_endpgm315 %v = call i32 @llvm.amdgcn.image.atomic.inc.1d.i32.i32(i32 %data, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)316 ret void317}318 319define amdgpu_ps void @atomic_dec_1d(<8 x i32> inreg %rsrc, i32 %data, i32 %s) {320; GFX10PLUS-GISE-LABEL: atomic_dec_1d:321; GFX10PLUS-GISE: ; %bb.0:322; GFX10PLUS-GISE-NEXT: image_atomic_dec v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm323; GFX10PLUS-GISE-NEXT: s_endpgm324;325; GFX10PLUS-LABEL: atomic_dec_1d:326; GFX10PLUS: ; %bb.0:327; GFX10PLUS-NEXT: image_atomic_dec v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm328; GFX10PLUS-NEXT: s_endpgm329;330; GFX12-GISE-LABEL: atomic_dec_1d:331; GFX12-GISE: ; %bb.0:332; GFX12-GISE-NEXT: image_atomic_dec_uint v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D333; GFX12-GISE-NEXT: s_endpgm334;335; GFX12-LABEL: atomic_dec_1d:336; GFX12: ; %bb.0:337; GFX12-NEXT: image_atomic_dec_uint v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D338; GFX12-NEXT: s_endpgm339 %v = call i32 @llvm.amdgcn.image.atomic.dec.1d.i32.i32(i32 %data, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)340 ret void341}342 343define amdgpu_ps void @atomic_cmpswap_1d(<8 x i32> inreg %rsrc, i32 %cmp, i32 %swap, i32 %s) {344; GFX10PLUS-GISE-LABEL: atomic_cmpswap_1d:345; GFX10PLUS-GISE: ; %bb.0:346; GFX10PLUS-GISE-NEXT: image_atomic_cmpswap v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm347; GFX10PLUS-GISE-NEXT: s_endpgm348;349; GFX10PLUS-LABEL: atomic_cmpswap_1d:350; GFX10PLUS: ; %bb.0:351; GFX10PLUS-NEXT: image_atomic_cmpswap v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm352; GFX10PLUS-NEXT: s_endpgm353;354; GFX12-GISE-LABEL: atomic_cmpswap_1d:355; GFX12-GISE: ; %bb.0:356; GFX12-GISE-NEXT: image_atomic_cmpswap v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D357; GFX12-GISE-NEXT: s_endpgm358;359; GFX12-LABEL: atomic_cmpswap_1d:360; GFX12: ; %bb.0:361; GFX12-NEXT: image_atomic_cmpswap v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D362; GFX12-NEXT: s_endpgm363 %v = call i32 @llvm.amdgcn.image.atomic.cmpswap.1d.i32.i32(i32 %cmp, i32 %swap, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)364 ret void365}366 367define amdgpu_ps void @atomic_cmpswap_1d_64(<8 x i32> inreg %rsrc, i64 %cmp, i64 %swap, i32 %s) {368; GFX10PLUS-GISE-LABEL: atomic_cmpswap_1d_64:369; GFX10PLUS-GISE: ; %bb.0:370; GFX10PLUS-GISE-NEXT: image_atomic_cmpswap v[0:3], v4, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D unorm371; GFX10PLUS-GISE-NEXT: s_endpgm372;373; GFX10PLUS-LABEL: atomic_cmpswap_1d_64:374; GFX10PLUS: ; %bb.0:375; GFX10PLUS-NEXT: image_atomic_cmpswap v[0:3], v4, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D unorm376; GFX10PLUS-NEXT: s_endpgm377;378; GFX12-GISE-LABEL: atomic_cmpswap_1d_64:379; GFX12-GISE: ; %bb.0:380; GFX12-GISE-NEXT: image_atomic_cmpswap v[0:3], v4, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D381; GFX12-GISE-NEXT: s_endpgm382;383; GFX12-LABEL: atomic_cmpswap_1d_64:384; GFX12: ; %bb.0:385; GFX12-NEXT: image_atomic_cmpswap v[0:3], v4, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D386; GFX12-NEXT: s_endpgm387 %v = call i64 @llvm.amdgcn.image.atomic.cmpswap.1d.i64.i32(i64 %cmp, i64 %swap, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)388 ret void389}390 391define amdgpu_ps void @atomic_add_2d(<8 x i32> inreg %rsrc, i32 %data, i32 %s, i32 %t) {392; GFX10PLUS-GISE-LABEL: atomic_add_2d:393; GFX10PLUS-GISE: ; %bb.0:394; GFX10PLUS-GISE-NEXT: image_atomic_add v0, v[1:2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D unorm395; GFX10PLUS-GISE-NEXT: s_endpgm396;397; GFX10PLUS-LABEL: atomic_add_2d:398; GFX10PLUS: ; %bb.0:399; GFX10PLUS-NEXT: image_atomic_add v0, v[1:2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D unorm400; GFX10PLUS-NEXT: s_endpgm401;402; GFX12-GISE-LABEL: atomic_add_2d:403; GFX12-GISE: ; %bb.0:404; GFX12-GISE-NEXT: image_atomic_add_uint v0, [v1, v2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D405; GFX12-GISE-NEXT: s_endpgm406;407; GFX12-LABEL: atomic_add_2d:408; GFX12: ; %bb.0:409; GFX12-NEXT: image_atomic_add_uint v0, [v1, v2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D410; GFX12-NEXT: s_endpgm411 %v = call i32 @llvm.amdgcn.image.atomic.add.2d.i32.i32(i32 %data, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)412 ret void413}414 415define amdgpu_ps void @atomic_add_3d(<8 x i32> inreg %rsrc, i32 %data, i32 %s, i32 %t, i32 %r) {416; GFX10PLUS-GISE-LABEL: atomic_add_3d:417; GFX10PLUS-GISE: ; %bb.0:418; GFX10PLUS-GISE-NEXT: image_atomic_add v0, v[1:3], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_3D unorm419; GFX10PLUS-GISE-NEXT: s_endpgm420;421; GFX10PLUS-LABEL: atomic_add_3d:422; GFX10PLUS: ; %bb.0:423; GFX10PLUS-NEXT: image_atomic_add v0, v[1:3], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_3D unorm424; GFX10PLUS-NEXT: s_endpgm425;426; GFX12-GISE-LABEL: atomic_add_3d:427; GFX12-GISE: ; %bb.0:428; GFX12-GISE-NEXT: image_atomic_add_uint v0, [v1, v2, v3], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_3D429; GFX12-GISE-NEXT: s_endpgm430;431; GFX12-LABEL: atomic_add_3d:432; GFX12: ; %bb.0:433; GFX12-NEXT: image_atomic_add_uint v0, [v1, v2, v3], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_3D434; GFX12-NEXT: s_endpgm435 %v = call i32 @llvm.amdgcn.image.atomic.add.3d.i32.i32(i32 %data, i32 %s, i32 %t, i32 %r, <8 x i32> %rsrc, i32 0, i32 0)436 ret void437}438 439define amdgpu_ps void @atomic_add_cube(<8 x i32> inreg %rsrc, i32 %data, i32 %s, i32 %t, i32 %face) {440; GFX10PLUS-GISE-LABEL: atomic_add_cube:441; GFX10PLUS-GISE: ; %bb.0:442; GFX10PLUS-GISE-NEXT: image_atomic_add v0, v[1:3], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_CUBE unorm443; GFX10PLUS-GISE-NEXT: s_endpgm444;445; GFX10PLUS-LABEL: atomic_add_cube:446; GFX10PLUS: ; %bb.0:447; GFX10PLUS-NEXT: image_atomic_add v0, v[1:3], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_CUBE unorm448; GFX10PLUS-NEXT: s_endpgm449;450; GFX12-GISE-LABEL: atomic_add_cube:451; GFX12-GISE: ; %bb.0:452; GFX12-GISE-NEXT: image_atomic_add_uint v0, [v1, v2, v3], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_CUBE453; GFX12-GISE-NEXT: s_endpgm454;455; GFX12-LABEL: atomic_add_cube:456; GFX12: ; %bb.0:457; GFX12-NEXT: image_atomic_add_uint v0, [v1, v2, v3], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_CUBE458; GFX12-NEXT: s_endpgm459 %v = call i32 @llvm.amdgcn.image.atomic.add.cube.i32.i32(i32 %data, i32 %s, i32 %t, i32 %face, <8 x i32> %rsrc, i32 0, i32 0)460 ret void461}462 463define amdgpu_ps void @atomic_add_1darray(<8 x i32> inreg %rsrc, i32 %data, i32 %s, i32 %slice) {464; GFX10PLUS-GISE-LABEL: atomic_add_1darray:465; GFX10PLUS-GISE: ; %bb.0:466; GFX10PLUS-GISE-NEXT: image_atomic_add v0, v[1:2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D_ARRAY unorm467; GFX10PLUS-GISE-NEXT: s_endpgm468;469; GFX10PLUS-LABEL: atomic_add_1darray:470; GFX10PLUS: ; %bb.0:471; GFX10PLUS-NEXT: image_atomic_add v0, v[1:2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D_ARRAY unorm472; GFX10PLUS-NEXT: s_endpgm473;474; GFX12-GISE-LABEL: atomic_add_1darray:475; GFX12-GISE: ; %bb.0:476; GFX12-GISE-NEXT: image_atomic_add_uint v0, [v1, v2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D_ARRAY477; GFX12-GISE-NEXT: s_endpgm478;479; GFX12-LABEL: atomic_add_1darray:480; GFX12: ; %bb.0:481; GFX12-NEXT: image_atomic_add_uint v0, [v1, v2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D_ARRAY482; GFX12-NEXT: s_endpgm483 %v = call i32 @llvm.amdgcn.image.atomic.add.1darray.i32.i32(i32 %data, i32 %s, i32 %slice, <8 x i32> %rsrc, i32 0, i32 0)484 ret void485}486 487define amdgpu_ps void @atomic_add_2darray(<8 x i32> inreg %rsrc, i32 %data, i32 %s, i32 %t, i32 %slice) {488; GFX10PLUS-GISE-LABEL: atomic_add_2darray:489; GFX10PLUS-GISE: ; %bb.0:490; GFX10PLUS-GISE-NEXT: image_atomic_add v0, v[1:3], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_ARRAY unorm491; GFX10PLUS-GISE-NEXT: s_endpgm492;493; GFX10PLUS-LABEL: atomic_add_2darray:494; GFX10PLUS: ; %bb.0:495; GFX10PLUS-NEXT: image_atomic_add v0, v[1:3], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_ARRAY unorm496; GFX10PLUS-NEXT: s_endpgm497;498; GFX12-GISE-LABEL: atomic_add_2darray:499; GFX12-GISE: ; %bb.0:500; GFX12-GISE-NEXT: image_atomic_add_uint v0, [v1, v2, v3], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_ARRAY501; GFX12-GISE-NEXT: s_endpgm502;503; GFX12-LABEL: atomic_add_2darray:504; GFX12: ; %bb.0:505; GFX12-NEXT: image_atomic_add_uint v0, [v1, v2, v3], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_ARRAY506; GFX12-NEXT: s_endpgm507 %v = call i32 @llvm.amdgcn.image.atomic.add.2darray.i32.i32(i32 %data, i32 %s, i32 %t, i32 %slice, <8 x i32> %rsrc, i32 0, i32 0)508 ret void509}510 511define amdgpu_ps void @atomic_add_2dmsaa(<8 x i32> inreg %rsrc, i32 %data, i32 %s, i32 %t, i32 %fragid) {512; GFX10PLUS-GISE-LABEL: atomic_add_2dmsaa:513; GFX10PLUS-GISE: ; %bb.0:514; GFX10PLUS-GISE-NEXT: image_atomic_add v0, v[1:3], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA unorm515; GFX10PLUS-GISE-NEXT: s_endpgm516;517; GFX10PLUS-LABEL: atomic_add_2dmsaa:518; GFX10PLUS: ; %bb.0:519; GFX10PLUS-NEXT: image_atomic_add v0, v[1:3], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA unorm520; GFX10PLUS-NEXT: s_endpgm521;522; GFX12-GISE-LABEL: atomic_add_2dmsaa:523; GFX12-GISE: ; %bb.0:524; GFX12-GISE-NEXT: image_atomic_add_uint v0, [v1, v2, v3], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA525; GFX12-GISE-NEXT: s_endpgm526;527; GFX12-LABEL: atomic_add_2dmsaa:528; GFX12: ; %bb.0:529; GFX12-NEXT: image_atomic_add_uint v0, [v1, v2, v3], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA530; GFX12-NEXT: s_endpgm531 %v = call i32 @llvm.amdgcn.image.atomic.add.2dmsaa.i32.i32(i32 %data, i32 %s, i32 %t, i32 %fragid, <8 x i32> %rsrc, i32 0, i32 0)532 ret void533}534 535define amdgpu_ps void @atomic_add_2darraymsaa(<8 x i32> inreg %rsrc, i32 %data, i32 %s, i32 %t, i32 %slice, i32 %fragid) {536; GFX10PLUS-GISE-LABEL: atomic_add_2darraymsaa:537; GFX10PLUS-GISE: ; %bb.0:538; GFX10PLUS-GISE-NEXT: image_atomic_add v0, v[1:4], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm539; GFX10PLUS-GISE-NEXT: s_endpgm540;541; GFX10PLUS-LABEL: atomic_add_2darraymsaa:542; GFX10PLUS: ; %bb.0:543; GFX10PLUS-NEXT: image_atomic_add v0, v[1:4], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm544; GFX10PLUS-NEXT: s_endpgm545;546; GFX12-GISE-LABEL: atomic_add_2darraymsaa:547; GFX12-GISE: ; %bb.0:548; GFX12-GISE-NEXT: image_atomic_add_uint v0, [v1, v2, v3, v4], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY549; GFX12-GISE-NEXT: s_endpgm550;551; GFX12-LABEL: atomic_add_2darraymsaa:552; GFX12: ; %bb.0:553; GFX12-NEXT: image_atomic_add_uint v0, [v1, v2, v3, v4], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY554; GFX12-NEXT: s_endpgm555 %v = call i32 @llvm.amdgcn.image.atomic.add.2darraymsaa.i32.i32(i32 %data, i32 %s, i32 %t, i32 %slice, i32 %fragid, <8 x i32> %rsrc, i32 0, i32 0)556 ret void557}558 559define amdgpu_ps void @atomic_add_1d_slc(<8 x i32> inreg %rsrc, i32 %data, i32 %s) {560; GFX10PLUS-GISE-LABEL: atomic_add_1d_slc:561; GFX10PLUS-GISE: ; %bb.0:562; GFX10PLUS-GISE-NEXT: image_atomic_add v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm slc563; GFX10PLUS-GISE-NEXT: s_endpgm564;565; GFX10PLUS-LABEL: atomic_add_1d_slc:566; GFX10PLUS: ; %bb.0:567; GFX10PLUS-NEXT: image_atomic_add v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm slc568; GFX10PLUS-NEXT: s_endpgm569;570; GFX12-GISE-LABEL: atomic_add_1d_slc:571; GFX12-GISE: ; %bb.0:572; GFX12-GISE-NEXT: image_atomic_add_uint v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_NT573; GFX12-GISE-NEXT: s_endpgm574;575; GFX12-LABEL: atomic_add_1d_slc:576; GFX12: ; %bb.0:577; GFX12-NEXT: image_atomic_add_uint v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_NT578; GFX12-NEXT: s_endpgm579 %v = call i32 @llvm.amdgcn.image.atomic.add.1d.i32.i32(i32 %data, i32 %s, <8 x i32> %rsrc, i32 0, i32 2)580 ret void581}582