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1; RUN: llc -amdgpu-nsa-threshold=3 -mtriple=amdgcn -mcpu=gfx1010 -mattr=-nsa-encoding < %s | FileCheck -check-prefixes=GCN,NONSA,GFX10-NONSA %s2; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -amdgpu-nsa-threshold=32 < %s | FileCheck -check-prefixes=GCN,NONSA,GFX10-NONSA %s3; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -amdgpu-nsa-threshold=2 < %s | FileCheck -check-prefixes=GCN,NSA,NSA-T2 %s4; RUN: llc -amdgpu-nsa-threshold=3 -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GCN,NSA,NSA-T3,GFX1010-NSA %s5; RUN: llc -amdgpu-nsa-threshold=3 -mtriple=amdgcn -mcpu=gfx1030 < %s | FileCheck -check-prefixes=GCN,NSA,NSA-T3,GFX1030-NSA %s6; RUN: llc -amdgpu-nsa-threshold=3 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-nsa-encoding < %s | FileCheck -check-prefixes=GCN,NONSA,GFX11-NONSA %s7; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -amdgpu-nsa-threshold=32 < %s | FileCheck -check-prefixes=GCN,NONSA,GFX11-NONSA %s8; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -amdgpu-nsa-threshold=2 < %s | FileCheck -check-prefixes=GCN,NSA,NSA-T2 %s9; RUN: llc -amdgpu-nsa-threshold=3 -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GCN,NSA,NSA-T3,GFX11-NSA %s10 11; Default NSA threshold is 3 addresses12; GCN-LABEL: {{^}}sample_2d:13; NONSA: v_mov_b32_e32 v2, v014; NONSA: image_sample v[0:3], v[1:2],15; NSA-T2: image_sample v[0:3], [v1, v0],16; NSA-T3: v_mov_b32_e32 v2, v017; NSA-T3: image_sample v[0:3], v[1:2],18define amdgpu_ps <4 x float> @sample_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %t, float %s) {19main_body:20 %v = call <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32 15, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)21 ret <4 x float> %v22}23 24; GCN-LABEL: {{^}}sample_3d:25; NONSA: v_mov_b32_e32 v3, v026; NONSA: image_sample v[0:3], v[1:3],27; NSA: image_sample v[0:3], [v1, v2, v0],28define amdgpu_ps <4 x float> @sample_3d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %r, float %s, float %t) {29main_body:30 %v = call <4 x float> @llvm.amdgcn.image.sample.3d.v4f32.f32(i32 15, float %s, float %t, float %r, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)31 ret <4 x float> %v32}33 34; GCN-LABEL: {{^}}sample_d_3d:35; GFX1010-NSA: image_sample_d v[0:3], v[7:15],36; GFX1030-NSA: image_sample_d v[0:3], [v3, v8, v7, v5, v4, v6, v0, v2, v1],37; GFX11-NSA: image_sample_d v[0:3], [v3, v8, v7, v5, v[9:13]],38define amdgpu_ps <4 x float> @sample_d_3d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s, float %r, float %t, float %dsdh, float %dtdv, float %dsdv, float %drdv, float %drdh, float %dtdh) {39main_body:40 %v = call <4 x float> @llvm.amdgcn.image.sample.d.3d.v4f32.f32(i32 15, float %dsdh, float %dtdh, float %drdh, float %dsdv, float %dtdv, float %drdv, float %s, float %t, float %r, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)41 ret <4 x float> %v42}43 44; GCN-LABEL: {{^}}sample_contig_nsa:45; GFX10-NONSA: image_sample_c_l v5, v[0:4],46; GFX11-NONSA: image_sample_c_l v0, v[0:4],47; GFX1010-NSA: image_sample_c_l v8, v[0:4],48; GFX1010-NSA: image_sample v9, [v6, v7, v5],49; GFX1030-NSA: image_sample_c_l v0, v[0:4],50; GFX1030-NSA: image_sample v1, [v6, v7, v5],51; GFX11-NSA: image_sample_c_l v0, v[0:4],52; GFX11-NSA: image_sample v1, [v6, v7, v5],53define amdgpu_ps <2 x float> @sample_contig_nsa(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %s1, float %t1, float %r1, float %lod, float %r2, float %s2, float %t2) {54main_body:55 %v1 = call float @llvm.amdgcn.image.sample.c.l.3d.f32.f32(i32 1, float %zcompare, float %s1, float %t1, float %r1, float %lod, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)56 %v2 = call float @llvm.amdgcn.image.sample.3d.f32.f32(i32 1, float %s2, float %t2, float %r2, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)57 %r.0 = insertelement <2 x float> poison, float %v1, i32 058 %r = insertelement <2 x float> %r.0, float %v2, i32 159 ret <2 x float> %r60}61 62; GCN-LABEL: {{^}}sample_nsa_nsa:63; GFX1010-NSA: image_sample_c_l v8, [v1, v2, v3, v4, v0],64; GFX1010-NSA: image_sample v9, [v6, v7, v5],65; GFX1030-NSA: image_sample_c_l v0, [v1, v2, v3, v4, v0],66; GFX1030-NSA: image_sample v1, [v6, v7, v5],67; GFX11-NSA: image_sample_c_l v0, [v1, v2, v3, v4, v0],68; GFX11-NSA: image_sample v1, [v6, v7, v5],69define amdgpu_ps <2 x float> @sample_nsa_nsa(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %lod, float %zcompare, float %s1, float %t1, float %r1, float %r2, float %s2, float %t2) {70main_body:71 %v1 = call float @llvm.amdgcn.image.sample.c.l.3d.f32.f32(i32 1, float %zcompare, float %s1, float %t1, float %r1, float %lod, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)72 %v2 = call float @llvm.amdgcn.image.sample.3d.f32.f32(i32 1, float %s2, float %t2, float %r2, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)73 %r.0 = insertelement <2 x float> poison, float %v1, i32 074 %r = insertelement <2 x float> %r.0, float %v2, i32 175 ret <2 x float> %r76}77 78; GCN-LABEL: {{^}}sample_nsa_contig:79; GFX1010-NSA: image_sample_c_l v8, [v1, v2, v3, v4, v0],80; GFX1010-NSA: image_sample v9, v[5:7],81; GFX1030-NSA: image_sample_c_l v0, [v1, v2, v3, v4, v0],82; GFX1030-NSA: image_sample v1, v[5:7],83; GFX11-NSA: image_sample_c_l v0, [v1, v2, v3, v4, v0],84; GFX11-NSA: image_sample v1, v[5:7],85define amdgpu_ps <2 x float> @sample_nsa_contig(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %lod, float %zcompare, float %s1, float %t1, float %r1, float %s2, float %t2, float %r2) {86main_body:87 %v1 = call float @llvm.amdgcn.image.sample.c.l.3d.f32.f32(i32 1, float %zcompare, float %s1, float %t1, float %r1, float %lod, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)88 %v2 = call float @llvm.amdgcn.image.sample.3d.f32.f32(i32 1, float %s2, float %t2, float %r2, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)89 %r.0 = insertelement <2 x float> poison, float %v1, i32 090 %r = insertelement <2 x float> %r.0, float %v2, i32 191 ret <2 x float> %r92}93 94; GCN-LABEL: {{^}}sample_contig_contig:95; GFX1010-NSA: image_sample_c_l v8, v[0:4],96; GFX1010-NSA: image_sample v9, v[5:7],97; GFX1030-NSA: image_sample_c_l v0, v[0:4],98; GFX1030-NSA: image_sample v1, v[5:7],99; GFX11-NSA: image_sample_c_l v0, v[0:4],100; GFX11-NSA: image_sample v1, v[5:7],101; GFX10-NONSA: image_sample_c_l v8, v[0:4],102; GFX10-NONSA: image_sample v9, v[5:7],103; GFX11-NONSA: image_sample_c_l v0, v[0:4],104; GFX11-NONSA: image_sample v1, v[5:7],105define amdgpu_ps <2 x float> @sample_contig_contig(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %s1, float %t1, float %r1, float %lod, float %s2, float %t2, float %r2) {106main_body:107 %v1 = call float @llvm.amdgcn.image.sample.c.l.3d.f32.f32(i32 1, float %zcompare, float %s1, float %t1, float %r1, float %lod, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)108 %v2 = call float @llvm.amdgcn.image.sample.3d.f32.f32(i32 1, float %s2, float %t2, float %r2, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)109 %r.0 = insertelement <2 x float> poison, float %v1, i32 0110 %r = insertelement <2 x float> %r.0, float %v2, i32 1111 ret <2 x float> %r112}113 114; Test that undef inputs with NSA are handled safely; these tests used to crash.115 116; GCN-LABEL: {{^}}sample_undef_undef_undef_undef:117; GCN: image_sample_c_b v0, v[0:3], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_1D_ARRAY118define amdgpu_ps float @sample_undef_undef_undef_undef(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp) {119 %r = call float @llvm.amdgcn.image.sample.c.b.1darray.f32.f32.f32(i32 1, float poison, float poison, float poison, float poison, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)120 ret float %r121}122 123; GCN-LABEL: {{^}}sample_undef_undef_undef_def:124; NONSA: v_mov_b32_e32 v3, v0125; NONSA: image_sample_c_b v0, v[0:3], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_1D_ARRAY126; NSA: image_sample_c_b v0, [v0, v0, v0, v0], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_1D_ARRAY127define amdgpu_ps float @sample_undef_undef_undef_def(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %layer) {128 %r = call float @llvm.amdgcn.image.sample.c.b.1darray.f32.f32.f32(i32 1, float poison, float poison, float poison, float %layer, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)129 ret float %r130}131 132; GCN-LABEL: {{^}}sample_undef_undef_undef_def_rnd:133; GCN: v_rndne_f32_e32 v3, v0134; GCN: image_sample_c_b v0, v[0:3], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_1D_ARRAY135define amdgpu_ps float @sample_undef_undef_undef_def_rnd(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %layer) {136 %layer_rnd = call float @llvm.rint.f32(float %layer)137 %r = call float @llvm.amdgcn.image.sample.c.b.1darray.f32.f32.f32(i32 1, float poison, float poison, float poison, float %layer_rnd, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)138 ret float %r139}140 141; GCN-LABEL: {{^}}sample_def_undef_undef_undef:142; GCN: v_add_f32_e32 v0, 1.0, v0143; GCN: image_sample_c_b v0, v[0:3], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_1D_ARRAY144define amdgpu_ps float @sample_def_undef_undef_undef(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %z0) {145 ; The NSA reassign pass is conservative (quite reasonably!) when one of the operands146 ; comes directly from a function argument (via COPY). To test that NSA can be147 ; eliminated in the presence of undef, just add an arbitrary intermediate148 ; computation.149 %c0 = fadd float %z0, 1.0150 %r = call float @llvm.amdgcn.image.sample.c.b.1darray.f32.f32.f32(i32 1, float %c0, float poison, float poison, float poison, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)151 ret float %r152}153 154declare <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1155declare <4 x float> @llvm.amdgcn.image.sample.3d.v4f32.f32(i32, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1156declare <4 x float> @llvm.amdgcn.image.sample.d.3d.v4f32.f32(i32, float, float, float, float, float, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1157 158declare float @llvm.amdgcn.image.sample.3d.f32.f32(i32, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1159declare float @llvm.amdgcn.image.sample.c.l.3d.f32.f32(i32, float, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1160 161declare float @llvm.rint.f32(float) #2162declare float @llvm.amdgcn.image.sample.c.b.1darray.f32.f32.f32(i32 immarg, float, float, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #1163 164attributes #1 = { nounwind readonly }165attributes #2 = { nounwind readnone speculatable willreturn }166