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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX9 %s3; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10 %s4 5define amdgpu_ps <4 x float> @sample_cd_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dsdv, half %s) {6; GFX9-LABEL: sample_cd_1d:7; GFX9: ; %bb.0: ; %main_body8; GFX9-NEXT: image_sample_cd v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf a169; GFX9-NEXT: s_waitcnt vmcnt(0)10; GFX9-NEXT: ; return to shader part epilog11;12; GFX10-LABEL: sample_cd_1d:13; GFX10: ; %bb.0: ; %main_body14; GFX10-NEXT: image_sample_cd_g16 v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a1615; GFX10-NEXT: s_waitcnt vmcnt(0)16; GFX10-NEXT: ; return to shader part epilog17main_body:18 %v = call <4 x float> @llvm.amdgcn.image.sample.cd.1d.v4f32.f16.f16(i32 15, half %dsdh, half %dsdv, half %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)19 ret <4 x float> %v20}21 22define amdgpu_ps <4 x float> @sample_cd_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dtdh, half %dsdv, half %dtdv, half %s, half %t) {23; GFX9-LABEL: sample_cd_2d:24; GFX9: ; %bb.0: ; %main_body25; GFX9-NEXT: s_mov_b32 s12, 0x504010026; GFX9-NEXT: v_perm_b32 v4, v5, v4, s1227; GFX9-NEXT: v_perm_b32 v3, v3, v2, s1228; GFX9-NEXT: v_perm_b32 v2, v1, v0, s1229; GFX9-NEXT: image_sample_cd v[0:3], v[2:4], s[0:7], s[8:11] dmask:0xf a1630; GFX9-NEXT: s_waitcnt vmcnt(0)31; GFX9-NEXT: ; return to shader part epilog32;33; GFX10-LABEL: sample_cd_2d:34; GFX10: ; %bb.0: ; %main_body35; GFX10-NEXT: v_perm_b32 v4, v5, v4, 0x504010036; GFX10-NEXT: v_perm_b32 v3, v3, v2, 0x504010037; GFX10-NEXT: v_perm_b32 v2, v1, v0, 0x504010038; GFX10-NEXT: image_sample_cd_g16 v[0:3], v[2:4], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a1639; GFX10-NEXT: s_waitcnt vmcnt(0)40; GFX10-NEXT: ; return to shader part epilog41main_body:42 %v = call <4 x float> @llvm.amdgcn.image.sample.cd.2d.v4f32.f16.f16(i32 15, half %dsdh, half %dtdh, half %dsdv, half %dtdv, half %s, half %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)43 ret <4 x float> %v44}45 46define amdgpu_ps <4 x float> @sample_c_cd_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dsdv, half %s) {47; GFX9-LABEL: sample_c_cd_1d:48; GFX9: ; %bb.0: ; %main_body49; GFX9-NEXT: image_sample_c_cd v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf a1650; GFX9-NEXT: s_waitcnt vmcnt(0)51; GFX9-NEXT: ; return to shader part epilog52;53; GFX10-LABEL: sample_c_cd_1d:54; GFX10: ; %bb.0: ; %main_body55; GFX10-NEXT: image_sample_c_cd_g16 v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a1656; GFX10-NEXT: s_waitcnt vmcnt(0)57; GFX10-NEXT: ; return to shader part epilog58main_body:59 %v = call <4 x float> @llvm.amdgcn.image.sample.c.cd.1d.v4f32.f32.f16(i32 15, float %zcompare, half %dsdh, half %dsdv, half %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)60 ret <4 x float> %v61}62 63define amdgpu_ps <4 x float> @sample_c_cd_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, half %s, half %t) {64; GFX9-LABEL: sample_c_cd_2d:65; GFX9: ; %bb.0: ; %main_body66; GFX9-NEXT: v_mov_b32_e32 v7, v367; GFX9-NEXT: v_mov_b32_e32 v8, v268; GFX9-NEXT: s_mov_b32 s12, 0x504010069; GFX9-NEXT: v_perm_b32 v3, v6, v5, s1270; GFX9-NEXT: v_perm_b32 v2, v4, v7, s1271; GFX9-NEXT: v_perm_b32 v1, v8, v1, s1272; GFX9-NEXT: image_sample_c_cd v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf a1673; GFX9-NEXT: s_waitcnt vmcnt(0)74; GFX9-NEXT: ; return to shader part epilog75;76; GFX10-LABEL: sample_c_cd_2d:77; GFX10: ; %bb.0: ; %main_body78; GFX10-NEXT: v_perm_b32 v5, v6, v5, 0x504010079; GFX10-NEXT: v_perm_b32 v3, v4, v3, 0x504010080; GFX10-NEXT: v_perm_b32 v1, v2, v1, 0x504010081; GFX10-NEXT: image_sample_c_cd_g16 v[0:3], [v0, v1, v3, v5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a1682; GFX10-NEXT: s_waitcnt vmcnt(0)83; GFX10-NEXT: ; return to shader part epilog84main_body:85 %v = call <4 x float> @llvm.amdgcn.image.sample.c.cd.2d.v4f32.f32.f16(i32 15, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, half %s, half %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)86 ret <4 x float> %v87}88 89define amdgpu_ps <4 x float> @sample_cd_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dsdv, half %s, half %clamp) {90; GFX9-LABEL: sample_cd_cl_1d:91; GFX9: ; %bb.0: ; %main_body92; GFX9-NEXT: s_mov_b32 s12, 0x504010093; GFX9-NEXT: v_perm_b32 v2, v3, v2, s1294; GFX9-NEXT: image_sample_cd_cl v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf a1695; GFX9-NEXT: s_waitcnt vmcnt(0)96; GFX9-NEXT: ; return to shader part epilog97;98; GFX10-LABEL: sample_cd_cl_1d:99; GFX10: ; %bb.0: ; %main_body100; GFX10-NEXT: v_perm_b32 v2, v3, v2, 0x5040100101; GFX10-NEXT: image_sample_cd_cl_g16 v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16102; GFX10-NEXT: s_waitcnt vmcnt(0)103; GFX10-NEXT: ; return to shader part epilog104main_body:105 %v = call <4 x float> @llvm.amdgcn.image.sample.cd.cl.1d.v4f32.f16.f16(i32 15, half %dsdh, half %dsdv, half %s, half %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)106 ret <4 x float> %v107}108 109define amdgpu_ps <4 x float> @sample_cd_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dtdh, half %dsdv, half %dtdv, half %s, half %t, half %clamp) {110; GFX9-LABEL: sample_cd_cl_2d:111; GFX9: ; %bb.0: ; %main_body112; GFX9-NEXT: s_mov_b32 s12, 0x5040100113; GFX9-NEXT: v_perm_b32 v5, v5, v4, s12114; GFX9-NEXT: v_perm_b32 v4, v3, v2, s12115; GFX9-NEXT: v_perm_b32 v3, v1, v0, s12116; GFX9-NEXT: image_sample_cd_cl v[0:3], v[3:6], s[0:7], s[8:11] dmask:0xf a16117; GFX9-NEXT: s_waitcnt vmcnt(0)118; GFX9-NEXT: ; return to shader part epilog119;120; GFX10-LABEL: sample_cd_cl_2d:121; GFX10: ; %bb.0: ; %main_body122; GFX10-NEXT: v_perm_b32 v4, v5, v4, 0x5040100123; GFX10-NEXT: v_perm_b32 v2, v3, v2, 0x5040100124; GFX10-NEXT: v_perm_b32 v0, v1, v0, 0x5040100125; GFX10-NEXT: image_sample_cd_cl_g16 v[0:3], [v0, v2, v4, v6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16126; GFX10-NEXT: s_waitcnt vmcnt(0)127; GFX10-NEXT: ; return to shader part epilog128main_body:129 %v = call <4 x float> @llvm.amdgcn.image.sample.cd.cl.2d.v4f32.f16.f16(i32 15, half %dsdh, half %dtdh, half %dsdv, half %dtdv, half %s, half %t, half %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)130 ret <4 x float> %v131}132 133define amdgpu_ps <4 x float> @sample_c_cd_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dsdv, half %s, half %clamp) {134; GFX9-LABEL: sample_c_cd_cl_1d:135; GFX9: ; %bb.0: ; %main_body136; GFX9-NEXT: s_mov_b32 s12, 0x5040100137; GFX9-NEXT: v_perm_b32 v3, v4, v3, s12138; GFX9-NEXT: image_sample_c_cd_cl v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf a16139; GFX9-NEXT: s_waitcnt vmcnt(0)140; GFX9-NEXT: ; return to shader part epilog141;142; GFX10-LABEL: sample_c_cd_cl_1d:143; GFX10: ; %bb.0: ; %main_body144; GFX10-NEXT: v_perm_b32 v3, v4, v3, 0x5040100145; GFX10-NEXT: image_sample_c_cd_cl_g16 v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16146; GFX10-NEXT: s_waitcnt vmcnt(0)147; GFX10-NEXT: ; return to shader part epilog148main_body:149 %v = call <4 x float> @llvm.amdgcn.image.sample.c.cd.cl.1d.v4f32.f32.f16(i32 15, float %zcompare, half %dsdh, half %dsdv, half %s, half %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)150 ret <4 x float> %v151}152 153define amdgpu_ps <4 x float> @sample_c_cd_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, half %s, half %t, half %clamp) {154; GFX9-LABEL: sample_c_cd_cl_2d:155; GFX9: ; %bb.0: ; %main_body156; GFX9-NEXT: s_mov_b32 s12, 0x5040100157; GFX9-NEXT: v_mov_b32_e32 v11, v7158; GFX9-NEXT: v_mov_b32_e32 v7, v0159; GFX9-NEXT: v_perm_b32 v10, v6, v5, s12160; GFX9-NEXT: v_perm_b32 v9, v4, v3, s12161; GFX9-NEXT: v_perm_b32 v8, v2, v1, s12162; GFX9-NEXT: image_sample_c_cd_cl v[0:3], v[7:11], s[0:7], s[8:11] dmask:0xf a16163; GFX9-NEXT: s_waitcnt vmcnt(0)164; GFX9-NEXT: ; return to shader part epilog165;166; GFX10-LABEL: sample_c_cd_cl_2d:167; GFX10: ; %bb.0: ; %main_body168; GFX10-NEXT: v_perm_b32 v5, v6, v5, 0x5040100169; GFX10-NEXT: v_perm_b32 v3, v4, v3, 0x5040100170; GFX10-NEXT: v_perm_b32 v1, v2, v1, 0x5040100171; GFX10-NEXT: image_sample_c_cd_cl_g16 v[0:3], [v0, v1, v3, v5, v7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16172; GFX10-NEXT: s_waitcnt vmcnt(0)173; GFX10-NEXT: ; return to shader part epilog174main_body:175 %v = call <4 x float> @llvm.amdgcn.image.sample.c.cd.cl.2d.v4f32.f32.f16(i32 15, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, half %s, half %t, half %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)176 ret <4 x float> %v177}178 179declare <4 x float> @llvm.amdgcn.image.sample.cd.1d.v4f32.f16.f16(i32, half, half, half, <8 x i32>, <4 x i32>, i1, i32, i32) #1180declare <4 x float> @llvm.amdgcn.image.sample.cd.2d.v4f32.f16.f16(i32, half, half, half, half, half, half, <8 x i32>, <4 x i32>, i1, i32, i32) #1181declare <4 x float> @llvm.amdgcn.image.sample.c.cd.1d.v4f32.f32.f16(i32, float, half, half, half, <8 x i32>, <4 x i32>, i1, i32, i32) #1182declare <4 x float> @llvm.amdgcn.image.sample.c.cd.2d.v4f32.f32.f16(i32, float, half, half, half, half, half, half, <8 x i32>, <4 x i32>, i1, i32, i32) #1183declare <4 x float> @llvm.amdgcn.image.sample.cd.cl.1d.v4f32.f16.f16(i32, half, half, half, half, <8 x i32>, <4 x i32>, i1, i32, i32) #1184declare <4 x float> @llvm.amdgcn.image.sample.cd.cl.2d.v4f32.f16.f16(i32, half, half, half, half, half, half, half, <8 x i32>, <4 x i32>, i1, i32, i32) #1185declare <4 x float> @llvm.amdgcn.image.sample.c.cd.cl.1d.v4f32.f32.f16(i32, float, half, half, half, half, <8 x i32>, <4 x i32>, i1, i32, i32) #1186declare <4 x float> @llvm.amdgcn.image.sample.c.cd.cl.2d.v4f32.f32.f16(i32, float, half, half, half, half, half, half, half, <8 x i32>, <4 x i32>, i1, i32, i32) #1187 188attributes #0 = { nounwind }189attributes #1 = { nounwind readonly }190attributes #2 = { nounwind readnone }191