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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1030 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX10PLUS-SDAG,GFX10,GFX10-SDAG %s3; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1030 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX10PLUS-GISEL,GFX10,GFX10-GISEL %s4; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX10PLUS-SDAG,GFX11,GFX11-SDAG,GFX11-SDAG-TRUE16 %s5; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX10PLUS-SDAG,GFX11,GFX11-SDAG,GFX11-SDAG-FAKE16 %s6; FIXME-TRUE16. enable gisel7; XUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX10PLUS-GISEL,GFX11,GFX11-GISEL,GFX11-GISEL-TRUE16 %s8; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX10PLUS-GISEL,GFX11,GFX11-GISEL,GFX11-GISEL-FAKE16 %s9; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG,GFX12-SDAG-TRUE16 %s10; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG,GFX12-SDAG-FAKE16 %s11; XUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-TRUE16 %s12; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-FAKE16 %s13 14define amdgpu_ps void @sample_1d_nortn(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s) {15; GFX10PLUS-LABEL: sample_1d_nortn:16; GFX10PLUS: ; %bb.0: ; %main_body17; GFX10PLUS-NEXT: s_wqm_b32 exec_lo, exec_lo18; GFX10PLUS-NEXT: image_sample off, v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D19; GFX10PLUS-NEXT: s_endpgm20;21; GFX12-LABEL: sample_1d_nortn:22; GFX12: ; %bb.0: ; %main_body23; GFX12-NEXT: s_wqm_b32 exec_lo, exec_lo24; GFX12-NEXT: image_sample off, v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D25; GFX12-NEXT: s_endpgm26main_body:27 call void @llvm.amdgcn.image.sample.1d.nortn.f32(i32 15, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)28 ret void29}30 31define amdgpu_ps void @sample_2d_nortn(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s, float %t) {32; GFX10PLUS-LABEL: sample_2d_nortn:33; GFX10PLUS: ; %bb.0: ; %main_body34; GFX10PLUS-NEXT: s_wqm_b32 exec_lo, exec_lo35; GFX10PLUS-NEXT: image_sample off, v[0:1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D36; GFX10PLUS-NEXT: s_endpgm37;38; GFX12-LABEL: sample_2d_nortn:39; GFX12: ; %bb.0: ; %main_body40; GFX12-NEXT: s_wqm_b32 exec_lo, exec_lo41; GFX12-NEXT: image_sample off, [v0, v1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D42; GFX12-NEXT: s_endpgm43main_body:44 call void @llvm.amdgcn.image.sample.2d.nortn.f32(i32 15, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)45 ret void46}47 48define amdgpu_ps void @sample_3d_nortn(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s, float %t, float %r) {49; GFX10PLUS-LABEL: sample_3d_nortn:50; GFX10PLUS: ; %bb.0: ; %main_body51; GFX10PLUS-NEXT: s_wqm_b32 exec_lo, exec_lo52; GFX10PLUS-NEXT: image_sample off, v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D53; GFX10PLUS-NEXT: s_endpgm54;55; GFX12-LABEL: sample_3d_nortn:56; GFX12: ; %bb.0: ; %main_body57; GFX12-NEXT: s_wqm_b32 exec_lo, exec_lo58; GFX12-NEXT: image_sample off, [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D59; GFX12-NEXT: s_endpgm60main_body:61 call void @llvm.amdgcn.image.sample.3d.nortn.f32(i32 15, float %s, float %t, float %r, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)62 ret void63}64 65define amdgpu_ps void @sample_cube_nortn(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s, float %t, float %face) {66; GFX10PLUS-LABEL: sample_cube_nortn:67; GFX10PLUS: ; %bb.0: ; %main_body68; GFX10PLUS-NEXT: s_wqm_b32 exec_lo, exec_lo69; GFX10PLUS-NEXT: image_sample off, v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_CUBE70; GFX10PLUS-NEXT: s_endpgm71;72; GFX12-LABEL: sample_cube_nortn:73; GFX12: ; %bb.0: ; %main_body74; GFX12-NEXT: s_wqm_b32 exec_lo, exec_lo75; GFX12-NEXT: image_sample off, [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_CUBE76; GFX12-NEXT: s_endpgm77main_body:78 call void @llvm.amdgcn.image.sample.cube.nortn.f32(i32 15, float %s, float %t, float %face, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)79 ret void80}81 82define amdgpu_ps void @sample_1darray_nortn(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s, float %slice) {83; GFX10PLUS-LABEL: sample_1darray_nortn:84; GFX10PLUS: ; %bb.0: ; %main_body85; GFX10PLUS-NEXT: s_wqm_b32 exec_lo, exec_lo86; GFX10PLUS-NEXT: image_sample off, v[0:1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D_ARRAY87; GFX10PLUS-NEXT: s_endpgm88;89; GFX12-LABEL: sample_1darray_nortn:90; GFX12: ; %bb.0: ; %main_body91; GFX12-NEXT: s_wqm_b32 exec_lo, exec_lo92; GFX12-NEXT: image_sample off, [v0, v1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D_ARRAY93; GFX12-NEXT: s_endpgm94main_body:95 call void @llvm.amdgcn.image.sample.1darray.nortn.f32(i32 15, float %s, float %slice, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)96 ret void97}98 99define amdgpu_ps void @sample_2darray_nortn(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s, float %t, float %slice) {100; GFX10PLUS-LABEL: sample_2darray_nortn:101; GFX10PLUS: ; %bb.0: ; %main_body102; GFX10PLUS-NEXT: s_wqm_b32 exec_lo, exec_lo103; GFX10PLUS-NEXT: image_sample off, v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY104; GFX10PLUS-NEXT: s_endpgm105;106; GFX12-LABEL: sample_2darray_nortn:107; GFX12: ; %bb.0: ; %main_body108; GFX12-NEXT: s_wqm_b32 exec_lo, exec_lo109; GFX12-NEXT: image_sample off, [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY110; GFX12-NEXT: s_endpgm111main_body:112 call void @llvm.amdgcn.image.sample.2darray.nortn.f32(i32 15, float %s, float %t, float %slice, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)113 ret void114}115 116define amdgpu_ps void @sample_b_1d_nortn(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %s) {117; GFX10PLUS-LABEL: sample_b_1d_nortn:118; GFX10PLUS: ; %bb.0: ; %main_body119; GFX10PLUS-NEXT: s_wqm_b32 exec_lo, exec_lo120; GFX10PLUS-NEXT: image_sample_b off, v[0:1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D121; GFX10PLUS-NEXT: s_endpgm122;123; GFX12-LABEL: sample_b_1d_nortn:124; GFX12: ; %bb.0: ; %main_body125; GFX12-NEXT: s_wqm_b32 exec_lo, exec_lo126; GFX12-NEXT: image_sample_b off, [v0, v1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D127; GFX12-NEXT: s_endpgm128main_body:129 call void @llvm.amdgcn.image.sample.b.1d.nortn.f32(i32 15, float %zcompare, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)130 ret void131}132 133define amdgpu_ps void @sample_b_2d_nortn(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %s, float %t) {134; GFX10PLUS-LABEL: sample_b_2d_nortn:135; GFX10PLUS: ; %bb.0: ; %main_body136; GFX10PLUS-NEXT: s_wqm_b32 exec_lo, exec_lo137; GFX10PLUS-NEXT: image_sample_b off, v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D138; GFX10PLUS-NEXT: s_endpgm139;140; GFX12-LABEL: sample_b_2d_nortn:141; GFX12: ; %bb.0: ; %main_body142; GFX12-NEXT: s_wqm_b32 exec_lo, exec_lo143; GFX12-NEXT: image_sample_b off, [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D144; GFX12-NEXT: s_endpgm145main_body:146 call void @llvm.amdgcn.image.sample.b.2d.nortn.f32(i32 15, float %zcompare, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)147 ret void148}149 150define amdgpu_ps void @sample_c_1d_nortn(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %s) {151; GFX10PLUS-LABEL: sample_c_1d_nortn:152; GFX10PLUS: ; %bb.0: ; %main_body153; GFX10PLUS-NEXT: s_wqm_b32 exec_lo, exec_lo154; GFX10PLUS-NEXT: image_sample_c off, v[0:1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D155; GFX10PLUS-NEXT: s_endpgm156;157; GFX12-LABEL: sample_c_1d_nortn:158; GFX12: ; %bb.0: ; %main_body159; GFX12-NEXT: s_wqm_b32 exec_lo, exec_lo160; GFX12-NEXT: image_sample_c off, [v0, v1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D161; GFX12-NEXT: s_endpgm162main_body:163 call void @llvm.amdgcn.image.sample.c.1d.nortn.f32(i32 15, float %zcompare, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)164 ret void165}166 167define amdgpu_ps void @sample_c_2d_nortn(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %s, float %t) {168; GFX10PLUS-LABEL: sample_c_2d_nortn:169; GFX10PLUS: ; %bb.0: ; %main_body170; GFX10PLUS-NEXT: s_wqm_b32 exec_lo, exec_lo171; GFX10PLUS-NEXT: image_sample_c off, v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D172; GFX10PLUS-NEXT: s_endpgm173;174; GFX12-LABEL: sample_c_2d_nortn:175; GFX12: ; %bb.0: ; %main_body176; GFX12-NEXT: s_wqm_b32 exec_lo, exec_lo177; GFX12-NEXT: image_sample_c off, [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D178; GFX12-NEXT: s_endpgm179main_body:180 call void @llvm.amdgcn.image.sample.c.2d.nortn.f32(i32 15, float %zcompare, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)181 ret void182}183 184define amdgpu_ps void @sample_d_1d_nortn(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %dsdh, float %dsdv, float %s) {185; GFX10PLUS-LABEL: sample_d_1d_nortn:186; GFX10PLUS: ; %bb.0: ; %main_body187; GFX10PLUS-NEXT: image_sample_d off, v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D188; GFX10PLUS-NEXT: s_endpgm189;190; GFX12-LABEL: sample_d_1d_nortn:191; GFX12: ; %bb.0: ; %main_body192; GFX12-NEXT: image_sample_d off, [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D193; GFX12-NEXT: s_endpgm194main_body:195 call void @llvm.amdgcn.image.sample.d.1d.nortn.f32.f32(i32 15, float %dsdh, float %dsdv, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)196 ret void197}198 199define amdgpu_ps void @sample_d_2d_nortn(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %dsdh, float %dtdh, float %dsdv, float %dtdv, float %s, float %t) {200; GFX10PLUS-LABEL: sample_d_2d_nortn:201; GFX10PLUS: ; %bb.0: ; %main_body202; GFX10PLUS-NEXT: image_sample_d off, v[0:5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D203; GFX10PLUS-NEXT: s_endpgm204;205; GFX12-LABEL: sample_d_2d_nortn:206; GFX12: ; %bb.0: ; %main_body207; GFX12-NEXT: image_sample_d off, [v0, v1, v2, v[3:5]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D208; GFX12-NEXT: s_endpgm209main_body:210 call void @llvm.amdgcn.image.sample.d.2d.nortn.f32.f32(i32 15, float %dsdh, float %dtdh, float %dsdv, float %dtdv, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)211 ret void212}213 214define amdgpu_ps void @sample_l_1d_nortn(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s, float %lod) {215; GFX10PLUS-LABEL: sample_l_1d_nortn:216; GFX10PLUS: ; %bb.0: ; %main_body217; GFX10PLUS-NEXT: image_sample_l off, v[0:1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D218; GFX10PLUS-NEXT: s_endpgm219;220; GFX12-LABEL: sample_l_1d_nortn:221; GFX12: ; %bb.0: ; %main_body222; GFX12-NEXT: image_sample_l off, [v0, v1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D223; GFX12-NEXT: s_endpgm224main_body:225 call void @llvm.amdgcn.image.sample.l.1d.nortn.f32(i32 15, float %s, float %lod, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)226 ret void227}228 229define amdgpu_ps void @sample_l_2d_nortn(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s, float %t, float %lod) {230; GFX10PLUS-LABEL: sample_l_2d_nortn:231; GFX10PLUS: ; %bb.0: ; %main_body232; GFX10PLUS-NEXT: image_sample_l off, v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D233; GFX10PLUS-NEXT: s_endpgm234;235; GFX12-LABEL: sample_l_2d_nortn:236; GFX12: ; %bb.0: ; %main_body237; GFX12-NEXT: image_sample_l off, [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D238; GFX12-NEXT: s_endpgm239main_body:240 call void @llvm.amdgcn.image.sample.l.2d.nortn.f32(i32 15, float %s, float %t, float %lod, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)241 ret void242}243 244define amdgpu_ps <4 x float> @sample_nortn_mix_1(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s) {245; GFX10PLUS-LABEL: sample_nortn_mix_1:246; GFX10PLUS: ; %bb.0: ; %main_body247; GFX10PLUS-NEXT: s_mov_b32 s12, exec_lo248; GFX10PLUS-NEXT: s_wqm_b32 exec_lo, exec_lo249; GFX10PLUS-NEXT: s_and_b32 exec_lo, exec_lo, s12250; GFX10PLUS-NEXT: image_sample off, v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D251; GFX10PLUS-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D252; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)253; GFX10PLUS-NEXT: ; return to shader part epilog254;255; GFX12-LABEL: sample_nortn_mix_1:256; GFX12: ; %bb.0: ; %main_body257; GFX12-NEXT: s_mov_b32 s12, exec_lo258; GFX12-NEXT: s_wqm_b32 exec_lo, exec_lo259; GFX12-NEXT: s_and_b32 exec_lo, exec_lo, s12260; GFX12-NEXT: image_sample off, v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D261; GFX12-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D262; GFX12-NEXT: s_wait_samplecnt 0x0263; GFX12-NEXT: ; return to shader part epilog264main_body:265 call void @llvm.amdgcn.image.sample.1d.nortn.f32(i32 15, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)266 %v = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)267 ret <4 x float> %v268}269 270define amdgpu_ps <4 x float> @sample_nortn_mix_2(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s) {271; GFX10PLUS-LABEL: sample_nortn_mix_2:272; GFX10PLUS: ; %bb.0: ; %main_body273; GFX10PLUS-NEXT: s_mov_b32 s12, exec_lo274; GFX10PLUS-NEXT: s_wqm_b32 exec_lo, exec_lo275; GFX10PLUS-NEXT: v_mov_b32_e32 v4, v0276; GFX10PLUS-NEXT: s_and_b32 exec_lo, exec_lo, s12277; GFX10PLUS-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D278; GFX10PLUS-NEXT: image_sample off, v4, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D279; GFX10PLUS-NEXT: s_waitcnt vmcnt(0)280; GFX10PLUS-NEXT: ; return to shader part epilog281;282; GFX12-LABEL: sample_nortn_mix_2:283; GFX12: ; %bb.0: ; %main_body284; GFX12-NEXT: s_mov_b32 s12, exec_lo285; GFX12-NEXT: s_wqm_b32 exec_lo, exec_lo286; GFX12-NEXT: v_mov_b32_e32 v4, v0287; GFX12-NEXT: s_and_b32 exec_lo, exec_lo, s12288; GFX12-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D289; GFX12-NEXT: image_sample off, v4, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D290; GFX12-NEXT: s_wait_samplecnt 0x0291; GFX12-NEXT: ; return to shader part epilog292main_body:293 %v = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)294 call void @llvm.amdgcn.image.sample.1d.nortn.f32(i32 15, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)295 ret <4 x float> %v296}297 298define amdgpu_ps <4 x float> @sample_nortn_mix_3(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s) {299; GFX10PLUS-SDAG-LABEL: sample_nortn_mix_3:300; GFX10PLUS-SDAG: ; %bb.0: ; %main_body301; GFX10PLUS-SDAG-NEXT: s_mov_b32 s12, exec_lo302; GFX10PLUS-SDAG-NEXT: s_wqm_b32 exec_lo, exec_lo303; GFX10PLUS-SDAG-NEXT: image_sample v1, v0, s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_1D304; GFX10PLUS-SDAG-NEXT: s_and_b32 exec_lo, exec_lo, s12305; GFX10PLUS-SDAG-NEXT: image_sample off, v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D306; GFX10PLUS-SDAG-NEXT: s_waitcnt vmcnt(1)307; GFX10PLUS-SDAG-NEXT: image_sample v[0:3], v1, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D308; GFX10PLUS-SDAG-NEXT: s_waitcnt vmcnt(0)309; GFX10PLUS-SDAG-NEXT: ; return to shader part epilog310;311; GFX10PLUS-GISEL-LABEL: sample_nortn_mix_3:312; GFX10PLUS-GISEL: ; %bb.0: ; %main_body313; GFX10PLUS-GISEL-NEXT: s_mov_b32 s12, exec_lo314; GFX10PLUS-GISEL-NEXT: s_wqm_b32 exec_lo, exec_lo315; GFX10PLUS-GISEL-NEXT: image_sample v[1:4], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D316; GFX10PLUS-GISEL-NEXT: s_and_b32 exec_lo, exec_lo, s12317; GFX10PLUS-GISEL-NEXT: image_sample off, v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D318; GFX10PLUS-GISEL-NEXT: s_waitcnt vmcnt(1)319; GFX10PLUS-GISEL-NEXT: image_sample v[0:3], v1, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D320; GFX10PLUS-GISEL-NEXT: s_waitcnt vmcnt(0)321; GFX10PLUS-GISEL-NEXT: ; return to shader part epilog322;323; GFX12-SDAG-LABEL: sample_nortn_mix_3:324; GFX12-SDAG: ; %bb.0: ; %main_body325; GFX12-SDAG-NEXT: s_mov_b32 s12, exec_lo326; GFX12-SDAG-NEXT: s_wqm_b32 exec_lo, exec_lo327; GFX12-SDAG-NEXT: image_sample v1, v0, s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_1D328; GFX12-SDAG-NEXT: s_and_b32 exec_lo, exec_lo, s12329; GFX12-SDAG-NEXT: image_sample off, v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D330; GFX12-SDAG-NEXT: s_wait_samplecnt 0x1331; GFX12-SDAG-NEXT: image_sample v[0:3], v1, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D332; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0333; GFX12-SDAG-NEXT: ; return to shader part epilog334;335; GFX12-GISEL-LABEL: sample_nortn_mix_3:336; GFX12-GISEL: ; %bb.0: ; %main_body337; GFX12-GISEL-NEXT: s_mov_b32 s12, exec_lo338; GFX12-GISEL-NEXT: s_wqm_b32 exec_lo, exec_lo339; GFX12-GISEL-NEXT: image_sample v[1:4], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D340; GFX12-GISEL-NEXT: s_and_b32 exec_lo, exec_lo, s12341; GFX12-GISEL-NEXT: image_sample off, v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D342; GFX12-GISEL-NEXT: s_wait_samplecnt 0x1343; GFX12-GISEL-NEXT: image_sample v[0:3], v1, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D344; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0345; GFX12-GISEL-NEXT: ; return to shader part epilog346main_body:347 %v = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)348 %v.0 = extractelement <4 x float> %v, i32 0349 call void @llvm.amdgcn.image.sample.1d.nortn.f32(i32 15, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)350 %u = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %v.0, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)351 ret <4 x float> %u352}353 354define amdgpu_ps <4 x float> @sample_nortn_mix_4(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s) {355; GFX10PLUS-SDAG-LABEL: sample_nortn_mix_4:356; GFX10PLUS-SDAG: ; %bb.0: ; %main_body357; GFX10PLUS-SDAG-NEXT: s_mov_b32 s12, exec_lo358; GFX10PLUS-SDAG-NEXT: s_wqm_b32 exec_lo, exec_lo359; GFX10PLUS-SDAG-NEXT: image_sample v4, v0, s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_1D360; GFX10PLUS-SDAG-NEXT: image_sample off, v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D361; GFX10PLUS-SDAG-NEXT: s_waitcnt vmcnt(1)362; GFX10PLUS-SDAG-NEXT: image_sample off, v4, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D363; GFX10PLUS-SDAG-NEXT: image_sample v[0:3], v4, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D364; GFX10PLUS-SDAG-NEXT: s_and_b32 exec_lo, exec_lo, s12365; GFX10PLUS-SDAG-NEXT: image_sample off, v4, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D366; GFX10PLUS-SDAG-NEXT: image_sample off, v4, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D367; GFX10PLUS-SDAG-NEXT: s_waitcnt vmcnt(2)368; GFX10PLUS-SDAG-NEXT: image_sample off, v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D369; GFX10PLUS-SDAG-NEXT: s_waitcnt vmcnt(0)370; GFX10PLUS-SDAG-NEXT: ; return to shader part epilog371;372; GFX10PLUS-GISEL-LABEL: sample_nortn_mix_4:373; GFX10PLUS-GISEL: ; %bb.0: ; %main_body374; GFX10PLUS-GISEL-NEXT: s_mov_b32 s12, exec_lo375; GFX10PLUS-GISEL-NEXT: s_wqm_b32 exec_lo, exec_lo376; GFX10PLUS-GISEL-NEXT: image_sample v[4:7], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D377; GFX10PLUS-GISEL-NEXT: image_sample off, v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D378; GFX10PLUS-GISEL-NEXT: s_waitcnt vmcnt(1)379; GFX10PLUS-GISEL-NEXT: image_sample off, v4, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D380; GFX10PLUS-GISEL-NEXT: image_sample v[0:3], v4, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D381; GFX10PLUS-GISEL-NEXT: s_and_b32 exec_lo, exec_lo, s12382; GFX10PLUS-GISEL-NEXT: image_sample off, v4, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D383; GFX10PLUS-GISEL-NEXT: image_sample off, v4, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D384; GFX10PLUS-GISEL-NEXT: s_waitcnt vmcnt(2)385; GFX10PLUS-GISEL-NEXT: image_sample off, v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D386; GFX10PLUS-GISEL-NEXT: s_waitcnt vmcnt(0)387; GFX10PLUS-GISEL-NEXT: ; return to shader part epilog388;389; GFX12-SDAG-LABEL: sample_nortn_mix_4:390; GFX12-SDAG: ; %bb.0: ; %main_body391; GFX12-SDAG-NEXT: s_mov_b32 s12, exec_lo392; GFX12-SDAG-NEXT: s_wqm_b32 exec_lo, exec_lo393; GFX12-SDAG-NEXT: image_sample v4, v0, s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_1D394; GFX12-SDAG-NEXT: image_sample off, v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D395; GFX12-SDAG-NEXT: s_wait_samplecnt 0x1396; GFX12-SDAG-NEXT: image_sample off, v4, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D397; GFX12-SDAG-NEXT: image_sample v[0:3], v4, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D398; GFX12-SDAG-NEXT: s_and_b32 exec_lo, exec_lo, s12399; GFX12-SDAG-NEXT: image_sample off, v4, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D400; GFX12-SDAG-NEXT: image_sample off, v4, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D401; GFX12-SDAG-NEXT: s_wait_samplecnt 0x2402; GFX12-SDAG-NEXT: image_sample off, v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D403; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0404; GFX12-SDAG-NEXT: ; return to shader part epilog405;406; GFX12-GISEL-LABEL: sample_nortn_mix_4:407; GFX12-GISEL: ; %bb.0: ; %main_body408; GFX12-GISEL-NEXT: s_mov_b32 s12, exec_lo409; GFX12-GISEL-NEXT: s_wqm_b32 exec_lo, exec_lo410; GFX12-GISEL-NEXT: image_sample v[4:7], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D411; GFX12-GISEL-NEXT: image_sample off, v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D412; GFX12-GISEL-NEXT: s_wait_samplecnt 0x1413; GFX12-GISEL-NEXT: image_sample off, v4, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D414; GFX12-GISEL-NEXT: image_sample v[0:3], v4, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D415; GFX12-GISEL-NEXT: s_and_b32 exec_lo, exec_lo, s12416; GFX12-GISEL-NEXT: image_sample off, v4, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D417; GFX12-GISEL-NEXT: image_sample off, v4, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D418; GFX12-GISEL-NEXT: s_wait_samplecnt 0x2419; GFX12-GISEL-NEXT: image_sample off, v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D420; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0421; GFX12-GISEL-NEXT: ; return to shader part epilog422main_body:423 %v = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)424 %v.0 = extractelement <4 x float> %v, i32 0425 %v.1 = extractelement <4 x float> %v, i32 0426 %v.2 = extractelement <4 x float> %v, i32 0427 %v.3 = extractelement <4 x float> %v, i32 0428 call void @llvm.amdgcn.image.sample.1d.nortn.f32(i32 15, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)429 call void @llvm.amdgcn.image.sample.1d.nortn.f32(i32 15, float %v.0, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)430 %u = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %v.1, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)431 %u.0 = extractelement <4 x float> %u, i32 0432 call void @llvm.amdgcn.image.sample.1d.nortn.f32(i32 15, float %v.2, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)433 call void @llvm.amdgcn.image.sample.1d.nortn.f32(i32 15, float %v.3, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)434 call void @llvm.amdgcn.image.sample.1d.nortn.f32(i32 15, float %u.0, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)435 ret <4 x float> %u436}437 438define amdgpu_ps void @sample_d_1d_g16_nortn(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dsdv, float %s) {439; GFX10PLUS-LABEL: sample_d_1d_g16_nortn:440; GFX10PLUS: ; %bb.0: ; %main_body441; GFX10PLUS-NEXT: image_sample_d_g16 off, v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D442; GFX10PLUS-NEXT: s_endpgm443;444; GFX12-LABEL: sample_d_1d_g16_nortn:445; GFX12: ; %bb.0: ; %main_body446; GFX12-NEXT: image_sample_d_g16 off, [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D447; GFX12-NEXT: s_endpgm448main_body:449 call void @llvm.amdgcn.image.sample.d.1d.nortn.f16.f32(i32 15, half %dsdh, half %dsdv, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)450 ret void451}452 453declare void @llvm.amdgcn.image.sample.1d.nortn.f32(i32, float, <8 x i32>, <4 x i32>, i1, i32, i32) #0454declare void @llvm.amdgcn.image.sample.2d.nortn.f32(i32, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #0455declare void @llvm.amdgcn.image.sample.3d.nortn.f32(i32, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #0456declare void @llvm.amdgcn.image.sample.cube.nortn.f32(i32, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #0457declare void @llvm.amdgcn.image.sample.1darray.nortn.f32(i32, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #0458declare void @llvm.amdgcn.image.sample.2darray.nortn.f32(i32, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #0459 460declare void @llvm.amdgcn.image.sample.b.1d.nortn.f32(i32, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #0461declare void @llvm.amdgcn.image.sample.b.2d.nortn.f32(i32, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #0462 463declare void @llvm.amdgcn.image.sample.c.1d.nortn.f32(i32, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #0464declare void @llvm.amdgcn.image.sample.c.2d.nortn.f32(i32, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #0465 466declare void @llvm.amdgcn.image.sample.d.1d.f32.nortn.f32(i32, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #0467declare void @llvm.amdgcn.image.sample.d.2d.f32.nortn.f32(i32, float, float, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #0468 469declare void @llvm.amdgcn.image.sample.l.1d.nortn.f32(i32, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #0470declare void @llvm.amdgcn.image.sample.l.2d.nortn.f32(i32, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #0471 472declare <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1473 474declare void @llvm.amdgcn.image.sample.d.1d.nortn.f16.f32(i32, half, half, float, <8 x i32>, <4 x i32>, i1, i32, i32) #0475 476attributes #0 = { nounwind }477attributes #1 = { nounwind readonly }478;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:479; GFX10: {{.*}}480; GFX10-GISEL: {{.*}}481; GFX10-SDAG: {{.*}}482; GFX11: {{.*}}483; GFX11-GISEL: {{.*}}484; GFX11-GISEL-FAKE16: {{.*}}485; GFX11-SDAG: {{.*}}486; GFX11-SDAG-FAKE16: {{.*}}487; GFX11-SDAG-TRUE16: {{.*}}488; GFX12-GISEL-FAKE16: {{.*}}489; GFX12-SDAG-FAKE16: {{.*}}490; GFX12-SDAG-TRUE16: {{.*}}491