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1; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefix=GCN %s2; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefix=GCN %s3; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefix=GCN %s4; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefix=GCN %s5; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefix=GCN %s6; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefix=GCN %s7 8; GCN-LABEL: {{^}}full_mask:9; GCN: s_mov_b64 exec, -110; GCN: v_add_f32_e32 v0,11define amdgpu_ps float @full_mask(float %a, float %b) {12main_body:13 %s = fadd float %a, %b14 call void @llvm.amdgcn.init.exec(i64 -1)15 ret float %s16}17 18; GCN-LABEL: {{^}}partial_mask:19; GCN: s_mov_b64 exec, 0x1e24020; GCN: v_add_f32_e32 v0,21define amdgpu_ps float @partial_mask(float %a, float %b) {22main_body:23 %s = fadd float %a, %b24 call void @llvm.amdgcn.init.exec(i64 123456)25 ret float %s26}27 28; GCN-LABEL: {{^}}input_s3off8:29; GCN: s_bfe_u32 s0, s3, 0x7000830; GCN: s_bfm_b64 exec, s0, 031; GCN: s_cmp_eq_u32 s0, 6432; GCN: s_cmov_b64 exec, -133; GCN: v_add_f32_e32 v0,34define amdgpu_ps float @input_s3off8(i32 inreg, i32 inreg, i32 inreg, i32 inreg %count, float %a, float %b) {35main_body:36 %s = fadd float %a, %b37 call void @llvm.amdgcn.init.exec.from.input(i32 %count, i32 8)38 ret float %s39}40 41; GCN-LABEL: {{^}}input_s0off19:42; GCN: s_bfe_u32 s0, s0, 0x7001343; GCN: s_bfm_b64 exec, s0, 044; GCN: s_cmp_eq_u32 s0, 6445; GCN: s_cmov_b64 exec, -146; GCN: v_add_f32_e32 v0,47define amdgpu_ps float @input_s0off19(i32 inreg %count, float %a, float %b) {48main_body:49 %s = fadd float %a, %b50 call void @llvm.amdgcn.init.exec.from.input(i32 %count, i32 19)51 ret float %s52}53 54; GCN-LABEL: {{^}}reuse_input:55; GCN: s_bfe_u32 s1, s0, 0x7001356; GCN: s_bfm_b64 exec, s1, 057; GCN: s_cmp_eq_u32 s1, 6458; GCN: s_cmov_b64 exec, -159; GCN: v_add{{(_nc)?}}_u32_e32 v0, s0, v060define amdgpu_ps float @reuse_input(i32 inreg %count, i32 %a) {61main_body:62 call void @llvm.amdgcn.init.exec.from.input(i32 %count, i32 19)63 %s = add i32 %a, %count64 %f = sitofp i32 %s to float65 ret float %f66}67 68; GCN-LABEL: {{^}}reuse_input2:69; GCN: s_bfe_u32 s1, s0, 0x7001370; GCN: s_bfm_b64 exec, s1, 071; GCN: s_cmp_eq_u32 s1, 6472; GCN: s_cmov_b64 exec, -173; GCN: v_add{{(_nc)?}}_u32_e32 v0, s0, v074define amdgpu_ps float @reuse_input2(i32 inreg %count, i32 %a) {75main_body:76 %s = add i32 %a, %count77 %f = sitofp i32 %s to float78 call void @llvm.amdgcn.init.exec.from.input(i32 %count, i32 19)79 ret float %f80}81 82; GCN-LABEL: {{^}}init_unreachable:83;84; This used to crash.85define amdgpu_ps void @init_unreachable() {86main_body:87 call void @llvm.amdgcn.init.exec(i64 -1)88 unreachable89}90 91; GCN-LABEL: {{^}}init_exec_before_frame_materialize:92; GCN-NOT: {{^}}v_93; GCN: s_mov_b64 exec, -194; GCN: v_mov95; GCN: v_add96define amdgpu_ps float @init_exec_before_frame_materialize(i32 inreg %a, i32 inreg %b) {97main_body:98 %array0 = alloca [1024 x i32], align 16, addrspace(5)99 %array1 = alloca [20 x i32], align 16, addrspace(5)100 call void @llvm.amdgcn.init.exec(i64 -1)101 102 %ptr0 = getelementptr inbounds [1024 x i32], ptr addrspace(5) %array0, i32 0, i32 1103 store i32 %a, ptr addrspace(5) %ptr0, align 4104 105 %ptr1 = getelementptr inbounds [20 x i32], ptr addrspace(5) %array1, i32 0, i32 1106 store i32 %a, ptr addrspace(5) %ptr1, align 4107 108 %ptr2 = getelementptr inbounds [20 x i32], ptr addrspace(5) %array1, i32 0, i32 2109 store i32 %b, ptr addrspace(5) %ptr2, align 4110 111 %ptr3 = getelementptr inbounds [20 x i32], ptr addrspace(5) %array1, i32 0, i32 %b112 %v3 = load i32, ptr addrspace(5) %ptr3, align 4113 114 %ptr4 = getelementptr inbounds [1024 x i32], ptr addrspace(5) %array0, i32 0, i32 %b115 %v4 = load i32, ptr addrspace(5) %ptr4, align 4116 117 %v5 = add i32 %v3, %v4118 %v = bitcast i32 %v5 to float119 ret float %v120}121 122; GCN-LABEL: {{^}}init_exec_input_before_frame_materialize:123; GCN-NOT: {{^}}v_124; GCN: s_bfe_u32 s2, s2, 0x70008125; GCN-NEXT: s_bfm_b64 exec, s2, 0126; GCN-NEXT: s_cmp_eq_u32 s2, 64127; GCN-NEXT: s_cmov_b64 exec, -1128; GCN: v_mov129; GCN: v_add130define amdgpu_ps float @init_exec_input_before_frame_materialize(i32 inreg %a, i32 inreg %b, i32 inreg %count) {131main_body:132 %array0 = alloca [1024 x i32], align 16, addrspace(5)133 %array1 = alloca [20 x i32], align 16, addrspace(5)134 call void @llvm.amdgcn.init.exec.from.input(i32 %count, i32 8)135 136 %ptr0 = getelementptr inbounds [1024 x i32], ptr addrspace(5) %array0, i32 0, i32 1137 store i32 %a, ptr addrspace(5) %ptr0, align 4138 139 %ptr1 = getelementptr inbounds [20 x i32], ptr addrspace(5) %array1, i32 0, i32 1140 store i32 %a, ptr addrspace(5) %ptr1, align 4141 142 %ptr2 = getelementptr inbounds [20 x i32], ptr addrspace(5) %array1, i32 0, i32 2143 store i32 %b, ptr addrspace(5) %ptr2, align 4144 145 %ptr3 = getelementptr inbounds [20 x i32], ptr addrspace(5) %array1, i32 0, i32 %b146 %v3 = load i32, ptr addrspace(5) %ptr3, align 4147 148 %ptr4 = getelementptr inbounds [1024 x i32], ptr addrspace(5) %array0, i32 0, i32 %b149 %v4 = load i32, ptr addrspace(5) %ptr4, align 4150 151 %v5 = add i32 %v3, %v4152 %v = bitcast i32 %v5 to float153 ret float %v154}155 156; GCN-LABEL: {{^}}init_exec_input_before_frame_materialize_nonentry:157; GCN-NOT: {{^}}v_158; GCN: %endif159; GCN: s_bfe_u32 [[S:s[0-9]+]], s2, 0x70008160; GCN-NEXT: s_bfm_b64 exec, [[S]], 0161; GCN-NEXT: s_cmp_eq_u32 [[S]], 64162; GCN-NEXT: s_cmov_b64 exec, -1163; GCN: v_mov164; GCN: v_add165define amdgpu_ps float @init_exec_input_before_frame_materialize_nonentry(i32 inreg %a, i32 inreg %b, i32 inreg %count) {166main_body:167 ; ideally these alloca would be in %endif, but this causes problems on Windows GlobalISel168 %array0 = alloca [1024 x i32], align 16, addrspace(5)169 %array1 = alloca [20 x i32], align 16, addrspace(5)170 171 %cc = icmp uge i32 %count, 32172 br i1 %cc, label %endif, label %if173 174if:175 call void asm sideeffect "", ""()176 br label %endif177 178endif:179 call void @llvm.amdgcn.init.exec.from.input(i32 %count, i32 8)180 181 %ptr0 = getelementptr inbounds [1024 x i32], ptr addrspace(5) %array0, i32 0, i32 1182 store i32 %a, ptr addrspace(5) %ptr0, align 4183 184 %ptr1 = getelementptr inbounds [20 x i32], ptr addrspace(5) %array1, i32 0, i32 1185 store i32 %a, ptr addrspace(5) %ptr1, align 4186 187 %ptr2 = getelementptr inbounds [20 x i32], ptr addrspace(5) %array1, i32 0, i32 2188 store i32 %b, ptr addrspace(5) %ptr2, align 4189 190 %ptr3 = getelementptr inbounds [20 x i32], ptr addrspace(5) %array1, i32 0, i32 %b191 %v3 = load i32, ptr addrspace(5) %ptr3, align 4192 193 %ptr4 = getelementptr inbounds [1024 x i32], ptr addrspace(5) %array0, i32 0, i32 %b194 %v4 = load i32, ptr addrspace(5) %ptr4, align 4195 196 %v5 = add i32 %v3, %v4197 %v6 = add i32 %v5, %count198 %v = bitcast i32 %v6 to float199 ret float %v200}201 202declare void @llvm.amdgcn.init.exec(i64) #1203declare void @llvm.amdgcn.init.exec.from.input(i32, i32) #1204 205attributes #1 = { convergent }206