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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -global-isel=1 -O2 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64 < %s | FileCheck --check-prefix=GISEL12 %s3; RUN: llc -global-isel=0 -O2 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64 < %s | FileCheck --check-prefix=DAGISEL12 %s4; RUN: llc -global-isel=1 -O2 -mtriple=amdgcn -mcpu=gfx1030 -mattr=+wavefrontsize64 < %s | FileCheck --check-prefix=GISEL10 %s5; RUN: llc -global-isel=0 -O2 -mtriple=amdgcn -mcpu=gfx1030 -mattr=+wavefrontsize64 < %s | FileCheck --check-prefix=DAGISEL10 %s6 7; This shouldn't be too different from wave32, so we'll only test one case.8 9define amdgpu_cs_chain void @basic(<3 x i32> inreg %sgpr, ptr inreg %callee, i64 inreg %exec, { i32, ptr addrspace(5), i32, i64 } %vgpr, i32 %x, i32 %y) {10; GISEL12-LABEL: basic:11; GISEL12: ; %bb.0: ; %entry12; GISEL12-NEXT: s_wait_loadcnt_dscnt 0x013; GISEL12-NEXT: s_wait_expcnt 0x014; GISEL12-NEXT: s_wait_samplecnt 0x015; GISEL12-NEXT: s_wait_bvhcnt 0x016; GISEL12-NEXT: s_wait_kmcnt 0x017; GISEL12-NEXT: s_or_saveexec_b64 s[10:11], -118; GISEL12-NEXT: s_mov_b32 s8, s319; GISEL12-NEXT: s_mov_b32 s9, s420; GISEL12-NEXT: s_mov_b32 s4, s521; GISEL12-NEXT: s_mov_b32 s5, s622; GISEL12-NEXT: s_wait_alu depctr_sa_sdst(0)23; GISEL12-NEXT: s_and_saveexec_b64 s[6:7], s[10:11]24; GISEL12-NEXT: s_cbranch_execz .LBB0_225; GISEL12-NEXT: ; %bb.1: ; %shader26; GISEL12-NEXT: s_or_saveexec_b64 s[10:11], -127; GISEL12-NEXT: s_wait_alu depctr_sa_sdst(0)28; GISEL12-NEXT: v_cndmask_b32_e64 v0, 0x47, v13, s[10:11]29; GISEL12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)30; GISEL12-NEXT: v_cmp_ne_u32_e64 s[12:13], 0, v031; GISEL12-NEXT: s_wait_alu depctr_va_sdst(0)32; GISEL12-NEXT: v_mov_b32_e32 v0, s1233; GISEL12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)34; GISEL12-NEXT: v_mov_b32_e32 v1, s1335; GISEL12-NEXT: s_mov_b64 exec, s[10:11]36; GISEL12-NEXT: v_mov_b32_e32 v11, v037; GISEL12-NEXT: v_add_nc_u32_e32 v10, 42, v1338; GISEL12-NEXT: s_delay_alu instid0(VALU_DEP_3)39; GISEL12-NEXT: v_mov_b32_e32 v12, v140; GISEL12-NEXT: .LBB0_2: ; %tail41; GISEL12-NEXT: s_wait_alu depctr_sa_sdst(0)42; GISEL12-NEXT: s_or_b64 exec, exec, s[6:7]43; GISEL12-NEXT: s_mov_b64 exec, s[4:5]44; GISEL12-NEXT: s_setpc_b64 s[8:9]45;46; DAGISEL12-LABEL: basic:47; DAGISEL12: ; %bb.0: ; %entry48; DAGISEL12-NEXT: s_wait_loadcnt_dscnt 0x049; DAGISEL12-NEXT: s_wait_expcnt 0x050; DAGISEL12-NEXT: s_wait_samplecnt 0x051; DAGISEL12-NEXT: s_wait_bvhcnt 0x052; DAGISEL12-NEXT: s_wait_kmcnt 0x053; DAGISEL12-NEXT: s_or_saveexec_b64 s[10:11], -154; DAGISEL12-NEXT: s_mov_b32 s7, s655; DAGISEL12-NEXT: s_mov_b32 s6, s556; DAGISEL12-NEXT: s_mov_b32 s5, s457; DAGISEL12-NEXT: s_mov_b32 s4, s358; DAGISEL12-NEXT: s_wait_alu depctr_sa_sdst(0)59; DAGISEL12-NEXT: s_and_saveexec_b64 s[8:9], s[10:11]60; DAGISEL12-NEXT: ; %bb.1: ; %shader61; DAGISEL12-NEXT: s_or_saveexec_b64 s[10:11], -162; DAGISEL12-NEXT: s_wait_alu depctr_sa_sdst(0)63; DAGISEL12-NEXT: v_cndmask_b32_e64 v0, 0x47, v13, s[10:11]64; DAGISEL12-NEXT: s_delay_alu instid0(VALU_DEP_1)65; DAGISEL12-NEXT: v_cmp_ne_u32_e64 s[12:13], 0, v066; DAGISEL12-NEXT: s_mov_b64 exec, s[10:11]67; DAGISEL12-NEXT: v_mov_b32_e32 v11, s1268; DAGISEL12-NEXT: v_add_nc_u32_e32 v10, 42, v1369; DAGISEL12-NEXT: v_mov_b32_e32 v12, s1370; DAGISEL12-NEXT: ; %bb.2: ; %tail71; DAGISEL12-NEXT: s_or_b64 exec, exec, s[8:9]72; DAGISEL12-NEXT: s_mov_b64 exec, s[6:7]73; DAGISEL12-NEXT: s_setpc_b64 s[4:5]74;75; GISEL10-LABEL: basic:76; GISEL10: ; %bb.0: ; %entry77; GISEL10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)78; GISEL10-NEXT: s_or_saveexec_b64 s[10:11], -179; GISEL10-NEXT: s_mov_b32 s8, s380; GISEL10-NEXT: s_mov_b32 s9, s481; GISEL10-NEXT: s_mov_b32 s4, s582; GISEL10-NEXT: s_mov_b32 s5, s683; GISEL10-NEXT: s_and_saveexec_b64 s[6:7], s[10:11]84; GISEL10-NEXT: s_cbranch_execz .LBB0_285; GISEL10-NEXT: ; %bb.1: ; %shader86; GISEL10-NEXT: s_or_saveexec_b64 s[10:11], -187; GISEL10-NEXT: v_cndmask_b32_e64 v0, 0x47, v13, s[10:11]88; GISEL10-NEXT: v_cmp_ne_u32_e64 s[12:13], 0, v089; GISEL10-NEXT: v_mov_b32_e32 v0, s1290; GISEL10-NEXT: v_mov_b32_e32 v1, s1391; GISEL10-NEXT: s_mov_b64 exec, s[10:11]92; GISEL10-NEXT: v_mov_b32_e32 v11, v093; GISEL10-NEXT: v_add_nc_u32_e32 v10, 42, v1394; GISEL10-NEXT: v_mov_b32_e32 v12, v195; GISEL10-NEXT: .LBB0_2: ; %tail96; GISEL10-NEXT: s_or_b64 exec, exec, s[6:7]97; GISEL10-NEXT: s_mov_b64 exec, s[4:5]98; GISEL10-NEXT: s_setpc_b64 s[8:9]99;100; DAGISEL10-LABEL: basic:101; DAGISEL10: ; %bb.0: ; %entry102; DAGISEL10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)103; DAGISEL10-NEXT: s_or_saveexec_b64 s[10:11], -1104; DAGISEL10-NEXT: s_mov_b32 s7, s6105; DAGISEL10-NEXT: s_mov_b32 s6, s5106; DAGISEL10-NEXT: s_mov_b32 s5, s4107; DAGISEL10-NEXT: s_mov_b32 s4, s3108; DAGISEL10-NEXT: s_and_saveexec_b64 s[8:9], s[10:11]109; DAGISEL10-NEXT: ; %bb.1: ; %shader110; DAGISEL10-NEXT: s_or_saveexec_b64 s[10:11], -1111; DAGISEL10-NEXT: v_cndmask_b32_e64 v0, 0x47, v13, s[10:11]112; DAGISEL10-NEXT: v_cmp_ne_u32_e64 s[12:13], 0, v0113; DAGISEL10-NEXT: s_mov_b64 exec, s[10:11]114; DAGISEL10-NEXT: v_mov_b32_e32 v11, s12115; DAGISEL10-NEXT: v_add_nc_u32_e32 v10, 42, v13116; DAGISEL10-NEXT: v_mov_b32_e32 v12, s13117; DAGISEL10-NEXT: ; %bb.2: ; %tail118; DAGISEL10-NEXT: s_or_b64 exec, exec, s[8:9]119; DAGISEL10-NEXT: s_mov_b64 exec, s[6:7]120; DAGISEL10-NEXT: s_setpc_b64 s[4:5]121entry:122 %entry_exec = call i1 @llvm.amdgcn.init.whole.wave()123 br i1 %entry_exec, label %shader, label %tail124 125shader:126 %nonwwm = add i32 %x, 42127 %vgpr.1 = insertvalue { i32, ptr addrspace(5), i32, i64} %vgpr, i32 %nonwwm, 2128 129 %full.vgpr = call i32 @llvm.amdgcn.set.inactive.i32(i32 %x, i32 71)130 %non.zero = icmp ne i32 %full.vgpr, 0131 %ballot = call i64 @llvm.amdgcn.ballot.i64(i1 %non.zero)132 %wwm = call i64 @llvm.amdgcn.strict.wwm.i64(i64 %ballot)133 %vgpr.2 = insertvalue { i32, ptr addrspace(5), i32, i64} %vgpr.1, i64 %wwm, 3134 135 br label %tail136 137tail:138 %vgpr.args = phi { i32, ptr addrspace(5), i32, i64} [%vgpr, %entry], [%vgpr.2, %shader]139 call void(ptr, i64, <3 x i32>, { i32, ptr addrspace(5), i32, i64 }, i32, ...) @llvm.amdgcn.cs.chain(ptr %callee, i64 %exec, <3 x i32> inreg %sgpr, { i32, ptr addrspace(5), i32, i64 } %vgpr.args, i32 0)140 unreachable141}142