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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX9-32BANK %s3; RUN: llc -mtriple=amdgcn -mcpu=fiji < %s | FileCheck -check-prefixes=GFX8-32BANK %s4; RUN: llc -mtriple=amdgcn -mcpu=gfx810 < %s | FileCheck -check-prefixes=GFX8-16BANK %s5 6define amdgpu_ps half @interp_f16(float inreg %i, float inreg %j, i32 inreg %m0) #0 {7; GFX9-32BANK-LABEL: interp_f16:8; GFX9-32BANK: ; %bb.0: ; %main_body9; GFX9-32BANK-NEXT: s_mov_b32 m0, s210; GFX9-32BANK-NEXT: v_mov_b32_e32 v0, s011; GFX9-32BANK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 312; GFX9-32BANK-NEXT: v_interp_p1ll_f16 v1, v0, attr2.y13; GFX9-32BANK-NEXT: v_mov_b32_e32 v2, s114; GFX9-32BANK-NEXT: v_interp_p1ll_f16 v0, v0, attr2.y high15; GFX9-32BANK-NEXT: v_interp_p2_legacy_f16 v1, v2, attr2.y, v116; GFX9-32BANK-NEXT: v_interp_p2_legacy_f16 v0, v2, attr2.y, v0 high17; GFX9-32BANK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 018; GFX9-32BANK-NEXT: v_add_f16_e32 v0, v1, v019; GFX9-32BANK-NEXT: ; return to shader part epilog20;21; GFX8-32BANK-LABEL: interp_f16:22; GFX8-32BANK: ; %bb.0: ; %main_body23; GFX8-32BANK-NEXT: s_mov_b32 m0, s224; GFX8-32BANK-NEXT: v_mov_b32_e32 v0, s025; GFX8-32BANK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 326; GFX8-32BANK-NEXT: v_interp_p1ll_f16 v1, v0, attr2.y27; GFX8-32BANK-NEXT: v_mov_b32_e32 v2, s128; GFX8-32BANK-NEXT: v_interp_p1ll_f16 v0, v0, attr2.y high29; GFX8-32BANK-NEXT: v_interp_p2_f16 v1, v2, attr2.y, v130; GFX8-32BANK-NEXT: v_interp_p2_f16 v0, v2, attr2.y, v0 high31; GFX8-32BANK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 032; GFX8-32BANK-NEXT: v_add_f16_e32 v0, v1, v033; GFX8-32BANK-NEXT: ; return to shader part epilog34;35; GFX8-16BANK-LABEL: interp_f16:36; GFX8-16BANK: ; %bb.0: ; %main_body37; GFX8-16BANK-NEXT: s_mov_b32 m0, s238; GFX8-16BANK-NEXT: v_interp_mov_f32_e32 v0, p0, attr2.y39; GFX8-16BANK-NEXT: v_mov_b32_e32 v1, s040; GFX8-16BANK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 341; GFX8-16BANK-NEXT: v_interp_p1lv_f16 v2, v1, attr2.y, v042; GFX8-16BANK-NEXT: v_mov_b32_e32 v3, s143; GFX8-16BANK-NEXT: v_interp_p1lv_f16 v0, v1, attr2.y, v0 high44; GFX8-16BANK-NEXT: v_interp_p2_f16 v2, v3, attr2.y, v245; GFX8-16BANK-NEXT: v_interp_p2_f16 v0, v3, attr2.y, v0 high46; GFX8-16BANK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 047; GFX8-16BANK-NEXT: v_add_f16_e32 v0, v2, v048; GFX8-16BANK-NEXT: ; return to shader part epilog49main_body:50 %p1_0 = call float @llvm.amdgcn.interp.p1.f16(float %i, i32 1, i32 2, i1 0, i32 %m0)51 %p2_0 = call half @llvm.amdgcn.interp.p2.f16(float %p1_0, float %j, i32 1, i32 2, i1 0, i32 %m0)52 %p1_1 = call float @llvm.amdgcn.interp.p1.f16(float %i, i32 1, i32 2, i1 1, i32 %m0)53 %p2_1 = call half @llvm.amdgcn.interp.p2.f16(float %p1_1, float %j, i32 1, i32 2, i1 1, i32 %m0)54 %res = fadd half %p2_0, %p2_155 ret half %res56}57 58; check that m0 is setup correctly before the interp p1 instruction59define amdgpu_ps half @interp_p1_m0_setup(float inreg %i, float inreg %j, i32 inreg %m0) #0 {60; GFX9-32BANK-LABEL: interp_p1_m0_setup:61; GFX9-32BANK: ; %bb.0: ; %main_body62; GFX9-32BANK-NEXT: ;;#ASMSTART63; GFX9-32BANK-NEXT: s_mov_b32 m0, 064; GFX9-32BANK-NEXT: ;;#ASMEND65; GFX9-32BANK-NEXT: s_mov_b32 s3, m066; GFX9-32BANK-NEXT: v_mov_b32_e32 v0, s067; GFX9-32BANK-NEXT: s_mov_b32 m0, s268; GFX9-32BANK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 369; GFX9-32BANK-NEXT: v_interp_p1ll_f16 v0, v0, attr2.y70; GFX9-32BANK-NEXT: v_mov_b32_e32 v1, s171; GFX9-32BANK-NEXT: v_interp_p2_legacy_f16 v0, v1, attr2.y, v072; GFX9-32BANK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 073; GFX9-32BANK-NEXT: v_add_f16_e32 v0, s3, v074; GFX9-32BANK-NEXT: ; return to shader part epilog75;76; GFX8-32BANK-LABEL: interp_p1_m0_setup:77; GFX8-32BANK: ; %bb.0: ; %main_body78; GFX8-32BANK-NEXT: ;;#ASMSTART79; GFX8-32BANK-NEXT: s_mov_b32 m0, 080; GFX8-32BANK-NEXT: ;;#ASMEND81; GFX8-32BANK-NEXT: s_mov_b32 s3, m082; GFX8-32BANK-NEXT: v_mov_b32_e32 v0, s083; GFX8-32BANK-NEXT: s_mov_b32 m0, s284; GFX8-32BANK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 385; GFX8-32BANK-NEXT: v_interp_p1ll_f16 v0, v0, attr2.y86; GFX8-32BANK-NEXT: v_mov_b32_e32 v1, s187; GFX8-32BANK-NEXT: v_interp_p2_f16 v0, v1, attr2.y, v088; GFX8-32BANK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 089; GFX8-32BANK-NEXT: v_add_f16_e32 v0, s3, v090; GFX8-32BANK-NEXT: ; return to shader part epilog91;92; GFX8-16BANK-LABEL: interp_p1_m0_setup:93; GFX8-16BANK: ; %bb.0: ; %main_body94; GFX8-16BANK-NEXT: ;;#ASMSTART95; GFX8-16BANK-NEXT: s_mov_b32 m0, 096; GFX8-16BANK-NEXT: ;;#ASMEND97; GFX8-16BANK-NEXT: s_mov_b32 s3, m098; GFX8-16BANK-NEXT: s_mov_b32 m0, s299; GFX8-16BANK-NEXT: v_interp_mov_f32_e32 v0, p0, attr2.y100; GFX8-16BANK-NEXT: v_mov_b32_e32 v1, s0101; GFX8-16BANK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 3102; GFX8-16BANK-NEXT: v_interp_p1lv_f16 v0, v1, attr2.y, v0103; GFX8-16BANK-NEXT: v_mov_b32_e32 v1, s1104; GFX8-16BANK-NEXT: v_interp_p2_f16 v0, v1, attr2.y, v0105; GFX8-16BANK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0106; GFX8-16BANK-NEXT: v_add_f16_e32 v0, s3, v0107; GFX8-16BANK-NEXT: ; return to shader part epilog108main_body:109 %mx = call i32 asm sideeffect "s_mov_b32 m0, 0", "={m0}"() #0110 %p1_0 = call float @llvm.amdgcn.interp.p1.f16(float %i, i32 1, i32 2, i1 0, i32 %m0)111 %p2_0 = call half @llvm.amdgcn.interp.p2.f16(float %p1_0, float %j, i32 1, i32 2, i1 0, i32 %m0)112 %my = trunc i32 %mx to i16113 %mh = bitcast i16 %my to half114 %res = fadd half %p2_0, %mh115 ret half %res116}117 118; check that m0 is setup correctly before the interp p2 instruction119define amdgpu_ps half @interp_p2_m0_setup(float inreg %i, float inreg %j, i32 inreg %m0) #0 {120; GFX9-32BANK-LABEL: interp_p2_m0_setup:121; GFX9-32BANK: ; %bb.0: ; %main_body122; GFX9-32BANK-NEXT: s_mov_b32 m0, s2123; GFX9-32BANK-NEXT: v_mov_b32_e32 v0, s0124; GFX9-32BANK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 3125; GFX9-32BANK-NEXT: v_interp_p1ll_f16 v0, v0, attr2.y126; GFX9-32BANK-NEXT: ;;#ASMSTART127; GFX9-32BANK-NEXT: s_mov_b32 m0, 0128; GFX9-32BANK-NEXT: ;;#ASMEND129; GFX9-32BANK-NEXT: s_mov_b32 s0, m0130; GFX9-32BANK-NEXT: v_mov_b32_e32 v1, s1131; GFX9-32BANK-NEXT: s_mov_b32 m0, s2132; GFX9-32BANK-NEXT: v_interp_p2_legacy_f16 v0, v1, attr2.y, v0133; GFX9-32BANK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0134; GFX9-32BANK-NEXT: v_add_f16_e32 v0, s0, v0135; GFX9-32BANK-NEXT: ; return to shader part epilog136;137; GFX8-32BANK-LABEL: interp_p2_m0_setup:138; GFX8-32BANK: ; %bb.0: ; %main_body139; GFX8-32BANK-NEXT: s_mov_b32 m0, s2140; GFX8-32BANK-NEXT: v_mov_b32_e32 v0, s0141; GFX8-32BANK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 3142; GFX8-32BANK-NEXT: v_interp_p1ll_f16 v0, v0, attr2.y143; GFX8-32BANK-NEXT: ;;#ASMSTART144; GFX8-32BANK-NEXT: s_mov_b32 m0, 0145; GFX8-32BANK-NEXT: ;;#ASMEND146; GFX8-32BANK-NEXT: s_mov_b32 s0, m0147; GFX8-32BANK-NEXT: v_mov_b32_e32 v1, s1148; GFX8-32BANK-NEXT: s_mov_b32 m0, s2149; GFX8-32BANK-NEXT: v_interp_p2_f16 v0, v1, attr2.y, v0150; GFX8-32BANK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0151; GFX8-32BANK-NEXT: v_add_f16_e32 v0, s0, v0152; GFX8-32BANK-NEXT: ; return to shader part epilog153;154; GFX8-16BANK-LABEL: interp_p2_m0_setup:155; GFX8-16BANK: ; %bb.0: ; %main_body156; GFX8-16BANK-NEXT: s_mov_b32 m0, s2157; GFX8-16BANK-NEXT: v_interp_mov_f32_e32 v0, p0, attr2.y158; GFX8-16BANK-NEXT: v_mov_b32_e32 v1, s0159; GFX8-16BANK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 3160; GFX8-16BANK-NEXT: v_interp_p1lv_f16 v0, v1, attr2.y, v0161; GFX8-16BANK-NEXT: ;;#ASMSTART162; GFX8-16BANK-NEXT: s_mov_b32 m0, 0163; GFX8-16BANK-NEXT: ;;#ASMEND164; GFX8-16BANK-NEXT: s_mov_b32 s0, m0165; GFX8-16BANK-NEXT: v_mov_b32_e32 v1, s1166; GFX8-16BANK-NEXT: s_mov_b32 m0, s2167; GFX8-16BANK-NEXT: v_interp_p2_f16 v0, v1, attr2.y, v0168; GFX8-16BANK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0169; GFX8-16BANK-NEXT: v_add_f16_e32 v0, s0, v0170; GFX8-16BANK-NEXT: ; return to shader part epilog171main_body:172 %p1_0 = call float @llvm.amdgcn.interp.p1.f16(float %i, i32 1, i32 2, i1 0, i32 %m0)173 %mx = call i32 asm sideeffect "s_mov_b32 m0, 0", "={m0}"() #0174 %p2_0 = call half @llvm.amdgcn.interp.p2.f16(float %p1_0, float %j, i32 1, i32 2, i1 0, i32 %m0)175 %my = trunc i32 %mx to i16176 %mh = bitcast i16 %my to half177 %res = fadd half %p2_0, %mh178 ret half %res179}180 181; float @llvm.amdgcn.interp.p1.f16(i, attrchan, attr, high, m0)182declare float @llvm.amdgcn.interp.p1.f16(float, i32, i32, i1, i32) #0183; half @llvm.amdgcn.interp.p1.f16(p1, j, attrchan, attr, high, m0)184declare half @llvm.amdgcn.interp.p2.f16(float, float, i32, i32, i1, i32) #0185declare float @llvm.amdgcn.interp.mov(i32, i32, i32, i32) #0186 187attributes #0 = { nounwind readnone }188