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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s3; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s4; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-TRUE16 %s5; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-FAKE16 %s6 7define amdgpu_ps void @v_interp_f32(float inreg %i, float inreg %j, i32 inreg %m0) #0 {8; GFX11-LABEL: v_interp_f32:9; GFX11: ; %bb.0: ; %main_body10; GFX11-NEXT: s_mov_b32 s3, exec_lo11; GFX11-NEXT: s_wqm_b32 exec_lo, exec_lo12; GFX11-NEXT: s_mov_b32 m0, s213; GFX11-NEXT: lds_param_load v0, attr0.y wait_vdst:1514; GFX11-NEXT: lds_param_load v1, attr1.x wait_vdst:1515; GFX11-NEXT: s_mov_b32 exec_lo, s316; GFX11-NEXT: v_mov_b32_e32 v2, s017; GFX11-NEXT: v_mov_b32_e32 v4, s118; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)19; GFX11-NEXT: v_interp_p10_f32 v3, v0, v2, v0 wait_exp:120; GFX11-NEXT: v_interp_p10_f32 v2, v1, v2, v1 wait_exp:021; GFX11-NEXT: v_interp_p2_f32 v5, v0, v4, v3 wait_exp:722; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)23; GFX11-NEXT: v_interp_p2_f32 v4, v1, v4, v5 wait_exp:724; GFX11-NEXT: exp mrt0 v3, v2, v5, v4 done25; GFX11-NEXT: s_endpgm26;27; GFX12-LABEL: v_interp_f32:28; GFX12: ; %bb.0: ; %main_body29; GFX12-NEXT: s_mov_b32 s3, exec_lo30; GFX12-NEXT: s_wqm_b32 exec_lo, exec_lo31; GFX12-NEXT: s_mov_b32 m0, s232; GFX12-NEXT: ds_param_load v0, attr0.y wait_va_vdst:15 wait_vm_vsrc:133; GFX12-NEXT: ds_param_load v1, attr1.x wait_va_vdst:15 wait_vm_vsrc:134; GFX12-NEXT: s_mov_b32 exec_lo, s335; GFX12-NEXT: v_mov_b32_e32 v2, s036; GFX12-NEXT: v_mov_b32_e32 v4, s137; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)38; GFX12-NEXT: v_interp_p10_f32 v3, v0, v2, v0 wait_exp:139; GFX12-NEXT: v_interp_p10_f32 v2, v1, v2, v1 wait_exp:040; GFX12-NEXT: v_interp_p2_f32 v5, v0, v4, v3 wait_exp:741; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)42; GFX12-NEXT: v_interp_p2_f32 v4, v1, v4, v5 wait_exp:743; GFX12-NEXT: export mrt0 v3, v2, v5, v4 done44; GFX12-NEXT: s_endpgm45main_body:46 %p0 = call float @llvm.amdgcn.lds.param.load(i32 1, i32 0, i32 %m0)47 %p1 = call float @llvm.amdgcn.lds.param.load(i32 0, i32 1, i32 %m0)48 %p0_0 = call float @llvm.amdgcn.interp.inreg.p10(float %p0, float %i, float %p0)49 %p1_0 = call float @llvm.amdgcn.interp.inreg.p2(float %p0, float %j, float %p0_0)50 %p0_1 = call float @llvm.amdgcn.interp.inreg.p10(float %p1, float %i, float %p1)51 %p1_1 = call float @llvm.amdgcn.interp.inreg.p2(float %p1, float %j, float %p1_0)52 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %p0_0, float %p0_1, float %p1_0, float %p1_1, i1 true, i1 true) #053 ret void54}55 56define amdgpu_ps void @v_interp_f32_many(float inreg %i, float inreg %j, i32 inreg %m0) #0 {57; GFX11-LABEL: v_interp_f32_many:58; GFX11: ; %bb.0: ; %main_body59; GFX11-NEXT: s_mov_b32 s3, exec_lo60; GFX11-NEXT: s_wqm_b32 exec_lo, exec_lo61; GFX11-NEXT: s_mov_b32 m0, s262; GFX11-NEXT: lds_param_load v0, attr0.x wait_vdst:1563; GFX11-NEXT: lds_param_load v1, attr1.x wait_vdst:1564; GFX11-NEXT: lds_param_load v2, attr2.x wait_vdst:1565; GFX11-NEXT: lds_param_load v3, attr3.x wait_vdst:1566; GFX11-NEXT: s_mov_b32 exec_lo, s367; GFX11-NEXT: v_dual_mov_b32 v4, s0 :: v_dual_mov_b32 v5, s168; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)69; GFX11-NEXT: v_interp_p10_f32 v6, v0, v4, v0 wait_exp:370; GFX11-NEXT: v_interp_p10_f32 v7, v1, v4, v1 wait_exp:271; GFX11-NEXT: v_interp_p10_f32 v8, v2, v4, v2 wait_exp:172; GFX11-NEXT: v_interp_p10_f32 v4, v3, v4, v3 wait_exp:073; GFX11-NEXT: v_interp_p2_f32 v6, v0, v5, v6 wait_exp:774; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)75; GFX11-NEXT: v_interp_p2_f32 v7, v1, v5, v7 wait_exp:776; GFX11-NEXT: v_interp_p2_f32 v8, v2, v5, v8 wait_exp:777; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)78; GFX11-NEXT: v_interp_p2_f32 v4, v3, v5, v4 wait_exp:779; GFX11-NEXT: exp mrt0 v6, v7, v8, v4 done80; GFX11-NEXT: s_endpgm81;82; GFX12-LABEL: v_interp_f32_many:83; GFX12: ; %bb.0: ; %main_body84; GFX12-NEXT: s_mov_b32 s3, exec_lo85; GFX12-NEXT: s_wqm_b32 exec_lo, exec_lo86; GFX12-NEXT: s_mov_b32 m0, s287; GFX12-NEXT: ds_param_load v0, attr0.x wait_va_vdst:15 wait_vm_vsrc:188; GFX12-NEXT: ds_param_load v1, attr1.x wait_va_vdst:15 wait_vm_vsrc:189; GFX12-NEXT: ds_param_load v2, attr2.x wait_va_vdst:15 wait_vm_vsrc:190; GFX12-NEXT: ds_param_load v3, attr3.x wait_va_vdst:15 wait_vm_vsrc:191; GFX12-NEXT: s_mov_b32 exec_lo, s392; GFX12-NEXT: v_dual_mov_b32 v4, s0 :: v_dual_mov_b32 v5, s193; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)94; GFX12-NEXT: v_interp_p10_f32 v6, v0, v4, v0 wait_exp:395; GFX12-NEXT: v_interp_p10_f32 v7, v1, v4, v1 wait_exp:296; GFX12-NEXT: v_interp_p10_f32 v8, v2, v4, v2 wait_exp:197; GFX12-NEXT: v_interp_p10_f32 v4, v3, v4, v3 wait_exp:098; GFX12-NEXT: v_interp_p2_f32 v6, v0, v5, v6 wait_exp:799; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)100; GFX12-NEXT: v_interp_p2_f32 v7, v1, v5, v7 wait_exp:7101; GFX12-NEXT: v_interp_p2_f32 v8, v2, v5, v8 wait_exp:7102; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_4)103; GFX12-NEXT: v_interp_p2_f32 v4, v3, v5, v4 wait_exp:7104; GFX12-NEXT: export mrt0 v6, v7, v8, v4 done105; GFX12-NEXT: s_endpgm106main_body:107 %p0 = call float @llvm.amdgcn.lds.param.load(i32 0, i32 0, i32 %m0)108 %p1 = call float @llvm.amdgcn.lds.param.load(i32 0, i32 1, i32 %m0)109 %p2 = call float @llvm.amdgcn.lds.param.load(i32 0, i32 2, i32 %m0)110 %p3 = call float @llvm.amdgcn.lds.param.load(i32 0, i32 3, i32 %m0)111 %p0_0 = call float @llvm.amdgcn.interp.inreg.p10(float %p0, float %i, float %p0)112 %p0_1 = call float @llvm.amdgcn.interp.inreg.p2(float %p0, float %j, float %p0_0)113 %p1_0 = call float @llvm.amdgcn.interp.inreg.p10(float %p1, float %i, float %p1)114 %p1_1 = call float @llvm.amdgcn.interp.inreg.p2(float %p1, float %j, float %p1_0)115 %p2_0 = call float @llvm.amdgcn.interp.inreg.p10(float %p2, float %i, float %p2)116 %p2_1 = call float @llvm.amdgcn.interp.inreg.p2(float %p2, float %j, float %p2_0)117 %p3_0 = call float @llvm.amdgcn.interp.inreg.p10(float %p3, float %i, float %p3)118 %p3_1 = call float @llvm.amdgcn.interp.inreg.p2(float %p3, float %j, float %p3_0)119 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %p0_1, float %p1_1, float %p2_1, float %p3_1, i1 true, i1 true) #0120 ret void121}122 123define amdgpu_ps void @v_interp_f32_many_vm(ptr addrspace(1) %ptr, i32 inreg %m0) #0 {124; GFX11-LABEL: v_interp_f32_many_vm:125; GFX11: ; %bb.0: ; %main_body126; GFX11-NEXT: global_load_b64 v[0:1], v[0:1], off offset:4127; GFX11-NEXT: s_mov_b32 m0, s0128; GFX11-NEXT: s_mov_b32 s0, exec_lo129; GFX11-NEXT: s_wqm_b32 exec_lo, exec_lo130; GFX11-NEXT: lds_param_load v2, attr0.x wait_vdst:15131; GFX11-NEXT: lds_param_load v3, attr1.x wait_vdst:15132; GFX11-NEXT: lds_param_load v4, attr2.x wait_vdst:15133; GFX11-NEXT: lds_param_load v5, attr3.x wait_vdst:15134; GFX11-NEXT: s_mov_b32 exec_lo, s0135; GFX11-NEXT: s_waitcnt vmcnt(0)136; GFX11-NEXT: v_interp_p10_f32 v6, v2, v0, v2 wait_exp:3137; GFX11-NEXT: v_interp_p10_f32 v7, v3, v0, v3 wait_exp:2138; GFX11-NEXT: v_interp_p10_f32 v8, v4, v0, v4 wait_exp:1139; GFX11-NEXT: v_interp_p10_f32 v0, v5, v0, v5 wait_exp:0140; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)141; GFX11-NEXT: v_interp_p2_f32 v6, v2, v1, v6 wait_exp:7142; GFX11-NEXT: v_interp_p2_f32 v7, v3, v1, v7 wait_exp:7143; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)144; GFX11-NEXT: v_interp_p2_f32 v8, v4, v1, v8 wait_exp:7145; GFX11-NEXT: v_interp_p2_f32 v0, v5, v1, v0 wait_exp:7146; GFX11-NEXT: exp mrt0 v6, v7, v8, v0 done147; GFX11-NEXT: s_endpgm148;149; GFX12-LABEL: v_interp_f32_many_vm:150; GFX12: ; %bb.0: ; %main_body151; GFX12-NEXT: global_load_b64 v[0:1], v[0:1], off offset:4152; GFX12-NEXT: s_mov_b32 m0, s0153; GFX12-NEXT: s_mov_b32 s0, exec_lo154; GFX12-NEXT: s_wqm_b32 exec_lo, exec_lo155; GFX12-NEXT: ds_param_load v2, attr0.x wait_va_vdst:15 wait_vm_vsrc:1156; GFX12-NEXT: ds_param_load v3, attr1.x wait_va_vdst:15 wait_vm_vsrc:1157; GFX12-NEXT: ds_param_load v4, attr2.x wait_va_vdst:15 wait_vm_vsrc:1158; GFX12-NEXT: ds_param_load v5, attr3.x wait_va_vdst:15 wait_vm_vsrc:1159; GFX12-NEXT: s_mov_b32 exec_lo, s0160; GFX12-NEXT: s_wait_loadcnt 0x0161; GFX12-NEXT: v_interp_p10_f32 v6, v2, v0, v2 wait_exp:3162; GFX12-NEXT: v_interp_p10_f32 v7, v3, v0, v3 wait_exp:2163; GFX12-NEXT: v_interp_p10_f32 v8, v4, v0, v4 wait_exp:1164; GFX12-NEXT: v_interp_p10_f32 v0, v5, v0, v5 wait_exp:0165; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)166; GFX12-NEXT: v_interp_p2_f32 v6, v2, v1, v6 wait_exp:7167; GFX12-NEXT: v_interp_p2_f32 v7, v3, v1, v7 wait_exp:7168; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)169; GFX12-NEXT: v_interp_p2_f32 v8, v4, v1, v8 wait_exp:7170; GFX12-NEXT: v_interp_p2_f32 v0, v5, v1, v0 wait_exp:7171; GFX12-NEXT: export mrt0 v6, v7, v8, v0 done172; GFX12-NEXT: s_endpgm173main_body:174 %i.ptr = getelementptr float, ptr addrspace(1) %ptr, i32 1175 %i = load float, ptr addrspace(1) %i.ptr, align 4176 %j.ptr = getelementptr float, ptr addrspace(1) %ptr, i32 2177 %j = load float, ptr addrspace(1) %j.ptr, align 4178 %p0 = call float @llvm.amdgcn.lds.param.load(i32 0, i32 0, i32 %m0)179 %p1 = call float @llvm.amdgcn.lds.param.load(i32 0, i32 1, i32 %m0)180 %p2 = call float @llvm.amdgcn.lds.param.load(i32 0, i32 2, i32 %m0)181 %p3 = call float @llvm.amdgcn.lds.param.load(i32 0, i32 3, i32 %m0)182 %p0_0 = call float @llvm.amdgcn.interp.inreg.p10(float %p0, float %i, float %p0)183 %p0_1 = call float @llvm.amdgcn.interp.inreg.p2(float %p0, float %j, float %p0_0)184 %p1_0 = call float @llvm.amdgcn.interp.inreg.p10(float %p1, float %i, float %p1)185 %p1_1 = call float @llvm.amdgcn.interp.inreg.p2(float %p1, float %j, float %p1_0)186 %p2_0 = call float @llvm.amdgcn.interp.inreg.p10(float %p2, float %i, float %p2)187 %p2_1 = call float @llvm.amdgcn.interp.inreg.p2(float %p2, float %j, float %p2_0)188 %p3_0 = call float @llvm.amdgcn.interp.inreg.p10(float %p3, float %i, float %p3)189 %p3_1 = call float @llvm.amdgcn.interp.inreg.p2(float %p3, float %j, float %p3_0)190 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %p0_1, float %p1_1, float %p2_1, float %p3_1, i1 true, i1 true) #0191 ret void192}193 194define amdgpu_ps half @v_interp_f16(float inreg %i, float inreg %j, i32 inreg %m0) #0 {195; GFX11-TRUE16-LABEL: v_interp_f16:196; GFX11-TRUE16: ; %bb.0: ; %main_body197; GFX11-TRUE16-NEXT: s_mov_b32 s3, exec_lo198; GFX11-TRUE16-NEXT: s_wqm_b32 exec_lo, exec_lo199; GFX11-TRUE16-NEXT: s_mov_b32 m0, s2200; GFX11-TRUE16-NEXT: lds_param_load v1, attr0.x wait_vdst:15201; GFX11-TRUE16-NEXT: s_mov_b32 exec_lo, s3202; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, s0203; GFX11-TRUE16-NEXT: v_mov_b32_e32 v2, s1204; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)205; GFX11-TRUE16-NEXT: v_interp_p10_f16_f32 v3, v1.l, v0, v1.l wait_exp:0206; GFX11-TRUE16-NEXT: v_interp_p10_f16_f32 v4, v1.h, v0, v1.h wait_exp:7207; GFX11-TRUE16-NEXT: v_interp_p2_f16_f32 v0.l, v1.l, v2, v3 wait_exp:7208; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)209; GFX11-TRUE16-NEXT: v_interp_p2_f16_f32 v0.h, v1.h, v2, v4 wait_exp:7210; GFX11-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h211; GFX11-TRUE16-NEXT: ; return to shader part epilog212;213; GFX11-FAKE16-LABEL: v_interp_f16:214; GFX11-FAKE16: ; %bb.0: ; %main_body215; GFX11-FAKE16-NEXT: s_mov_b32 s3, exec_lo216; GFX11-FAKE16-NEXT: s_wqm_b32 exec_lo, exec_lo217; GFX11-FAKE16-NEXT: s_mov_b32 m0, s2218; GFX11-FAKE16-NEXT: lds_param_load v1, attr0.x wait_vdst:15219; GFX11-FAKE16-NEXT: s_mov_b32 exec_lo, s3220; GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, s0221; GFX11-FAKE16-NEXT: v_mov_b32_e32 v2, s1222; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)223; GFX11-FAKE16-NEXT: v_interp_p10_f16_f32 v3, v1, v0, v1 wait_exp:0224; GFX11-FAKE16-NEXT: v_interp_p10_f16_f32 v0, v1, v0, v1 op_sel:[1,0,1,0] wait_exp:7225; GFX11-FAKE16-NEXT: v_interp_p2_f16_f32 v3, v1, v2, v3 wait_exp:7226; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)227; GFX11-FAKE16-NEXT: v_interp_p2_f16_f32 v0, v1, v2, v0 op_sel:[1,0,0,0] wait_exp:7228; GFX11-FAKE16-NEXT: v_add_f16_e32 v0, v3, v0229; GFX11-FAKE16-NEXT: ; return to shader part epilog230;231; GFX12-TRUE16-LABEL: v_interp_f16:232; GFX12-TRUE16: ; %bb.0: ; %main_body233; GFX12-TRUE16-NEXT: s_mov_b32 s3, exec_lo234; GFX12-TRUE16-NEXT: s_wqm_b32 exec_lo, exec_lo235; GFX12-TRUE16-NEXT: s_mov_b32 m0, s2236; GFX12-TRUE16-NEXT: ds_param_load v1, attr0.x wait_va_vdst:15 wait_vm_vsrc:1237; GFX12-TRUE16-NEXT: s_mov_b32 exec_lo, s3238; GFX12-TRUE16-NEXT: v_mov_b32_e32 v0, s0239; GFX12-TRUE16-NEXT: v_mov_b32_e32 v2, s1240; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)241; GFX12-TRUE16-NEXT: v_interp_p10_f16_f32 v3, v1.l, v0, v1.l wait_exp:0242; GFX12-TRUE16-NEXT: v_interp_p10_f16_f32 v4, v1.h, v0, v1.h wait_exp:7243; GFX12-TRUE16-NEXT: v_interp_p2_f16_f32 v0.l, v1.l, v2, v3 wait_exp:7244; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)245; GFX12-TRUE16-NEXT: v_interp_p2_f16_f32 v0.h, v1.h, v2, v4 wait_exp:7246; GFX12-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h247; GFX12-TRUE16-NEXT: ; return to shader part epilog248;249; GFX12-FAKE16-LABEL: v_interp_f16:250; GFX12-FAKE16: ; %bb.0: ; %main_body251; GFX12-FAKE16-NEXT: s_mov_b32 s3, exec_lo252; GFX12-FAKE16-NEXT: s_wqm_b32 exec_lo, exec_lo253; GFX12-FAKE16-NEXT: s_mov_b32 m0, s2254; GFX12-FAKE16-NEXT: ds_param_load v1, attr0.x wait_va_vdst:15 wait_vm_vsrc:1255; GFX12-FAKE16-NEXT: s_mov_b32 exec_lo, s3256; GFX12-FAKE16-NEXT: v_mov_b32_e32 v0, s0257; GFX12-FAKE16-NEXT: v_mov_b32_e32 v2, s1258; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)259; GFX12-FAKE16-NEXT: v_interp_p10_f16_f32 v3, v1, v0, v1 wait_exp:0260; GFX12-FAKE16-NEXT: v_interp_p10_f16_f32 v0, v1, v0, v1 op_sel:[1,0,1,0] wait_exp:7261; GFX12-FAKE16-NEXT: v_interp_p2_f16_f32 v3, v1, v2, v3 wait_exp:7262; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)263; GFX12-FAKE16-NEXT: v_interp_p2_f16_f32 v0, v1, v2, v0 op_sel:[1,0,0,0] wait_exp:7264; GFX12-FAKE16-NEXT: v_add_f16_e32 v0, v3, v0265; GFX12-FAKE16-NEXT: ; return to shader part epilog266main_body:267 %p0 = call float @llvm.amdgcn.lds.param.load(i32 0, i32 0, i32 %m0)268 %l_p0 = call float @llvm.amdgcn.interp.inreg.p10.f16(float %p0, float %i, float %p0, i1 0)269 %l_p1 = call half @llvm.amdgcn.interp.inreg.p2.f16(float %p0, float %j, float %l_p0, i1 0)270 %h_p0 = call float @llvm.amdgcn.interp.inreg.p10.f16(float %p0, float %i, float %p0, i1 1)271 %h_p1 = call half @llvm.amdgcn.interp.inreg.p2.f16(float %p0, float %j, float %h_p0, i1 1)272 %res = fadd half %l_p1, %h_p1273 ret half %res274}275 276define amdgpu_ps half @v_interp_rtz_f16(float inreg %i, float inreg %j, i32 inreg %m0) #0 {277; GFX11-TRUE16-LABEL: v_interp_rtz_f16:278; GFX11-TRUE16: ; %bb.0: ; %main_body279; GFX11-TRUE16-NEXT: s_mov_b32 s3, exec_lo280; GFX11-TRUE16-NEXT: s_wqm_b32 exec_lo, exec_lo281; GFX11-TRUE16-NEXT: s_mov_b32 m0, s2282; GFX11-TRUE16-NEXT: lds_param_load v1, attr0.x wait_vdst:15283; GFX11-TRUE16-NEXT: s_mov_b32 exec_lo, s3284; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, s0285; GFX11-TRUE16-NEXT: v_mov_b32_e32 v2, s1286; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)287; GFX11-TRUE16-NEXT: v_interp_p10_rtz_f16_f32 v3, v1.l, v0, v1.l wait_exp:0288; GFX11-TRUE16-NEXT: v_interp_p10_rtz_f16_f32 v4, v1.h, v0, v1.h wait_exp:7289; GFX11-TRUE16-NEXT: v_interp_p2_rtz_f16_f32 v0.l, v1.l, v2, v3 wait_exp:7290; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)291; GFX11-TRUE16-NEXT: v_interp_p2_rtz_f16_f32 v0.h, v1.h, v2, v4 wait_exp:7292; GFX11-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h293; GFX11-TRUE16-NEXT: ; return to shader part epilog294;295; GFX11-FAKE16-LABEL: v_interp_rtz_f16:296; GFX11-FAKE16: ; %bb.0: ; %main_body297; GFX11-FAKE16-NEXT: s_mov_b32 s3, exec_lo298; GFX11-FAKE16-NEXT: s_wqm_b32 exec_lo, exec_lo299; GFX11-FAKE16-NEXT: s_mov_b32 m0, s2300; GFX11-FAKE16-NEXT: lds_param_load v1, attr0.x wait_vdst:15301; GFX11-FAKE16-NEXT: s_mov_b32 exec_lo, s3302; GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, s0303; GFX11-FAKE16-NEXT: v_mov_b32_e32 v2, s1304; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)305; GFX11-FAKE16-NEXT: v_interp_p10_rtz_f16_f32 v3, v1, v0, v1 wait_exp:0306; GFX11-FAKE16-NEXT: v_interp_p10_rtz_f16_f32 v0, v1, v0, v1 op_sel:[1,0,1,0] wait_exp:7307; GFX11-FAKE16-NEXT: v_interp_p2_rtz_f16_f32 v3, v1, v2, v3 wait_exp:7308; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)309; GFX11-FAKE16-NEXT: v_interp_p2_rtz_f16_f32 v0, v1, v2, v0 op_sel:[1,0,0,0] wait_exp:7310; GFX11-FAKE16-NEXT: v_add_f16_e32 v0, v3, v0311; GFX11-FAKE16-NEXT: ; return to shader part epilog312;313; GFX12-TRUE16-LABEL: v_interp_rtz_f16:314; GFX12-TRUE16: ; %bb.0: ; %main_body315; GFX12-TRUE16-NEXT: s_mov_b32 s3, exec_lo316; GFX12-TRUE16-NEXT: s_wqm_b32 exec_lo, exec_lo317; GFX12-TRUE16-NEXT: s_mov_b32 m0, s2318; GFX12-TRUE16-NEXT: ds_param_load v1, attr0.x wait_va_vdst:15 wait_vm_vsrc:1319; GFX12-TRUE16-NEXT: s_mov_b32 exec_lo, s3320; GFX12-TRUE16-NEXT: v_mov_b32_e32 v0, s0321; GFX12-TRUE16-NEXT: v_mov_b32_e32 v2, s1322; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)323; GFX12-TRUE16-NEXT: v_interp_p10_rtz_f16_f32 v3, v1.l, v0, v1.l wait_exp:0324; GFX12-TRUE16-NEXT: v_interp_p10_rtz_f16_f32 v4, v1.h, v0, v1.h wait_exp:7325; GFX12-TRUE16-NEXT: v_interp_p2_rtz_f16_f32 v0.l, v1.l, v2, v3 wait_exp:7326; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)327; GFX12-TRUE16-NEXT: v_interp_p2_rtz_f16_f32 v0.h, v1.h, v2, v4 wait_exp:7328; GFX12-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h329; GFX12-TRUE16-NEXT: ; return to shader part epilog330;331; GFX12-FAKE16-LABEL: v_interp_rtz_f16:332; GFX12-FAKE16: ; %bb.0: ; %main_body333; GFX12-FAKE16-NEXT: s_mov_b32 s3, exec_lo334; GFX12-FAKE16-NEXT: s_wqm_b32 exec_lo, exec_lo335; GFX12-FAKE16-NEXT: s_mov_b32 m0, s2336; GFX12-FAKE16-NEXT: ds_param_load v1, attr0.x wait_va_vdst:15 wait_vm_vsrc:1337; GFX12-FAKE16-NEXT: s_mov_b32 exec_lo, s3338; GFX12-FAKE16-NEXT: v_mov_b32_e32 v0, s0339; GFX12-FAKE16-NEXT: v_mov_b32_e32 v2, s1340; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)341; GFX12-FAKE16-NEXT: v_interp_p10_rtz_f16_f32 v3, v1, v0, v1 wait_exp:0342; GFX12-FAKE16-NEXT: v_interp_p10_rtz_f16_f32 v0, v1, v0, v1 op_sel:[1,0,1,0] wait_exp:7343; GFX12-FAKE16-NEXT: v_interp_p2_rtz_f16_f32 v3, v1, v2, v3 wait_exp:7344; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)345; GFX12-FAKE16-NEXT: v_interp_p2_rtz_f16_f32 v0, v1, v2, v0 op_sel:[1,0,0,0] wait_exp:7346; GFX12-FAKE16-NEXT: v_add_f16_e32 v0, v3, v0347; GFX12-FAKE16-NEXT: ; return to shader part epilog348main_body:349 %p0 = call float @llvm.amdgcn.lds.param.load(i32 0, i32 0, i32 %m0)350 %l_p0 = call float @llvm.amdgcn.interp.p10.rtz.f16(float %p0, float %i, float %p0, i1 0)351 %l_p1 = call half @llvm.amdgcn.interp.p2.rtz.f16(float %p0, float %j, float %l_p0, i1 0)352 %h_p0 = call float @llvm.amdgcn.interp.p10.rtz.f16(float %p0, float %i, float %p0, i1 1)353 %h_p1 = call half @llvm.amdgcn.interp.p2.rtz.f16(float %p0, float %j, float %h_p0, i1 1)354 %res = fadd half %l_p1, %h_p1355 ret half %res356}357 358define amdgpu_ps half @v_interp_f16_imm_params(float inreg %i, float inreg %j) #0 {359; GFX11-TRUE16-LABEL: v_interp_f16_imm_params:360; GFX11-TRUE16: ; %bb.0: ; %main_body361; GFX11-TRUE16-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, s0362; GFX11-TRUE16-NEXT: v_mov_b32_e32 v3, s1363; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)364; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v1.l365; GFX11-TRUE16-NEXT: v_interp_p10_f16_f32 v2, v0.l, v2, v0.l wait_exp:7366; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)367; GFX11-TRUE16-NEXT: v_interp_p2_f16_f32 v0.l, v0.l, v3, v1 wait_exp:7368; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.h, v2369; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)370; GFX11-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.h, v0.l371; GFX11-TRUE16-NEXT: ; return to shader part epilog372;373; GFX11-FAKE16-LABEL: v_interp_f16_imm_params:374; GFX11-FAKE16: ; %bb.0: ; %main_body375; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0376; GFX11-FAKE16-NEXT: v_mov_b32_e32 v2, s1377; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)378; GFX11-FAKE16-NEXT: v_interp_p10_f16_f32 v1, v0, v1, v0 wait_exp:7379; GFX11-FAKE16-NEXT: v_interp_p2_f16_f32 v0, v0, v2, v0 wait_exp:7380; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)381; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v1, v1382; GFX11-FAKE16-NEXT: v_add_f16_e32 v0, v1, v0383; GFX11-FAKE16-NEXT: ; return to shader part epilog384;385; GFX12-TRUE16-LABEL: v_interp_f16_imm_params:386; GFX12-TRUE16: ; %bb.0: ; %main_body387; GFX12-TRUE16-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, s0388; GFX12-TRUE16-NEXT: v_mov_b32_e32 v3, s1389; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)390; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, v1.l391; GFX12-TRUE16-NEXT: v_interp_p10_f16_f32 v2, v0.l, v2, v0.l wait_exp:7392; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)393; GFX12-TRUE16-NEXT: v_interp_p2_f16_f32 v0.l, v0.l, v3, v1 wait_exp:7394; GFX12-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.h, v2395; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)396; GFX12-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.h, v0.l397; GFX12-TRUE16-NEXT: ; return to shader part epilog398;399; GFX12-FAKE16-LABEL: v_interp_f16_imm_params:400; GFX12-FAKE16: ; %bb.0: ; %main_body401; GFX12-FAKE16-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0402; GFX12-FAKE16-NEXT: v_mov_b32_e32 v2, s1403; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)404; GFX12-FAKE16-NEXT: v_interp_p10_f16_f32 v1, v0, v1, v0 wait_exp:7405; GFX12-FAKE16-NEXT: v_interp_p2_f16_f32 v0, v0, v2, v0 wait_exp:7406; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)407; GFX12-FAKE16-NEXT: v_cvt_f16_f32_e32 v1, v1408; GFX12-FAKE16-NEXT: v_add_f16_e32 v0, v1, v0409; GFX12-FAKE16-NEXT: ; return to shader part epilog410main_body:411 %l_p0 = call float @llvm.amdgcn.interp.inreg.p10.f16(float 0.0, float %i, float 0.0, i1 0)412 %l_p1 = call half @llvm.amdgcn.interp.inreg.p2.f16(float 0.0, float %j, float 0.0, i1 0)413 %h = fptrunc float %l_p0 to half414 %res = fadd half %h, %l_p1415 ret half %res416}417 418declare float @llvm.amdgcn.lds.param.load(i32, i32, i32) #1419declare float @llvm.amdgcn.interp.inreg.p10(float, float, float) #0420declare float @llvm.amdgcn.interp.inreg.p2(float, float, float) #0421declare float @llvm.amdgcn.interp.inreg.p10.f16(float, float, float, i1) #0422declare half @llvm.amdgcn.interp.inreg.p2.f16(float, float, float, i1) #0423declare float @llvm.amdgcn.interp.p10.rtz.f16(float, float, float, i1) #0424declare half @llvm.amdgcn.interp.p2.rtz.f16(float, float, float, i1) #0425declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #0426declare void @llvm.amdgcn.exp.f16(i32, i32, float, float, float, float, i1, i1) #0427 428attributes #0 = { nounwind }429attributes #1 = { nounwind readnone }430