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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 22; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -mattr=+wavefrontsize32 -global-isel=1 < %s | FileCheck -check-prefixes=GFX11,GISEL %s3; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -mattr=+wavefrontsize32 -global-isel=0 < %s | FileCheck -check-prefixes=GFX11,SDAG %s4 5; RUN: not llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64 -global-isel=1 < %s 2>&1 | FileCheck -check-prefix=GISEL-ERR %s6; RUN: not --crash llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64 -global-isel=0 < %s 2>&1 | FileCheck -check-prefix=SDAG-ERR %s7 8; GISEL-ERR: LLVM ERROR: cannot select: {{.*}} = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.inverse.ballot)9; SDAG-ERR: LLVM ERROR: Cannot select: intrinsic %llvm.amdgcn.inverse.ballot10 11declare i1 @llvm.amdgcn.inverse.ballot(i32)12 13; Test ballot(0)14define amdgpu_cs void @constant_false_inverse_ballot(ptr addrspace(1) %out) {15; GFX11-LABEL: constant_false_inverse_ballot:16; GFX11: ; %bb.0: ; %entry17; GFX11-NEXT: s_mov_b32 s0, 018; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 1, s019; GFX11-NEXT: global_store_b32 v[0:1], v2, off20; GFX11-NEXT: s_endpgm21entry:22 %ballot = call i1 @llvm.amdgcn.inverse.ballot(i32 0)23 %sel = select i1 %ballot, i32 1, i32 024 store i32 %sel, ptr addrspace(1) %out25 ret void26}27 28; Test ballot(1)29 30define amdgpu_cs void @constant_true_inverse_ballot(ptr addrspace(1) %out) {31; GFX11-LABEL: constant_true_inverse_ballot:32; GFX11: ; %bb.0: ; %entry33; GFX11-NEXT: s_mov_b32 s0, -134; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 1, s035; GFX11-NEXT: global_store_b32 v[0:1], v2, off36; GFX11-NEXT: s_endpgm37entry:38 %ballot = call i1 @llvm.amdgcn.inverse.ballot(i32 u0xFFFFFFFF)39 %sel = select i1 %ballot, i32 1, i32 040 store i32 %sel, ptr addrspace(1) %out41 ret void42}43 44define amdgpu_cs void @constant_mask_inverse_ballot(ptr addrspace(1) %out) {45; GFX11-LABEL: constant_mask_inverse_ballot:46; GFX11: ; %bb.0: ; %entry47; GFX11-NEXT: s_movk_i32 s0, 0x100048; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 1, s049; GFX11-NEXT: global_store_b32 v[0:1], v2, off50; GFX11-NEXT: s_endpgm51entry:52 %ballot = call i1 @llvm.amdgcn.inverse.ballot(i32 u0x00001000)53 %sel = select i1 %ballot, i32 1, i32 054 store i32 %sel, ptr addrspace(1) %out55 ret void56}57 58; Test inverse ballot using a vgpr as input59 60define amdgpu_cs void @vgpr_inverse_ballot(i32 %input, ptr addrspace(1) %out) {61; GFX11-LABEL: vgpr_inverse_ballot:62; GFX11: ; %bb.0: ; %entry63; GFX11-NEXT: v_readfirstlane_b32 s0, v064; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s065; GFX11-NEXT: global_store_b32 v[1:2], v0, off66; GFX11-NEXT: s_endpgm67entry:68 %ballot = call i1 @llvm.amdgcn.inverse.ballot(i32 %input)69 %sel = select i1 %ballot, i32 1, i32 070 store i32 %sel, ptr addrspace(1) %out71 ret void72}73 74define amdgpu_cs void @sgpr_inverse_ballot(i32 inreg %input, ptr addrspace(1) %out) {75; GFX11-LABEL: sgpr_inverse_ballot:76; GFX11: ; %bb.0: ; %entry77; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 1, s078; GFX11-NEXT: global_store_b32 v[0:1], v2, off79; GFX11-NEXT: s_endpgm80entry:81 %ballot = call i1 @llvm.amdgcn.inverse.ballot(i32 %input)82 %sel = select i1 %ballot, i32 1, i32 083 store i32 %sel, ptr addrspace(1) %out84 ret void85}86 87; Test ballot after phi88define amdgpu_cs void @phi_uniform(i32 inreg %s0_1, i32 inreg %s2, ptr addrspace(1) %out) {89; GFX11-LABEL: phi_uniform:90; GFX11: ; %bb.0: ; %entry91; GFX11-NEXT: s_cmp_lg_u32 s1, 092; GFX11-NEXT: s_cbranch_scc1 .LBB5_293; GFX11-NEXT: ; %bb.1: ; %if94; GFX11-NEXT: s_add_i32 s0, s0, 195; GFX11-NEXT: .LBB5_2: ; %endif96; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 1, s097; GFX11-NEXT: global_store_b32 v[0:1], v2, off98; GFX11-NEXT: s_endpgm99entry:100 %cc = icmp ne i32 %s2, 0101 br i1 %cc, label %endif, label %if102 103if:104 %tmp = add i32 %s0_1, 1105 br label %endif106 107endif:108 %input = phi i32 [ %s0_1, %entry ], [ %tmp, %if ]109 110 %ballot = call i1 @llvm.amdgcn.inverse.ballot(i32 %input)111 %sel = select i1 %ballot, i32 1, i32 0112 store i32 %sel, ptr addrspace(1) %out113 ret void114}115 116; Test for branching117; GISel implementation is currently incorrect.118; The change in the branch affects all lanes, not just the branching ones.119; This test will be fixed once GISel correctly takes uniformity analysis into account.120define amdgpu_cs void @inverse_ballot_branch(i32 inreg %s0_1, i32 inreg %s2, ptr addrspace(1) %out) {121; GISEL-LABEL: inverse_ballot_branch:122; GISEL: ; %bb.0: ; %entry123; GISEL-NEXT: s_xor_b32 s2, s1, -1124; GISEL-NEXT: s_and_saveexec_b32 s1, s2125; GISEL-NEXT: ; %bb.1: ; %if126; GISEL-NEXT: s_add_i32 s0, s0, 1127; GISEL-NEXT: ; %bb.2: ; %endif128; GISEL-NEXT: s_or_b32 exec_lo, exec_lo, s1129; GISEL-NEXT: v_mov_b32_e32 v2, s0130; GISEL-NEXT: global_store_b32 v[0:1], v2, off131; GISEL-NEXT: s_endpgm132;133; SDAG-LABEL: inverse_ballot_branch:134; SDAG: ; %bb.0: ; %entry135; SDAG-NEXT: v_mov_b32_e32 v2, s0136; SDAG-NEXT: s_xor_b32 s2, s1, -1137; SDAG-NEXT: s_and_saveexec_b32 s1, s2138; SDAG-NEXT: ; %bb.1: ; %if139; SDAG-NEXT: s_add_i32 s0, s0, 1140; SDAG-NEXT: v_mov_b32_e32 v2, s0141; SDAG-NEXT: ; %bb.2: ; %endif142; SDAG-NEXT: s_or_b32 exec_lo, exec_lo, s1143; SDAG-NEXT: global_store_b32 v[0:1], v2, off144; SDAG-NEXT: s_endpgm145entry:146 %ballot = call i1 @llvm.amdgcn.inverse.ballot(i32 %s2)147 br i1 %ballot, label %endif, label %if148 149if:150 %tmp = add i32 %s0_1, 1151 br label %endif152 153endif:154 %input = phi i32 [ %s0_1, %entry ], [ %tmp, %if ]155 store i32 %input, ptr addrspace(1) %out156 ret void157}158