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1; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri < %s | FileCheck -check-prefixes=CO-V4,HSA,ALL %s2; RUN: llc -mtriple=amdgcn-mesa-mesa3d < %s | FileCheck -check-prefixes=CO-V4,OS-MESA3D,ALL %s3; RUN: llc -mtriple=amdgcn-mesa-unknown < %s | FileCheck -check-prefixes=OS-UNKNOWN,ALL %s4 5; ALL-LABEL: {{^}}test:6; OS-MESA3D: enable_sgpr_kernarg_segment_ptr = 17; CO-V4: s_load_dword s{{[0-9]+}}, s[8:9], 0xa8 9; OS-UNKNOWN: s_load_dword s{{[0-9]+}}, s[4:5], 0xa10 11; HSA: .amdhsa_kernarg_size 812; HSA: .amdhsa_user_sgpr_kernarg_segment_ptr 113define amdgpu_kernel void @test(ptr addrspace(1) %out) #1 {14 %kernarg.segment.ptr = call noalias ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()15 %gep = getelementptr i32, ptr addrspace(4) %kernarg.segment.ptr, i64 1016 %value = load i32, ptr addrspace(4) %gep17 store i32 %value, ptr addrspace(1) %out18 ret void19}20 21; ALL-LABEL: {{^}}test_implicit:22; OS-MESA3D: kernarg_segment_byte_size = 2423; OS-MESA3D: kernarg_segment_alignment = 424 25; 10 + 9 (36 prepended implicit bytes) + 2(out pointer) = 21 = 0x1526; OS-UNKNOWN: s_load_dword s{{[0-9]+}}, s[4:5], 0x1527; HSA: .amdhsa_kernarg_size 828define amdgpu_kernel void @test_implicit(ptr addrspace(1) %out) #1 {29 %implicitarg.ptr = call noalias ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()30 %gep = getelementptr i32, ptr addrspace(4) %implicitarg.ptr, i64 1031 %value = load i32, ptr addrspace(4) %gep32 store i32 %value, ptr addrspace(1) %out33 ret void34}35 36; ALL-LABEL: {{^}}test_implicit_alignment:37; OS-MESA3D: kernarg_segment_byte_size = 2838; OS-MESA3D: kernarg_segment_alignment = 439 40; OS-UNKNOWN: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0xc41; HSA: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x442; OS-MESA3D: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x343; ALL: v_mov_b32_e32 [[V_VAL:v[0-9]+]], [[VAL]]44; MESA: buffer_store_dword [[V_VAL]]45; HSA: flat_store_dword v[{{[0-9]+:[0-9]+}}], [[V_VAL]]46 47; HSA: .amdhsa_kernarg_size 1248define amdgpu_kernel void @test_implicit_alignment(ptr addrspace(1) %out, <2 x i8> %in) #1 {49 %implicitarg.ptr = call noalias ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()50 %val = load i32, ptr addrspace(4) %implicitarg.ptr51 store i32 %val, ptr addrspace(1) %out52 ret void53}54 55; ALL-LABEL: {{^}}opencl_test_implicit_alignment56; OS-MESA3D: kernarg_segment_byte_size = 2857; OS-MESA3D: kernarg_segment_alignment = 458 59; OS-UNKNOWN: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0xc60; HSA: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x461; OS-MESA3D: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x362; ALL: v_mov_b32_e32 [[V_VAL:v[0-9]+]], [[VAL]]63; MESA: buffer_store_dword [[V_VAL]]64; HSA: flat_store_dword v[{{[0-9]+:[0-9]+}}], [[V_VAL]]65; HSA: .amdhsa_kernarg_size 6466define amdgpu_kernel void @opencl_test_implicit_alignment(ptr addrspace(1) %out, <2 x i8> %in) #2 {67 %implicitarg.ptr = call noalias ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()68 %val = load i32, ptr addrspace(4) %implicitarg.ptr69 store i32 %val, ptr addrspace(1) %out70 ret void71}72 73; ALL-LABEL: {{^}}test_no_kernargs:74; OS-MESA3D: enable_sgpr_kernarg_segment_ptr = 075; OS-MESA3D: kernarg_segment_byte_size = 076; OS-MESA3D: kernarg_segment_alignment = 477 78 79; HSA: .amdhsa_kernarg_size 080; HSA: .amdhsa_user_sgpr_kernarg_segment_ptr 081define amdgpu_kernel void @test_no_kernargs() #4 {82 %kernarg.segment.ptr = call noalias ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()83 %gep = getelementptr i32, ptr addrspace(4) %kernarg.segment.ptr, i64 1084 %value = load i32, ptr addrspace(4) %gep85 store volatile i32 %value, ptr addrspace(1) poison86 ret void87}88 89; ALL-LABEL: {{^}}opencl_test_implicit_alignment_no_explicit_kernargs:90; OS-MESA3D: kernarg_segment_byte_size = 1691; OS-MESA3D: kernarg_segment_alignment = 492; HSA: .amdhsa_kernarg_size 4893define amdgpu_kernel void @opencl_test_implicit_alignment_no_explicit_kernargs() #2 {94 %implicitarg.ptr = call noalias ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()95 %val = load volatile i32, ptr addrspace(4) %implicitarg.ptr96 store volatile i32 %val, ptr addrspace(1) null97 ret void98}99 100; ALL-LABEL: {{^}}opencl_test_implicit_alignment_no_explicit_kernargs_round_up:101; OS-MESA3D: kernarg_segment_byte_size = 16102; OS-MESA3D: kernarg_segment_alignment = 4103; HSA: .amdhsa_kernarg_size 40104define amdgpu_kernel void @opencl_test_implicit_alignment_no_explicit_kernargs_round_up() #3 {105 %implicitarg.ptr = call noalias ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()106 %val = load volatile i32, ptr addrspace(4) %implicitarg.ptr107 store volatile i32 %val, ptr addrspace(1) null108 ret void109}110 111; ALL-LABEL: {{^}}func_kernarg_segment_ptr:112; ALL: v_mov_b32_e32 v0, 0{{$}}113; ALL: v_mov_b32_e32 v1, 0{{$}}114define ptr addrspace(4) @func_kernarg_segment_ptr() {115 %ptr = call ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()116 ret ptr addrspace(4) %ptr117}118 119declare ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr() #0120declare ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr() #0121 122attributes #0 = { nounwind readnone }123attributes #1 = { nounwind "amdgpu-implicitarg-num-bytes"="0" }124attributes #2 = { nounwind "amdgpu-implicitarg-num-bytes"="48" }125attributes #3 = { nounwind "amdgpu-implicitarg-num-bytes"="38" }126attributes #4 = { nounwind "amdgpu-implicitarg-num-bytes"="0" "amdgpu-no-implicitarg-ptr" }127 128!llvm.module.flags = !{!0}129!0 = !{i32 1, !"amdhsa_code_object_version", i32 400}130