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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI %s3; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize64 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX10 %s4; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64 -amdgpu-enable-delay-alu=0 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX11-12,GFX11 %s5; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64 -amdgpu-enable-delay-alu=0 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX11-12,GFX12 %s6 7define amdgpu_gs void @gs_const() {8; SI-LABEL: gs_const:9; SI: ; %bb.0:10; SI-NEXT: s_mov_b64 s[0:1], exec11; SI-NEXT: s_andn2_b64 s[0:1], s[0:1], exec12; SI-NEXT: s_mov_b64 exec, 013; SI-NEXT: s_mov_b32 m0, 014; SI-NEXT: s_nop 015; SI-NEXT: s_sendmsg sendmsg(MSG_GS_DONE, GS_OP_NOP)16; SI-NEXT: s_endpgm17; SI-NEXT: ; %bb.1:18; SI-NEXT: s_mov_b64 exec, 019; SI-NEXT: s_endpgm20;21; GFX10-LABEL: gs_const:22; GFX10: ; %bb.0:23; GFX10-NEXT: s_mov_b64 s[0:1], exec24; GFX10-NEXT: s_andn2_b64 s[0:1], s[0:1], exec25; GFX10-NEXT: s_mov_b64 exec, 026; GFX10-NEXT: s_mov_b32 m0, 027; GFX10-NEXT: s_sendmsg sendmsg(MSG_GS_DONE, GS_OP_NOP)28; GFX10-NEXT: s_endpgm29; GFX10-NEXT: ; %bb.1:30; GFX10-NEXT: s_mov_b64 exec, 031; GFX10-NEXT: s_endpgm32;33; GFX11-12-LABEL: gs_const:34; GFX11-12: ; %bb.0:35; GFX11-12-NEXT: s_mov_b64 s[0:1], exec36; GFX11-12-NEXT: s_and_not1_b64 s[0:1], s[0:1], exec37; GFX11-12-NEXT: s_mov_b64 exec, 038; GFX11-12-NEXT: s_mov_b32 m0, 039; GFX11-12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)40; GFX11-12-NEXT: s_endpgm41; GFX11-12-NEXT: ; %bb.1:42; GFX11-12-NEXT: s_mov_b64 exec, 043; GFX11-12-NEXT: s_endpgm44 %tmp = icmp ule i32 0, 345 %tmp1 = select i1 %tmp, float 1.000000e+00, float -1.000000e+0046 %c1 = fcmp oge float %tmp1, 0.047 call void @llvm.amdgcn.kill(i1 %c1)48 %tmp2 = icmp ule i32 3, 049 %tmp3 = select i1 %tmp2, float 1.000000e+00, float -1.000000e+0050 %c2 = fcmp oge float %tmp3, 0.051 call void @llvm.amdgcn.kill(i1 %c2)52 call void @llvm.amdgcn.s.sendmsg(i32 3, i32 0)53 ret void54}55 56define amdgpu_ps void @vcc_implicit_def(float %arg13, float %arg14) {57; SI-LABEL: vcc_implicit_def:58; SI: ; %bb.0:59; SI-NEXT: v_cmp_nle_f32_e32 vcc, 0, v160; SI-NEXT: v_cmp_gt_f32_e64 s[0:1], 0, v061; SI-NEXT: s_andn2_b64 exec, exec, vcc62; SI-NEXT: s_cbranch_scc0 .LBB1_263; SI-NEXT: ; %bb.1:64; SI-NEXT: s_andn2_b64 exec, exec, vcc65; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, s[0:1]66; SI-NEXT: exp mrt1 v0, v0, v0, v0 done vm67; SI-NEXT: s_mov_b32 m0, 068; SI-NEXT: s_nop 069; SI-NEXT: s_sendmsg sendmsg(MSG_GS_DONE, GS_OP_NOP)70; SI-NEXT: s_endpgm71; SI-NEXT: .LBB1_2:72; SI-NEXT: s_mov_b64 exec, 073; SI-NEXT: exp null off, off, off, off done vm74; SI-NEXT: s_endpgm75;76; GFX10-LABEL: vcc_implicit_def:77; GFX10: ; %bb.0:78; GFX10-NEXT: v_cmp_nle_f32_e32 vcc, 0, v179; GFX10-NEXT: v_cmp_gt_f32_e64 s[0:1], 0, v080; GFX10-NEXT: s_andn2_b64 exec, exec, vcc81; GFX10-NEXT: s_cbranch_scc0 .LBB1_282; GFX10-NEXT: ; %bb.1:83; GFX10-NEXT: s_andn2_b64 exec, exec, vcc84; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, s[0:1]85; GFX10-NEXT: s_mov_b32 m0, 086; GFX10-NEXT: s_sendmsg sendmsg(MSG_GS_DONE, GS_OP_NOP)87; GFX10-NEXT: exp mrt1 v0, v0, v0, v0 done vm88; GFX10-NEXT: s_endpgm89; GFX10-NEXT: .LBB1_2:90; GFX10-NEXT: s_mov_b64 exec, 091; GFX10-NEXT: exp null off, off, off, off done vm92; GFX10-NEXT: s_endpgm93;94; GFX11-LABEL: vcc_implicit_def:95; GFX11: ; %bb.0:96; GFX11-NEXT: v_cmp_nle_f32_e32 vcc, 0, v197; GFX11-NEXT: v_cmp_gt_f32_e64 s[0:1], 0, v098; GFX11-NEXT: s_and_not1_b64 exec, exec, vcc99; GFX11-NEXT: s_cbranch_scc0 .LBB1_2100; GFX11-NEXT: ; %bb.1:101; GFX11-NEXT: s_and_not1_b64 exec, exec, vcc102; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, s[0:1]103; GFX11-NEXT: s_mov_b32 m0, 0104; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)105; GFX11-NEXT: exp mrt1 v0, v0, v0, v0 done106; GFX11-NEXT: s_endpgm107; GFX11-NEXT: .LBB1_2:108; GFX11-NEXT: s_mov_b64 exec, 0109; GFX11-NEXT: exp mrt0 off, off, off, off done110; GFX11-NEXT: s_endpgm111;112; GFX12-LABEL: vcc_implicit_def:113; GFX12: ; %bb.0:114; GFX12-NEXT: v_cmp_le_f32_e64 s[0:1], 0, v1115; GFX12-NEXT: s_mov_b64 s[2:3], exec116; GFX12-NEXT: v_cmp_gt_f32_e32 vcc, 0, v0117; GFX12-NEXT: s_and_not1_b64 s[0:1], exec, s[0:1]118; GFX12-NEXT: s_and_not1_b64 s[2:3], s[2:3], s[0:1]119; GFX12-NEXT: s_cbranch_scc0 .LBB1_2120; GFX12-NEXT: ; %bb.1:121; GFX12-NEXT: s_and_b64 exec, exec, s[2:3]122; GFX12-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc123; GFX12-NEXT: s_mov_b32 m0, 0124; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)125; GFX12-NEXT: export mrt1 v0, v0, v0, v0 done126; GFX12-NEXT: s_endpgm127; GFX12-NEXT: .LBB1_2:128; GFX12-NEXT: s_mov_b64 exec, 0129; GFX12-NEXT: export mrt0 off, off, off, off done130; GFX12-NEXT: s_endpgm131 %tmp0 = fcmp olt float %arg13, 0.000000e+00132 %c1 = fcmp oge float %arg14, 0.0133 call void @llvm.amdgcn.kill(i1 %c1)134 %tmp1 = select i1 %tmp0, float 1.000000e+00, float 0.000000e+00135 call void @llvm.amdgcn.exp.f32(i32 1, i32 15, float %tmp1, float %tmp1, float %tmp1, float %tmp1, i1 true, i1 true) #0136 call void @llvm.amdgcn.s.sendmsg(i32 3, i32 0)137 ret void138}139 140define amdgpu_gs void @true() {141; GCN-LABEL: true:142; GCN: ; %bb.0:143; GCN-NEXT: s_endpgm144 call void @llvm.amdgcn.kill(i1 true)145 ret void146}147 148define amdgpu_gs void @false() {149; SI-LABEL: false:150; SI: ; %bb.0:151; SI-NEXT: s_andn2_b64 exec, exec, exec152; SI-NEXT: s_mov_b64 exec, 0153; SI-NEXT: s_mov_b32 m0, 0154; SI-NEXT: s_nop 0155; SI-NEXT: s_sendmsg sendmsg(MSG_GS_DONE, GS_OP_NOP)156; SI-NEXT: s_endpgm157; SI-NEXT: ; %bb.1:158; SI-NEXT: s_mov_b64 exec, 0159; SI-NEXT: s_endpgm160;161; GFX10-LABEL: false:162; GFX10: ; %bb.0:163; GFX10-NEXT: s_andn2_b64 exec, exec, exec164; GFX10-NEXT: s_mov_b64 exec, 0165; GFX10-NEXT: s_mov_b32 m0, 0166; GFX10-NEXT: s_sendmsg sendmsg(MSG_GS_DONE, GS_OP_NOP)167; GFX10-NEXT: s_endpgm168; GFX10-NEXT: ; %bb.1:169; GFX10-NEXT: s_mov_b64 exec, 0170; GFX10-NEXT: s_endpgm171;172; GFX11-12-LABEL: false:173; GFX11-12: ; %bb.0:174; GFX11-12-NEXT: s_and_not1_b64 exec, exec, exec175; GFX11-12-NEXT: s_mov_b64 exec, 0176; GFX11-12-NEXT: s_mov_b32 m0, 0177; GFX11-12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)178; GFX11-12-NEXT: s_endpgm179; GFX11-12-NEXT: ; %bb.1:180; GFX11-12-NEXT: s_mov_b64 exec, 0181; GFX11-12-NEXT: s_endpgm182 call void @llvm.amdgcn.kill(i1 false)183 call void @llvm.amdgcn.s.sendmsg(i32 3, i32 0)184 ret void185}186 187define amdgpu_gs void @and(i32 %a, i32 %b, i32 %c, i32 %d) {188; SI-LABEL: and:189; SI: ; %bb.0:190; SI-NEXT: v_cmp_lt_i32_e32 vcc, v0, v1191; SI-NEXT: v_cmp_lt_i32_e64 s[0:1], v2, v3192; SI-NEXT: s_or_b64 s[0:1], vcc, s[0:1]193; SI-NEXT: s_mov_b64 s[2:3], exec194; SI-NEXT: s_andn2_b64 s[0:1], exec, s[0:1]195; SI-NEXT: s_andn2_b64 s[2:3], s[2:3], s[0:1]196; SI-NEXT: s_and_b64 exec, exec, s[2:3]197; SI-NEXT: s_mov_b32 m0, 0198; SI-NEXT: s_nop 0199; SI-NEXT: s_sendmsg sendmsg(MSG_GS_DONE, GS_OP_NOP)200; SI-NEXT: s_endpgm201; SI-NEXT: ; %bb.1:202; SI-NEXT: s_mov_b64 exec, 0203; SI-NEXT: s_endpgm204;205; GFX10-LABEL: and:206; GFX10: ; %bb.0:207; GFX10-NEXT: v_cmp_lt_i32_e32 vcc, v0, v1208; GFX10-NEXT: v_cmp_lt_i32_e64 s[0:1], v2, v3209; GFX10-NEXT: s_mov_b64 s[2:3], exec210; GFX10-NEXT: s_or_b64 s[0:1], vcc, s[0:1]211; GFX10-NEXT: s_andn2_b64 s[0:1], exec, s[0:1]212; GFX10-NEXT: s_andn2_b64 s[2:3], s[2:3], s[0:1]213; GFX10-NEXT: s_and_b64 exec, exec, s[2:3]214; GFX10-NEXT: s_mov_b32 m0, 0215; GFX10-NEXT: s_sendmsg sendmsg(MSG_GS_DONE, GS_OP_NOP)216; GFX10-NEXT: s_endpgm217; GFX10-NEXT: ; %bb.1:218; GFX10-NEXT: s_mov_b64 exec, 0219; GFX10-NEXT: s_endpgm220;221; GFX11-12-LABEL: and:222; GFX11-12: ; %bb.0:223; GFX11-12-NEXT: v_cmp_lt_i32_e32 vcc, v0, v1224; GFX11-12-NEXT: v_cmp_lt_i32_e64 s[0:1], v2, v3225; GFX11-12-NEXT: s_mov_b64 s[2:3], exec226; GFX11-12-NEXT: s_or_b64 s[0:1], vcc, s[0:1]227; GFX11-12-NEXT: s_and_not1_b64 s[0:1], exec, s[0:1]228; GFX11-12-NEXT: s_and_not1_b64 s[2:3], s[2:3], s[0:1]229; GFX11-12-NEXT: s_and_b64 exec, exec, s[2:3]230; GFX11-12-NEXT: s_mov_b32 m0, 0231; GFX11-12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)232; GFX11-12-NEXT: s_endpgm233; GFX11-12-NEXT: ; %bb.1:234; GFX11-12-NEXT: s_mov_b64 exec, 0235; GFX11-12-NEXT: s_endpgm236 %c1 = icmp slt i32 %a, %b237 %c2 = icmp slt i32 %c, %d238 %x = or i1 %c1, %c2239 call void @llvm.amdgcn.kill(i1 %x)240 call void @llvm.amdgcn.s.sendmsg(i32 3, i32 0)241 ret void242}243 244define amdgpu_gs void @andn2(i32 %a, i32 %b, i32 %c, i32 %d) {245; SI-LABEL: andn2:246; SI: ; %bb.0:247; SI-NEXT: v_cmp_lt_i32_e32 vcc, v0, v1248; SI-NEXT: v_cmp_lt_i32_e64 s[0:1], v2, v3249; SI-NEXT: s_mov_b64 s[2:3], exec250; SI-NEXT: s_xor_b64 s[0:1], vcc, s[0:1]251; SI-NEXT: s_andn2_b64 s[2:3], s[2:3], s[0:1]252; SI-NEXT: s_and_b64 exec, exec, s[2:3]253; SI-NEXT: s_mov_b32 m0, 0254; SI-NEXT: s_nop 0255; SI-NEXT: s_sendmsg sendmsg(MSG_GS_DONE, GS_OP_NOP)256; SI-NEXT: s_endpgm257; SI-NEXT: ; %bb.1:258; SI-NEXT: s_mov_b64 exec, 0259; SI-NEXT: s_endpgm260;261; GFX10-LABEL: andn2:262; GFX10: ; %bb.0:263; GFX10-NEXT: v_cmp_lt_i32_e32 vcc, v0, v1264; GFX10-NEXT: v_cmp_lt_i32_e64 s[0:1], v2, v3265; GFX10-NEXT: s_mov_b64 s[2:3], exec266; GFX10-NEXT: s_xor_b64 s[0:1], vcc, s[0:1]267; GFX10-NEXT: s_andn2_b64 s[2:3], s[2:3], s[0:1]268; GFX10-NEXT: s_and_b64 exec, exec, s[2:3]269; GFX10-NEXT: s_mov_b32 m0, 0270; GFX10-NEXT: s_sendmsg sendmsg(MSG_GS_DONE, GS_OP_NOP)271; GFX10-NEXT: s_endpgm272; GFX10-NEXT: ; %bb.1:273; GFX10-NEXT: s_mov_b64 exec, 0274; GFX10-NEXT: s_endpgm275;276; GFX11-12-LABEL: andn2:277; GFX11-12: ; %bb.0:278; GFX11-12-NEXT: v_cmp_lt_i32_e32 vcc, v0, v1279; GFX11-12-NEXT: v_cmp_lt_i32_e64 s[0:1], v2, v3280; GFX11-12-NEXT: s_mov_b64 s[2:3], exec281; GFX11-12-NEXT: s_xor_b64 s[0:1], vcc, s[0:1]282; GFX11-12-NEXT: s_and_not1_b64 s[2:3], s[2:3], s[0:1]283; GFX11-12-NEXT: s_and_b64 exec, exec, s[2:3]284; GFX11-12-NEXT: s_mov_b32 m0, 0285; GFX11-12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)286; GFX11-12-NEXT: s_endpgm287; GFX11-12-NEXT: ; %bb.1:288; GFX11-12-NEXT: s_mov_b64 exec, 0289; GFX11-12-NEXT: s_endpgm290 %c1 = icmp slt i32 %a, %b291 %c2 = icmp slt i32 %c, %d292 %x = xor i1 %c1, %c2293 %y = xor i1 %x, 1294 call void @llvm.amdgcn.kill(i1 %y)295 call void @llvm.amdgcn.s.sendmsg(i32 3, i32 0)296 ret void297}298 299; Should use v_cmp_neq_f32300define amdgpu_gs void @oeq(float %a) {301; SI-LABEL: oeq:302; SI: ; %bb.0:303; SI-NEXT: v_cmp_neq_f32_e32 vcc, 0, v0304; SI-NEXT: s_andn2_b64 exec, exec, vcc305; SI-NEXT: s_andn2_b64 exec, exec, vcc306; SI-NEXT: s_mov_b32 m0, 0307; SI-NEXT: s_nop 0308; SI-NEXT: s_sendmsg sendmsg(MSG_GS_DONE, GS_OP_NOP)309; SI-NEXT: s_endpgm310; SI-NEXT: ; %bb.1:311; SI-NEXT: s_mov_b64 exec, 0312; SI-NEXT: s_endpgm313;314; GFX10-LABEL: oeq:315; GFX10: ; %bb.0:316; GFX10-NEXT: v_cmp_neq_f32_e32 vcc, 0, v0317; GFX10-NEXT: s_andn2_b64 exec, exec, vcc318; GFX10-NEXT: s_andn2_b64 exec, exec, vcc319; GFX10-NEXT: s_mov_b32 m0, 0320; GFX10-NEXT: s_sendmsg sendmsg(MSG_GS_DONE, GS_OP_NOP)321; GFX10-NEXT: s_endpgm322; GFX10-NEXT: ; %bb.1:323; GFX10-NEXT: s_mov_b64 exec, 0324; GFX10-NEXT: s_endpgm325;326; GFX11-LABEL: oeq:327; GFX11: ; %bb.0:328; GFX11-NEXT: v_cmp_neq_f32_e32 vcc, 0, v0329; GFX11-NEXT: s_and_not1_b64 exec, exec, vcc330; GFX11-NEXT: s_and_not1_b64 exec, exec, vcc331; GFX11-NEXT: s_mov_b32 m0, 0332; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)333; GFX11-NEXT: s_endpgm334; GFX11-NEXT: ; %bb.1:335; GFX11-NEXT: s_mov_b64 exec, 0336; GFX11-NEXT: s_endpgm337;338; GFX12-LABEL: oeq:339; GFX12: ; %bb.0:340; GFX12-NEXT: v_cmp_eq_f32_e32 vcc, 0, v0341; GFX12-NEXT: s_mov_b64 s[0:1], exec342; GFX12-NEXT: s_and_not1_b64 s[2:3], exec, vcc343; GFX12-NEXT: s_and_not1_b64 s[0:1], s[0:1], s[2:3]344; GFX12-NEXT: s_and_b64 exec, exec, s[0:1]345; GFX12-NEXT: s_mov_b32 m0, 0346; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)347; GFX12-NEXT: s_endpgm348; GFX12-NEXT: ; %bb.1:349; GFX12-NEXT: s_mov_b64 exec, 0350; GFX12-NEXT: s_endpgm351 %c1 = fcmp oeq float %a, 0.0352 call void @llvm.amdgcn.kill(i1 %c1)353 call void @llvm.amdgcn.s.sendmsg(i32 3, i32 0)354 ret void355}356 357; Should use v_cmp_nlt_f32358define amdgpu_gs void @ogt(float %a) {359; SI-LABEL: ogt:360; SI: ; %bb.0:361; SI-NEXT: v_cmp_nlt_f32_e32 vcc, 0, v0362; SI-NEXT: s_andn2_b64 exec, exec, vcc363; SI-NEXT: s_andn2_b64 exec, exec, vcc364; SI-NEXT: s_mov_b32 m0, 0365; SI-NEXT: s_nop 0366; SI-NEXT: s_sendmsg sendmsg(MSG_GS_DONE, GS_OP_NOP)367; SI-NEXT: s_endpgm368; SI-NEXT: ; %bb.1:369; SI-NEXT: s_mov_b64 exec, 0370; SI-NEXT: s_endpgm371;372; GFX10-LABEL: ogt:373; GFX10: ; %bb.0:374; GFX10-NEXT: v_cmp_nlt_f32_e32 vcc, 0, v0375; GFX10-NEXT: s_andn2_b64 exec, exec, vcc376; GFX10-NEXT: s_andn2_b64 exec, exec, vcc377; GFX10-NEXT: s_mov_b32 m0, 0378; GFX10-NEXT: s_sendmsg sendmsg(MSG_GS_DONE, GS_OP_NOP)379; GFX10-NEXT: s_endpgm380; GFX10-NEXT: ; %bb.1:381; GFX10-NEXT: s_mov_b64 exec, 0382; GFX10-NEXT: s_endpgm383;384; GFX11-LABEL: ogt:385; GFX11: ; %bb.0:386; GFX11-NEXT: v_cmp_nlt_f32_e32 vcc, 0, v0387; GFX11-NEXT: s_and_not1_b64 exec, exec, vcc388; GFX11-NEXT: s_and_not1_b64 exec, exec, vcc389; GFX11-NEXT: s_mov_b32 m0, 0390; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)391; GFX11-NEXT: s_endpgm392; GFX11-NEXT: ; %bb.1:393; GFX11-NEXT: s_mov_b64 exec, 0394; GFX11-NEXT: s_endpgm395;396; GFX12-LABEL: ogt:397; GFX12: ; %bb.0:398; GFX12-NEXT: v_cmp_lt_f32_e32 vcc, 0, v0399; GFX12-NEXT: s_mov_b64 s[0:1], exec400; GFX12-NEXT: s_and_not1_b64 s[2:3], exec, vcc401; GFX12-NEXT: s_and_not1_b64 s[0:1], s[0:1], s[2:3]402; GFX12-NEXT: s_and_b64 exec, exec, s[0:1]403; GFX12-NEXT: s_mov_b32 m0, 0404; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)405; GFX12-NEXT: s_endpgm406; GFX12-NEXT: ; %bb.1:407; GFX12-NEXT: s_mov_b64 exec, 0408; GFX12-NEXT: s_endpgm409 %c1 = fcmp ogt float %a, 0.0410 call void @llvm.amdgcn.kill(i1 %c1)411 call void @llvm.amdgcn.s.sendmsg(i32 3, i32 0)412 ret void413}414 415; Should use v_cmp_nle_f32416define amdgpu_gs void @oge(float %a) {417; SI-LABEL: oge:418; SI: ; %bb.0:419; SI-NEXT: v_cmp_nle_f32_e32 vcc, 0, v0420; SI-NEXT: s_andn2_b64 exec, exec, vcc421; SI-NEXT: s_andn2_b64 exec, exec, vcc422; SI-NEXT: s_mov_b32 m0, 0423; SI-NEXT: s_nop 0424; SI-NEXT: s_sendmsg sendmsg(MSG_GS_DONE, GS_OP_NOP)425; SI-NEXT: s_endpgm426; SI-NEXT: ; %bb.1:427; SI-NEXT: s_mov_b64 exec, 0428; SI-NEXT: s_endpgm429;430; GFX10-LABEL: oge:431; GFX10: ; %bb.0:432; GFX10-NEXT: v_cmp_nle_f32_e32 vcc, 0, v0433; GFX10-NEXT: s_andn2_b64 exec, exec, vcc434; GFX10-NEXT: s_andn2_b64 exec, exec, vcc435; GFX10-NEXT: s_mov_b32 m0, 0436; GFX10-NEXT: s_sendmsg sendmsg(MSG_GS_DONE, GS_OP_NOP)437; GFX10-NEXT: s_endpgm438; GFX10-NEXT: ; %bb.1:439; GFX10-NEXT: s_mov_b64 exec, 0440; GFX10-NEXT: s_endpgm441;442; GFX11-LABEL: oge:443; GFX11: ; %bb.0:444; GFX11-NEXT: v_cmp_nle_f32_e32 vcc, 0, v0445; GFX11-NEXT: s_and_not1_b64 exec, exec, vcc446; GFX11-NEXT: s_and_not1_b64 exec, exec, vcc447; GFX11-NEXT: s_mov_b32 m0, 0448; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)449; GFX11-NEXT: s_endpgm450; GFX11-NEXT: ; %bb.1:451; GFX11-NEXT: s_mov_b64 exec, 0452; GFX11-NEXT: s_endpgm453;454; GFX12-LABEL: oge:455; GFX12: ; %bb.0:456; GFX12-NEXT: v_cmp_le_f32_e32 vcc, 0, v0457; GFX12-NEXT: s_mov_b64 s[0:1], exec458; GFX12-NEXT: s_and_not1_b64 s[2:3], exec, vcc459; GFX12-NEXT: s_and_not1_b64 s[0:1], s[0:1], s[2:3]460; GFX12-NEXT: s_and_b64 exec, exec, s[0:1]461; GFX12-NEXT: s_mov_b32 m0, 0462; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)463; GFX12-NEXT: s_endpgm464; GFX12-NEXT: ; %bb.1:465; GFX12-NEXT: s_mov_b64 exec, 0466; GFX12-NEXT: s_endpgm467 %c1 = fcmp oge float %a, 0.0468 call void @llvm.amdgcn.kill(i1 %c1)469 call void @llvm.amdgcn.s.sendmsg(i32 3, i32 0)470 ret void471}472 473; Should use v_cmp_ngt_f32474define amdgpu_gs void @olt(float %a) {475; SI-LABEL: olt:476; SI: ; %bb.0:477; SI-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v0478; SI-NEXT: s_andn2_b64 exec, exec, vcc479; SI-NEXT: s_andn2_b64 exec, exec, vcc480; SI-NEXT: s_mov_b32 m0, 0481; SI-NEXT: s_nop 0482; SI-NEXT: s_sendmsg sendmsg(MSG_GS_DONE, GS_OP_NOP)483; SI-NEXT: s_endpgm484; SI-NEXT: ; %bb.1:485; SI-NEXT: s_mov_b64 exec, 0486; SI-NEXT: s_endpgm487;488; GFX10-LABEL: olt:489; GFX10: ; %bb.0:490; GFX10-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v0491; GFX10-NEXT: s_andn2_b64 exec, exec, vcc492; GFX10-NEXT: s_andn2_b64 exec, exec, vcc493; GFX10-NEXT: s_mov_b32 m0, 0494; GFX10-NEXT: s_sendmsg sendmsg(MSG_GS_DONE, GS_OP_NOP)495; GFX10-NEXT: s_endpgm496; GFX10-NEXT: ; %bb.1:497; GFX10-NEXT: s_mov_b64 exec, 0498; GFX10-NEXT: s_endpgm499;500; GFX11-LABEL: olt:501; GFX11: ; %bb.0:502; GFX11-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v0503; GFX11-NEXT: s_and_not1_b64 exec, exec, vcc504; GFX11-NEXT: s_and_not1_b64 exec, exec, vcc505; GFX11-NEXT: s_mov_b32 m0, 0506; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)507; GFX11-NEXT: s_endpgm508; GFX11-NEXT: ; %bb.1:509; GFX11-NEXT: s_mov_b64 exec, 0510; GFX11-NEXT: s_endpgm511;512; GFX12-LABEL: olt:513; GFX12: ; %bb.0:514; GFX12-NEXT: v_cmp_gt_f32_e32 vcc, 0, v0515; GFX12-NEXT: s_mov_b64 s[0:1], exec516; GFX12-NEXT: s_and_not1_b64 s[2:3], exec, vcc517; GFX12-NEXT: s_and_not1_b64 s[0:1], s[0:1], s[2:3]518; GFX12-NEXT: s_and_b64 exec, exec, s[0:1]519; GFX12-NEXT: s_mov_b32 m0, 0520; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)521; GFX12-NEXT: s_endpgm522; GFX12-NEXT: ; %bb.1:523; GFX12-NEXT: s_mov_b64 exec, 0524; GFX12-NEXT: s_endpgm525 %c1 = fcmp olt float %a, 0.0526 call void @llvm.amdgcn.kill(i1 %c1)527 call void @llvm.amdgcn.s.sendmsg(i32 3, i32 0)528 ret void529}530 531; Should use v_cmp_nge_f32532define amdgpu_gs void @ole(float %a) {533; SI-LABEL: ole:534; SI: ; %bb.0:535; SI-NEXT: v_cmp_nge_f32_e32 vcc, 0, v0536; SI-NEXT: s_andn2_b64 exec, exec, vcc537; SI-NEXT: s_andn2_b64 exec, exec, vcc538; SI-NEXT: s_mov_b32 m0, 0539; SI-NEXT: s_nop 0540; SI-NEXT: s_sendmsg sendmsg(MSG_GS_DONE, GS_OP_NOP)541; SI-NEXT: s_endpgm542; SI-NEXT: ; %bb.1:543; SI-NEXT: s_mov_b64 exec, 0544; SI-NEXT: s_endpgm545;546; GFX10-LABEL: ole:547; GFX10: ; %bb.0:548; GFX10-NEXT: v_cmp_nge_f32_e32 vcc, 0, v0549; GFX10-NEXT: s_andn2_b64 exec, exec, vcc550; GFX10-NEXT: s_andn2_b64 exec, exec, vcc551; GFX10-NEXT: s_mov_b32 m0, 0552; GFX10-NEXT: s_sendmsg sendmsg(MSG_GS_DONE, GS_OP_NOP)553; GFX10-NEXT: s_endpgm554; GFX10-NEXT: ; %bb.1:555; GFX10-NEXT: s_mov_b64 exec, 0556; GFX10-NEXT: s_endpgm557;558; GFX11-LABEL: ole:559; GFX11: ; %bb.0:560; GFX11-NEXT: v_cmp_nge_f32_e32 vcc, 0, v0561; GFX11-NEXT: s_and_not1_b64 exec, exec, vcc562; GFX11-NEXT: s_and_not1_b64 exec, exec, vcc563; GFX11-NEXT: s_mov_b32 m0, 0564; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)565; GFX11-NEXT: s_endpgm566; GFX11-NEXT: ; %bb.1:567; GFX11-NEXT: s_mov_b64 exec, 0568; GFX11-NEXT: s_endpgm569;570; GFX12-LABEL: ole:571; GFX12: ; %bb.0:572; GFX12-NEXT: v_cmp_ge_f32_e32 vcc, 0, v0573; GFX12-NEXT: s_mov_b64 s[0:1], exec574; GFX12-NEXT: s_and_not1_b64 s[2:3], exec, vcc575; GFX12-NEXT: s_and_not1_b64 s[0:1], s[0:1], s[2:3]576; GFX12-NEXT: s_and_b64 exec, exec, s[0:1]577; GFX12-NEXT: s_mov_b32 m0, 0578; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)579; GFX12-NEXT: s_endpgm580; GFX12-NEXT: ; %bb.1:581; GFX12-NEXT: s_mov_b64 exec, 0582; GFX12-NEXT: s_endpgm583 %c1 = fcmp ole float %a, 0.0584 call void @llvm.amdgcn.kill(i1 %c1)585 call void @llvm.amdgcn.s.sendmsg(i32 3, i32 0)586 ret void587}588 589; Should use v_cmp_nlg_f32590define amdgpu_gs void @one(float %a) {591; SI-LABEL: one:592; SI: ; %bb.0:593; SI-NEXT: v_cmp_nlg_f32_e32 vcc, 0, v0594; SI-NEXT: s_andn2_b64 exec, exec, vcc595; SI-NEXT: s_andn2_b64 exec, exec, vcc596; SI-NEXT: s_mov_b32 m0, 0597; SI-NEXT: s_nop 0598; SI-NEXT: s_sendmsg sendmsg(MSG_GS_DONE, GS_OP_NOP)599; SI-NEXT: s_endpgm600; SI-NEXT: ; %bb.1:601; SI-NEXT: s_mov_b64 exec, 0602; SI-NEXT: s_endpgm603;604; GFX10-LABEL: one:605; GFX10: ; %bb.0:606; GFX10-NEXT: v_cmp_nlg_f32_e32 vcc, 0, v0607; GFX10-NEXT: s_andn2_b64 exec, exec, vcc608; GFX10-NEXT: s_andn2_b64 exec, exec, vcc609; GFX10-NEXT: s_mov_b32 m0, 0610; GFX10-NEXT: s_sendmsg sendmsg(MSG_GS_DONE, GS_OP_NOP)611; GFX10-NEXT: s_endpgm612; GFX10-NEXT: ; %bb.1:613; GFX10-NEXT: s_mov_b64 exec, 0614; GFX10-NEXT: s_endpgm615;616; GFX11-LABEL: one:617; GFX11: ; %bb.0:618; GFX11-NEXT: v_cmp_nlg_f32_e32 vcc, 0, v0619; GFX11-NEXT: s_and_not1_b64 exec, exec, vcc620; GFX11-NEXT: s_and_not1_b64 exec, exec, vcc621; GFX11-NEXT: s_mov_b32 m0, 0622; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)623; GFX11-NEXT: s_endpgm624; GFX11-NEXT: ; %bb.1:625; GFX11-NEXT: s_mov_b64 exec, 0626; GFX11-NEXT: s_endpgm627;628; GFX12-LABEL: one:629; GFX12: ; %bb.0:630; GFX12-NEXT: v_cmp_lg_f32_e32 vcc, 0, v0631; GFX12-NEXT: s_mov_b64 s[0:1], exec632; GFX12-NEXT: s_and_not1_b64 s[2:3], exec, vcc633; GFX12-NEXT: s_and_not1_b64 s[0:1], s[0:1], s[2:3]634; GFX12-NEXT: s_and_b64 exec, exec, s[0:1]635; GFX12-NEXT: s_mov_b32 m0, 0636; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)637; GFX12-NEXT: s_endpgm638; GFX12-NEXT: ; %bb.1:639; GFX12-NEXT: s_mov_b64 exec, 0640; GFX12-NEXT: s_endpgm641 %c1 = fcmp one float %a, 0.0642 call void @llvm.amdgcn.kill(i1 %c1)643 call void @llvm.amdgcn.s.sendmsg(i32 3, i32 0)644 ret void645}646 647; Should use v_cmp_o_f32648define amdgpu_gs void @ord(float %a) {649; SI-LABEL: ord:650; SI: ; %bb.0:651; SI-NEXT: v_cmp_o_f32_e32 vcc, v0, v0652; SI-NEXT: s_mov_b64 s[0:1], exec653; SI-NEXT: s_andn2_b64 s[2:3], exec, vcc654; SI-NEXT: s_andn2_b64 s[0:1], s[0:1], s[2:3]655; SI-NEXT: s_and_b64 exec, exec, s[0:1]656; SI-NEXT: s_mov_b32 m0, 0657; SI-NEXT: s_nop 0658; SI-NEXT: s_sendmsg sendmsg(MSG_GS_DONE, GS_OP_NOP)659; SI-NEXT: s_endpgm660; SI-NEXT: ; %bb.1:661; SI-NEXT: s_mov_b64 exec, 0662; SI-NEXT: s_endpgm663;664; GFX10-LABEL: ord:665; GFX10: ; %bb.0:666; GFX10-NEXT: v_cmp_o_f32_e32 vcc, v0, v0667; GFX10-NEXT: s_mov_b64 s[0:1], exec668; GFX10-NEXT: s_andn2_b64 s[2:3], exec, vcc669; GFX10-NEXT: s_andn2_b64 s[0:1], s[0:1], s[2:3]670; GFX10-NEXT: s_and_b64 exec, exec, s[0:1]671; GFX10-NEXT: s_mov_b32 m0, 0672; GFX10-NEXT: s_sendmsg sendmsg(MSG_GS_DONE, GS_OP_NOP)673; GFX10-NEXT: s_endpgm674; GFX10-NEXT: ; %bb.1:675; GFX10-NEXT: s_mov_b64 exec, 0676; GFX10-NEXT: s_endpgm677;678; GFX11-12-LABEL: ord:679; GFX11-12: ; %bb.0:680; GFX11-12-NEXT: v_cmp_o_f32_e32 vcc, v0, v0681; GFX11-12-NEXT: s_mov_b64 s[0:1], exec682; GFX11-12-NEXT: s_and_not1_b64 s[2:3], exec, vcc683; GFX11-12-NEXT: s_and_not1_b64 s[0:1], s[0:1], s[2:3]684; GFX11-12-NEXT: s_and_b64 exec, exec, s[0:1]685; GFX11-12-NEXT: s_mov_b32 m0, 0686; GFX11-12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)687; GFX11-12-NEXT: s_endpgm688; GFX11-12-NEXT: ; %bb.1:689; GFX11-12-NEXT: s_mov_b64 exec, 0690; GFX11-12-NEXT: s_endpgm691 %c1 = fcmp ord float %a, 0.0692 call void @llvm.amdgcn.kill(i1 %c1)693 call void @llvm.amdgcn.s.sendmsg(i32 3, i32 0)694 ret void695}696 697; Should use v_cmp_u_f32698define amdgpu_gs void @uno(float %a) {699; SI-LABEL: uno:700; SI: ; %bb.0:701; SI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0702; SI-NEXT: s_mov_b64 s[0:1], exec703; SI-NEXT: s_andn2_b64 s[2:3], exec, vcc704; SI-NEXT: s_andn2_b64 s[0:1], s[0:1], s[2:3]705; SI-NEXT: s_and_b64 exec, exec, s[0:1]706; SI-NEXT: s_mov_b32 m0, 0707; SI-NEXT: s_nop 0708; SI-NEXT: s_sendmsg sendmsg(MSG_GS_DONE, GS_OP_NOP)709; SI-NEXT: s_endpgm710; SI-NEXT: ; %bb.1:711; SI-NEXT: s_mov_b64 exec, 0712; SI-NEXT: s_endpgm713;714; GFX10-LABEL: uno:715; GFX10: ; %bb.0:716; GFX10-NEXT: v_cmp_u_f32_e32 vcc, v0, v0717; GFX10-NEXT: s_mov_b64 s[0:1], exec718; GFX10-NEXT: s_andn2_b64 s[2:3], exec, vcc719; GFX10-NEXT: s_andn2_b64 s[0:1], s[0:1], s[2:3]720; GFX10-NEXT: s_and_b64 exec, exec, s[0:1]721; GFX10-NEXT: s_mov_b32 m0, 0722; GFX10-NEXT: s_sendmsg sendmsg(MSG_GS_DONE, GS_OP_NOP)723; GFX10-NEXT: s_endpgm724; GFX10-NEXT: ; %bb.1:725; GFX10-NEXT: s_mov_b64 exec, 0726; GFX10-NEXT: s_endpgm727;728; GFX11-12-LABEL: uno:729; GFX11-12: ; %bb.0:730; GFX11-12-NEXT: v_cmp_u_f32_e32 vcc, v0, v0731; GFX11-12-NEXT: s_mov_b64 s[0:1], exec732; GFX11-12-NEXT: s_and_not1_b64 s[2:3], exec, vcc733; GFX11-12-NEXT: s_and_not1_b64 s[0:1], s[0:1], s[2:3]734; GFX11-12-NEXT: s_and_b64 exec, exec, s[0:1]735; GFX11-12-NEXT: s_mov_b32 m0, 0736; GFX11-12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)737; GFX11-12-NEXT: s_endpgm738; GFX11-12-NEXT: ; %bb.1:739; GFX11-12-NEXT: s_mov_b64 exec, 0740; GFX11-12-NEXT: s_endpgm741 %c1 = fcmp uno float %a, 0.0742 call void @llvm.amdgcn.kill(i1 %c1)743 call void @llvm.amdgcn.s.sendmsg(i32 3, i32 0)744 ret void745}746 747; Should use v_cmp_lg_f32748define amdgpu_gs void @ueq(float %a) {749; SI-LABEL: ueq:750; SI: ; %bb.0:751; SI-NEXT: v_cmp_lg_f32_e32 vcc, 0, v0752; SI-NEXT: s_andn2_b64 exec, exec, vcc753; SI-NEXT: s_andn2_b64 exec, exec, vcc754; SI-NEXT: s_mov_b32 m0, 0755; SI-NEXT: s_nop 0756; SI-NEXT: s_sendmsg sendmsg(MSG_GS_DONE, GS_OP_NOP)757; SI-NEXT: s_endpgm758; SI-NEXT: ; %bb.1:759; SI-NEXT: s_mov_b64 exec, 0760; SI-NEXT: s_endpgm761;762; GFX10-LABEL: ueq:763; GFX10: ; %bb.0:764; GFX10-NEXT: v_cmp_lg_f32_e32 vcc, 0, v0765; GFX10-NEXT: s_andn2_b64 exec, exec, vcc766; GFX10-NEXT: s_andn2_b64 exec, exec, vcc767; GFX10-NEXT: s_mov_b32 m0, 0768; GFX10-NEXT: s_sendmsg sendmsg(MSG_GS_DONE, GS_OP_NOP)769; GFX10-NEXT: s_endpgm770; GFX10-NEXT: ; %bb.1:771; GFX10-NEXT: s_mov_b64 exec, 0772; GFX10-NEXT: s_endpgm773;774; GFX11-LABEL: ueq:775; GFX11: ; %bb.0:776; GFX11-NEXT: v_cmp_lg_f32_e32 vcc, 0, v0777; GFX11-NEXT: s_and_not1_b64 exec, exec, vcc778; GFX11-NEXT: s_and_not1_b64 exec, exec, vcc779; GFX11-NEXT: s_mov_b32 m0, 0780; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)781; GFX11-NEXT: s_endpgm782; GFX11-NEXT: ; %bb.1:783; GFX11-NEXT: s_mov_b64 exec, 0784; GFX11-NEXT: s_endpgm785;786; GFX12-LABEL: ueq:787; GFX12: ; %bb.0:788; GFX12-NEXT: v_cmp_nlg_f32_e32 vcc, 0, v0789; GFX12-NEXT: s_mov_b64 s[0:1], exec790; GFX12-NEXT: s_and_not1_b64 s[2:3], exec, vcc791; GFX12-NEXT: s_and_not1_b64 s[0:1], s[0:1], s[2:3]792; GFX12-NEXT: s_and_b64 exec, exec, s[0:1]793; GFX12-NEXT: s_mov_b32 m0, 0794; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)795; GFX12-NEXT: s_endpgm796; GFX12-NEXT: ; %bb.1:797; GFX12-NEXT: s_mov_b64 exec, 0798; GFX12-NEXT: s_endpgm799 %c1 = fcmp ueq float %a, 0.0800 call void @llvm.amdgcn.kill(i1 %c1)801 call void @llvm.amdgcn.s.sendmsg(i32 3, i32 0)802 ret void803}804 805; Should use v_cmp_ge_f32806define amdgpu_gs void @ugt(float %a) {807; SI-LABEL: ugt:808; SI: ; %bb.0:809; SI-NEXT: v_cmp_ge_f32_e32 vcc, 0, v0810; SI-NEXT: s_andn2_b64 exec, exec, vcc811; SI-NEXT: s_andn2_b64 exec, exec, vcc812; SI-NEXT: s_mov_b32 m0, 0813; SI-NEXT: s_nop 0814; SI-NEXT: s_sendmsg sendmsg(MSG_GS_DONE, GS_OP_NOP)815; SI-NEXT: s_endpgm816; SI-NEXT: ; %bb.1:817; SI-NEXT: s_mov_b64 exec, 0818; SI-NEXT: s_endpgm819;820; GFX10-LABEL: ugt:821; GFX10: ; %bb.0:822; GFX10-NEXT: v_cmp_ge_f32_e32 vcc, 0, v0823; GFX10-NEXT: s_andn2_b64 exec, exec, vcc824; GFX10-NEXT: s_andn2_b64 exec, exec, vcc825; GFX10-NEXT: s_mov_b32 m0, 0826; GFX10-NEXT: s_sendmsg sendmsg(MSG_GS_DONE, GS_OP_NOP)827; GFX10-NEXT: s_endpgm828; GFX10-NEXT: ; %bb.1:829; GFX10-NEXT: s_mov_b64 exec, 0830; GFX10-NEXT: s_endpgm831;832; GFX11-LABEL: ugt:833; GFX11: ; %bb.0:834; GFX11-NEXT: v_cmp_ge_f32_e32 vcc, 0, v0835; GFX11-NEXT: s_and_not1_b64 exec, exec, vcc836; GFX11-NEXT: s_and_not1_b64 exec, exec, vcc837; GFX11-NEXT: s_mov_b32 m0, 0838; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)839; GFX11-NEXT: s_endpgm840; GFX11-NEXT: ; %bb.1:841; GFX11-NEXT: s_mov_b64 exec, 0842; GFX11-NEXT: s_endpgm843;844; GFX12-LABEL: ugt:845; GFX12: ; %bb.0:846; GFX12-NEXT: v_cmp_nge_f32_e32 vcc, 0, v0847; GFX12-NEXT: s_mov_b64 s[0:1], exec848; GFX12-NEXT: s_and_not1_b64 s[2:3], exec, vcc849; GFX12-NEXT: s_and_not1_b64 s[0:1], s[0:1], s[2:3]850; GFX12-NEXT: s_and_b64 exec, exec, s[0:1]851; GFX12-NEXT: s_mov_b32 m0, 0852; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)853; GFX12-NEXT: s_endpgm854; GFX12-NEXT: ; %bb.1:855; GFX12-NEXT: s_mov_b64 exec, 0856; GFX12-NEXT: s_endpgm857 %c1 = fcmp ugt float %a, 0.0858 call void @llvm.amdgcn.kill(i1 %c1)859 call void @llvm.amdgcn.s.sendmsg(i32 3, i32 0)860 ret void861}862 863; Should use v_cmp_gt_f32_e32 vcc, -1.0864define amdgpu_gs void @uge(float %a) {865; SI-LABEL: uge:866; SI: ; %bb.0:867; SI-NEXT: v_cmp_gt_f32_e32 vcc, -1.0, v0868; SI-NEXT: s_andn2_b64 exec, exec, vcc869; SI-NEXT: s_andn2_b64 exec, exec, vcc870; SI-NEXT: s_mov_b32 m0, 0871; SI-NEXT: s_nop 0872; SI-NEXT: s_sendmsg sendmsg(MSG_GS_DONE, GS_OP_NOP)873; SI-NEXT: s_endpgm874; SI-NEXT: ; %bb.1:875; SI-NEXT: s_mov_b64 exec, 0876; SI-NEXT: s_endpgm877;878; GFX10-LABEL: uge:879; GFX10: ; %bb.0:880; GFX10-NEXT: v_cmp_gt_f32_e32 vcc, -1.0, v0881; GFX10-NEXT: s_andn2_b64 exec, exec, vcc882; GFX10-NEXT: s_andn2_b64 exec, exec, vcc883; GFX10-NEXT: s_mov_b32 m0, 0884; GFX10-NEXT: s_sendmsg sendmsg(MSG_GS_DONE, GS_OP_NOP)885; GFX10-NEXT: s_endpgm886; GFX10-NEXT: ; %bb.1:887; GFX10-NEXT: s_mov_b64 exec, 0888; GFX10-NEXT: s_endpgm889;890; GFX11-LABEL: uge:891; GFX11: ; %bb.0:892; GFX11-NEXT: v_cmp_gt_f32_e32 vcc, -1.0, v0893; GFX11-NEXT: s_and_not1_b64 exec, exec, vcc894; GFX11-NEXT: s_and_not1_b64 exec, exec, vcc895; GFX11-NEXT: s_mov_b32 m0, 0896; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)897; GFX11-NEXT: s_endpgm898; GFX11-NEXT: ; %bb.1:899; GFX11-NEXT: s_mov_b64 exec, 0900; GFX11-NEXT: s_endpgm901;902; GFX12-LABEL: uge:903; GFX12: ; %bb.0:904; GFX12-NEXT: v_cmp_ngt_f32_e32 vcc, -1.0, v0905; GFX12-NEXT: s_mov_b64 s[0:1], exec906; GFX12-NEXT: s_and_not1_b64 s[2:3], exec, vcc907; GFX12-NEXT: s_and_not1_b64 s[0:1], s[0:1], s[2:3]908; GFX12-NEXT: s_and_b64 exec, exec, s[0:1]909; GFX12-NEXT: s_mov_b32 m0, 0910; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)911; GFX12-NEXT: s_endpgm912; GFX12-NEXT: ; %bb.1:913; GFX12-NEXT: s_mov_b64 exec, 0914; GFX12-NEXT: s_endpgm915 %c1 = fcmp uge float %a, -1.0916 call void @llvm.amdgcn.kill(i1 %c1)917 call void @llvm.amdgcn.s.sendmsg(i32 3, i32 0)918 ret void919}920 921; Should use v_cmp_le_f32_e32 vcc, -2.0922define amdgpu_gs void @ult(float %a) {923; SI-LABEL: ult:924; SI: ; %bb.0:925; SI-NEXT: v_cmp_le_f32_e32 vcc, -2.0, v0926; SI-NEXT: s_andn2_b64 exec, exec, vcc927; SI-NEXT: s_andn2_b64 exec, exec, vcc928; SI-NEXT: s_mov_b32 m0, 0929; SI-NEXT: s_nop 0930; SI-NEXT: s_sendmsg sendmsg(MSG_GS_DONE, GS_OP_NOP)931; SI-NEXT: s_endpgm932; SI-NEXT: ; %bb.1:933; SI-NEXT: s_mov_b64 exec, 0934; SI-NEXT: s_endpgm935;936; GFX10-LABEL: ult:937; GFX10: ; %bb.0:938; GFX10-NEXT: v_cmp_le_f32_e32 vcc, -2.0, v0939; GFX10-NEXT: s_andn2_b64 exec, exec, vcc940; GFX10-NEXT: s_andn2_b64 exec, exec, vcc941; GFX10-NEXT: s_mov_b32 m0, 0942; GFX10-NEXT: s_sendmsg sendmsg(MSG_GS_DONE, GS_OP_NOP)943; GFX10-NEXT: s_endpgm944; GFX10-NEXT: ; %bb.1:945; GFX10-NEXT: s_mov_b64 exec, 0946; GFX10-NEXT: s_endpgm947;948; GFX11-LABEL: ult:949; GFX11: ; %bb.0:950; GFX11-NEXT: v_cmp_le_f32_e32 vcc, -2.0, v0951; GFX11-NEXT: s_and_not1_b64 exec, exec, vcc952; GFX11-NEXT: s_and_not1_b64 exec, exec, vcc953; GFX11-NEXT: s_mov_b32 m0, 0954; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)955; GFX11-NEXT: s_endpgm956; GFX11-NEXT: ; %bb.1:957; GFX11-NEXT: s_mov_b64 exec, 0958; GFX11-NEXT: s_endpgm959;960; GFX12-LABEL: ult:961; GFX12: ; %bb.0:962; GFX12-NEXT: v_cmp_nle_f32_e32 vcc, -2.0, v0963; GFX12-NEXT: s_mov_b64 s[0:1], exec964; GFX12-NEXT: s_and_not1_b64 s[2:3], exec, vcc965; GFX12-NEXT: s_and_not1_b64 s[0:1], s[0:1], s[2:3]966; GFX12-NEXT: s_and_b64 exec, exec, s[0:1]967; GFX12-NEXT: s_mov_b32 m0, 0968; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)969; GFX12-NEXT: s_endpgm970; GFX12-NEXT: ; %bb.1:971; GFX12-NEXT: s_mov_b64 exec, 0972; GFX12-NEXT: s_endpgm973 %c1 = fcmp ult float %a, -2.0974 call void @llvm.amdgcn.kill(i1 %c1)975 call void @llvm.amdgcn.s.sendmsg(i32 3, i32 0)976 ret void977}978 979; Should use v_cmp_lt_f32_e32 vcc, 2.0980define amdgpu_gs void @ule(float %a) {981; SI-LABEL: ule:982; SI: ; %bb.0:983; SI-NEXT: v_cmp_lt_f32_e32 vcc, 2.0, v0984; SI-NEXT: s_andn2_b64 exec, exec, vcc985; SI-NEXT: s_andn2_b64 exec, exec, vcc986; SI-NEXT: s_mov_b32 m0, 0987; SI-NEXT: s_nop 0988; SI-NEXT: s_sendmsg sendmsg(MSG_GS_DONE, GS_OP_NOP)989; SI-NEXT: s_endpgm990; SI-NEXT: ; %bb.1:991; SI-NEXT: s_mov_b64 exec, 0992; SI-NEXT: s_endpgm993;994; GFX10-LABEL: ule:995; GFX10: ; %bb.0:996; GFX10-NEXT: v_cmp_lt_f32_e32 vcc, 2.0, v0997; GFX10-NEXT: s_andn2_b64 exec, exec, vcc998; GFX10-NEXT: s_andn2_b64 exec, exec, vcc999; GFX10-NEXT: s_mov_b32 m0, 01000; GFX10-NEXT: s_sendmsg sendmsg(MSG_GS_DONE, GS_OP_NOP)1001; GFX10-NEXT: s_endpgm1002; GFX10-NEXT: ; %bb.1:1003; GFX10-NEXT: s_mov_b64 exec, 01004; GFX10-NEXT: s_endpgm1005;1006; GFX11-LABEL: ule:1007; GFX11: ; %bb.0:1008; GFX11-NEXT: v_cmp_lt_f32_e32 vcc, 2.0, v01009; GFX11-NEXT: s_and_not1_b64 exec, exec, vcc1010; GFX11-NEXT: s_and_not1_b64 exec, exec, vcc1011; GFX11-NEXT: s_mov_b32 m0, 01012; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)1013; GFX11-NEXT: s_endpgm1014; GFX11-NEXT: ; %bb.1:1015; GFX11-NEXT: s_mov_b64 exec, 01016; GFX11-NEXT: s_endpgm1017;1018; GFX12-LABEL: ule:1019; GFX12: ; %bb.0:1020; GFX12-NEXT: v_cmp_nlt_f32_e32 vcc, 2.0, v01021; GFX12-NEXT: s_mov_b64 s[0:1], exec1022; GFX12-NEXT: s_and_not1_b64 s[2:3], exec, vcc1023; GFX12-NEXT: s_and_not1_b64 s[0:1], s[0:1], s[2:3]1024; GFX12-NEXT: s_and_b64 exec, exec, s[0:1]1025; GFX12-NEXT: s_mov_b32 m0, 01026; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)1027; GFX12-NEXT: s_endpgm1028; GFX12-NEXT: ; %bb.1:1029; GFX12-NEXT: s_mov_b64 exec, 01030; GFX12-NEXT: s_endpgm1031 %c1 = fcmp ule float %a, 2.01032 call void @llvm.amdgcn.kill(i1 %c1)1033 call void @llvm.amdgcn.s.sendmsg(i32 3, i32 0)1034 ret void1035}1036 1037; Should use v_cmp_eq_f32_e32 vcc, 01038define amdgpu_gs void @une(float %a) {1039; SI-LABEL: une:1040; SI: ; %bb.0:1041; SI-NEXT: v_cmp_eq_f32_e32 vcc, 0, v01042; SI-NEXT: s_andn2_b64 exec, exec, vcc1043; SI-NEXT: s_andn2_b64 exec, exec, vcc1044; SI-NEXT: s_mov_b32 m0, 01045; SI-NEXT: s_nop 01046; SI-NEXT: s_sendmsg sendmsg(MSG_GS_DONE, GS_OP_NOP)1047; SI-NEXT: s_endpgm1048; SI-NEXT: ; %bb.1:1049; SI-NEXT: s_mov_b64 exec, 01050; SI-NEXT: s_endpgm1051;1052; GFX10-LABEL: une:1053; GFX10: ; %bb.0:1054; GFX10-NEXT: v_cmp_eq_f32_e32 vcc, 0, v01055; GFX10-NEXT: s_andn2_b64 exec, exec, vcc1056; GFX10-NEXT: s_andn2_b64 exec, exec, vcc1057; GFX10-NEXT: s_mov_b32 m0, 01058; GFX10-NEXT: s_sendmsg sendmsg(MSG_GS_DONE, GS_OP_NOP)1059; GFX10-NEXT: s_endpgm1060; GFX10-NEXT: ; %bb.1:1061; GFX10-NEXT: s_mov_b64 exec, 01062; GFX10-NEXT: s_endpgm1063;1064; GFX11-LABEL: une:1065; GFX11: ; %bb.0:1066; GFX11-NEXT: v_cmp_eq_f32_e32 vcc, 0, v01067; GFX11-NEXT: s_and_not1_b64 exec, exec, vcc1068; GFX11-NEXT: s_and_not1_b64 exec, exec, vcc1069; GFX11-NEXT: s_mov_b32 m0, 01070; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)1071; GFX11-NEXT: s_endpgm1072; GFX11-NEXT: ; %bb.1:1073; GFX11-NEXT: s_mov_b64 exec, 01074; GFX11-NEXT: s_endpgm1075;1076; GFX12-LABEL: une:1077; GFX12: ; %bb.0:1078; GFX12-NEXT: v_cmp_neq_f32_e32 vcc, 0, v01079; GFX12-NEXT: s_mov_b64 s[0:1], exec1080; GFX12-NEXT: s_and_not1_b64 s[2:3], exec, vcc1081; GFX12-NEXT: s_and_not1_b64 s[0:1], s[0:1], s[2:3]1082; GFX12-NEXT: s_and_b64 exec, exec, s[0:1]1083; GFX12-NEXT: s_mov_b32 m0, 01084; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)1085; GFX12-NEXT: s_endpgm1086; GFX12-NEXT: ; %bb.1:1087; GFX12-NEXT: s_mov_b64 exec, 01088; GFX12-NEXT: s_endpgm1089 %c1 = fcmp une float %a, 0.01090 call void @llvm.amdgcn.kill(i1 %c1)1091 call void @llvm.amdgcn.s.sendmsg(i32 3, i32 0)1092 ret void1093}1094 1095; Should use v_cmp_gt_f32_e32 vcc, 1.01096define amdgpu_gs void @neg_olt(float %a) {1097; SI-LABEL: neg_olt:1098; SI: ; %bb.0:1099; SI-NEXT: v_cmp_gt_f32_e32 vcc, 1.0, v01100; SI-NEXT: s_andn2_b64 exec, exec, vcc1101; SI-NEXT: s_andn2_b64 exec, exec, vcc1102; SI-NEXT: s_mov_b32 m0, 01103; SI-NEXT: s_nop 01104; SI-NEXT: s_sendmsg sendmsg(MSG_GS_DONE, GS_OP_NOP)1105; SI-NEXT: s_endpgm1106; SI-NEXT: ; %bb.1:1107; SI-NEXT: s_mov_b64 exec, 01108; SI-NEXT: s_endpgm1109;1110; GFX10-LABEL: neg_olt:1111; GFX10: ; %bb.0:1112; GFX10-NEXT: v_cmp_gt_f32_e32 vcc, 1.0, v01113; GFX10-NEXT: s_andn2_b64 exec, exec, vcc1114; GFX10-NEXT: s_andn2_b64 exec, exec, vcc1115; GFX10-NEXT: s_mov_b32 m0, 01116; GFX10-NEXT: s_sendmsg sendmsg(MSG_GS_DONE, GS_OP_NOP)1117; GFX10-NEXT: s_endpgm1118; GFX10-NEXT: ; %bb.1:1119; GFX10-NEXT: s_mov_b64 exec, 01120; GFX10-NEXT: s_endpgm1121;1122; GFX11-LABEL: neg_olt:1123; GFX11: ; %bb.0:1124; GFX11-NEXT: v_cmp_gt_f32_e32 vcc, 1.0, v01125; GFX11-NEXT: s_and_not1_b64 exec, exec, vcc1126; GFX11-NEXT: s_and_not1_b64 exec, exec, vcc1127; GFX11-NEXT: s_mov_b32 m0, 01128; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)1129; GFX11-NEXT: s_endpgm1130; GFX11-NEXT: ; %bb.1:1131; GFX11-NEXT: s_mov_b64 exec, 01132; GFX11-NEXT: s_endpgm1133;1134; GFX12-LABEL: neg_olt:1135; GFX12: ; %bb.0:1136; GFX12-NEXT: v_cmp_ngt_f32_e32 vcc, 1.0, v01137; GFX12-NEXT: s_mov_b64 s[0:1], exec1138; GFX12-NEXT: s_and_not1_b64 s[2:3], exec, vcc1139; GFX12-NEXT: s_and_not1_b64 s[0:1], s[0:1], s[2:3]1140; GFX12-NEXT: s_and_b64 exec, exec, s[0:1]1141; GFX12-NEXT: s_mov_b32 m0, 01142; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)1143; GFX12-NEXT: s_endpgm1144; GFX12-NEXT: ; %bb.1:1145; GFX12-NEXT: s_mov_b64 exec, 01146; GFX12-NEXT: s_endpgm1147 %c1 = fcmp olt float %a, 1.01148 %c2 = xor i1 %c1, 11149 call void @llvm.amdgcn.kill(i1 %c2)1150 call void @llvm.amdgcn.s.sendmsg(i32 3, i32 0)1151 ret void1152}1153 1154; FIXME: LLVM should be able to combine these fcmp opcodes.1155define amdgpu_ps void @fcmp_x2(float %a) #0 {1156; SI-LABEL: fcmp_x2:1157; SI: ; %bb.0:1158; SI-NEXT: s_mov_b32 s0, 0x3e8000001159; SI-NEXT: v_cmp_lt_f32_e32 vcc, s0, v01160; SI-NEXT: v_cndmask_b32_e64 v0, 0, -1.0, vcc1161; SI-NEXT: v_cmp_nle_f32_e32 vcc, 0, v01162; SI-NEXT: s_andn2_b64 exec, exec, vcc1163; SI-NEXT: s_cbranch_scc0 .LBB21_11164; SI-NEXT: s_endpgm1165; SI-NEXT: .LBB21_1:1166; SI-NEXT: s_mov_b64 exec, 01167; SI-NEXT: exp null off, off, off, off done vm1168; SI-NEXT: s_endpgm1169;1170; GFX10-LABEL: fcmp_x2:1171; GFX10: ; %bb.0:1172; GFX10-NEXT: v_cmp_lt_f32_e32 vcc, 0x3e800000, v01173; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, -1.0, vcc1174; GFX10-NEXT: v_cmp_nle_f32_e32 vcc, 0, v01175; GFX10-NEXT: s_andn2_b64 exec, exec, vcc1176; GFX10-NEXT: s_cbranch_scc0 .LBB21_11177; GFX10-NEXT: s_endpgm1178; GFX10-NEXT: .LBB21_1:1179; GFX10-NEXT: s_mov_b64 exec, 01180; GFX10-NEXT: exp null off, off, off, off done vm1181; GFX10-NEXT: s_endpgm1182;1183; GFX11-LABEL: fcmp_x2:1184; GFX11: ; %bb.0:1185; GFX11-NEXT: v_cmp_lt_f32_e32 vcc, 0x3e800000, v01186; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, -1.0, vcc1187; GFX11-NEXT: v_cmp_nle_f32_e32 vcc, 0, v01188; GFX11-NEXT: s_waitcnt_depctr depctr_va_vcc(0)1189; GFX11-NEXT: s_and_not1_b64 exec, exec, vcc1190; GFX11-NEXT: s_cbranch_scc0 .LBB21_11191; GFX11-NEXT: s_endpgm1192; GFX11-NEXT: .LBB21_1:1193; GFX11-NEXT: s_mov_b64 exec, 01194; GFX11-NEXT: exp mrt0 off, off, off, off done1195; GFX11-NEXT: s_endpgm1196;1197; GFX12-LABEL: fcmp_x2:1198; GFX12: ; %bb.0:1199; GFX12-NEXT: v_cmp_lt_f32_e32 vcc, 0x3e800000, v01200; GFX12-NEXT: v_cndmask_b32_e64 v0, 0, -1.0, vcc1201; GFX12-NEXT: v_cmp_le_f32_e32 vcc, 0, v01202; GFX12-NEXT: s_and_not1_b64 s[2:3], exec, vcc1203; GFX12-NEXT: s_and_not1_b64 s[0:1], exec, s[2:3]1204; GFX12-NEXT: s_cbranch_scc0 .LBB21_11205; GFX12-NEXT: s_endpgm1206; GFX12-NEXT: .LBB21_1:1207; GFX12-NEXT: s_mov_b64 exec, 01208; GFX12-NEXT: export mrt0 off, off, off, off done1209; GFX12-NEXT: s_endpgm1210 %ogt = fcmp nsz ogt float %a, 2.500000e-011211 %k = select i1 %ogt, float -1.000000e+00, float 0.000000e+001212 %c = fcmp nsz oge float %k, 0.000000e+001213 call void @llvm.amdgcn.kill(i1 %c) #11214 ret void1215}1216 1217; Note: an almost identical test for this exists in llvm.amdgcn.wqm.vote.ll1218define amdgpu_ps float @wqm(float %a) {1219; SI-LABEL: wqm:1220; SI: ; %bb.0:1221; SI-NEXT: v_cmp_neq_f32_e32 vcc, 0, v01222; SI-NEXT: s_wqm_b64 s[2:3], vcc1223; SI-NEXT: s_mov_b64 s[0:1], exec1224; SI-NEXT: s_andn2_b64 s[2:3], exec, s[2:3]1225; SI-NEXT: s_andn2_b64 s[0:1], s[0:1], s[2:3]1226; SI-NEXT: s_cbranch_scc0 .LBB22_21227; SI-NEXT: ; %bb.1:1228; SI-NEXT: s_and_b64 exec, exec, s[0:1]1229; SI-NEXT: v_mov_b32_e32 v0, 01230; SI-NEXT: s_branch .LBB22_31231; SI-NEXT: .LBB22_2:1232; SI-NEXT: s_mov_b64 exec, 01233; SI-NEXT: exp null off, off, off, off done vm1234; SI-NEXT: s_endpgm1235; SI-NEXT: .LBB22_3:1236;1237; GFX10-LABEL: wqm:1238; GFX10: ; %bb.0:1239; GFX10-NEXT: v_cmp_neq_f32_e32 vcc, 0, v01240; GFX10-NEXT: s_mov_b64 s[0:1], exec1241; GFX10-NEXT: s_wqm_b64 s[2:3], vcc1242; GFX10-NEXT: s_andn2_b64 s[2:3], exec, s[2:3]1243; GFX10-NEXT: s_andn2_b64 s[0:1], s[0:1], s[2:3]1244; GFX10-NEXT: s_cbranch_scc0 .LBB22_21245; GFX10-NEXT: ; %bb.1:1246; GFX10-NEXT: s_and_b64 exec, exec, s[0:1]1247; GFX10-NEXT: v_mov_b32_e32 v0, 01248; GFX10-NEXT: s_branch .LBB22_31249; GFX10-NEXT: .LBB22_2:1250; GFX10-NEXT: s_mov_b64 exec, 01251; GFX10-NEXT: exp null off, off, off, off done vm1252; GFX10-NEXT: s_endpgm1253; GFX10-NEXT: .LBB22_3:1254;1255; GFX11-LABEL: wqm:1256; GFX11: ; %bb.0:1257; GFX11-NEXT: v_cmp_neq_f32_e32 vcc, 0, v01258; GFX11-NEXT: s_mov_b64 s[0:1], exec1259; GFX11-NEXT: s_wqm_b64 s[2:3], vcc1260; GFX11-NEXT: s_and_not1_b64 s[2:3], exec, s[2:3]1261; GFX11-NEXT: s_and_not1_b64 s[0:1], s[0:1], s[2:3]1262; GFX11-NEXT: s_cbranch_scc0 .LBB22_21263; GFX11-NEXT: ; %bb.1:1264; GFX11-NEXT: s_and_b64 exec, exec, s[0:1]1265; GFX11-NEXT: v_mov_b32_e32 v0, 01266; GFX11-NEXT: s_branch .LBB22_31267; GFX11-NEXT: .LBB22_2:1268; GFX11-NEXT: s_mov_b64 exec, 01269; GFX11-NEXT: exp mrt0 off, off, off, off done1270; GFX11-NEXT: s_endpgm1271; GFX11-NEXT: .LBB22_3:1272;1273; GFX12-LABEL: wqm:1274; GFX12: ; %bb.0:1275; GFX12-NEXT: v_cmp_neq_f32_e32 vcc, 0, v01276; GFX12-NEXT: s_mov_b64 s[0:1], exec1277; GFX12-NEXT: s_wqm_b64 s[2:3], vcc1278; GFX12-NEXT: s_and_not1_b64 s[2:3], exec, s[2:3]1279; GFX12-NEXT: s_and_not1_b64 s[0:1], s[0:1], s[2:3]1280; GFX12-NEXT: s_cbranch_scc0 .LBB22_21281; GFX12-NEXT: ; %bb.1:1282; GFX12-NEXT: s_and_b64 exec, exec, s[0:1]1283; GFX12-NEXT: v_mov_b32_e32 v0, 01284; GFX12-NEXT: s_branch .LBB22_31285; GFX12-NEXT: .LBB22_2:1286; GFX12-NEXT: s_mov_b64 exec, 01287; GFX12-NEXT: export mrt0 off, off, off, off done1288; GFX12-NEXT: s_endpgm1289; GFX12-NEXT: .LBB22_3:1290 %c1 = fcmp une float %a, 0.01291 %c2 = call i1 @llvm.amdgcn.wqm.vote(i1 %c1)1292 call void @llvm.amdgcn.kill(i1 %c2)1293 ret float 0.01294}1295 1296; This checks that we use the 64-bit encoding when the operand is a SGPR.1297define amdgpu_ps void @test_sgpr(float inreg %a) #0 {1298; SI-LABEL: test_sgpr:1299; SI: ; %bb.0:1300; SI-NEXT: v_cmp_nle_f32_e64 vcc, s0, 1.01301; SI-NEXT: s_andn2_b64 exec, exec, vcc1302; SI-NEXT: s_cbranch_scc0 .LBB23_11303; SI-NEXT: s_endpgm1304; SI-NEXT: .LBB23_1:1305; SI-NEXT: s_mov_b64 exec, 01306; SI-NEXT: exp null off, off, off, off done vm1307; SI-NEXT: s_endpgm1308;1309; GFX10-LABEL: test_sgpr:1310; GFX10: ; %bb.0:1311; GFX10-NEXT: v_cmp_nle_f32_e64 vcc, s0, 1.01312; GFX10-NEXT: s_andn2_b64 exec, exec, vcc1313; GFX10-NEXT: s_cbranch_scc0 .LBB23_11314; GFX10-NEXT: s_endpgm1315; GFX10-NEXT: .LBB23_1:1316; GFX10-NEXT: s_mov_b64 exec, 01317; GFX10-NEXT: exp null off, off, off, off done vm1318; GFX10-NEXT: s_endpgm1319;1320; GFX11-LABEL: test_sgpr:1321; GFX11: ; %bb.0:1322; GFX11-NEXT: v_cmp_nle_f32_e64 vcc, s0, 1.01323; GFX11-NEXT: s_and_not1_b64 exec, exec, vcc1324; GFX11-NEXT: s_cbranch_scc0 .LBB23_11325; GFX11-NEXT: s_endpgm1326; GFX11-NEXT: .LBB23_1:1327; GFX11-NEXT: s_mov_b64 exec, 01328; GFX11-NEXT: exp mrt0 off, off, off, off done1329; GFX11-NEXT: s_endpgm1330;1331; GFX12-LABEL: test_sgpr:1332; GFX12: ; %bb.0:1333; GFX12-NEXT: s_cmp_le_f32 s0, 1.01334; GFX12-NEXT: s_cselect_b64 s[0:1], -1, 01335; GFX12-NEXT: s_and_not1_b64 s[0:1], exec, s[0:1]1336; GFX12-NEXT: s_and_not1_b64 s[2:3], exec, s[0:1]1337; GFX12-NEXT: s_cbranch_scc0 .LBB23_11338; GFX12-NEXT: s_endpgm1339; GFX12-NEXT: .LBB23_1:1340; GFX12-NEXT: s_mov_b64 exec, 01341; GFX12-NEXT: export mrt0 off, off, off, off done1342; GFX12-NEXT: s_endpgm1343 %c = fcmp ole float %a, 1.000000e+001344 call void @llvm.amdgcn.kill(i1 %c) #11345 ret void1346}1347 1348define amdgpu_ps void @test_non_inline_imm_sgpr(float inreg %a) #0 {1349; SI-LABEL: test_non_inline_imm_sgpr:1350; SI: ; %bb.0:1351; SI-NEXT: v_mov_b32_e32 v0, 0x3fc000001352; SI-NEXT: v_cmp_le_f32_e32 vcc, s0, v01353; SI-NEXT: s_andn2_b64 s[0:1], exec, vcc1354; SI-NEXT: s_andn2_b64 s[2:3], exec, s[0:1]1355; SI-NEXT: s_cbranch_scc0 .LBB24_11356; SI-NEXT: s_endpgm1357; SI-NEXT: .LBB24_1:1358; SI-NEXT: s_mov_b64 exec, 01359; SI-NEXT: exp null off, off, off, off done vm1360; SI-NEXT: s_endpgm1361;1362; GFX10-LABEL: test_non_inline_imm_sgpr:1363; GFX10: ; %bb.0:1364; GFX10-NEXT: v_cmp_ge_f32_e64 s[0:1], 0x3fc00000, s01365; GFX10-NEXT: s_andn2_b64 s[0:1], exec, s[0:1]1366; GFX10-NEXT: s_andn2_b64 s[2:3], exec, s[0:1]1367; GFX10-NEXT: s_cbranch_scc0 .LBB24_11368; GFX10-NEXT: s_endpgm1369; GFX10-NEXT: .LBB24_1:1370; GFX10-NEXT: s_mov_b64 exec, 01371; GFX10-NEXT: exp null off, off, off, off done vm1372; GFX10-NEXT: s_endpgm1373;1374; GFX11-LABEL: test_non_inline_imm_sgpr:1375; GFX11: ; %bb.0:1376; GFX11-NEXT: v_cmp_ge_f32_e64 s[0:1], 0x3fc00000, s01377; GFX11-NEXT: s_and_not1_b64 s[0:1], exec, s[0:1]1378; GFX11-NEXT: s_and_not1_b64 s[2:3], exec, s[0:1]1379; GFX11-NEXT: s_cbranch_scc0 .LBB24_11380; GFX11-NEXT: s_endpgm1381; GFX11-NEXT: .LBB24_1:1382; GFX11-NEXT: s_mov_b64 exec, 01383; GFX11-NEXT: exp mrt0 off, off, off, off done1384; GFX11-NEXT: s_endpgm1385;1386; GFX12-LABEL: test_non_inline_imm_sgpr:1387; GFX12: ; %bb.0:1388; GFX12-NEXT: s_cmp_le_f32 s0, 0x3fc000001389; GFX12-NEXT: s_cselect_b64 s[0:1], -1, 01390; GFX12-NEXT: s_and_not1_b64 s[0:1], exec, s[0:1]1391; GFX12-NEXT: s_and_not1_b64 s[2:3], exec, s[0:1]1392; GFX12-NEXT: s_cbranch_scc0 .LBB24_11393; GFX12-NEXT: s_endpgm1394; GFX12-NEXT: .LBB24_1:1395; GFX12-NEXT: s_mov_b64 exec, 01396; GFX12-NEXT: export mrt0 off, off, off, off done1397; GFX12-NEXT: s_endpgm1398 %c = fcmp ole float %a, 1.500000e+001399 call void @llvm.amdgcn.kill(i1 %c) #11400 ret void1401}1402 1403define amdgpu_ps void @test_scc_liveness() #0 {1404; SI-LABEL: test_scc_liveness:1405; SI: ; %bb.0: ; %main_body1406; SI-NEXT: s_mov_b64 s[0:1], exec1407; SI-NEXT: s_mov_b32 s2, 01408; SI-NEXT: .LBB25_1: ; %loop31409; SI-NEXT: ; =>This Inner Loop Header: Depth=11410; SI-NEXT: s_cmp_gt_i32 s2, 01411; SI-NEXT: s_cselect_b64 s[4:5], -1, 01412; SI-NEXT: s_andn2_b64 s[4:5], exec, s[4:5]1413; SI-NEXT: s_andn2_b64 s[0:1], s[0:1], s[4:5]1414; SI-NEXT: s_cbranch_scc0 .LBB25_41415; SI-NEXT: ; %bb.2: ; %loop31416; SI-NEXT: ; in Loop: Header=BB25_1 Depth=11417; SI-NEXT: s_and_b64 exec, exec, s[0:1]1418; SI-NEXT: s_add_i32 s3, s2, 11419; SI-NEXT: s_cmp_lt_i32 s2, 11420; SI-NEXT: s_mov_b32 s2, s31421; SI-NEXT: s_cbranch_scc1 .LBB25_11422; SI-NEXT: ; %bb.3: ; %endloop151423; SI-NEXT: s_endpgm1424; SI-NEXT: .LBB25_4:1425; SI-NEXT: s_mov_b64 exec, 01426; SI-NEXT: exp null off, off, off, off done vm1427; SI-NEXT: s_endpgm1428;1429; GFX10-LABEL: test_scc_liveness:1430; GFX10: ; %bb.0: ; %main_body1431; GFX10-NEXT: s_mov_b64 s[0:1], exec1432; GFX10-NEXT: s_mov_b32 s2, 01433; GFX10-NEXT: .LBB25_1: ; %loop31434; GFX10-NEXT: ; =>This Inner Loop Header: Depth=11435; GFX10-NEXT: s_cmp_gt_i32 s2, 01436; GFX10-NEXT: s_cselect_b64 s[4:5], -1, 01437; GFX10-NEXT: s_andn2_b64 s[4:5], exec, s[4:5]1438; GFX10-NEXT: s_andn2_b64 s[0:1], s[0:1], s[4:5]1439; GFX10-NEXT: s_cbranch_scc0 .LBB25_41440; GFX10-NEXT: ; %bb.2: ; %loop31441; GFX10-NEXT: ; in Loop: Header=BB25_1 Depth=11442; GFX10-NEXT: s_and_b64 exec, exec, s[0:1]1443; GFX10-NEXT: s_add_i32 s3, s2, 11444; GFX10-NEXT: s_cmp_lt_i32 s2, 11445; GFX10-NEXT: s_mov_b32 s2, s31446; GFX10-NEXT: s_cbranch_scc1 .LBB25_11447; GFX10-NEXT: ; %bb.3: ; %endloop151448; GFX10-NEXT: s_endpgm1449; GFX10-NEXT: .LBB25_4:1450; GFX10-NEXT: s_mov_b64 exec, 01451; GFX10-NEXT: exp null off, off, off, off done vm1452; GFX10-NEXT: s_endpgm1453;1454; GFX11-LABEL: test_scc_liveness:1455; GFX11: ; %bb.0: ; %main_body1456; GFX11-NEXT: s_mov_b64 s[0:1], exec1457; GFX11-NEXT: s_mov_b32 s2, 01458; GFX11-NEXT: .LBB25_1: ; %loop31459; GFX11-NEXT: ; =>This Inner Loop Header: Depth=11460; GFX11-NEXT: s_cmp_gt_i32 s2, 01461; GFX11-NEXT: s_cselect_b64 s[4:5], -1, 01462; GFX11-NEXT: s_and_not1_b64 s[4:5], exec, s[4:5]1463; GFX11-NEXT: s_and_not1_b64 s[0:1], s[0:1], s[4:5]1464; GFX11-NEXT: s_cbranch_scc0 .LBB25_41465; GFX11-NEXT: ; %bb.2: ; %loop31466; GFX11-NEXT: ; in Loop: Header=BB25_1 Depth=11467; GFX11-NEXT: s_and_b64 exec, exec, s[0:1]1468; GFX11-NEXT: s_add_i32 s3, s2, 11469; GFX11-NEXT: s_cmp_lt_i32 s2, 11470; GFX11-NEXT: s_mov_b32 s2, s31471; GFX11-NEXT: s_cbranch_scc1 .LBB25_11472; GFX11-NEXT: ; %bb.3: ; %endloop151473; GFX11-NEXT: s_endpgm1474; GFX11-NEXT: .LBB25_4:1475; GFX11-NEXT: s_mov_b64 exec, 01476; GFX11-NEXT: exp mrt0 off, off, off, off done1477; GFX11-NEXT: s_endpgm1478;1479; GFX12-LABEL: test_scc_liveness:1480; GFX12: ; %bb.0: ; %main_body1481; GFX12-NEXT: s_mov_b64 s[0:1], exec1482; GFX12-NEXT: s_mov_b32 s2, 01483; GFX12-NEXT: .LBB25_1: ; %loop31484; GFX12-NEXT: ; =>This Inner Loop Header: Depth=11485; GFX12-NEXT: s_cmp_gt_i32 s2, 01486; GFX12-NEXT: s_cselect_b64 s[4:5], -1, 01487; GFX12-NEXT: s_and_not1_b64 s[4:5], exec, s[4:5]1488; GFX12-NEXT: s_and_not1_b64 s[0:1], s[0:1], s[4:5]1489; GFX12-NEXT: s_cbranch_scc0 .LBB25_41490; GFX12-NEXT: ; %bb.2: ; %loop31491; GFX12-NEXT: ; in Loop: Header=BB25_1 Depth=11492; GFX12-NEXT: s_and_b64 exec, exec, s[0:1]1493; GFX12-NEXT: s_add_co_i32 s3, s2, 11494; GFX12-NEXT: s_cmp_lt_i32 s2, 11495; GFX12-NEXT: s_mov_b32 s2, s31496; GFX12-NEXT: s_cbranch_scc1 .LBB25_11497; GFX12-NEXT: ; %bb.3: ; %endloop151498; GFX12-NEXT: s_endpgm1499; GFX12-NEXT: .LBB25_4:1500; GFX12-NEXT: s_mov_b64 exec, 01501; GFX12-NEXT: export mrt0 off, off, off, off done1502; GFX12-NEXT: s_endpgm1503main_body:1504 br label %loop31505 1506loop3: ; preds = %loop3, %main_body1507 %tmp = phi i32 [ 0, %main_body ], [ %tmp5, %loop3 ]1508 %tmp1 = icmp sgt i32 %tmp, 01509 call void @llvm.amdgcn.kill(i1 %tmp1) #11510 %tmp5 = add i32 %tmp, 11511 br i1 %tmp1, label %endloop15, label %loop31512 1513endloop15: ; preds = %loop31514 ret void1515}1516 1517; Check this compiles.1518; If kill is marked as defining VCC then this will fail with live interval issues.1519define amdgpu_ps void @kill_with_loop_exit(float inreg %inp0, float inreg %inp1, <4 x i32> inreg %inp2, float inreg %inp3) {1520; SI-LABEL: kill_with_loop_exit:1521; SI: ; %bb.0: ; %.entry1522; SI-NEXT: v_mov_b32_e32 v0, 0x430000001523; SI-NEXT: v_cmp_lt_f32_e32 vcc, s0, v01524; SI-NEXT: v_cmp_lt_f32_e64 s[0:1], s1, v01525; SI-NEXT: s_and_b64 s[0:1], vcc, s[0:1]1526; SI-NEXT: s_and_b64 vcc, exec, s[0:1]1527; SI-NEXT: v_mov_b32_e32 v0, 1.01528; SI-NEXT: s_cbranch_vccnz .LBB26_51529; SI-NEXT: ; %bb.1: ; %.preheader1.preheader1530; SI-NEXT: v_cmp_ngt_f32_e64 s[0:1], s6, 01531; SI-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1]1532; SI-NEXT: s_mov_b64 s[2:3], exec1533; SI-NEXT: v_mov_b32_e32 v0, 0x3fc000001534; SI-NEXT: v_cmp_ne_u32_e64 s[0:1], 1, v11535; SI-NEXT: .LBB26_2: ; %bb1536; SI-NEXT: ; =>This Inner Loop Header: Depth=11537; SI-NEXT: s_and_b64 vcc, exec, s[0:1]1538; SI-NEXT: v_add_f32_e32 v0, 0x3e800000, v01539; SI-NEXT: s_cbranch_vccnz .LBB26_21540; SI-NEXT: ; %bb.3: ; %bb331541; SI-NEXT: s_andn2_b64 s[2:3], s[2:3], exec1542; SI-NEXT: s_cbranch_scc0 .LBB26_61543; SI-NEXT: ; %bb.4: ; %bb331544; SI-NEXT: s_mov_b64 exec, 01545; SI-NEXT: .LBB26_5: ; %bb351546; SI-NEXT: exp mrt0 v0, v0, v0, v0 done vm1547; SI-NEXT: s_endpgm1548; SI-NEXT: .LBB26_6:1549; SI-NEXT: s_mov_b64 exec, 01550; SI-NEXT: exp null off, off, off, off done vm1551; SI-NEXT: s_endpgm1552;1553; GFX10-LABEL: kill_with_loop_exit:1554; GFX10: ; %bb.0: ; %.entry1555; GFX10-NEXT: v_cmp_gt_f32_e64 s[4:5], 0x43000000, s01556; GFX10-NEXT: v_cmp_gt_f32_e64 s[0:1], 0x43000000, s11557; GFX10-NEXT: v_mov_b32_e32 v0, 1.01558; GFX10-NEXT: s_and_b64 s[0:1], s[4:5], s[0:1]1559; GFX10-NEXT: s_and_b64 vcc, exec, s[0:1]1560; GFX10-NEXT: s_cbranch_vccnz .LBB26_51561; GFX10-NEXT: ; %bb.1: ; %.preheader1.preheader1562; GFX10-NEXT: v_cmp_ngt_f32_e64 s[0:1], s6, 01563; GFX10-NEXT: v_mov_b32_e32 v0, 0x3fc000001564; GFX10-NEXT: s_mov_b64 s[2:3], exec1565; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1]1566; GFX10-NEXT: v_cmp_ne_u32_e64 s[0:1], 1, v11567; GFX10-NEXT: .LBB26_2: ; %bb1568; GFX10-NEXT: ; =>This Inner Loop Header: Depth=11569; GFX10-NEXT: v_add_f32_e32 v0, 0x3e800000, v01570; GFX10-NEXT: s_and_b64 vcc, exec, s[0:1]1571; GFX10-NEXT: s_cbranch_vccnz .LBB26_21572; GFX10-NEXT: ; %bb.3: ; %bb331573; GFX10-NEXT: s_andn2_b64 s[2:3], s[2:3], exec1574; GFX10-NEXT: s_cbranch_scc0 .LBB26_61575; GFX10-NEXT: ; %bb.4: ; %bb331576; GFX10-NEXT: s_mov_b64 exec, 01577; GFX10-NEXT: .LBB26_5: ; %bb351578; GFX10-NEXT: exp mrt0 v0, v0, v0, v0 done vm1579; GFX10-NEXT: s_endpgm1580; GFX10-NEXT: .LBB26_6:1581; GFX10-NEXT: s_mov_b64 exec, 01582; GFX10-NEXT: exp null off, off, off, off done vm1583; GFX10-NEXT: s_endpgm1584;1585; GFX11-LABEL: kill_with_loop_exit:1586; GFX11: ; %bb.0: ; %.entry1587; GFX11-NEXT: v_cmp_gt_f32_e64 s[4:5], 0x43000000, s01588; GFX11-NEXT: v_cmp_gt_f32_e64 s[0:1], 0x43000000, s11589; GFX11-NEXT: v_mov_b32_e32 v0, 1.01590; GFX11-NEXT: s_and_b64 s[0:1], s[4:5], s[0:1]1591; GFX11-NEXT: s_and_b64 vcc, exec, s[0:1]1592; GFX11-NEXT: s_cbranch_vccnz .LBB26_51593; GFX11-NEXT: ; %bb.1: ; %.preheader1.preheader1594; GFX11-NEXT: v_cmp_ngt_f32_e64 s[0:1], s6, 01595; GFX11-NEXT: v_mov_b32_e32 v0, 0x3fc000001596; GFX11-NEXT: s_mov_b64 s[2:3], exec1597; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1]1598; GFX11-NEXT: v_cmp_ne_u32_e64 s[0:1], 1, v11599; GFX11-NEXT: s_waitcnt_depctr depctr_va_sdst(0)1600; GFX11-NEXT: .LBB26_2: ; %bb1601; GFX11-NEXT: ; =>This Inner Loop Header: Depth=11602; GFX11-NEXT: v_add_f32_e32 v0, 0x3e800000, v01603; GFX11-NEXT: s_and_b64 vcc, exec, s[0:1]1604; GFX11-NEXT: s_cbranch_vccnz .LBB26_21605; GFX11-NEXT: ; %bb.3: ; %bb331606; GFX11-NEXT: s_and_not1_b64 s[2:3], s[2:3], exec1607; GFX11-NEXT: s_cbranch_scc0 .LBB26_61608; GFX11-NEXT: ; %bb.4: ; %bb331609; GFX11-NEXT: s_mov_b64 exec, 01610; GFX11-NEXT: .LBB26_5: ; %bb351611; GFX11-NEXT: exp mrt0 v0, v0, v0, v0 done1612; GFX11-NEXT: s_endpgm1613; GFX11-NEXT: .LBB26_6:1614; GFX11-NEXT: s_mov_b64 exec, 01615; GFX11-NEXT: exp mrt0 off, off, off, off done1616; GFX11-NEXT: s_endpgm1617;1618; GFX12-LABEL: kill_with_loop_exit:1619; GFX12: ; %bb.0: ; %.entry1620; GFX12-NEXT: s_cmp_lt_f32 s0, 0x430000001621; GFX12-NEXT: s_cselect_b64 s[4:5], -1, 01622; GFX12-NEXT: s_cmp_lt_f32 s1, 0x430000001623; GFX12-NEXT: s_cselect_b64 s[0:1], -1, 01624; GFX12-NEXT: s_and_b64 s[0:1], s[4:5], s[0:1]1625; GFX12-NEXT: s_mov_b32 s4, 1.01626; GFX12-NEXT: s_and_b64 vcc, exec, s[0:1]1627; GFX12-NEXT: s_cbranch_vccnz .LBB26_51628; GFX12-NEXT: ; %bb.1: ; %.preheader1.preheader1629; GFX12-NEXT: s_cmp_ngt_f32 s6, 01630; GFX12-NEXT: s_mov_b64 s[2:3], exec1631; GFX12-NEXT: s_mov_b32 s4, 0x3fc000001632; GFX12-NEXT: s_cselect_b64 s[0:1], -1, 01633; GFX12-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]1634; GFX12-NEXT: v_cmp_ne_u32_e64 s[0:1], 1, v01635; GFX12-NEXT: .LBB26_2: ; %bb1636; GFX12-NEXT: ; =>This Inner Loop Header: Depth=11637; GFX12-NEXT: s_add_f32 s4, s4, 0x3e8000001638; GFX12-NEXT: s_and_b64 vcc, exec, s[0:1]1639; GFX12-NEXT: s_cbranch_vccnz .LBB26_21640; GFX12-NEXT: ; %bb.3: ; %bb331641; GFX12-NEXT: s_and_not1_b64 s[2:3], s[2:3], exec1642; GFX12-NEXT: s_cbranch_scc0 .LBB26_61643; GFX12-NEXT: ; %bb.4: ; %bb331644; GFX12-NEXT: s_mov_b64 exec, 01645; GFX12-NEXT: .LBB26_5: ; %bb351646; GFX12-NEXT: v_mov_b32_e32 v0, s41647; GFX12-NEXT: export mrt0 v0, v0, v0, v0 done1648; GFX12-NEXT: s_endpgm1649; GFX12-NEXT: .LBB26_6:1650; GFX12-NEXT: s_mov_b64 exec, 01651; GFX12-NEXT: export mrt0 off, off, off, off done1652; GFX12-NEXT: s_endpgm1653.entry:1654 %tmp24 = fcmp olt float %inp0, 1.280000e+021655 %tmp25 = fcmp olt float %inp1, 1.280000e+021656 %tmp26 = and i1 %tmp24, %tmp251657 br i1 %tmp26, label %bb35, label %.preheader1.preheader1658 1659.preheader1.preheader: ; preds = %.entry1660 %tmp31 = fcmp ogt float %inp3, 0.01661 br label %bb1662 1663bb: ; preds = %bb, %.preheader1.preheader1664 %tmp30 = phi float [ %tmp32, %bb ], [ 1.500000e+00, %.preheader1.preheader ]1665 %tmp32 = fadd reassoc nnan nsz arcp contract float %tmp30, 2.500000e-011666 %tmp34 = fadd reassoc nnan nsz arcp contract float %tmp30, 2.500000e-011667 br i1 %tmp31, label %bb, label %bb331668 1669bb33: ; preds = %bb1670 call void @llvm.amdgcn.kill(i1 false)1671 br label %bb351672 1673bb35: ; preds = %bb33, %.entry1674 %tmp36 = phi float [ %tmp34, %bb33 ], [ 1.000000e+00, %.entry ]1675 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %tmp36, float %tmp36, float %tmp36, float %tmp36, i1 true, i1 true) #31676 ret void1677}1678 1679declare void @llvm.amdgcn.kill(i1) #01680declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #01681declare void @llvm.amdgcn.s.sendmsg(i32, i32) #01682declare i1 @llvm.amdgcn.wqm.vote(i1)1683 1684attributes #0 = { nounwind }1685