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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-SDAG %s3; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-GISEL %s4 5declare i32 @llvm.amdgcn.global.load.monitor.b32.i32(ptr addrspace(1), i32)6declare <2 x i32> @llvm.amdgcn.global.load.monitor.b64.v2i32(ptr addrspace(1), i32)7declare <4 x i32> @llvm.amdgcn.global.load.monitor.b128.v4i32(ptr addrspace(1), i32)8declare i32 @llvm.amdgcn.flat.load.monitor.b32.i32(ptr, i32)9declare <2 x i32> @llvm.amdgcn.flat.load.monitor.b64.v2i32(ptr, i32)10declare <4 x i32> @llvm.amdgcn.flat.load.monitor.b128.v4i32(ptr, i32)11 12define amdgpu_ps void @global_load_monitor_b32_vaddr(ptr addrspace(1) %addr, ptr addrspace(1) %use) {13; GFX1250-LABEL: global_load_monitor_b32_vaddr:14; GFX1250: ; %bb.0: ; %entry15; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 116; GFX1250-NEXT: global_load_monitor_b32 v0, v[0:1], off offset:32 th:TH_LOAD_NT17; GFX1250-NEXT: s_wait_loadcnt 0x018; GFX1250-NEXT: global_store_b32 v[2:3], v0, off19; GFX1250-NEXT: s_endpgm20entry:21 %gep = getelementptr i64, ptr addrspace(1) %addr, i32 422 %val = call i32 @llvm.amdgcn.global.load.monitor.b32.i32(ptr addrspace(1) %gep, i32 1)23 store i32 %val, ptr addrspace(1) %use24 ret void25}26 27define amdgpu_ps void @global_load_monitor_b32_saddr(ptr addrspace(1) inreg %addr, ptr addrspace(1) %use) {28; GFX1250-LABEL: global_load_monitor_b32_saddr:29; GFX1250: ; %bb.0: ; %entry30; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 131; GFX1250-NEXT: v_mov_b32_e32 v2, 032; GFX1250-NEXT: global_load_monitor_b32 v2, v2, s[0:1] offset:32 th:TH_LOAD_HT scope:SCOPE_SE33; GFX1250-NEXT: s_wait_loadcnt 0x034; GFX1250-NEXT: global_store_b32 v[0:1], v2, off35; GFX1250-NEXT: s_endpgm36entry:37 %gep = getelementptr i64, ptr addrspace(1) %addr, i32 438 %val = call i32 @llvm.amdgcn.global.load.monitor.b32.i32(ptr addrspace(1) %gep, i32 10)39 store i32 %val, ptr addrspace(1) %use40 ret void41}42 43define amdgpu_ps void @global_load_monitor_b64_vaddr(ptr addrspace(1) %addr, ptr addrspace(1) %use) {44; GFX1250-LABEL: global_load_monitor_b64_vaddr:45; GFX1250: ; %bb.0: ; %entry46; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 147; GFX1250-NEXT: global_load_monitor_b64 v[0:1], v[0:1], off offset:32 th:TH_LOAD_NT_HT scope:SCOPE_DEV48; GFX1250-NEXT: s_wait_loadcnt 0x049; GFX1250-NEXT: global_store_b64 v[2:3], v[0:1], off50; GFX1250-NEXT: s_endpgm51entry:52 %gep = getelementptr i64, ptr addrspace(1) %addr, i32 453 %val = call <2 x i32> @llvm.amdgcn.global.load.monitor.b64.v2i32(ptr addrspace(1) %gep, i32 22)54 store <2 x i32> %val, ptr addrspace(1) %use55 ret void56}57 58define amdgpu_ps void @global_load_monitor_b64_saddr(ptr addrspace(1) inreg %addr, ptr addrspace(1) %use) {59; GFX1250-LABEL: global_load_monitor_b64_saddr:60; GFX1250: ; %bb.0: ; %entry61; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 162; GFX1250-NEXT: v_mov_b32_e32 v2, 063; GFX1250-NEXT: global_load_monitor_b64 v[2:3], v2, s[0:1] offset:32 th:TH_LOAD_BYPASS scope:SCOPE_SYS64; GFX1250-NEXT: s_wait_loadcnt 0x065; GFX1250-NEXT: global_store_b64 v[0:1], v[2:3], off66; GFX1250-NEXT: s_endpgm67entry:68 %gep = getelementptr i64, ptr addrspace(1) %addr, i32 469 %val = call <2 x i32> @llvm.amdgcn.global.load.monitor.b64.v2i32(ptr addrspace(1) %gep, i32 27)70 store <2 x i32> %val, ptr addrspace(1) %use71 ret void72}73 74define amdgpu_ps void @global_load_monitor_b128_vaddr(ptr addrspace(1) %addr, ptr addrspace(1) %use) {75; GFX1250-LABEL: global_load_monitor_b128_vaddr:76; GFX1250: ; %bb.0: ; %entry77; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 178; GFX1250-NEXT: global_load_monitor_b128 v[4:7], v[0:1], off offset:3279; GFX1250-NEXT: s_wait_loadcnt 0x080; GFX1250-NEXT: global_store_b128 v[2:3], v[4:7], off81; GFX1250-NEXT: s_endpgm82entry:83 %gep = getelementptr i64, ptr addrspace(1) %addr, i32 484 %val = call <4 x i32> @llvm.amdgcn.global.load.monitor.b128.v4i32(ptr addrspace(1) %gep, i32 0)85 store <4 x i32> %val, ptr addrspace(1) %use86 ret void87}88 89define amdgpu_ps void @global_load_monitor_b128_saddr(ptr addrspace(1) inreg %addr, ptr addrspace(1) %use) {90; GFX1250-LABEL: global_load_monitor_b128_saddr:91; GFX1250: ; %bb.0: ; %entry92; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 193; GFX1250-NEXT: v_mov_b32_e32 v2, 094; GFX1250-NEXT: global_load_monitor_b128 v[2:5], v2, s[0:1] offset:32 th:TH_LOAD_NT95; GFX1250-NEXT: s_wait_loadcnt 0x096; GFX1250-NEXT: global_store_b128 v[0:1], v[2:5], off97; GFX1250-NEXT: s_endpgm98entry:99 %gep = getelementptr i64, ptr addrspace(1) %addr, i32 4100 %val = call <4 x i32> @llvm.amdgcn.global.load.monitor.b128.v4i32(ptr addrspace(1) %gep, i32 1)101 store <4 x i32> %val, ptr addrspace(1) %use102 ret void103}104 105define amdgpu_ps void @flat_load_monitor_b32(ptr %addr, ptr addrspace(1) %use) {106; GFX1250-LABEL: flat_load_monitor_b32:107; GFX1250: ; %bb.0: ; %entry108; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1109; GFX1250-NEXT: flat_load_monitor_b32 v0, v[0:1] offset:32 th:TH_LOAD_HT scope:SCOPE_SE110; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0111; GFX1250-NEXT: global_store_b32 v[2:3], v0, off112; GFX1250-NEXT: s_endpgm113entry:114 %gep = getelementptr inbounds i64, ptr addrspace(0) %addr, i32 4115 %val = call i32 @llvm.amdgcn.flat.load.monitor.b32.i32(ptr addrspace(0) %gep, i32 10)116 store i32 %val, ptr addrspace(1) %use117 ret void118}119 120define amdgpu_ps void @flat_load_monitor_b64(ptr %addr, ptr addrspace(1) %use) {121; GFX1250-LABEL: flat_load_monitor_b64:122; GFX1250: ; %bb.0: ; %entry123; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1124; GFX1250-NEXT: flat_load_monitor_b64 v[0:1], v[0:1] offset:32 th:TH_LOAD_NT_HT scope:SCOPE_DEV125; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0126; GFX1250-NEXT: global_store_b64 v[2:3], v[0:1], off127; GFX1250-NEXT: s_endpgm128entry:129 %gep = getelementptr inbounds i64, ptr addrspace(0) %addr, i32 4130 %val = call <2 x i32> @llvm.amdgcn.flat.load.monitor.b64.v2i32(ptr addrspace(0) %gep, i32 22)131 store <2 x i32> %val, ptr addrspace(1) %use132 ret void133}134 135define amdgpu_ps void @flat_load_monitor_b128(ptr %addr, ptr addrspace(1) %use) {136; GFX1250-LABEL: flat_load_monitor_b128:137; GFX1250: ; %bb.0: ; %entry138; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1139; GFX1250-NEXT: flat_load_monitor_b128 v[4:7], v[0:1] offset:32 th:TH_LOAD_BYPASS scope:SCOPE_SYS140; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0141; GFX1250-NEXT: global_store_b128 v[2:3], v[4:7], off142; GFX1250-NEXT: s_endpgm143entry:144 %gep = getelementptr inbounds i64, ptr addrspace(0) %addr, i32 4145 %val = call <4 x i32> @llvm.amdgcn.flat.load.monitor.b128.v4i32(ptr addrspace(0) %gep, i32 27)146 store <4 x i32> %val, ptr addrspace(1) %use147 ret void148}149 150define amdgpu_ps void @global_load_monitor_b32_saddr_scale_offset(ptr addrspace(1) inreg %addr, ptr addrspace(1) %use, i32 %idx) {151; GFX1250-LABEL: global_load_monitor_b32_saddr_scale_offset:152; GFX1250: ; %bb.0: ; %entry153; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1154; GFX1250-NEXT: global_load_monitor_b32 v2, v2, s[0:1] scale_offset th:TH_LOAD_NT155; GFX1250-NEXT: s_wait_loadcnt 0x0156; GFX1250-NEXT: global_store_b32 v[0:1], v2, off157; GFX1250-NEXT: s_endpgm158entry:159 %idxprom = sext i32 %idx to i64160 %gep = getelementptr i32, ptr addrspace(1) %addr, i64 %idxprom161 %val = call i32 @llvm.amdgcn.global.load.monitor.b32.i32(ptr addrspace(1) %gep, i32 1)162 store i32 %val, ptr addrspace(1) %use163 ret void164}165 166define amdgpu_ps void @global_load_monitor_b64_saddr_scale_offset(ptr addrspace(1) inreg %addr, ptr addrspace(1) %use, i32 %idx) {167; GFX1250-LABEL: global_load_monitor_b64_saddr_scale_offset:168; GFX1250: ; %bb.0: ; %entry169; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1170; GFX1250-NEXT: global_load_monitor_b64 v[2:3], v2, s[0:1] scale_offset th:TH_LOAD_NT171; GFX1250-NEXT: s_wait_loadcnt 0x0172; GFX1250-NEXT: global_store_b64 v[0:1], v[2:3], off173; GFX1250-NEXT: s_endpgm174entry:175 %idxprom = sext i32 %idx to i64176 %gep = getelementptr i64, ptr addrspace(1) %addr, i64 %idxprom177 %val = call <2 x i32> @llvm.amdgcn.global.load.monitor.b64.v2i32(ptr addrspace(1) %gep, i32 1)178 store <2 x i32> %val, ptr addrspace(1) %use179 ret void180}181 182define amdgpu_ps void @global_load_monitor_b64_saddr_no_scale_offset(ptr addrspace(1) inreg %addr, ptr addrspace(1) %use, i32 %idx) {183; GFX1250-LABEL: global_load_monitor_b64_saddr_no_scale_offset:184; GFX1250: ; %bb.0: ; %entry185; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1186; GFX1250-NEXT: v_ashrrev_i32_e32 v3, 31, v2187; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)188; GFX1250-NEXT: v_lshl_add_u64 v[2:3], v[2:3], 2, s[0:1]189; GFX1250-NEXT: global_load_monitor_b64 v[2:3], v[2:3], off th:TH_LOAD_NT190; GFX1250-NEXT: s_wait_loadcnt 0x0191; GFX1250-NEXT: global_store_b64 v[0:1], v[2:3], off192; GFX1250-NEXT: s_endpgm193entry:194 %idxprom = sext i32 %idx to i64195 %gep = getelementptr i32, ptr addrspace(1) %addr, i64 %idxprom196 %val = call <2 x i32> @llvm.amdgcn.global.load.monitor.b64.v2i32(ptr addrspace(1) %gep, i32 1)197 store <2 x i32> %val, ptr addrspace(1) %use198 ret void199}200;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:201; GFX1250-GISEL: {{.*}}202; GFX1250-SDAG: {{.*}}203