129 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx950 < %s | FileCheck -check-prefix=GFX950-SDAG %s3; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx950 < %s | FileCheck -check-prefix=GFX950-GISEL %s4 5; RUN: not --crash llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx942 -filetype=null < %s 2>&1 | FileCheck -check-prefix=ERR-SDAG %s6; RUN: not llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx942 -filetype=null < %s 2>&1 | FileCheck -check-prefix=ERR-GISEL %s7 8; ERR-SDAG: LLVM ERROR: Cannot select: intrinsic %llvm.amdgcn.load.to.lds9 10; ERR-GISEL: LLVM ERROR: cannot select: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.load.to.lds),11 12;; Note: this is a bare-bones test to make sure that amdgcn.load.to.lds lowers to13;; the correct intrinsic.14 15declare void @llvm.amdgcn.load.to.lds.p1(ptr addrspace(1) nocapture %gptr, ptr addrspace(3) nocapture %lptr, i32 %size, i32 %offset, i32 %aux)16declare void @llvm.amdgcn.load.to.lds.p7(ptr addrspace(7) nocapture %gptr, ptr addrspace(3) nocapture %lptr, i32 %size, i32 %offset, i32 %aux)17 18;---------------------------------------------------------------------y19; dwordx320;---------------------------------------------------------------------21 22define amdgpu_ps void @global_load_lds_dwordx3_vaddr_saddr(ptr addrspace(1) nocapture %gptr, ptr addrspace(3) nocapture inreg %lptr) {23; GFX950-LABEL: global_load_lds_dwordx3_vaddr_saddr:24; GFX950: ; %bb.0:25; GFX950-NEXT: s_mov_b32 m0, s026; GFX950-NEXT: s_nop 027; GFX950-NEXT: global_load_lds_dwordx3 v[0:1], off offset:16 sc028; GFX950-NEXT: s_endpgm29; GFX950-SDAG-LABEL: global_load_lds_dwordx3_vaddr_saddr:30; GFX950-SDAG: ; %bb.0:31; GFX950-SDAG-NEXT: s_mov_b32 m0, s032; GFX950-SDAG-NEXT: s_nop 033; GFX950-SDAG-NEXT: global_load_lds_dwordx3 v[0:1], off offset:16 sc034; GFX950-SDAG-NEXT: s_endpgm35;36; GFX950-GISEL-LABEL: global_load_lds_dwordx3_vaddr_saddr:37; GFX950-GISEL: ; %bb.0:38; GFX950-GISEL-NEXT: s_mov_b32 m0, s039; GFX950-GISEL-NEXT: s_nop 040; GFX950-GISEL-NEXT: global_load_lds_dwordx3 v[0:1], off offset:16 sc041; GFX950-GISEL-NEXT: s_endpgm42 call void @llvm.amdgcn.load.to.lds.p1(ptr addrspace(1) %gptr, ptr addrspace(3) %lptr, i32 12, i32 16, i32 1)43 ret void44}45 46define amdgpu_ps void @buffer_load_lds_dwordx3_vaddr_saddr(ptr addrspace(7) nocapture inreg %gptr, i32 %off, ptr addrspace(3) nocapture inreg %lptr) {47; GFX950-LABEL: buffer_load_lds_dwordx3_vaddr_saddr:48; GFX950: ; %bb.0:49; GFX950-NEXT: v_add_u32_e32 v0, s4, v050; GFX950-NEXT: s_mov_b32 m0, s551; GFX950-NEXT: s_nop 052; GFX950-NEXT: buffer_load_dwordx3 v0, s[0:3], 0 offen offset:16 sc0 lds53; GFX950-NEXT: s_endpgm54; GFX950-SDAG-LABEL: buffer_load_lds_dwordx3_vaddr_saddr:55; GFX950-SDAG: ; %bb.0:56; GFX950-SDAG-NEXT: v_add_u32_e32 v0, s4, v057; GFX950-SDAG-NEXT: s_mov_b32 m0, s558; GFX950-SDAG-NEXT: s_nop 059; GFX950-SDAG-NEXT: buffer_load_dwordx3 v0, s[0:3], 0 offen offset:16 sc0 lds60; GFX950-SDAG-NEXT: s_endpgm61;62; GFX950-GISEL-LABEL: buffer_load_lds_dwordx3_vaddr_saddr:63; GFX950-GISEL: ; %bb.0:64; GFX950-GISEL-NEXT: v_add_u32_e32 v0, s4, v065; GFX950-GISEL-NEXT: s_mov_b32 m0, s566; GFX950-GISEL-NEXT: s_nop 067; GFX950-GISEL-NEXT: buffer_load_dwordx3 v0, s[0:3], 0 offen offset:16 sc0 lds68; GFX950-GISEL-NEXT: s_endpgm69 %gptr.off = getelementptr i8, ptr addrspace(7) %gptr, i32 %off70 call void @llvm.amdgcn.load.to.lds.p7(ptr addrspace(7) %gptr.off, ptr addrspace(3) %lptr, i32 12, i32 16, i32 1)71 ret void72}73 74;---------------------------------------------------------------------75; dwordx476;---------------------------------------------------------------------77 78define amdgpu_ps void @global_load_lds_dwordx4_vaddr_saddr(ptr addrspace(1) nocapture %gptr, ptr addrspace(3) nocapture inreg %lptr) {79; GFX950-LABEL: global_load_lds_dwordx4_vaddr_saddr:80; GFX950: ; %bb.0:81; GFX950-NEXT: s_mov_b32 m0, s082; GFX950-NEXT: s_nop 083; GFX950-NEXT: global_load_lds_dwordx4 v[0:1], off offset:16 sc084; GFX950-NEXT: s_endpgm85; GFX950-SDAG-LABEL: global_load_lds_dwordx4_vaddr_saddr:86; GFX950-SDAG: ; %bb.0:87; GFX950-SDAG-NEXT: s_mov_b32 m0, s088; GFX950-SDAG-NEXT: s_nop 089; GFX950-SDAG-NEXT: global_load_lds_dwordx4 v[0:1], off offset:16 sc090; GFX950-SDAG-NEXT: s_endpgm91;92; GFX950-GISEL-LABEL: global_load_lds_dwordx4_vaddr_saddr:93; GFX950-GISEL: ; %bb.0:94; GFX950-GISEL-NEXT: s_mov_b32 m0, s095; GFX950-GISEL-NEXT: s_nop 096; GFX950-GISEL-NEXT: global_load_lds_dwordx4 v[0:1], off offset:16 sc097; GFX950-GISEL-NEXT: s_endpgm98 call void @llvm.amdgcn.global.load.lds(ptr addrspace(1) %gptr, ptr addrspace(3) %lptr, i32 16, i32 16, i32 1)99 ret void100}101 102define amdgpu_ps void @buffer_load_lds_dwordx4_vaddr_saddr(ptr addrspace(7) nocapture inreg %gptr, i32 %off, ptr addrspace(3) nocapture inreg %lptr) {103; GFX950-LABEL: buffer_load_lds_dwordx4_vaddr_saddr:104; GFX950: ; %bb.0:105; GFX950-NEXT: v_add_u32_e32 v0, s4, v0106; GFX950-NEXT: s_mov_b32 m0, s5107; GFX950-NEXT: s_nop 0108; GFX950-NEXT: buffer_load_dwordx4 v0, s[0:3], 0 offen offset:16 sc0 lds109; GFX950-NEXT: s_endpgm110; GFX950-SDAG-LABEL: buffer_load_lds_dwordx4_vaddr_saddr:111; GFX950-SDAG: ; %bb.0:112; GFX950-SDAG-NEXT: v_add_u32_e32 v0, s4, v0113; GFX950-SDAG-NEXT: s_mov_b32 m0, s5114; GFX950-SDAG-NEXT: s_nop 0115; GFX950-SDAG-NEXT: buffer_load_dwordx4 v0, s[0:3], 0 offen offset:16 sc0 lds116; GFX950-SDAG-NEXT: s_endpgm117;118; GFX950-GISEL-LABEL: buffer_load_lds_dwordx4_vaddr_saddr:119; GFX950-GISEL: ; %bb.0:120; GFX950-GISEL-NEXT: v_add_u32_e32 v0, s4, v0121; GFX950-GISEL-NEXT: s_mov_b32 m0, s5122; GFX950-GISEL-NEXT: s_nop 0123; GFX950-GISEL-NEXT: buffer_load_dwordx4 v0, s[0:3], 0 offen offset:16 sc0 lds124; GFX950-GISEL-NEXT: s_endpgm125 %gptr.off = getelementptr i8, ptr addrspace(7) %gptr, i32 %off126 call void @llvm.amdgcn.load.to.lds.p7(ptr addrspace(7) %gptr.off, ptr addrspace(3) %lptr, i32 16, i32 16, i32 1)127 ret void128}129