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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1250 -mattr=+wavefrontsize32,-wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-SDAG %s3; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1250 -mattr=+wavefrontsize32,-wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-GISEL %s4 5declare <2 x i32> @llvm.amdgcn.global.load.tr4.b64.v2i32.p1(ptr addrspace(1))6declare <2 x i32> @llvm.amdgcn.global.load.tr.b64.v2i32.p1(ptr addrspace(1))7declare <3 x i32> @llvm.amdgcn.global.load.tr6.b96.v3i32.p1(ptr addrspace(1))8declare <8 x i16> @llvm.amdgcn.global.load.tr.b128.v8i16.p1(ptr addrspace(1))9declare <8 x half> @llvm.amdgcn.global.load.tr.b128.v8f16.p1(ptr addrspace(1))10declare <8 x bfloat> @llvm.amdgcn.global.load.tr.b128.v8bf16.p1(ptr addrspace(1))11 12declare <2 x i32> @llvm.amdgcn.ds.load.tr4.b64.v2i32.p3(ptr addrspace(3))13declare <2 x i32> @llvm.amdgcn.ds.load.tr8.b64.v2i32.p3(ptr addrspace(3))14declare <3 x i32> @llvm.amdgcn.ds.load.tr6.b96.v3i32.p3(ptr addrspace(3))15declare <8 x i16> @llvm.amdgcn.ds.load.tr16.b128.v8i16.p3(ptr addrspace(3))16declare <8 x half> @llvm.amdgcn.ds.load.tr16.b128.v8f16.p3(ptr addrspace(3))17declare <8 x bfloat> @llvm.amdgcn.ds.load.tr16.b128.v8bf16.p3(ptr addrspace(3))18 19 20define amdgpu_ps void @global_load_tr4_b64_vaddr(ptr addrspace(1) %addr, ptr addrspace(1) %use) {21; GFX1250-LABEL: global_load_tr4_b64_vaddr:22; GFX1250: ; %bb.0: ; %entry23; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 124; GFX1250-NEXT: global_load_tr4_b64 v[0:1], v[0:1], off offset:3225; GFX1250-NEXT: s_wait_loadcnt 0x026; GFX1250-NEXT: global_store_b64 v[2:3], v[0:1], off27; GFX1250-NEXT: s_endpgm28entry:29 %gep = getelementptr i64, ptr addrspace(1) %addr, i32 430 %val = call <2 x i32> @llvm.amdgcn.global.load.tr4.b64.v2i32.p1(ptr addrspace(1) %gep)31 store <2 x i32> %val, ptr addrspace(1) %use32 ret void33}34 35define amdgpu_ps void @global_load_tr4_b64_saddr(ptr addrspace(1) inreg %addr, ptr addrspace(1) %use) {36; GFX1250-LABEL: global_load_tr4_b64_saddr:37; GFX1250: ; %bb.0: ; %entry38; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 139; GFX1250-NEXT: v_mov_b32_e32 v2, 040; GFX1250-NEXT: global_load_tr4_b64 v[2:3], v2, s[0:1] offset:3241; GFX1250-NEXT: s_wait_loadcnt 0x042; GFX1250-NEXT: global_store_b64 v[0:1], v[2:3], off43; GFX1250-NEXT: s_endpgm44entry:45 %gep = getelementptr i64, ptr addrspace(1) %addr, i32 446 %val = call <2 x i32> @llvm.amdgcn.global.load.tr4.b64.v2i32.p1(ptr addrspace(1) %gep)47 store <2 x i32> %val, ptr addrspace(1) %use48 ret void49}50 51define amdgpu_ps void @global_load_tr8_b64_vaddr(ptr addrspace(1) %addr, ptr addrspace(1) %use) {52; GFX1250-LABEL: global_load_tr8_b64_vaddr:53; GFX1250: ; %bb.0: ; %entry54; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 155; GFX1250-NEXT: global_load_tr8_b64 v[0:1], v[0:1], off offset:3256; GFX1250-NEXT: s_wait_loadcnt 0x057; GFX1250-NEXT: global_store_b64 v[2:3], v[0:1], off58; GFX1250-NEXT: s_endpgm59entry:60 %gep = getelementptr i64, ptr addrspace(1) %addr, i32 461 %val = call <2 x i32> @llvm.amdgcn.global.load.tr.b64.v2i32.p1(ptr addrspace(1) %gep)62 store <2 x i32> %val, ptr addrspace(1) %use63 ret void64}65 66define amdgpu_ps void @global_load_tr8_b64_saddr(ptr addrspace(1) inreg %addr, ptr addrspace(1) %use) {67; GFX1250-LABEL: global_load_tr8_b64_saddr:68; GFX1250: ; %bb.0: ; %entry69; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 170; GFX1250-NEXT: v_mov_b32_e32 v2, 071; GFX1250-NEXT: global_load_tr8_b64 v[2:3], v2, s[0:1] offset:3272; GFX1250-NEXT: s_wait_loadcnt 0x073; GFX1250-NEXT: global_store_b64 v[0:1], v[2:3], off74; GFX1250-NEXT: s_endpgm75entry:76 %gep = getelementptr i64, ptr addrspace(1) %addr, i32 477 %val = call <2 x i32> @llvm.amdgcn.global.load.tr.b64.v2i32.p1(ptr addrspace(1) %gep)78 store <2 x i32> %val, ptr addrspace(1) %use79 ret void80}81 82define amdgpu_ps void @global_load_tr6_b96_vaddr(ptr addrspace(1) %addr, ptr addrspace(1) %use) {83; GFX1250-LABEL: global_load_tr6_b96_vaddr:84; GFX1250: ; %bb.0: ; %entry85; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 186; GFX1250-NEXT: global_load_tr6_b96 v[4:6], v[0:1], off offset:3287; GFX1250-NEXT: s_wait_loadcnt 0x088; GFX1250-NEXT: global_store_b96 v[2:3], v[4:6], off89; GFX1250-NEXT: s_endpgm90entry:91 %gep = getelementptr i64, ptr addrspace(1) %addr, i32 492 %val = call <3 x i32> @llvm.amdgcn.global.load.tr6.b96.v3i32.p1(ptr addrspace(1) %gep)93 store <3 x i32> %val, ptr addrspace(1) %use94 ret void95}96 97define amdgpu_ps void @global_load_tr6_b96_saddr(ptr addrspace(1) inreg %addr, ptr addrspace(1) %use) {98; GFX1250-LABEL: global_load_tr6_b96_saddr:99; GFX1250: ; %bb.0: ; %entry100; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1101; GFX1250-NEXT: v_mov_b32_e32 v2, 0102; GFX1250-NEXT: global_load_tr6_b96 v[2:4], v2, s[0:1] offset:32103; GFX1250-NEXT: s_wait_loadcnt 0x0104; GFX1250-NEXT: global_store_b96 v[0:1], v[2:4], off105; GFX1250-NEXT: s_endpgm106entry:107 %gep = getelementptr i64, ptr addrspace(1) %addr, i32 4108 %val = call <3 x i32> @llvm.amdgcn.global.load.tr6.b96.v3i32.p1(ptr addrspace(1) %gep)109 store <3 x i32> %val, ptr addrspace(1) %use110 ret void111}112 113define amdgpu_ps void @global_load_tr16_b128_v8i16_vaddr(ptr addrspace(1) %addr, ptr addrspace(1) %use) {114; GFX1250-LABEL: global_load_tr16_b128_v8i16_vaddr:115; GFX1250: ; %bb.0: ; %entry116; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1117; GFX1250-NEXT: global_load_tr16_b128 v[4:7], v[0:1], off offset:32118; GFX1250-NEXT: s_wait_loadcnt 0x0119; GFX1250-NEXT: global_store_b128 v[2:3], v[4:7], off120; GFX1250-NEXT: s_endpgm121entry:122 %gep = getelementptr i64, ptr addrspace(1) %addr, i32 4123 %val = call <8 x i16> @llvm.amdgcn.global.load.tr.b128.v8i16.p1(ptr addrspace(1) %gep)124 store <8 x i16> %val, ptr addrspace(1) %use125 ret void126}127 128define amdgpu_ps void @global_load_tr16_b128_v8i16_saddr(ptr addrspace(1) inreg %addr, ptr addrspace(1) %use) {129; GFX1250-LABEL: global_load_tr16_b128_v8i16_saddr:130; GFX1250: ; %bb.0: ; %entry131; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1132; GFX1250-NEXT: v_mov_b32_e32 v2, 0133; GFX1250-NEXT: global_load_tr16_b128 v[2:5], v2, s[0:1] offset:32134; GFX1250-NEXT: s_wait_loadcnt 0x0135; GFX1250-NEXT: global_store_b128 v[0:1], v[2:5], off136; GFX1250-NEXT: s_endpgm137entry:138 %gep = getelementptr i64, ptr addrspace(1) %addr, i32 4139 %val = call <8 x i16> @llvm.amdgcn.global.load.tr.b128.v8i16.p1(ptr addrspace(1) %gep)140 store <8 x i16> %val, ptr addrspace(1) %use141 ret void142}143 144define amdgpu_ps void @global_load_tr16_b128_v8f16_vaddr(ptr addrspace(1) %addr, ptr addrspace(1) %use) {145; GFX1250-LABEL: global_load_tr16_b128_v8f16_vaddr:146; GFX1250: ; %bb.0: ; %entry147; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1148; GFX1250-NEXT: global_load_tr16_b128 v[4:7], v[0:1], off offset:32149; GFX1250-NEXT: s_wait_loadcnt 0x0150; GFX1250-NEXT: global_store_b128 v[2:3], v[4:7], off151; GFX1250-NEXT: s_endpgm152entry:153 %gep = getelementptr i64, ptr addrspace(1) %addr, i32 4154 %val = call <8 x half> @llvm.amdgcn.global.load.tr.b128.v8f16.p1(ptr addrspace(1) %gep)155 store <8 x half> %val, ptr addrspace(1) %use156 ret void157}158 159define amdgpu_ps void @global_load_tr16_b128_v8f16_saddr(ptr addrspace(1) inreg %addr, ptr addrspace(1) %use) {160; GFX1250-LABEL: global_load_tr16_b128_v8f16_saddr:161; GFX1250: ; %bb.0: ; %entry162; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1163; GFX1250-NEXT: v_mov_b32_e32 v2, 0164; GFX1250-NEXT: global_load_tr16_b128 v[2:5], v2, s[0:1] offset:32165; GFX1250-NEXT: s_wait_loadcnt 0x0166; GFX1250-NEXT: global_store_b128 v[0:1], v[2:5], off167; GFX1250-NEXT: s_endpgm168entry:169 %gep = getelementptr i64, ptr addrspace(1) %addr, i32 4170 %val = call <8 x half> @llvm.amdgcn.global.load.tr.b128.v8f16.p1(ptr addrspace(1) %gep)171 store <8 x half> %val, ptr addrspace(1) %use172 ret void173}174 175define amdgpu_ps void @global_load_tr16_b128_v8b16_vaddr(ptr addrspace(1) %addr, ptr addrspace(1) %use) {176; GFX1250-LABEL: global_load_tr16_b128_v8b16_vaddr:177; GFX1250: ; %bb.0: ; %entry178; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1179; GFX1250-NEXT: global_load_tr16_b128 v[4:7], v[0:1], off offset:32180; GFX1250-NEXT: s_wait_loadcnt 0x0181; GFX1250-NEXT: global_store_b128 v[2:3], v[4:7], off182; GFX1250-NEXT: s_endpgm183entry:184 %gep = getelementptr i64, ptr addrspace(1) %addr, i32 4185 %val = call <8 x bfloat> @llvm.amdgcn.global.load.tr.b128.v8bf16.p1(ptr addrspace(1) %gep)186 store <8 x bfloat> %val, ptr addrspace(1) %use187 ret void188}189 190define amdgpu_ps void @global_load_tr16_b128_v8bf16_saddr(ptr addrspace(1) inreg %addr, ptr addrspace(1) %use) {191; GFX1250-LABEL: global_load_tr16_b128_v8bf16_saddr:192; GFX1250: ; %bb.0: ; %entry193; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1194; GFX1250-NEXT: v_mov_b32_e32 v2, 0195; GFX1250-NEXT: global_load_tr16_b128 v[2:5], v2, s[0:1] offset:32196; GFX1250-NEXT: s_wait_loadcnt 0x0197; GFX1250-NEXT: global_store_b128 v[0:1], v[2:5], off198; GFX1250-NEXT: s_endpgm199entry:200 %gep = getelementptr i64, ptr addrspace(1) %addr, i32 4201 %val = call <8 x bfloat> @llvm.amdgcn.global.load.tr.b128.v8bf16.p1(ptr addrspace(1) %gep)202 store <8 x bfloat> %val, ptr addrspace(1) %use203 ret void204}205 206define amdgpu_ps void @ds_load_tr4_b64(ptr addrspace(3) %addr, ptr addrspace(1) %use) {207; GFX1250-SDAG-LABEL: ds_load_tr4_b64:208; GFX1250-SDAG: ; %bb.0: ; %entry209; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1210; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1211; GFX1250-SDAG-NEXT: ds_load_tr4_b64 v[0:1], v0 offset:32212; GFX1250-SDAG-NEXT: s_wait_dscnt 0x0213; GFX1250-SDAG-NEXT: global_store_b64 v[2:3], v[0:1], off214; GFX1250-SDAG-NEXT: s_endpgm215;216; GFX1250-GISEL-LABEL: ds_load_tr4_b64:217; GFX1250-GISEL: ; %bb.0: ; %entry218; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1219; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2220; GFX1250-GISEL-NEXT: ds_load_tr4_b64 v[0:1], v0 offset:32221; GFX1250-GISEL-NEXT: s_wait_dscnt 0x0222; GFX1250-GISEL-NEXT: global_store_b64 v[4:5], v[0:1], off223; GFX1250-GISEL-NEXT: s_endpgm224entry:225 %gep = getelementptr i64, ptr addrspace(3) %addr, i32 4226 %val = call <2 x i32> @llvm.amdgcn.ds.load.tr4.b64.v2i32.p3(ptr addrspace(3) %gep)227 store <2 x i32> %val, ptr addrspace(1) %use228 ret void229}230 231define amdgpu_ps void @ds_load_tr8_b64(ptr addrspace(3) %addr, ptr addrspace(1) %use) {232; GFX1250-SDAG-LABEL: ds_load_tr8_b64:233; GFX1250-SDAG: ; %bb.0: ; %entry234; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1235; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1236; GFX1250-SDAG-NEXT: ds_load_tr8_b64 v[0:1], v0 offset:32237; GFX1250-SDAG-NEXT: s_wait_dscnt 0x0238; GFX1250-SDAG-NEXT: global_store_b64 v[2:3], v[0:1], off239; GFX1250-SDAG-NEXT: s_endpgm240;241; GFX1250-GISEL-LABEL: ds_load_tr8_b64:242; GFX1250-GISEL: ; %bb.0: ; %entry243; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1244; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2245; GFX1250-GISEL-NEXT: ds_load_tr8_b64 v[0:1], v0 offset:32246; GFX1250-GISEL-NEXT: s_wait_dscnt 0x0247; GFX1250-GISEL-NEXT: global_store_b64 v[4:5], v[0:1], off248; GFX1250-GISEL-NEXT: s_endpgm249entry:250 %gep = getelementptr i64, ptr addrspace(3) %addr, i32 4251 %val = call <2 x i32> @llvm.amdgcn.ds.load.tr8.b64.v2i32.p3(ptr addrspace(3) %gep)252 store <2 x i32> %val, ptr addrspace(1) %use253 ret void254}255 256define amdgpu_ps void @ds_load_tr6_b96(ptr addrspace(3) %addr, ptr addrspace(1) %use) {257; GFX1250-SDAG-LABEL: ds_load_tr6_b96:258; GFX1250-SDAG: ; %bb.0: ; %entry259; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1260; GFX1250-SDAG-NEXT: v_dual_mov_b32 v5, v2 :: v_dual_mov_b32 v4, v1261; GFX1250-SDAG-NEXT: ds_load_tr6_b96 v[0:2], v0 offset:32262; GFX1250-SDAG-NEXT: s_wait_dscnt 0x0263; GFX1250-SDAG-NEXT: global_store_b96 v[4:5], v[0:2], off264; GFX1250-SDAG-NEXT: s_endpgm265;266; GFX1250-GISEL-LABEL: ds_load_tr6_b96:267; GFX1250-GISEL: ; %bb.0: ; %entry268; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1269; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2270; GFX1250-GISEL-NEXT: ds_load_tr6_b96 v[0:2], v0 offset:32271; GFX1250-GISEL-NEXT: s_wait_dscnt 0x0272; GFX1250-GISEL-NEXT: global_store_b96 v[4:5], v[0:2], off273; GFX1250-GISEL-NEXT: s_endpgm274entry:275 %gep = getelementptr i64, ptr addrspace(3) %addr, i32 4276 %val = call <3 x i32> @llvm.amdgcn.ds.load.tr6.b96.v3i32.p3(ptr addrspace(3) %gep)277 store <3 x i32> %val, ptr addrspace(1) %use278 ret void279}280 281define amdgpu_ps void @ds_load_tr16_b128_v8i16(ptr addrspace(3) %addr, ptr addrspace(1) %use) {282; GFX1250-SDAG-LABEL: ds_load_tr16_b128_v8i16:283; GFX1250-SDAG: ; %bb.0: ; %entry284; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1285; GFX1250-SDAG-NEXT: v_dual_mov_b32 v5, v2 :: v_dual_mov_b32 v4, v1286; GFX1250-SDAG-NEXT: ds_load_tr16_b128 v[0:3], v0 offset:32287; GFX1250-SDAG-NEXT: s_wait_dscnt 0x0288; GFX1250-SDAG-NEXT: global_store_b128 v[4:5], v[0:3], off289; GFX1250-SDAG-NEXT: s_endpgm290;291; GFX1250-GISEL-LABEL: ds_load_tr16_b128_v8i16:292; GFX1250-GISEL: ; %bb.0: ; %entry293; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1294; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2295; GFX1250-GISEL-NEXT: ds_load_tr16_b128 v[0:3], v0 offset:32296; GFX1250-GISEL-NEXT: s_wait_dscnt 0x0297; GFX1250-GISEL-NEXT: global_store_b128 v[4:5], v[0:3], off298; GFX1250-GISEL-NEXT: s_endpgm299entry:300 %gep = getelementptr i64, ptr addrspace(3) %addr, i32 4301 %val = call <8 x i16> @llvm.amdgcn.ds.load.tr16.b128.v8i16.p3(ptr addrspace(3) %gep)302 store <8 x i16> %val, ptr addrspace(1) %use303 ret void304}305 306define amdgpu_ps void @ds_load_tr16_b128_v8f16(ptr addrspace(3) %addr, ptr addrspace(1) %use) {307; GFX1250-SDAG-LABEL: ds_load_tr16_b128_v8f16:308; GFX1250-SDAG: ; %bb.0: ; %entry309; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1310; GFX1250-SDAG-NEXT: v_dual_mov_b32 v5, v2 :: v_dual_mov_b32 v4, v1311; GFX1250-SDAG-NEXT: ds_load_tr16_b128 v[0:3], v0 offset:32312; GFX1250-SDAG-NEXT: s_wait_dscnt 0x0313; GFX1250-SDAG-NEXT: global_store_b128 v[4:5], v[0:3], off314; GFX1250-SDAG-NEXT: s_endpgm315;316; GFX1250-GISEL-LABEL: ds_load_tr16_b128_v8f16:317; GFX1250-GISEL: ; %bb.0: ; %entry318; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1319; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2320; GFX1250-GISEL-NEXT: ds_load_tr16_b128 v[0:3], v0 offset:32321; GFX1250-GISEL-NEXT: s_wait_dscnt 0x0322; GFX1250-GISEL-NEXT: global_store_b128 v[4:5], v[0:3], off323; GFX1250-GISEL-NEXT: s_endpgm324entry:325 %gep = getelementptr i64, ptr addrspace(3) %addr, i32 4326 %val = call <8 x half> @llvm.amdgcn.ds.load.tr16.b128.v8f16.p3(ptr addrspace(3) %gep)327 store <8 x half> %val, ptr addrspace(1) %use328 ret void329}330 331define amdgpu_ps void @ds_load_tr16_b128_v8bf16(ptr addrspace(3) %addr, ptr addrspace(1) %use) {332; GFX1250-LABEL: ds_load_tr16_b128_v8bf16:333; GFX1250: ; %bb.0: ; %entry334; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1335; GFX1250-NEXT: v_dual_mov_b32 v5, v2 :: v_dual_mov_b32 v4, v1336; GFX1250-NEXT: ds_load_tr16_b128 v[0:3], v0 offset:32337; GFX1250-NEXT: s_wait_dscnt 0x0338; GFX1250-NEXT: global_store_b128 v[4:5], v[0:3], off339; GFX1250-NEXT: s_endpgm340entry:341 %gep = getelementptr i64, ptr addrspace(3) %addr, i32 4342 %val = call <8 x bfloat> @llvm.amdgcn.ds.load.tr16.b128.v8bf16.p3(ptr addrspace(3) %gep)343 store <8 x bfloat> %val, ptr addrspace(1) %use344 ret void345}346 347; This is a special case that does not require aligned VGPRs. Make348; sure no copies are required for the unaligned ABI return value.349define { i32, <3 x i32> } @global_load_tr6_b96_vaddr_no_align2_requirement(ptr addrspace(1) %addr, ptr addrspace(1) %use) {350; GFX1250-LABEL: global_load_tr6_b96_vaddr_no_align2_requirement:351; GFX1250: ; %bb.0:352; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0353; GFX1250-NEXT: s_wait_kmcnt 0x0354; GFX1250-NEXT: global_load_tr6_b96 v[2:4], v[0:1], off offset:32355; GFX1250-NEXT: s_wait_loadcnt 0x0356; GFX1250-NEXT: s_wait_xcnt 0x0357; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, v2358; GFX1250-NEXT: v_dual_mov_b32 v2, v3 :: v_dual_mov_b32 v3, v4359; GFX1250-NEXT: s_set_pc_i64 s[30:31]360 %gep = getelementptr i64, ptr addrspace(1) %addr, i32 4361 %val = call <3 x i32> @llvm.amdgcn.global.load.tr6.b96.v3i32.p1(ptr addrspace(1) %gep)362 %insert0 = insertvalue { i32, <3 x i32> } poison, i32 0, 0363 %insert1 = insertvalue { i32, <3 x i32> } %insert0, <3 x i32> %val, 1364 ret { i32, <3 x i32> } %insert1365}366 367define { i32, <3 x i32> } @global_load_tr6_b96_saddr_no_align2_requirement(ptr addrspace(1) inreg %addr, ptr addrspace(1) %use) {368; GFX1250-LABEL: global_load_tr6_b96_saddr_no_align2_requirement:369; GFX1250: ; %bb.0:370; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0371; GFX1250-NEXT: s_wait_kmcnt 0x0372; GFX1250-NEXT: v_mov_b32_e32 v0, 0373; GFX1250-NEXT: global_load_tr6_b96 v[2:4], v0, s[0:1] offset:32374; GFX1250-NEXT: s_wait_loadcnt 0x0375; GFX1250-NEXT: s_wait_xcnt 0x0376; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, v2377; GFX1250-NEXT: v_dual_mov_b32 v2, v3 :: v_dual_mov_b32 v3, v4378; GFX1250-NEXT: s_set_pc_i64 s[30:31]379 %gep = getelementptr i64, ptr addrspace(1) %addr, i32 4380 %val = call <3 x i32> @llvm.amdgcn.global.load.tr6.b96.v3i32.p1(ptr addrspace(1) %gep)381 %insert0 = insertvalue { i32, <3 x i32> } poison, i32 0, 0382 %insert1 = insertvalue { i32, <3 x i32> } %insert0, <3 x i32> %val, 1383 ret { i32, <3 x i32> } %insert1384}385 386define { i32, <3 x i32> } @ds_load_tr6_b96_no_align2_requirement(ptr addrspace(3) %addr, ptr addrspace(1) %use) {387; GFX1250-LABEL: ds_load_tr6_b96_no_align2_requirement:388; GFX1250: ; %bb.0:389; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0390; GFX1250-NEXT: s_wait_kmcnt 0x0391; GFX1250-NEXT: ds_load_tr6_b96 v[2:4], v0 offset:32392; GFX1250-NEXT: s_wait_dscnt 0x0393; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, v2394; GFX1250-NEXT: v_dual_mov_b32 v2, v3 :: v_dual_mov_b32 v3, v4395; GFX1250-NEXT: s_set_pc_i64 s[30:31]396 %gep = getelementptr i64, ptr addrspace(3) %addr, i32 4397 %val = call <3 x i32> @llvm.amdgcn.ds.load.tr6.b96.v3i32.p3(ptr addrspace(3) %gep)398 %insert0 = insertvalue { i32, <3 x i32> } poison, i32 0, 0399 %insert1 = insertvalue { i32, <3 x i32> } %insert0, <3 x i32> %val, 1400 ret { i32, <3 x i32> } %insert1401}402