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1; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global -show-mc-encoding < %s | FileCheck -check-prefixes=VI,VI-OPT,PREGFX10,PREGFX10-OPT %s2; RUN: llc -O0 -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global -show-mc-encoding < %s | FileCheck -check-prefixes=VI,VI-NOOPT,PREGFX10,PREGFX10-NOOPT %s3; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -mattr=-flat-for-global -show-mc-encoding < %s | FileCheck -check-prefixes=VI,VI-OPT %s4; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-flat-for-global -amdgpu-enable-vopd=0 -show-mc-encoding < %s | FileCheck -check-prefixes=VI,VI-OPT %s5 6; FIXME: The register allocator / scheduler should be able to avoid these hazards.7 8; VI-LABEL: {{^}}dpp_test:9; VI: v_mov_b32_e32 v0, s{{[0-9]+}}10; VI-NOOPT: v_mov_b32_e32 v1, s{{[0-9]+}}11; PREGFX10: s_nop 112; VI-OPT: v_mov_b32_dpp v0, v0 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x01,0x08,0x11]13; VI-NOOPT: v_mov_b32_dpp v0, v1 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x02,0x00,0x7e,0x01,0x01,0x08,0x11]14define amdgpu_kernel void @dpp_test(ptr addrspace(1) %out, i32 %in) {15 %tmp0 = call i32 @llvm.amdgcn.mov.dpp.i32(i32 %in, i32 1, i32 1, i32 1, i1 1) #016 store i32 %tmp0, ptr addrspace(1) %out17 ret void18}19 20; VI-LABEL: {{^}}dpp_wait_states:21; VI-NOOPT: v_mov_b32_e32 [[VGPR1:v[0-9]+]], s{{[0-9]+}}22; VI: v_mov_b32_e32 [[VGPR0:v[0-9]+]], s{{[0-9]+}}23; PREGFX10: s_nop 124; VI-OPT: v_mov_b32_dpp [[VGPR0]], [[VGPR0]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:125; VI-NOOPT: v_mov_b32_dpp [[VGPR1]], [[VGPR0]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:26; PREGFX10: s_nop 127; VI-OPT: v_mov_b32_dpp v{{[0-9]+}}, [[VGPR0]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:128; VI-NOOPT: v_mov_b32_dpp v{{[0-9]+}}, [[VGPR1]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:129define amdgpu_kernel void @dpp_wait_states(ptr addrspace(1) %out, i32 %in) {30 %tmp0 = call i32 @llvm.amdgcn.mov.dpp.i32(i32 %in, i32 1, i32 1, i32 1, i1 1) #031 %tmp1 = call i32 @llvm.amdgcn.mov.dpp.i32(i32 %tmp0, i32 1, i32 1, i32 1, i1 1) #032 store i32 %tmp1, ptr addrspace(1) %out33 ret void34}35 36; VI-LABEL: {{^}}dpp_first_in_bb:37; VI: ; %endif38; PREGFX10-NOOPT: s_waitcnt39; PREGFX10-NOOPT: v_mov_b32_e3240; VI: v_mov_b32_dpp [[VGPR0:v[0-9]+]], v{{[0-9]+}} quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:141; PREGFX10-OPT: s_mov_b3242; PREGFX10-OPT: s_mov_b3243; VI: v_mov_b32_dpp [[VGPR1:v[0-9]+]], [[VGPR0]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:144; PREGFX10: s_nop 145; VI: v_mov_b32_dpp v{{[0-9]+}}, [[VGPR1]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:146define amdgpu_kernel void @dpp_first_in_bb(ptr addrspace(1) %out, ptr addrspace(1) %in, float %cond, float %a, float %b) {47 %cmp = fcmp oeq float %cond, 0.048 br i1 %cmp, label %if, label %else49 50if:51 %out_val = load float, ptr addrspace(1) %out52 %if_val = fadd float %a, %out_val53 br label %endif54 55else:56 %in_val = load float, ptr addrspace(1) %in57 %else_val = fadd float %b, %in_val58 br label %endif59 60endif:61 %val = phi float [%if_val, %if], [%else_val, %else]62 %val_i32 = bitcast float %val to i3263 %tmp0 = call i32 @llvm.amdgcn.mov.dpp.i32(i32 %val_i32, i32 1, i32 1, i32 1, i1 1) #064 %tmp1 = call i32 @llvm.amdgcn.mov.dpp.i32(i32 %tmp0, i32 1, i32 1, i32 1, i1 1) #065 %tmp2 = call i32 @llvm.amdgcn.mov.dpp.i32(i32 %tmp1, i32 1, i32 1, i32 1, i1 1) #066 %tmp_float = bitcast i32 %tmp2 to float67 store float %tmp_float, ptr addrspace(1) %out68 ret void69}70 71; VI-LABEL: {{^}}mov_dpp64_test:72; VI: v_mov_b32_dpp v{{[0-9]+}}, v{{[0-9]+}} quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x173; VI: v_mov_b32_dpp v{{[0-9]+}}, v{{[0-9]+}} quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x174define amdgpu_kernel void @mov_dpp64_test(ptr addrspace(1) %out, i64 %in1) {75 %tmp0 = call i64 @llvm.amdgcn.mov.dpp.i64(i64 %in1, i32 1, i32 1, i32 1, i1 0) #076 store i64 %tmp0, ptr addrspace(1) %out77 ret void78}79 80; VI-LABEL: {{^}}mov_dpp64_imm_test:81; VI-OPT-DAG: s_mov_b32 s[[SOLD_LO:[0-9]+]], 0x3afaedd982; VI-OPT-DAG: s_movk_i32 s[[SOLD_HI:[0-9]+]], 0x704783; VI-OPT-DAG: v_mov_b32_e32 v[[OLD_LO:[0-9]+]], s[[SOLD_LO]]84; VI-OPT-DAG: v_mov_b32_e32 v[[OLD_HI:[0-9]+]], s[[SOLD_HI]]85; VI-OPT-DAG: v_mov_b32_dpp v[[OLD_LO]], v[[OLD_LO]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x186; VI-OPT-DAG: v_mov_b32_dpp v[[OLD_HI]], v[[OLD_HI]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x187; VI-NOOPT-COUNT-2: v_mov_b32_dpp v{{[0-9]+}}, v{{[0-9]+}} quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x188define amdgpu_kernel void @mov_dpp64_imm_test(ptr addrspace(1) %out) {89 %tmp0 = call i64 @llvm.amdgcn.mov.dpp.i64(i64 123451234512345, i32 1, i32 1, i32 1, i1 0) #090 store i64 %tmp0, ptr addrspace(1) %out91 ret void92}93 94declare i32 @llvm.amdgcn.mov.dpp.i32(i32, i32, i32, i32, i1) #095declare i64 @llvm.amdgcn.mov.dpp.i64(i64, i32, i32, i32, i1) #096 97attributes #0 = { nounwind readnone convergent }98 99