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1; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10PLUS %s2; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10PLUS %s3; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefix=GFX10PLUS %s4; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1100 -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefix=GFX10PLUS %s5; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefix=GFX10PLUS %s6; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1200 -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefix=GFX10PLUS %s7 8; GFX10PLUS-LABEL: {{^}}dpp8_test:9; GFX10PLUS: v_mov_b32_e32 [[SRC:v[0-9]+]], s{{[0-9]+}}10; GFX10PLUS: v_mov_b32_dpp [[SRC]], [[SRC]] dpp8:[1,0,0,0,0,0,0,0]{{$}}11define amdgpu_kernel void @dpp8_test(ptr addrspace(1) %out, i32 %in) {12 %tmp0 = call i32 @llvm.amdgcn.mov.dpp8.i32(i32 %in, i32 1) #013 store i32 %tmp0, ptr addrspace(1) %out14 ret void15}16 17; GFX10PLUS-LABEL: {{^}}dpp8_wait_states:18; GFX10PLUS-NOOPT: v_mov_b32_e32 [[VGPR1:v[0-9]+]], s{{[0-9]+}}19; GFX10PLUS: v_mov_b32_e32 [[VGPR0:v[0-9]+]], s{{[0-9]+}}20; GFX10PLUS: v_mov_b32_dpp [[VGPR0]], [[VGPR0]] dpp8:[1,0,0,0,0,0,0,0]{{$}}21; GFX10PLUS: v_mov_b32_dpp [[VGPR0]], [[VGPR0]] dpp8:[5,0,0,0,0,0,0,0]{{$}}22define amdgpu_kernel void @dpp8_wait_states(ptr addrspace(1) %out, i32 %in) {23 %tmp0 = call i32 @llvm.amdgcn.mov.dpp8.i32(i32 %in, i32 1) #024 %tmp1 = call i32 @llvm.amdgcn.mov.dpp8.i32(i32 %tmp0, i32 5) #025 store i32 %tmp1, ptr addrspace(1) %out26 ret void27}28 29; GFX10PLUS-LABEL: {{^}}dpp8_i64:30; GFX10PLUS-DAG: v_mov_b32_dpp v0, v0 dpp8:[1,0,0,0,0,0,0,0]31; GFX10PLUS-DAG: v_mov_b32_dpp v1, v1 dpp8:[1,0,0,0,0,0,0,0]32; GFX10PLUS-DAG: global_store_{{dwordx2|b64}} v[2:3], v[0:1], off33define amdgpu_ps void @dpp8_i64(i64 %in, ptr addrspace(1) %out) {34 %tmp0 = call i64 @llvm.amdgcn.mov.dpp8.i64(i64 %in, i32 1)35 store i64 %tmp0, ptr addrspace(1) %out36 ret void37}38 39; GFX10PLUS-LABEL: {{^}}dpp8_v2i32:40; GFX10PLUS-DAG: v_mov_b32_dpp v0, v0 dpp8:[1,0,0,0,0,0,0,0]41; GFX10PLUS-DAG: v_mov_b32_dpp v1, v1 dpp8:[1,0,0,0,0,0,0,0]42; GFX10PLUS-DAG: global_store_{{dwordx2|b64}} v[2:3], v[0:1], off43define amdgpu_ps void @dpp8_v2i32(<2 x i32> %in, ptr addrspace(1) %out) {44 %tmp0 = call <2 x i32> @llvm.amdgcn.mov.dpp8.v3i32(<2 x i32> %in, i32 1)45 store <2 x i32> %tmp0, ptr addrspace(1) %out46 ret void47}48 49; GFX10PLUS-LABEL: {{^}}dpp8_v3i32:50; GFX10PLUS-DAG: v_mov_b32_dpp v0, v0 dpp8:[1,0,0,0,0,0,0,0]51; GFX10PLUS-DAG: v_mov_b32_dpp v1, v1 dpp8:[1,0,0,0,0,0,0,0]52; GFX10PLUS-DAG: v_mov_b32_dpp v2, v2 dpp8:[1,0,0,0,0,0,0,0]53; GFX10PLUS-DAG: global_store_{{dwordx3|b96}} v[3:4], v[0:2], off54define amdgpu_ps void @dpp8_v3i32(<3 x i32> %in, ptr addrspace(1) %out) {55 %tmp0 = call <3 x i32> @llvm.amdgcn.mov.dpp8.v3i32(<3 x i32> %in, i32 1)56 store <3 x i32> %tmp0, ptr addrspace(1) %out57 ret void58}59 60; GFX10PLUS-LABEL: {{^}}dpp8_v4i32:61; GFX10PLUS-DAG: v_mov_b32_dpp v0, v0 dpp8:[1,0,0,0,0,0,0,0]62; GFX10PLUS-DAG: v_mov_b32_dpp v1, v1 dpp8:[1,0,0,0,0,0,0,0]63; GFX10PLUS-DAG: v_mov_b32_dpp v2, v2 dpp8:[1,0,0,0,0,0,0,0]64; GFX10PLUS-DAG: v_mov_b32_dpp v3, v3 dpp8:[1,0,0,0,0,0,0,0]65; GFX10PLUS-DAG: global_store_{{dwordx4|b128}} v[4:5], v[0:3], off66define amdgpu_ps void @dpp8_v4i32(<4 x i32> %in, ptr addrspace(1) %out) {67 %tmp0 = call <4 x i32> @llvm.amdgcn.mov.dpp8.v3i32(<4 x i32> %in, i32 1)68 store <4 x i32> %tmp0, ptr addrspace(1) %out69 ret void70}71 72; GFX10PLUS-LABEL: {{^}}dpp8_p0:73; GFX10PLUS-DAG: v_mov_b32_dpp v0, v0 dpp8:[1,0,0,0,0,0,0,0]74; GFX10PLUS-DAG: v_mov_b32_dpp v1, v1 dpp8:[1,0,0,0,0,0,0,0]75; GFX10PLUS-DAG: global_store_{{dwordx2|b64}} v[2:3], v[0:1], off76define amdgpu_ps void @dpp8_p0(ptr %in, ptr addrspace(1) %out) {77 %tmp0 = call ptr @llvm.amdgcn.mov.dpp8.p0(ptr %in, i32 1)78 store ptr %tmp0, ptr addrspace(1) %out79 ret void80}81 82; GFX10PLUS-LABEL: {{^}}dpp8_p3:83; GFX10PLUS-DAG: v_mov_b32_dpp v0, v0 dpp8:[1,0,0,0,0,0,0,0]84; GFX10PLUS-DAG: global_store_{{dword|b32}} v[1:2], v0, off85define amdgpu_ps void @dpp8_p3(ptr addrspace(3) %in, ptr addrspace(1) %out) {86 %tmp0 = call ptr addrspace(3) @llvm.amdgcn.mov.dpp8.v3p3(ptr addrspace(3) %in, i32 1)87 store ptr addrspace(3) %tmp0, ptr addrspace(1) %out88 ret void89}90 91; GFX10PLUS-LABEL: {{^}}dpp8_v3p3:92; GFX10PLUS-DAG: v_mov_b32_dpp v0, v0 dpp8:[1,0,0,0,0,0,0,0]93; GFX10PLUS-DAG: v_mov_b32_dpp v1, v1 dpp8:[1,0,0,0,0,0,0,0]94; GFX10PLUS-DAG: v_mov_b32_dpp v2, v2 dpp8:[1,0,0,0,0,0,0,0]95; GFX10PLUS-DAG: global_store_{{dwordx3|b96}} v[3:4], v[0:2], off96define amdgpu_ps void @dpp8_v3p3(<3 x ptr addrspace(3)> %in, ptr addrspace(1) %out) {97 %tmp0 = call <3 x ptr addrspace(3)> @llvm.amdgcn.mov.dpp8.v3p3(<3 x ptr addrspace(3)> %in, i32 1)98 store <3 x ptr addrspace(3)> %tmp0, ptr addrspace(1) %out99 ret void100}101 102; GFX10PLUS-LABEL: {{^}}dpp8_i16:103; GFX10PLUS-DAG: v_mov_b32_dpp v0, v0 dpp8:[1,0,0,0,0,0,0,0]104; GFX10PLUS-DAG: global_store_{{short|b16}} v[1:2], v0, off105define amdgpu_ps void @dpp8_i16(i16 %in, ptr addrspace(1) %out) {106 %tmp0 = call i16 @llvm.amdgcn.mov.dpp8.i16(i16 %in, i32 1)107 store i16 %tmp0, ptr addrspace(1) %out108 ret void109}110 111; GFX10PLUS-LABEL: {{^}}dpp8_v4i16:112; GFX10PLUS-DAG: v_mov_b32_dpp v0, v0 dpp8:[1,0,0,0,0,0,0,0]113; GFX10PLUS-DAG: v_mov_b32_dpp v1, v1 dpp8:[1,0,0,0,0,0,0,0]114; GFX10PLUS-DAG: global_store_{{dwordx2|b64}} v[2:3], v[0:1], off115define amdgpu_ps void @dpp8_v4i16(<4 x i16> %in, ptr addrspace(1) %out) {116 %tmp0 = call <4 x i16> @llvm.amdgcn.mov.dpp8.v4i16(<4 x i16> %in, i32 1)117 store <4 x i16> %tmp0, ptr addrspace(1) %out118 ret void119}120 121; GFX10PLUS-LABEL: {{^}}dpp8_v4f16:122; GFX10PLUS-DAG: v_mov_b32_dpp v0, v0 dpp8:[1,0,0,0,0,0,0,0]123; GFX10PLUS-DAG: v_mov_b32_dpp v1, v1 dpp8:[1,0,0,0,0,0,0,0]124; GFX10PLUS-DAG: global_store_{{dwordx2|b64}} v[2:3], v[0:1], off125define amdgpu_ps void @dpp8_v4f16(<4 x half> %in, ptr addrspace(1) %out) {126 %tmp0 = call <4 x half> @llvm.amdgcn.mov.dpp8.v4f16(<4 x half> %in, i32 1)127 store <4 x half> %tmp0, ptr addrspace(1) %out128 ret void129}130 131; GFX10PLUS-LABEL: {{^}}dpp8_float:132; GFX10PLUS-DAG: v_mov_b32_dpp v0, v0 dpp8:[1,0,0,0,0,0,0,0]133; GFX10PLUS-DAG: global_store_{{dword|b32}} v[1:2], v0, off134define amdgpu_ps void @dpp8_float(float %in, ptr addrspace(1) %out) {135 %tmp0 = call float @llvm.amdgcn.mov.dpp8.f32(float %in, i32 1)136 store float %tmp0, ptr addrspace(1) %out137 ret void138}139 140; GFX10PLUS-LABEL: {{^}}dpp8_v3f32:141; GFX10PLUS-DAG: v_mov_b32_dpp v0, v0 dpp8:[1,0,0,0,0,0,0,0]142; GFX10PLUS-DAG: v_mov_b32_dpp v1, v1 dpp8:[1,0,0,0,0,0,0,0]143; GFX10PLUS-DAG: v_mov_b32_dpp v2, v2 dpp8:[1,0,0,0,0,0,0,0]144; GFX10PLUS-DAG: global_store_{{dwordx3|b96}} v[3:4], v[0:2], off145define amdgpu_ps void @dpp8_v3f32(<3 x float> %in, ptr addrspace(1) %out) {146 %tmp0 = call <3 x float> @llvm.amdgcn.mov.dpp8.v3f32(<3 x float> %in, i32 1)147 store <3 x float> %tmp0, ptr addrspace(1) %out148 ret void149}150 151; GFX10PLUS-LABEL: {{^}}dpp8_half:152; GFX10PLUS-DAG: v_mov_b32_dpp v0, v0 dpp8:[1,0,0,0,0,0,0,0]153; GFX10PLUS-DAG: global_store_{{short|b16}} v[1:2], v0, off154define amdgpu_ps void @dpp8_half(half %in, ptr addrspace(1) %out) {155 %tmp0 = call half @llvm.amdgcn.mov.dpp8.f16(half %in, i32 1)156 store half %tmp0, ptr addrspace(1) %out157 ret void158}159 160; GFX10PLUS-LABEL: {{^}}dpp8_bfloat:161; GFX10PLUS-DAG: v_mov_b32_dpp v0, v0 dpp8:[1,0,0,0,0,0,0,0]162; GFX10PLUS-DAG: global_store_{{short|b16}} v[1:2], v0, off163define amdgpu_ps void @dpp8_bfloat(bfloat %in, ptr addrspace(1) %out) {164 %tmp0 = call bfloat @llvm.amdgcn.mov.dpp8.bf16(bfloat %in, i32 1)165 store bfloat %tmp0, ptr addrspace(1) %out166 ret void167}168 169; GFX10PLUS-LABEL: {{^}}dpp8_v4bf16:170; GFX10PLUS-DAG: v_mov_b32_dpp v0, v0 dpp8:[1,0,0,0,0,0,0,0]171; GFX10PLUS-DAG: v_mov_b32_dpp v1, v1 dpp8:[1,0,0,0,0,0,0,0]172; GFX10PLUS-DAG: global_store_{{dwordx2|b64}} v[2:3], v[0:1], off173define amdgpu_ps void @dpp8_v4bf16(<4 x bfloat> %in, ptr addrspace(1) %out) {174 %tmp0 = call <4 x bfloat> @llvm.amdgcn.mov.dpp8.v4bf16(<4 x bfloat> %in, i32 1)175 store <4 x bfloat> %tmp0, ptr addrspace(1) %out176 ret void177}178 179; GFX10PLUS-LABEL: {{^}}dpp8_double:180; GFX10PLUS-DAG: v_mov_b32_dpp v0, v0 dpp8:[1,0,0,0,0,0,0,0]181; GFX10PLUS-DAG: v_mov_b32_dpp v1, v1 dpp8:[1,0,0,0,0,0,0,0]182; GFX10PLUS-DAG: global_store_{{dwordx2|b64}} v[2:3], v[0:1], off183define amdgpu_ps void @dpp8_double(double %in, ptr addrspace(1) %out) {184 %tmp0 = call double @llvm.amdgcn.mov.dpp8.f64(double %in, i32 1)185 store double %tmp0, ptr addrspace(1) %out186 ret void187}188 189declare i32 @llvm.amdgcn.mov.dpp8.i32(i32, i32) #0190 191attributes #0 = { nounwind readnone convergent }192