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1; RUN: llc -mtriple=amdgcn < %s | FileCheck -check-prefix=GCN %s2; RUN: llc -mtriple=amdgcn -mcpu=fiji < %s | FileCheck -check-prefix=GCN %s3 4declare <4 x i32> @llvm.amdgcn.mqsad.u32.u8(i64, i32, <4 x i32>) #05 6; GCN-LABEL: {{^}}v_mqsad_u32_u8_inline_integer_immediate:7; GCN-DAG: v_mov_b32_e32 v0, v28; GCN-DAG: v_mov_b32_e32 v1, v39; GCN: v_mqsad_u32_u8 v[2:5], v[0:1], v6, v[{{[0-9]+:[0-9]+}}]10define amdgpu_kernel void @v_mqsad_u32_u8_inline_integer_immediate(ptr addrspace(1) %out, i64 %src, i32 %a) {11 %tmp = call i64 asm "v_lsrlrev_b64 $0, $1, 1", "={v[2:3]},v"(i64 %src) #012 %tmp1 = call i32 asm "v_mov_b32 $0, $1", "={v4},v"(i32 %a) #013 %tmp2 = call <4 x i32> @llvm.amdgcn.mqsad.u32.u8(i64 %tmp, i32 %tmp1, <4 x i32> <i32 10, i32 20, i32 30, i32 40>) #014 %tmp3 = call <4 x i32> asm ";; force constraint", "=v,{v[2:5]}"(<4 x i32> %tmp2) #015 store <4 x i32> %tmp3, ptr addrspace(1) %out, align 416 ret void17}18 19; GCN-LABEL: {{^}}v_mqsad_u32_u8_non_immediate:20; GCN-DAG: v_mov_b32_e32 v0, v221; GCN-DAG: v_mov_b32_e32 v1, v322; GCN: v_mqsad_u32_u8 v[2:5], v[0:1], v6, v[{{[0-9]+:[0-9]+}}]23define amdgpu_kernel void @v_mqsad_u32_u8_non_immediate(ptr addrspace(1) %out, i64 %src, i32 %a, <4 x i32> %b) {24 %tmp = call i64 asm "v_lsrlrev_b64 $0, $1, 1", "={v[2:3]},v"(i64 %src) #025 %tmp1 = call i32 asm "v_mov_b32 $0, $1", "={v4},v"(i32 %a) #026 %tmp2 = call <4 x i32> @llvm.amdgcn.mqsad.u32.u8(i64 %tmp, i32 %tmp1, <4 x i32> %b) #027 %tmp3 = call <4 x i32> asm ";; force constraint", "=v,{v[2:5]}"(<4 x i32> %tmp2) #028 store <4 x i32> %tmp3, ptr addrspace(1) %out, align 429 ret void30}31 32; GCN-LABEL: {{^}}v_mqsad_u32_u8_inline_fp_immediate:33; GCN-DAG: v_mov_b32_e32 v0, v234; GCN-DAG: v_mov_b32_e32 v1, v335; GCN: v_mqsad_u32_u8 v[2:5], v[0:1], v6, v[{{[0-9]+:[0-9]+}}]36define amdgpu_kernel void @v_mqsad_u32_u8_inline_fp_immediate(ptr addrspace(1) %out, i64 %src, i32 %a) {37 %tmp = call i64 asm "v_lsrlrev_b64 $0, $1, 1", "={v[2:3]},v"(i64 %src) #038 %tmp1 = call i32 asm "v_mov_b32 $0, $1", "={v4},v"(i32 %a) #039 %tmp2 = call <4 x i32> @llvm.amdgcn.mqsad.u32.u8(i64 %tmp, i32 %tmp1, <4 x i32> <i32 1065353216, i32 0, i32 0, i32 0>) #040 %tmp3 = call <4 x i32> asm ";; force constraint", "=v,{v[2:5]}"(<4 x i32> %tmp2) #041 store <4 x i32> %tmp3, ptr addrspace(1) %out, align 442 ret void43}44 45; GCN-LABEL: {{^}}v_mqsad_u32_u8_use_sgpr_vgpr:46; GCN-DAG: v_mov_b32_e32 v0, v247; GCN-DAG: v_mov_b32_e32 v1, v348; GCN: v_mqsad_u32_u8 v[2:5], v[0:1], v6, v[{{[0-9]+:[0-9]+}}]49define amdgpu_kernel void @v_mqsad_u32_u8_use_sgpr_vgpr(ptr addrspace(1) %out, i64 %src, i32 %a, ptr addrspace(1) %input) {50 %in = load <4 x i32>, ptr addrspace(1) %input51 %tmp = call i64 asm "v_lsrlrev_b64 $0, $1, 1", "={v[2:3]},v"(i64 %src) #052 %tmp1 = call i32 asm "v_mov_b32 $0, $1", "={v4},v"(i32 %a) #053 %tmp2 = call <4 x i32> @llvm.amdgcn.mqsad.u32.u8(i64 %tmp, i32 %tmp1, <4 x i32> %in) #054 %tmp3 = call <4 x i32> asm ";; force constraint", "=v,{v[2:5]}"(<4 x i32> %tmp2) #055 store <4 x i32> %tmp3, ptr addrspace(1) %out, align 456 ret void57}58 59attributes #0 = { nounwind readnone }60