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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -global-isel=0 -amdgpu-load-store-vectorizer=0 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-SDAG %s3; RUN: llc -global-isel=1 -amdgpu-load-store-vectorizer=0 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-GISEL %s4 5define amdgpu_kernel void @v_permlane_bcast_b32_vss(ptr addrspace(1) %out, i32 %src0, i32 %src1, i32 %src2) {6; GFX1250-LABEL: v_permlane_bcast_b32_vss:7; GFX1250: ; %bb.0:8; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 19; GFX1250-NEXT: s_clause 0x110; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x2411; GFX1250-NEXT: s_load_b32 s6, s[4:5], 0x3412; GFX1250-NEXT: s_wait_kmcnt 0x013; GFX1250-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s214; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)15; GFX1250-NEXT: v_permlane_bcast_b32 v0, v0, s3, s616; GFX1250-NEXT: global_store_b32 v1, v0, s[0:1]17; GFX1250-NEXT: s_endpgm18 %v = call i32 @llvm.amdgcn.permlane.bcast(i32 %src0, i32 %src1, i32 %src2)19 store i32 %v, ptr addrspace(1) %out20 ret void21}22 23define amdgpu_kernel void @v_permlane_bcast_b32_vii(ptr addrspace(1) %out, i32 %src0) {24; GFX1250-LABEL: v_permlane_bcast_b32_vii:25; GFX1250: ; %bb.0:26; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 127; GFX1250-NEXT: s_load_b96 s[0:2], s[4:5], 0x2428; GFX1250-NEXT: s_wait_kmcnt 0x029; GFX1250-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s230; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)31; GFX1250-NEXT: v_permlane_bcast_b32 v0, v0, 1, 232; GFX1250-NEXT: global_store_b32 v1, v0, s[0:1]33; GFX1250-NEXT: s_endpgm34 %v = call i32 @llvm.amdgcn.permlane.bcast(i32 %src0, i32 1, i32 2)35 store i32 %v, ptr addrspace(1) %out36 ret void37}38 39define amdgpu_kernel void @v_permlane_bcast_b32_vll(ptr addrspace(1) %out, i32 %src0) {40; GFX1250-LABEL: v_permlane_bcast_b32_vll:41; GFX1250: ; %bb.0:42; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 143; GFX1250-NEXT: s_load_b96 s[0:2], s[4:5], 0x2444; GFX1250-NEXT: s_wait_kmcnt 0x045; GFX1250-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s246; GFX1250-NEXT: s_movk_i32 s2, 0x6447; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)48; GFX1250-NEXT: v_permlane_bcast_b32 v0, v0, s2, 0x6649; GFX1250-NEXT: global_store_b32 v1, v0, s[0:1]50; GFX1250-NEXT: s_endpgm51 %v = call i32 @llvm.amdgcn.permlane.bcast(i32 %src0, i32 100, i32 102)52 store i32 %v, ptr addrspace(1) %out53 ret void54}55 56define amdgpu_kernel void @v_permlane_bcast_b32_vvv(ptr addrspace(1) %out, i32 %src0) {57; GFX1250-SDAG-LABEL: v_permlane_bcast_b32_vvv:58; GFX1250-SDAG: ; %bb.0:59; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 160; GFX1250-SDAG-NEXT: s_load_b96 s[0:2], s[4:5], 0x2461; GFX1250-SDAG-NEXT: v_and_b32_e32 v1, 0x3ff, v062; GFX1250-SDAG-NEXT: v_bfe_u32 v0, v0, 10, 1063; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)64; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s3, v165; GFX1250-SDAG-NEXT: s_wait_kmcnt 0x066; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, s267; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s2, v068; GFX1250-SDAG-NEXT: v_mov_b32_e32 v0, 069; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2)70; GFX1250-SDAG-NEXT: v_permlane_bcast_b32 v1, v1, s3, s271; GFX1250-SDAG-NEXT: global_store_b32 v0, v1, s[0:1]72; GFX1250-SDAG-NEXT: s_endpgm73;74; GFX1250-GISEL-LABEL: v_permlane_bcast_b32_vvv:75; GFX1250-GISEL: ; %bb.0:76; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 177; GFX1250-GISEL-NEXT: s_load_b96 s[0:2], s[4:5], 0x2478; GFX1250-GISEL-NEXT: v_and_b32_e32 v1, 0x3ff, v079; GFX1250-GISEL-NEXT: v_bfe_u32 v0, v0, 10, 1080; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)81; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s3, v182; GFX1250-GISEL-NEXT: s_wait_xcnt 0x083; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s4, v084; GFX1250-GISEL-NEXT: s_wait_kmcnt 0x085; GFX1250-GISEL-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s286; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)87; GFX1250-GISEL-NEXT: v_permlane_bcast_b32 v0, v0, s3, s488; GFX1250-GISEL-NEXT: global_store_b32 v1, v0, s[0:1]89; GFX1250-GISEL-NEXT: s_endpgm90 %tidx = call i32 @llvm.amdgcn.workitem.id.x()91 %tidy = call i32 @llvm.amdgcn.workitem.id.y()92 %v = call i32 @llvm.amdgcn.permlane.bcast(i32 %src0, i32 %tidx, i32 %tidy)93 store i32 %v, ptr addrspace(1) %out94 ret void95}96 97define amdgpu_kernel void @v_permlane_down_b32_vss(ptr addrspace(1) %out, i32 %src0, i32 %src1, i32 %src2) {98; GFX1250-LABEL: v_permlane_down_b32_vss:99; GFX1250: ; %bb.0:100; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1101; GFX1250-NEXT: s_clause 0x1102; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24103; GFX1250-NEXT: s_load_b32 s6, s[4:5], 0x34104; GFX1250-NEXT: s_wait_kmcnt 0x0105; GFX1250-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2106; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)107; GFX1250-NEXT: v_permlane_down_b32 v0, v0, s3, s6108; GFX1250-NEXT: global_store_b32 v1, v0, s[0:1]109; GFX1250-NEXT: s_endpgm110 %v = call i32 @llvm.amdgcn.permlane.down(i32 %src0, i32 %src1, i32 %src2)111 store i32 %v, ptr addrspace(1) %out112 ret void113}114 115define amdgpu_kernel void @v_permlane_down_b32_vii(ptr addrspace(1) %out, i32 %src0) {116; GFX1250-LABEL: v_permlane_down_b32_vii:117; GFX1250: ; %bb.0:118; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1119; GFX1250-NEXT: s_load_b96 s[0:2], s[4:5], 0x24120; GFX1250-NEXT: s_wait_kmcnt 0x0121; GFX1250-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2122; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)123; GFX1250-NEXT: v_permlane_down_b32 v0, v0, 1, 2124; GFX1250-NEXT: global_store_b32 v1, v0, s[0:1]125; GFX1250-NEXT: s_endpgm126 %v = call i32 @llvm.amdgcn.permlane.down(i32 %src0, i32 1, i32 2)127 store i32 %v, ptr addrspace(1) %out128 ret void129}130 131define amdgpu_kernel void @v_permlane_down_b32_vll(ptr addrspace(1) %out, i32 %src0) {132; GFX1250-LABEL: v_permlane_down_b32_vll:133; GFX1250: ; %bb.0:134; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1135; GFX1250-NEXT: s_load_b96 s[0:2], s[4:5], 0x24136; GFX1250-NEXT: s_wait_kmcnt 0x0137; GFX1250-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2138; GFX1250-NEXT: s_movk_i32 s2, 0x64139; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)140; GFX1250-NEXT: v_permlane_down_b32 v0, v0, s2, 0x66141; GFX1250-NEXT: global_store_b32 v1, v0, s[0:1]142; GFX1250-NEXT: s_endpgm143 %v = call i32 @llvm.amdgcn.permlane.down(i32 %src0, i32 100, i32 102)144 store i32 %v, ptr addrspace(1) %out145 ret void146}147 148define amdgpu_kernel void @v_permlane_down_b32_vvv(ptr addrspace(1) %out, i32 %src0) {149; GFX1250-SDAG-LABEL: v_permlane_down_b32_vvv:150; GFX1250-SDAG: ; %bb.0:151; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1152; GFX1250-SDAG-NEXT: s_load_b96 s[0:2], s[4:5], 0x24153; GFX1250-SDAG-NEXT: v_and_b32_e32 v1, 0x3ff, v0154; GFX1250-SDAG-NEXT: v_bfe_u32 v0, v0, 10, 10155; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)156; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s3, v1157; GFX1250-SDAG-NEXT: s_wait_kmcnt 0x0158; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, s2159; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s2, v0160; GFX1250-SDAG-NEXT: v_mov_b32_e32 v0, 0161; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2)162; GFX1250-SDAG-NEXT: v_permlane_down_b32 v1, v1, s3, s2163; GFX1250-SDAG-NEXT: global_store_b32 v0, v1, s[0:1]164; GFX1250-SDAG-NEXT: s_endpgm165;166; GFX1250-GISEL-LABEL: v_permlane_down_b32_vvv:167; GFX1250-GISEL: ; %bb.0:168; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1169; GFX1250-GISEL-NEXT: s_load_b96 s[0:2], s[4:5], 0x24170; GFX1250-GISEL-NEXT: v_and_b32_e32 v1, 0x3ff, v0171; GFX1250-GISEL-NEXT: v_bfe_u32 v0, v0, 10, 10172; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)173; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s3, v1174; GFX1250-GISEL-NEXT: s_wait_xcnt 0x0175; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s4, v0176; GFX1250-GISEL-NEXT: s_wait_kmcnt 0x0177; GFX1250-GISEL-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2178; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)179; GFX1250-GISEL-NEXT: v_permlane_down_b32 v0, v0, s3, s4180; GFX1250-GISEL-NEXT: global_store_b32 v1, v0, s[0:1]181; GFX1250-GISEL-NEXT: s_endpgm182 %tidx = call i32 @llvm.amdgcn.workitem.id.x()183 %tidy = call i32 @llvm.amdgcn.workitem.id.y()184 %v = call i32 @llvm.amdgcn.permlane.down(i32 %src0, i32 %tidx, i32 %tidy)185 store i32 %v, ptr addrspace(1) %out186 ret void187}188 189define amdgpu_kernel void @v_permlane_up_b32_vss(ptr addrspace(1) %out, i32 %src0, i32 %src1, i32 %src2) {190; GFX1250-LABEL: v_permlane_up_b32_vss:191; GFX1250: ; %bb.0:192; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1193; GFX1250-NEXT: s_clause 0x1194; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24195; GFX1250-NEXT: s_load_b32 s6, s[4:5], 0x34196; GFX1250-NEXT: s_wait_kmcnt 0x0197; GFX1250-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2198; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)199; GFX1250-NEXT: v_permlane_up_b32 v0, v0, s3, s6200; GFX1250-NEXT: global_store_b32 v1, v0, s[0:1]201; GFX1250-NEXT: s_endpgm202 %v = call i32 @llvm.amdgcn.permlane.up(i32 %src0, i32 %src1, i32 %src2)203 store i32 %v, ptr addrspace(1) %out204 ret void205}206 207define amdgpu_kernel void @v_permlane_up_b32_vii(ptr addrspace(1) %out, i32 %src0) {208; GFX1250-LABEL: v_permlane_up_b32_vii:209; GFX1250: ; %bb.0:210; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1211; GFX1250-NEXT: s_load_b96 s[0:2], s[4:5], 0x24212; GFX1250-NEXT: s_wait_kmcnt 0x0213; GFX1250-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2214; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)215; GFX1250-NEXT: v_permlane_up_b32 v0, v0, 1, 2216; GFX1250-NEXT: global_store_b32 v1, v0, s[0:1]217; GFX1250-NEXT: s_endpgm218 %v = call i32 @llvm.amdgcn.permlane.up(i32 %src0, i32 1, i32 2)219 store i32 %v, ptr addrspace(1) %out220 ret void221}222 223define amdgpu_kernel void @v_permlane_up_b32_vll(ptr addrspace(1) %out, i32 %src0) {224; GFX1250-LABEL: v_permlane_up_b32_vll:225; GFX1250: ; %bb.0:226; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1227; GFX1250-NEXT: s_load_b96 s[0:2], s[4:5], 0x24228; GFX1250-NEXT: s_wait_kmcnt 0x0229; GFX1250-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2230; GFX1250-NEXT: s_movk_i32 s2, 0x64231; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)232; GFX1250-NEXT: v_permlane_up_b32 v0, v0, s2, 0x66233; GFX1250-NEXT: global_store_b32 v1, v0, s[0:1]234; GFX1250-NEXT: s_endpgm235 %v = call i32 @llvm.amdgcn.permlane.up(i32 %src0, i32 100, i32 102)236 store i32 %v, ptr addrspace(1) %out237 ret void238}239 240define amdgpu_kernel void @v_permlane_up_b32_vvv(ptr addrspace(1) %out, i32 %src0) {241; GFX1250-SDAG-LABEL: v_permlane_up_b32_vvv:242; GFX1250-SDAG: ; %bb.0:243; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1244; GFX1250-SDAG-NEXT: s_load_b96 s[0:2], s[4:5], 0x24245; GFX1250-SDAG-NEXT: v_and_b32_e32 v1, 0x3ff, v0246; GFX1250-SDAG-NEXT: v_bfe_u32 v0, v0, 10, 10247; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)248; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s3, v1249; GFX1250-SDAG-NEXT: s_wait_kmcnt 0x0250; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, s2251; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s2, v0252; GFX1250-SDAG-NEXT: v_mov_b32_e32 v0, 0253; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2)254; GFX1250-SDAG-NEXT: v_permlane_up_b32 v1, v1, s3, s2255; GFX1250-SDAG-NEXT: global_store_b32 v0, v1, s[0:1]256; GFX1250-SDAG-NEXT: s_endpgm257;258; GFX1250-GISEL-LABEL: v_permlane_up_b32_vvv:259; GFX1250-GISEL: ; %bb.0:260; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1261; GFX1250-GISEL-NEXT: s_load_b96 s[0:2], s[4:5], 0x24262; GFX1250-GISEL-NEXT: v_and_b32_e32 v1, 0x3ff, v0263; GFX1250-GISEL-NEXT: v_bfe_u32 v0, v0, 10, 10264; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)265; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s3, v1266; GFX1250-GISEL-NEXT: s_wait_xcnt 0x0267; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s4, v0268; GFX1250-GISEL-NEXT: s_wait_kmcnt 0x0269; GFX1250-GISEL-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2270; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)271; GFX1250-GISEL-NEXT: v_permlane_up_b32 v0, v0, s3, s4272; GFX1250-GISEL-NEXT: global_store_b32 v1, v0, s[0:1]273; GFX1250-GISEL-NEXT: s_endpgm274 %tidx = call i32 @llvm.amdgcn.workitem.id.x()275 %tidy = call i32 @llvm.amdgcn.workitem.id.y()276 %v = call i32 @llvm.amdgcn.permlane.up(i32 %src0, i32 %tidx, i32 %tidy)277 store i32 %v, ptr addrspace(1) %out278 ret void279}280 281define amdgpu_kernel void @v_permlane_xor_b32_vss(ptr addrspace(1) %out, i32 %src0, i32 %src1, i32 %src2) {282; GFX1250-LABEL: v_permlane_xor_b32_vss:283; GFX1250: ; %bb.0:284; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1285; GFX1250-NEXT: s_clause 0x1286; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24287; GFX1250-NEXT: s_load_b32 s6, s[4:5], 0x34288; GFX1250-NEXT: s_wait_kmcnt 0x0289; GFX1250-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2290; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)291; GFX1250-NEXT: v_permlane_xor_b32 v0, v0, s3, s6292; GFX1250-NEXT: global_store_b32 v1, v0, s[0:1]293; GFX1250-NEXT: s_endpgm294 %v = call i32 @llvm.amdgcn.permlane.xor(i32 %src0, i32 %src1, i32 %src2)295 store i32 %v, ptr addrspace(1) %out296 ret void297}298 299define amdgpu_kernel void @v_permlane_xor_b32_vii(ptr addrspace(1) %out, i32 %src0) {300; GFX1250-LABEL: v_permlane_xor_b32_vii:301; GFX1250: ; %bb.0:302; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1303; GFX1250-NEXT: s_load_b96 s[0:2], s[4:5], 0x24304; GFX1250-NEXT: s_wait_kmcnt 0x0305; GFX1250-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2306; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)307; GFX1250-NEXT: v_permlane_xor_b32 v0, v0, 1, 2308; GFX1250-NEXT: global_store_b32 v1, v0, s[0:1]309; GFX1250-NEXT: s_endpgm310 %v = call i32 @llvm.amdgcn.permlane.xor(i32 %src0, i32 1, i32 2)311 store i32 %v, ptr addrspace(1) %out312 ret void313}314 315define amdgpu_kernel void @v_permlane_xor_b32_vll(ptr addrspace(1) %out, i32 %src0) {316; GFX1250-LABEL: v_permlane_xor_b32_vll:317; GFX1250: ; %bb.0:318; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1319; GFX1250-NEXT: s_load_b96 s[0:2], s[4:5], 0x24320; GFX1250-NEXT: s_wait_kmcnt 0x0321; GFX1250-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2322; GFX1250-NEXT: s_movk_i32 s2, 0x64323; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)324; GFX1250-NEXT: v_permlane_xor_b32 v0, v0, s2, 0x66325; GFX1250-NEXT: global_store_b32 v1, v0, s[0:1]326; GFX1250-NEXT: s_endpgm327 %v = call i32 @llvm.amdgcn.permlane.xor(i32 %src0, i32 100, i32 102)328 store i32 %v, ptr addrspace(1) %out329 ret void330}331 332define amdgpu_kernel void @v_permlane_xor_b32_vvv(ptr addrspace(1) %out, i32 %src0) {333; GFX1250-SDAG-LABEL: v_permlane_xor_b32_vvv:334; GFX1250-SDAG: ; %bb.0:335; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1336; GFX1250-SDAG-NEXT: s_load_b96 s[0:2], s[4:5], 0x24337; GFX1250-SDAG-NEXT: v_and_b32_e32 v1, 0x3ff, v0338; GFX1250-SDAG-NEXT: v_bfe_u32 v0, v0, 10, 10339; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)340; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s3, v1341; GFX1250-SDAG-NEXT: s_wait_kmcnt 0x0342; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, s2343; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s2, v0344; GFX1250-SDAG-NEXT: v_mov_b32_e32 v0, 0345; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2)346; GFX1250-SDAG-NEXT: v_permlane_xor_b32 v1, v1, s3, s2347; GFX1250-SDAG-NEXT: global_store_b32 v0, v1, s[0:1]348; GFX1250-SDAG-NEXT: s_endpgm349;350; GFX1250-GISEL-LABEL: v_permlane_xor_b32_vvv:351; GFX1250-GISEL: ; %bb.0:352; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1353; GFX1250-GISEL-NEXT: s_load_b96 s[0:2], s[4:5], 0x24354; GFX1250-GISEL-NEXT: v_and_b32_e32 v1, 0x3ff, v0355; GFX1250-GISEL-NEXT: v_bfe_u32 v0, v0, 10, 10356; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)357; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s3, v1358; GFX1250-GISEL-NEXT: s_wait_xcnt 0x0359; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s4, v0360; GFX1250-GISEL-NEXT: s_wait_kmcnt 0x0361; GFX1250-GISEL-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2362; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)363; GFX1250-GISEL-NEXT: v_permlane_xor_b32 v0, v0, s3, s4364; GFX1250-GISEL-NEXT: global_store_b32 v1, v0, s[0:1]365; GFX1250-GISEL-NEXT: s_endpgm366 %tidx = call i32 @llvm.amdgcn.workitem.id.x()367 %tidy = call i32 @llvm.amdgcn.workitem.id.y()368 %v = call i32 @llvm.amdgcn.permlane.xor(i32 %src0, i32 %tidx, i32 %tidy)369 store i32 %v, ptr addrspace(1) %out370 ret void371}372 373define amdgpu_kernel void @v_permlane_idx_gen_b32_vs(ptr addrspace(1) %out, i32 %src0, i32 %src1) {374; GFX1250-LABEL: v_permlane_idx_gen_b32_vs:375; GFX1250: ; %bb.0:376; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1377; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24378; GFX1250-NEXT: s_wait_kmcnt 0x0379; GFX1250-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2380; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)381; GFX1250-NEXT: v_permlane_idx_gen_b32 v0, v0, s3382; GFX1250-NEXT: global_store_b32 v1, v0, s[0:1]383; GFX1250-NEXT: s_endpgm384 %v = call i32 @llvm.amdgcn.permlane.idx.gen(i32 %src0, i32 %src1)385 store i32 %v, ptr addrspace(1) %out386 ret void387}388 389define amdgpu_kernel void @v_permlane_idx_gen_b32_vi(ptr addrspace(1) %out, i32 %src0) {390; GFX1250-LABEL: v_permlane_idx_gen_b32_vi:391; GFX1250: ; %bb.0:392; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1393; GFX1250-NEXT: s_load_b96 s[0:2], s[4:5], 0x24394; GFX1250-NEXT: s_wait_kmcnt 0x0395; GFX1250-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2396; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)397; GFX1250-NEXT: v_permlane_idx_gen_b32 v0, v0, 1398; GFX1250-NEXT: global_store_b32 v1, v0, s[0:1]399; GFX1250-NEXT: s_endpgm400 %v = call i32 @llvm.amdgcn.permlane.idx.gen(i32 %src0, i32 1)401 store i32 %v, ptr addrspace(1) %out402 ret void403}404 405define amdgpu_kernel void @v_permlane_idx_gen_b32_vl(ptr addrspace(1) %out, i32 %src0) {406; GFX1250-LABEL: v_permlane_idx_gen_b32_vl:407; GFX1250: ; %bb.0:408; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1409; GFX1250-NEXT: s_load_b96 s[0:2], s[4:5], 0x24410; GFX1250-NEXT: s_wait_kmcnt 0x0411; GFX1250-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2412; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)413; GFX1250-NEXT: v_permlane_idx_gen_b32 v0, v0, 0x64414; GFX1250-NEXT: global_store_b32 v1, v0, s[0:1]415; GFX1250-NEXT: s_endpgm416 %v = call i32 @llvm.amdgcn.permlane.idx.gen(i32 %src0, i32 100)417 store i32 %v, ptr addrspace(1) %out418 ret void419}420 421define amdgpu_kernel void @v_permlane_idx_gen_b32_vv(ptr addrspace(1) %out) {422; GFX1250-LABEL: v_permlane_idx_gen_b32_vv:423; GFX1250: ; %bb.0:424; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1425; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x24426; GFX1250-NEXT: v_bfe_u32 v1, v0, 10, 10427; GFX1250-NEXT: v_and_b32_e32 v0, 0x3ff, v0428; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)429; GFX1250-NEXT: v_readfirstlane_b32 s2, v1430; GFX1250-NEXT: v_mov_b32_e32 v1, 0431; GFX1250-NEXT: v_permlane_idx_gen_b32 v0, v0, s2432; GFX1250-NEXT: s_wait_kmcnt 0x0433; GFX1250-NEXT: global_store_b32 v1, v0, s[0:1]434; GFX1250-NEXT: s_endpgm435 %tidx = call i32 @llvm.amdgcn.workitem.id.x()436 %tidy = call i32 @llvm.amdgcn.workitem.id.y()437 %v = call i32 @llvm.amdgcn.permlane.idx.gen(i32 %tidx, i32 %tidy)438 store i32 %v, ptr addrspace(1) %out439 ret void440}441