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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 22; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -global-isel=1 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL %s3; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -global-isel=0 < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG %s4 5declare i32 @llvm.amdgcn.s.quadmask.i32(i32)6declare i64 @llvm.amdgcn.s.quadmask.i64(i64)7 8define i32 @test_quadmask_constant_zero_i32() {9; GFX11-LABEL: test_quadmask_constant_zero_i32:10; GFX11: ; %bb.0: ; %entry11; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)12; GFX11-NEXT: v_mov_b32_e32 v0, 013; GFX11-NEXT: s_setpc_b64 s[30:31]14entry:15 %qm = call i32 @llvm.amdgcn.s.quadmask.i32(i32 0)16 ret i32 %qm17}18 19define i32 @test_quadmask_constant_neg_one_i32() {20; GFX11-LABEL: test_quadmask_constant_neg_one_i32:21; GFX11: ; %bb.0: ; %entry22; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)23; GFX11-NEXT: v_mov_b32_e32 v0, 0xff24; GFX11-NEXT: s_setpc_b64 s[30:31]25entry:26 %qm = call i32 @llvm.amdgcn.s.quadmask.i32(i32 -1)27 ret i32 %qm28}29 30define i32 @test_quadmask_constant_undef_i32() {31; GFX11-LABEL: test_quadmask_constant_undef_i32:32; GFX11: ; %bb.0: ; %entry33; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)34; GFX11-NEXT: s_quadmask_b32 s0, s035; GFX11-NEXT: v_mov_b32_e32 v0, s036; GFX11-NEXT: s_setpc_b64 s[30:31]37entry:38 %qm = call i32 @llvm.amdgcn.s.quadmask.i32(i32 undef)39 ret i32 %qm40}41 42define i32 @test_quadmask_constant_poison_i32() {43; GFX11-LABEL: test_quadmask_constant_poison_i32:44; GFX11: ; %bb.0: ; %entry45; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)46; GFX11-NEXT: s_quadmask_b32 s0, s047; GFX11-NEXT: v_mov_b32_e32 v0, s048; GFX11-NEXT: s_setpc_b64 s[30:31]49entry:50 %qm = call i32 @llvm.amdgcn.s.quadmask.i32(i32 poison)51 ret i32 %qm52}53 54define i32 @test_quadmask_constant_i32() {55; GFX11-LABEL: test_quadmask_constant_i32:56; GFX11: ; %bb.0: ; %entry57; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)58; GFX11-NEXT: v_mov_b32_e32 v0, 0xcb59; GFX11-NEXT: s_setpc_b64 s[30:31]60entry:61 %qm = call i32 @llvm.amdgcn.s.quadmask.i32(i32 u0x85003092)62 ret i32 %qm63}64 65define amdgpu_cs void @test_quadmask_sgpr_i32(i32 inreg %mask, ptr addrspace(1) %out) {66; GFX11-LABEL: test_quadmask_sgpr_i32:67; GFX11: ; %bb.0: ; %entry68; GFX11-NEXT: s_quadmask_b32 s0, s069; GFX11-NEXT: v_mov_b32_e32 v2, s070; GFX11-NEXT: global_store_b32 v[0:1], v2, off71; GFX11-NEXT: s_endpgm72entry:73 %qm = call i32 @llvm.amdgcn.s.quadmask.i32(i32 %mask)74 store i32 %qm, ptr addrspace(1) %out75 ret void76}77 78 79define i32 @test_quadmask_vgpr_i32(i32 %mask) {80; GFX11-LABEL: test_quadmask_vgpr_i32:81; GFX11: ; %bb.0: ; %entry82; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)83; GFX11-NEXT: v_readfirstlane_b32 s0, v084; GFX11-NEXT: s_quadmask_b32 s0, s085; GFX11-NEXT: v_mov_b32_e32 v0, s086; GFX11-NEXT: s_setpc_b64 s[30:31]87entry:88 %qm = call i32 @llvm.amdgcn.s.quadmask.i32(i32 %mask)89 ret i32 %qm90}91 92define i64 @test_quadmask_constant_i64() {93; GFX11-LABEL: test_quadmask_constant_i64:94; GFX11: ; %bb.0: ; %entry95; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)96; GFX11-NEXT: v_dual_mov_b32 v0, 0xe3e6 :: v_dual_mov_b32 v1, 097; GFX11-NEXT: s_setpc_b64 s[30:31]98entry:99 %qm = call i64 @llvm.amdgcn.s.quadmask.i64(i64 u0x67D000FC85F00A90)100 ret i64 %qm101}102 103define i64 @test_quadmask_constant_zero_i64() {104; GFX11-LABEL: test_quadmask_constant_zero_i64:105; GFX11: ; %bb.0: ; %entry106; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)107; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0108; GFX11-NEXT: s_setpc_b64 s[30:31]109entry:110 %qm = call i64 @llvm.amdgcn.s.quadmask.i64(i64 0)111 ret i64 %qm112}113 114define i64 @test_quadmask_constant_neg_one_i64() {115; GFX11-LABEL: test_quadmask_constant_neg_one_i64:116; GFX11: ; %bb.0: ; %entry117; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)118; GFX11-NEXT: v_dual_mov_b32 v0, 0xffff :: v_dual_mov_b32 v1, 0119; GFX11-NEXT: s_setpc_b64 s[30:31]120entry:121 %qm = call i64 @llvm.amdgcn.s.quadmask.i64(i64 -1)122 ret i64 %qm123}124 125define i64 @test_quadmask_constant_undef_i64() {126; GFX11-LABEL: test_quadmask_constant_undef_i64:127; GFX11: ; %bb.0: ; %entry128; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)129; GFX11-NEXT: s_quadmask_b64 s[0:1], s[0:1]130; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1131; GFX11-NEXT: s_setpc_b64 s[30:31]132entry:133 %qm = call i64 @llvm.amdgcn.s.quadmask.i64(i64 undef)134 ret i64 %qm135}136 137define i64 @test_quadmask_constant_poison_i64() {138; GFX11-LABEL: test_quadmask_constant_poison_i64:139; GFX11: ; %bb.0: ; %entry140; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)141; GFX11-NEXT: s_quadmask_b64 s[0:1], s[0:1]142; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1143; GFX11-NEXT: s_setpc_b64 s[30:31]144entry:145 %qm = call i64 @llvm.amdgcn.s.quadmask.i64(i64 poison)146 ret i64 %qm147}148 149define amdgpu_cs void @test_quadmask_sgpr_i64(i64 inreg %mask, ptr addrspace(1) %out) {150; GFX11-LABEL: test_quadmask_sgpr_i64:151; GFX11: ; %bb.0: ; %entry152; GFX11-NEXT: s_quadmask_b64 s[0:1], s[0:1]153; GFX11-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0154; GFX11-NEXT: global_store_b64 v[0:1], v[2:3], off155; GFX11-NEXT: s_endpgm156entry:157 %qm = call i64 @llvm.amdgcn.s.quadmask.i64(i64 %mask)158 store i64 %qm, ptr addrspace(1) %out159 ret void160}161 162define i64 @test_quadmask_vgpr_i64(i64 %mask) {163; GFX11-LABEL: test_quadmask_vgpr_i64:164; GFX11: ; %bb.0: ; %entry165; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)166; GFX11-NEXT: v_readfirstlane_b32 s0, v0167; GFX11-NEXT: v_readfirstlane_b32 s1, v1168; GFX11-NEXT: s_quadmask_b64 s[0:1], s[0:1]169; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1170; GFX11-NEXT: s_setpc_b64 s[30:31]171entry:172 %qm = call i64 @llvm.amdgcn.s.quadmask.i64(i64 %mask)173 ret i64 %qm174}175 176;; Ensure that AND/ICMP cannot be fused into an AND because s_quadmask_b32 implicitly defines SCC.177define amdgpu_kernel void @test_scc_quadmask_32(i32 %val0, i32 %val1, ptr addrspace(1) %ptr) {178; GFX11-GISEL-LABEL: test_scc_quadmask_32:179; GFX11-GISEL: ; %bb.0:180; GFX11-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24181; GFX11-GISEL-NEXT: v_mov_b32_e32 v0, 0182; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)183; GFX11-GISEL-NEXT: s_and_b32 s0, s0, 1184; GFX11-GISEL-NEXT: s_quadmask_b32 s1, s1185; GFX11-GISEL-NEXT: s_cmp_eq_u32 s0, 0186; GFX11-GISEL-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v3, s1187; GFX11-GISEL-NEXT: s_cselect_b32 s0, 1, 0188; GFX11-GISEL-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v4, s0189; GFX11-GISEL-NEXT: global_store_b32 v2, v3, s[2:3]190; GFX11-GISEL-NEXT: global_store_b32 v[0:1], v4, off191; GFX11-GISEL-NEXT: s_endpgm192;193; GFX11-SDAG-LABEL: test_scc_quadmask_32:194; GFX11-SDAG: ; %bb.0:195; GFX11-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x24196; GFX11-SDAG-NEXT: v_mov_b32_e32 v2, 0197; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)198; GFX11-SDAG-NEXT: s_and_b32 s0, s0, 1199; GFX11-SDAG-NEXT: s_quadmask_b32 s1, s1200; GFX11-SDAG-NEXT: s_cmp_eq_u32 s0, 0201; GFX11-SDAG-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v3, s1202; GFX11-SDAG-NEXT: s_cselect_b32 s0, -1, 0203; GFX11-SDAG-NEXT: v_mov_b32_e32 v1, 0204; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v4, 0, 1, s0205; GFX11-SDAG-NEXT: global_store_b32 v2, v3, s[2:3]206; GFX11-SDAG-NEXT: global_store_b32 v[0:1], v4, off207; GFX11-SDAG-NEXT: s_endpgm208 %and = and i32 %val0, 1209 %result = call i32 @llvm.amdgcn.s.quadmask.i32(i32 %val1) nounwind readnone210 store i32 %result, ptr addrspace(1) %ptr211 %cmp = icmp eq i32 %and, 0212 %sel = select i1 %cmp, i32 1, i32 0213 store i32 %sel, ptr addrspace(1) null, align 4214 ret void215}216 217;; Ensure that AND/ICMP cannot be fused into an AND because s_quadmask_b64 implicitly defines SCC.218define amdgpu_kernel void @test_scc_quadmask_64(i32 %val0, i64 %val1, ptr addrspace(1) %ptr) {219; GFX11-GISEL-LABEL: test_scc_quadmask_64:220; GFX11-GISEL: ; %bb.0:221; GFX11-GISEL-NEXT: s_clause 0x1222; GFX11-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x2c223; GFX11-GISEL-NEXT: s_load_b32 s4, s[4:5], 0x24224; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)225; GFX11-GISEL-NEXT: s_quadmask_b64 s[0:1], s[0:1]226; GFX11-GISEL-NEXT: s_and_b32 s4, s4, 1227; GFX11-GISEL-NEXT: v_mov_b32_e32 v0, s0228; GFX11-GISEL-NEXT: s_cmp_eq_u32 s4, 0229; GFX11-GISEL-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v1, s1230; GFX11-GISEL-NEXT: s_cselect_b32 s0, 1, 0231; GFX11-GISEL-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v5, s0232; GFX11-GISEL-NEXT: v_mov_b32_e32 v3, 0233; GFX11-GISEL-NEXT: global_store_b64 v4, v[0:1], s[2:3]234; GFX11-GISEL-NEXT: global_store_b32 v[2:3], v5, off235; GFX11-GISEL-NEXT: s_endpgm236;237; GFX11-SDAG-LABEL: test_scc_quadmask_64:238; GFX11-SDAG: ; %bb.0:239; GFX11-SDAG-NEXT: s_clause 0x1240; GFX11-SDAG-NEXT: s_load_b32 s6, s[4:5], 0x24241; GFX11-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x2c242; GFX11-SDAG-NEXT: v_mov_b32_e32 v4, 0243; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)244; GFX11-SDAG-NEXT: s_and_b32 s4, s6, 1245; GFX11-SDAG-NEXT: s_quadmask_b64 s[0:1], s[0:1]246; GFX11-SDAG-NEXT: s_cmp_eq_u32 s4, 0247; GFX11-SDAG-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v3, s1248; GFX11-SDAG-NEXT: v_mov_b32_e32 v2, s0249; GFX11-SDAG-NEXT: s_cselect_b32 s0, -1, 0250; GFX11-SDAG-NEXT: v_mov_b32_e32 v1, 0251; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v5, 0, 1, s0252; GFX11-SDAG-NEXT: global_store_b64 v4, v[2:3], s[2:3]253; GFX11-SDAG-NEXT: global_store_b32 v[0:1], v5, off254; GFX11-SDAG-NEXT: s_endpgm255 %and = and i32 %val0, 1256 %result = call i64 @llvm.amdgcn.s.quadmask.i64(i64 %val1) nounwind readnone257 store i64 %result, ptr addrspace(1) %ptr258 %cmp = icmp eq i32 %and, 0259 %sel = select i1 %cmp, i32 1, i32 0260 store i32 %sel, ptr addrspace(1) null, align 4261 ret void262}263