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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx908 < %s | FileCheck -check-prefix=GFX9 %s3; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1250 < %s | FileCheck -check-prefix=GFX12 %s4 5define void @raw_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset(float %val, <4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {6; GFX9-LABEL: raw_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset:7; GFX9: ; %bb.0:8; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)9; GFX9-NEXT: buffer_atomic_add_f32 v0, v1, s[16:19], s20 offen offset:2410; GFX9-NEXT: s_waitcnt vmcnt(0)11; GFX9-NEXT: s_setpc_b64 s[30:31]12;13; GFX12-LABEL: raw_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset:14; GFX12: ; %bb.0:15; GFX12-NEXT: s_wait_loadcnt_dscnt 0x016; GFX12-NEXT: s_wait_kmcnt 0x017; GFX12-NEXT: v_add_nc_u32_e32 v1, 24, v118; GFX12-NEXT: buffer_atomic_add_f32 v0, v1, s[0:3], s16 offen19; GFX12-NEXT: s_set_pc_i64 s[30:31]20 %voffset.add = add i32 %voffset, 2421 %ret = call float @llvm.amdgcn.raw.buffer.atomic.fadd.f32(float %val, <4 x i32> %rsrc, i32 %voffset.add, i32 %soffset, i32 0)22 ret void23}24 25define void @raw_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__0_voffset__sgpr_soffset(float %val, <4 x i32> inreg %rsrc, i32 inreg %soffset) {26; GFX9-LABEL: raw_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__0_voffset__sgpr_soffset:27; GFX9: ; %bb.0:28; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)29; GFX9-NEXT: buffer_atomic_add_f32 v0, off, s[16:19], s2030; GFX9-NEXT: s_waitcnt vmcnt(0)31; GFX9-NEXT: s_setpc_b64 s[30:31]32;33; GFX12-LABEL: raw_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__0_voffset__sgpr_soffset:34; GFX12: ; %bb.0:35; GFX12-NEXT: s_wait_loadcnt_dscnt 0x036; GFX12-NEXT: s_wait_kmcnt 0x037; GFX12-NEXT: buffer_atomic_add_f32 v0, off, s[0:3], s1638; GFX12-NEXT: s_set_pc_i64 s[30:31]39 %ret = call float @llvm.amdgcn.raw.buffer.atomic.fadd.f32(float %val, <4 x i32> %rsrc, i32 0, i32 %soffset, i32 0)40 ret void41}42 43define void @raw_buffer_atomic_add_v2f16_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset(<2 x half> %val, <4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {44; GFX9-LABEL: raw_buffer_atomic_add_v2f16_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset:45; GFX9: ; %bb.0:46; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)47; GFX9-NEXT: buffer_atomic_pk_add_f16 v0, v1, s[16:19], s20 offen48; GFX9-NEXT: s_waitcnt vmcnt(0)49; GFX9-NEXT: s_setpc_b64 s[30:31]50;51; GFX12-LABEL: raw_buffer_atomic_add_v2f16_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset:52; GFX12: ; %bb.0:53; GFX12-NEXT: s_wait_loadcnt_dscnt 0x054; GFX12-NEXT: s_wait_kmcnt 0x055; GFX12-NEXT: buffer_atomic_pk_add_f16 v0, v1, s[0:3], s16 offen56; GFX12-NEXT: s_set_pc_i64 s[30:31]57 %ret = call <2 x half> @llvm.amdgcn.raw.buffer.atomic.fadd.v2f16(<2 x half> %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)58 ret void59}60 61define void @raw_buffer_atomic_add_v2f16_noret__vgpr_val__sgpr_rsrc__0_voffset__sgpr_soffset(<2 x half> %val, <4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {62; GFX9-LABEL: raw_buffer_atomic_add_v2f16_noret__vgpr_val__sgpr_rsrc__0_voffset__sgpr_soffset:63; GFX9: ; %bb.0:64; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)65; GFX9-NEXT: buffer_atomic_pk_add_f16 v0, off, s[16:19], s20 offset:9266; GFX9-NEXT: s_waitcnt vmcnt(0)67; GFX9-NEXT: s_setpc_b64 s[30:31]68;69; GFX12-LABEL: raw_buffer_atomic_add_v2f16_noret__vgpr_val__sgpr_rsrc__0_voffset__sgpr_soffset:70; GFX12: ; %bb.0:71; GFX12-NEXT: s_wait_loadcnt_dscnt 0x072; GFX12-NEXT: s_wait_kmcnt 0x073; GFX12-NEXT: buffer_atomic_pk_add_f16 v0, off, s[0:3], s16 offset:9274; GFX12-NEXT: s_set_pc_i64 s[30:31]75 %ret = call <2 x half> @llvm.amdgcn.raw.buffer.atomic.fadd.v2f16(<2 x half> %val, <4 x i32> %rsrc, i32 92, i32 %soffset, i32 0)76 ret void77}78 79define void @raw_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc(float %val, <4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {80; GFX9-LABEL: raw_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc:81; GFX9: ; %bb.0:82; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)83; GFX9-NEXT: buffer_atomic_add_f32 v0, v1, s[16:19], s20 offen slc84; GFX9-NEXT: s_waitcnt vmcnt(0)85; GFX9-NEXT: s_setpc_b64 s[30:31]86;87; GFX12-LABEL: raw_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc:88; GFX12: ; %bb.0:89; GFX12-NEXT: s_wait_loadcnt_dscnt 0x090; GFX12-NEXT: s_wait_kmcnt 0x091; GFX12-NEXT: buffer_atomic_add_f32 v0, v1, s[0:3], s16 offen th:TH_ATOMIC_NT92; GFX12-NEXT: s_set_pc_i64 s[30:31]93 %ret = call float @llvm.amdgcn.raw.buffer.atomic.fadd.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 2)94 ret void95}96 97declare float @llvm.amdgcn.raw.buffer.atomic.fadd.f32(float, <4 x i32>, i32, i32, i32 immarg) #098declare <2 x half> @llvm.amdgcn.raw.buffer.atomic.fadd.v2f16(<2 x half>, <4 x i32>, i32, i32, i32 immarg) #099 100attributes #0 = { nounwind }101