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1; RUN: llc < %s -mtriple=amdgcn -mcpu=tonga -show-mc-encoding | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=UNPACKED %s2; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx810 | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=PACKED %s3; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx900 | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=PACKED %s4 5; GCN-LABEL: {{^}}buffer_load_format_d16_x:6; GCN: buffer_load_format_d16_x v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], 07define amdgpu_ps half @buffer_load_format_d16_x(<4 x i32> inreg %rsrc) {8main_body:9 %data = call half @llvm.amdgcn.raw.buffer.load.format.f16(<4 x i32> %rsrc, i32 0, i32 0, i32 0)10 ret half %data11}12 13; GCN-LABEL: {{^}}buffer_load_format_d16_xy:14; UNPACKED: buffer_load_format_d16_xy v[{{[0-9]+}}:[[HI:[0-9]+]]], off, s[{{[0-9]+:[0-9]+}}], 015; UNPACKED: v_mov_b32_e32 v{{[0-9]+}}, v[[HI]]16 17; PACKED: buffer_load_format_d16_xy v[[FULL:[0-9]+]], off, s[{{[0-9]+:[0-9]+}}], 018; PACKED: v_lshrrev_b32_e32 v{{[0-9]+}}, 16, v[[FULL]]19define amdgpu_ps half @buffer_load_format_d16_xy(<4 x i32> inreg %rsrc) {20main_body:21 %data = call <2 x half> @llvm.amdgcn.raw.buffer.load.format.v2f16(<4 x i32> %rsrc, i32 0, i32 0, i32 0)22 %elt = extractelement <2 x half> %data, i32 123 ret half %elt24}25 26; GCN-LABEL: {{^}}buffer_load_format_d16_xyz:27; UNPACKED: buffer_load_format_d16_xyz v[{{[0-9]+}}:[[HI:[0-9]+]]], off, s[{{[0-9]+:[0-9]+}}], 028; UNPACKED: v_mov_b32_e32 v{{[0-9]+}}, v[[HI]]29 30; PACKED: buffer_load_format_d16_xyz v[{{[0-9]+}}:[[HI:[0-9]+]]], off, s[{{[0-9]+:[0-9]+}}], 031define amdgpu_ps half @buffer_load_format_d16_xyz(<4 x i32> inreg %rsrc) {32main_body:33 %data = call <3 x half> @llvm.amdgcn.raw.buffer.load.format.v3f16(<4 x i32> %rsrc, i32 0, i32 0, i32 0)34 %elt = extractelement <3 x half> %data, i32 235 ret half %elt36}37 38; GCN-LABEL: {{^}}buffer_load_format_d16_xyzw:39; UNPACKED: buffer_load_format_d16_xyzw v[{{[0-9]+}}:[[HI:[0-9]+]]], off, s[{{[0-9]+:[0-9]+}}], 040; UNPACKED: v_mov_b32_e32 v{{[0-9]+}}, v[[HI]]41 42; PACKED: buffer_load_format_d16_xyzw v[{{[0-9]+}}:[[HI:[0-9]+]]], off, s[{{[0-9]+:[0-9]+}}], 043; PACKED: v_lshrrev_b32_e32 v{{[0-9]+}}, 16, v[[HI]]44define amdgpu_ps half @buffer_load_format_d16_xyzw(<4 x i32> inreg %rsrc) {45main_body:46 %data = call <4 x half> @llvm.amdgcn.raw.buffer.load.format.v4f16(<4 x i32> %rsrc, i32 0, i32 0, i32 0)47 %elt = extractelement <4 x half> %data, i32 348 ret half %elt49}50 51declare half @llvm.amdgcn.raw.buffer.load.format.f16(<4 x i32>, i32, i32, i32)52declare <2 x half> @llvm.amdgcn.raw.buffer.load.format.v2f16(<4 x i32>, i32, i32, i32)53declare <3 x half> @llvm.amdgcn.raw.buffer.load.format.v3f16(<4 x i32>, i32, i32, i32)54declare <4 x half> @llvm.amdgcn.raw.buffer.load.format.v4f16(<4 x i32>, i32, i32, i32)55