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1;RUN: llc < %s -mtriple=amdgcn -mcpu=verde | FileCheck %s2;RUN: llc < %s -mtriple=amdgcn -mcpu=tonga | FileCheck %s3 4;CHECK-LABEL: {{^}}buffer_load:5;CHECK: buffer_load_format_xyzw v[0:3], off, s[0:3], 06;CHECK: buffer_load_format_xyzw v[4:7], off, s[0:3], 0 glc7;CHECK: buffer_load_format_xyzw v[8:11], off, s[0:3], 0 slc8;CHECK: s_waitcnt9define amdgpu_ps {<4 x float>, <4 x float>, <4 x float>} @buffer_load(<4 x i32> inreg) {10main_body:11 %data = call <4 x float> @llvm.amdgcn.raw.buffer.load.format.v4f32(<4 x i32> %0, i32 0, i32 0, i32 0)12 %data_glc = call <4 x float> @llvm.amdgcn.raw.buffer.load.format.v4f32(<4 x i32> %0, i32 0, i32 0, i32 1)13 %data_slc = call <4 x float> @llvm.amdgcn.raw.buffer.load.format.v4f32(<4 x i32> %0, i32 0, i32 0, i32 2)14 %r0 = insertvalue {<4 x float>, <4 x float>, <4 x float>} poison, <4 x float> %data, 015 %r1 = insertvalue {<4 x float>, <4 x float>, <4 x float>} %r0, <4 x float> %data_glc, 116 %r2 = insertvalue {<4 x float>, <4 x float>, <4 x float>} %r1, <4 x float> %data_slc, 217 ret {<4 x float>, <4 x float>, <4 x float>} %r218}19 20;CHECK-LABEL: {{^}}buffer_load_v4i32:21;CHECK: buffer_load_format_xyzw v[0:3], off, s[0:3], 022;CHECK: buffer_load_format_xyzw v[4:7], off, s[0:3], 0 glc23;CHECK: buffer_load_format_xyzw v[8:11], off, s[0:3], 0 slc24;CHECK: s_waitcnt25define amdgpu_ps {<4 x float>, <4 x float>, <4 x float>} @buffer_load_v4i32(<4 x i32> inreg) {26main_body:27 %data = call <4 x i32> @llvm.amdgcn.raw.buffer.load.format.v4i32(<4 x i32> %0, i32 0, i32 0, i32 0)28 %data_glc = call <4 x i32> @llvm.amdgcn.raw.buffer.load.format.v4i32(<4 x i32> %0, i32 0, i32 0, i32 1)29 %data_slc = call <4 x i32> @llvm.amdgcn.raw.buffer.load.format.v4i32(<4 x i32> %0, i32 0, i32 0, i32 2)30 %fdata = bitcast <4 x i32> %data to <4 x float>31 %fdata_glc = bitcast <4 x i32> %data_glc to <4 x float>32 %fdata_slc = bitcast <4 x i32> %data_slc to <4 x float>33 %r0 = insertvalue {<4 x float>, <4 x float>, <4 x float>} poison, <4 x float> %fdata, 034 %r1 = insertvalue {<4 x float>, <4 x float>, <4 x float>} %r0, <4 x float> %fdata_glc, 135 %r2 = insertvalue {<4 x float>, <4 x float>, <4 x float>} %r1, <4 x float> %fdata_slc, 236 ret {<4 x float>, <4 x float>, <4 x float>} %r237}38 39;CHECK-LABEL: {{^}}buffer_load_immoffs:40;CHECK: buffer_load_format_xyzw v[0:3], off, s[0:3], 0 offset:4241;CHECK: s_waitcnt42define amdgpu_ps <4 x float> @buffer_load_immoffs(<4 x i32> inreg) {43main_body:44 %data = call <4 x float> @llvm.amdgcn.raw.buffer.load.format.v4f32(<4 x i32> %0, i32 42, i32 0, i32 0)45 ret <4 x float> %data46}47 48;CHECK-LABEL: {{^}}buffer_load_immoffs_v4i32:49;CHECK: buffer_load_format_xyzw v[0:3], off, s[0:3], 0 offset:4250;CHECK: s_waitcnt51define amdgpu_ps <4 x float> @buffer_load_immoffs_v4i32(<4 x i32> inreg) {52main_body:53 %data = call <4 x i32> @llvm.amdgcn.raw.buffer.load.format.v4i32(<4 x i32> %0, i32 42, i32 0, i32 0)54 %fdata = bitcast <4 x i32> %data to <4 x float>55 ret <4 x float> %fdata56}57 58;CHECK-LABEL: {{^}}buffer_load_immoffs_large:59;CHECK-DAG: buffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, off, s[0:3], 60 offset:409260;CHECK-DAG: s_movk_i32 [[OFS1:s[0-9]+]], 0x7ffc61;CHECK-DAG: buffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, off, s[0:3], [[OFS1]] offset:409262;CHECK-DAG: s_mov_b32 [[OFS2:s[0-9]+]], 0x8ffc63;CHECK-DAG: buffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, off, s[0:3], [[OFS2]] offset:464;CHECK: s_waitcnt65define amdgpu_ps <4 x float> @buffer_load_immoffs_large(<4 x i32> inreg) {66main_body:67 %d.0 = call <4 x float> @llvm.amdgcn.raw.buffer.load.format.v4f32(<4 x i32> %0, i32 4092, i32 60, i32 0)68 %d.1 = call <4 x float> @llvm.amdgcn.raw.buffer.load.format.v4f32(<4 x i32> %0, i32 4092, i32 32764, i32 0)69 %d.2 = call <4 x float> @llvm.amdgcn.raw.buffer.load.format.v4f32(<4 x i32> %0, i32 4, i32 36860, i32 0)70 %d.3 = fadd <4 x float> %d.0, %d.171 %data = fadd <4 x float> %d.2, %d.372 ret <4 x float> %data73}74 75;CHECK-LABEL: {{^}}buffer_load_immoffs_large_v4i32:76;CHECK-DAG: buffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, off, s[0:3], 60 offset:409277;CHECK-DAG: s_movk_i32 [[OFS1:s[0-9]+]], 0x7ffc78;CHECK-DAG: buffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, off, s[0:3], [[OFS1]] offset:409279;CHECK-DAG: s_mov_b32 [[OFS2:s[0-9]+]], 0x8ffc80;CHECK-DAG: buffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, off, s[0:3], [[OFS2]] offset:481;CHECK: s_waitcnt82define amdgpu_ps <4 x float> @buffer_load_immoffs_large_v4i32(<4 x i32> inreg) {83main_body:84 %d.0 = call <4 x i32> @llvm.amdgcn.raw.buffer.load.format.v4i32(<4 x i32> %0, i32 4092, i32 60, i32 0)85 %d.1 = call <4 x i32> @llvm.amdgcn.raw.buffer.load.format.v4i32(<4 x i32> %0, i32 4092, i32 32764, i32 0)86 %d.2 = call <4 x i32> @llvm.amdgcn.raw.buffer.load.format.v4i32(<4 x i32> %0, i32 4, i32 36860, i32 0)87 %fd.0 = bitcast <4 x i32> %d.0 to <4 x float>88 %fd.1 = bitcast <4 x i32> %d.1 to <4 x float>89 %fd.2 = bitcast <4 x i32> %d.2 to <4 x float>90 %d.3 = fadd <4 x float> %fd.0, %fd.191 %data = fadd <4 x float> %fd.2, %d.392 ret <4 x float> %data93}94 95;CHECK-LABEL: {{^}}buffer_load_ofs:96;CHECK: buffer_load_format_xyzw v[0:3], v0, s[0:3], 0 offen97;CHECK: s_waitcnt98define amdgpu_ps <4 x float> @buffer_load_ofs(<4 x i32> inreg, i32) {99main_body:100 %data = call <4 x float> @llvm.amdgcn.raw.buffer.load.format.v4f32(<4 x i32> %0, i32 %1, i32 0, i32 0)101 ret <4 x float> %data102}103 104;CHECK-LABEL: {{^}}buffer_load_ofs_v4i32:105;CHECK: buffer_load_format_xyzw v[0:3], v0, s[0:3], 0 offen106;CHECK: s_waitcnt107define amdgpu_ps <4 x float> @buffer_load_ofs_v4i32(<4 x i32> inreg, i32) {108main_body:109 %data = call <4 x i32> @llvm.amdgcn.raw.buffer.load.format.v4i32(<4 x i32> %0, i32 %1, i32 0, i32 0)110 %fdata = bitcast <4 x i32> %data to <4 x float>111 ret <4 x float> %fdata112}113 114;CHECK-LABEL: {{^}}buffer_load_ofs_imm:115;CHECK: buffer_load_format_xyzw v[0:3], v0, s[0:3], 0 offen offset:60116;CHECK: s_waitcnt117define amdgpu_ps <4 x float> @buffer_load_ofs_imm(<4 x i32> inreg, i32) {118main_body:119 %ofs = add i32 %1, 60120 %data = call <4 x float> @llvm.amdgcn.raw.buffer.load.format.v4f32(<4 x i32> %0, i32 %ofs, i32 0, i32 0)121 ret <4 x float> %data122}123 124;CHECK-LABEL: {{^}}buffer_load_ofs_imm_v4i32:125;CHECK: buffer_load_format_xyzw v[0:3], v0, s[0:3], 0 offen offset:60126;CHECK: s_waitcnt127define amdgpu_ps <4 x float> @buffer_load_ofs_imm_v4i32(<4 x i32> inreg, i32) {128main_body:129 %ofs = add i32 %1, 60130 %data = call <4 x i32> @llvm.amdgcn.raw.buffer.load.format.v4i32(<4 x i32> %0, i32 %ofs, i32 0, i32 0)131 %fdata = bitcast <4 x i32> %data to <4 x float>132 ret <4 x float> %fdata133}134 135;CHECK-LABEL: {{^}}buffer_load_x:136;CHECK: buffer_load_format_x v0, off, s[0:3], 0137;CHECK: s_waitcnt138define amdgpu_ps float @buffer_load_x(<4 x i32> inreg %rsrc) {139main_body:140 %data = call float @llvm.amdgcn.raw.buffer.load.format.f32(<4 x i32> %rsrc, i32 0, i32 0, i32 0)141 ret float %data142}143 144;CHECK-LABEL: {{^}}buffer_load_xy:145;CHECK: buffer_load_format_xy v[0:1], off, s[0:3], 0146;CHECK: s_waitcnt147define amdgpu_ps <2 x float> @buffer_load_xy(<4 x i32> inreg %rsrc) {148main_body:149 %data = call <2 x float> @llvm.amdgcn.raw.buffer.load.format.v2f32(<4 x i32> %rsrc, i32 0, i32 0, i32 0)150 ret <2 x float> %data151}152 153declare float @llvm.amdgcn.raw.buffer.load.format.f32(<4 x i32>, i32, i32, i32) #0154declare <2 x float> @llvm.amdgcn.raw.buffer.load.format.v2f32(<4 x i32>, i32, i32, i32) #0155declare <4 x float> @llvm.amdgcn.raw.buffer.load.format.v4f32(<4 x i32>, i32, i32, i32) #0156declare <4 x i32> @llvm.amdgcn.raw.buffer.load.format.v4i32(<4 x i32>, i32, i32, i32) #0157 158attributes #0 = { nounwind readonly }159