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1;RUN: llc < %s -mtriple=amdgcn -mcpu=verde | FileCheck -check-prefix=VERDE %s2;RUN: llc < %s -mtriple=amdgcn -mcpu=tonga | FileCheck %s3 4;CHECK-LABEL: {{^}}buffer_store:5;CHECK-NOT: s_waitcnt6;CHECK: buffer_store_format_xyzw v[0:3], off, s[0:3], 07;CHECK: buffer_store_format_xyzw v[4:7], off, s[0:3], 0 glc8;CHECK: buffer_store_format_xyzw v[8:11], off, s[0:3], 0 slc9define amdgpu_ps void @buffer_store(<4 x i32> inreg, <4 x float>, <4 x float>, <4 x float>) {10main_body:11 call void @llvm.amdgcn.raw.buffer.store.format.v4f32(<4 x float> %1, <4 x i32> %0, i32 0, i32 0, i32 0)12 call void @llvm.amdgcn.raw.buffer.store.format.v4f32(<4 x float> %2, <4 x i32> %0, i32 0, i32 0, i32 1)13 call void @llvm.amdgcn.raw.buffer.store.format.v4f32(<4 x float> %3, <4 x i32> %0, i32 0, i32 0, i32 2)14 ret void15}16 17;CHECK-LABEL: {{^}}buffer_store_immoffs:18;CHECK-NOT: s_waitcnt19;CHECK: buffer_store_format_xyzw v[0:3], off, s[0:3], 0 offset:4220define amdgpu_ps void @buffer_store_immoffs(<4 x i32> inreg, <4 x float>) {21main_body:22 call void @llvm.amdgcn.raw.buffer.store.format.v4f32(<4 x float> %1, <4 x i32> %0, i32 42, i32 0, i32 0)23 ret void24}25 26;CHECK-LABEL: {{^}}buffer_store_ofs:27;CHECK-NOT: s_waitcnt28;CHECK: buffer_store_format_xyzw v[0:3], v4, s[0:3], 0 offen29define amdgpu_ps void @buffer_store_ofs(<4 x i32> inreg, <4 x float>, i32) {30main_body:31 call void @llvm.amdgcn.raw.buffer.store.format.v4f32(<4 x float> %1, <4 x i32> %0, i32 %2, i32 0, i32 0)32 ret void33}34 35; Ideally, the register allocator would avoid the wait here36;37;CHECK-LABEL: {{^}}buffer_store_wait:38;CHECK-NOT: s_waitcnt39;CHECK: buffer_store_format_xyzw v[0:3], v4, s[0:3], 0 offen40;VERDE: s_waitcnt expcnt(0)41;CHECK: buffer_load_format_xyzw v[0:3], v5, s[0:3], 0 offen42;CHECK: s_waitcnt vmcnt(0)43;CHECK: buffer_store_format_xyzw v[0:3], v6, s[0:3], 0 offen44define amdgpu_ps void @buffer_store_wait(<4 x i32> inreg, <4 x float>, i32, i32, i32) {45main_body:46 call void @llvm.amdgcn.raw.buffer.store.format.v4f32(<4 x float> %1, <4 x i32> %0, i32 %2, i32 0, i32 0)47 %data = call <4 x float> @llvm.amdgcn.raw.buffer.load.format.v4f32(<4 x i32> %0, i32 %3, i32 0, i32 0)48 call void @llvm.amdgcn.raw.buffer.store.format.v4f32(<4 x float> %data, <4 x i32> %0, i32 %4, i32 0, i32 0)49 ret void50}51 52;CHECK-LABEL: {{^}}buffer_store_x1:53;CHECK-NOT: s_waitcnt54;CHECK: buffer_store_format_x v0, v1, s[0:3], 0 offen55define amdgpu_ps void @buffer_store_x1(<4 x i32> inreg %rsrc, float %data, i32 %offset) {56main_body:57 call void @llvm.amdgcn.raw.buffer.store.format.f32(float %data, <4 x i32> %rsrc, i32 %offset, i32 0, i32 0)58 ret void59}60 61;CHECK-LABEL: {{^}}buffer_store_x2:62;CHECK-NOT: s_waitcnt63;CHECK: buffer_store_format_xy v[0:1], v2, s[0:3], 0 offen64define amdgpu_ps void @buffer_store_x2(<4 x i32> inreg %rsrc, <2 x float> %data, i32 %offset) {65main_body:66 call void @llvm.amdgcn.raw.buffer.store.format.v2f32(<2 x float> %data, <4 x i32> %rsrc, i32 %offset, i32 0, i32 0)67 ret void68}69 70declare void @llvm.amdgcn.raw.buffer.store.format.f32(float, <4 x i32>, i32, i32, i32) #071declare void @llvm.amdgcn.raw.buffer.store.format.v2f32(<2 x float>, <4 x i32>, i32, i32, i32) #072declare void @llvm.amdgcn.raw.buffer.store.format.v4f32(<4 x float>, <4 x i32>, i32, i32, i32) #073declare <4 x float> @llvm.amdgcn.raw.buffer.load.format.v4f32(<4 x i32>, i32, i32, i32) #174 75attributes #0 = { nounwind }76attributes #1 = { nounwind readonly }77