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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 22; RUN: llc < %s -mtriple=amdgcn -mcpu=verde | FileCheck -check-prefixes=GFX68,VERDE %s3; RUN: llc < %s -mtriple=amdgcn -mcpu=tonga | FileCheck -check-prefixes=GFX68,GFX8 %s4; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1100 | FileCheck -check-prefixes=GFX11 %s5; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1200 | FileCheck -check-prefixes=GFX1200 %s6; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1250 | FileCheck -check-prefixes=GFX1250 %s7 8define amdgpu_ps void @buffer_store(<4 x i32> inreg, <4 x float>, <4 x float>, <4 x float>) {9; GFX68-LABEL: buffer_store:10; GFX68: ; %bb.0: ; %main_body11; GFX68-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 012; GFX68-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 glc13; GFX68-NEXT: buffer_store_dwordx4 v[8:11], off, s[0:3], 0 slc14; GFX68-NEXT: s_endpgm15;16; GFX11-LABEL: buffer_store:17; GFX11: ; %bb.0: ; %main_body18; GFX11-NEXT: s_clause 0x219; GFX11-NEXT: buffer_store_b128 v[0:3], off, s[0:3], 020; GFX11-NEXT: buffer_store_b128 v[4:7], off, s[0:3], 0 glc21; GFX11-NEXT: buffer_store_b128 v[8:11], off, s[0:3], 0 slc22; GFX11-NEXT: s_endpgm23;24; GFX1200-LABEL: buffer_store:25; GFX1200: ; %bb.0: ; %main_body26; GFX1200-NEXT: s_clause 0x227; GFX1200-NEXT: buffer_store_b128 v[0:3], off, s[0:3], null28; GFX1200-NEXT: buffer_store_b128 v[4:7], off, s[0:3], null th:TH_STORE_NT29; GFX1200-NEXT: buffer_store_b128 v[8:11], off, s[0:3], null th:TH_STORE_HT30; GFX1200-NEXT: s_endpgm31;32; GFX1250-LABEL: buffer_store:33; GFX1250: ; %bb.0: ; %main_body34; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 135; GFX1250-NEXT: s_clause 0x236; GFX1250-NEXT: buffer_store_b128 v[0:3], off, s[0:3], null37; GFX1250-NEXT: buffer_store_b128 v[4:7], off, s[0:3], null th:TH_STORE_NT38; GFX1250-NEXT: buffer_store_b128 v[8:11], off, s[0:3], null th:TH_STORE_HT39; GFX1250-NEXT: s_endpgm40main_body:41 call void @llvm.amdgcn.raw.buffer.store.v4f32(<4 x float> %1, <4 x i32> %0, i32 0, i32 0, i32 0)42 call void @llvm.amdgcn.raw.buffer.store.v4f32(<4 x float> %2, <4 x i32> %0, i32 0, i32 0, i32 1)43 call void @llvm.amdgcn.raw.buffer.store.v4f32(<4 x float> %3, <4 x i32> %0, i32 0, i32 0, i32 2)44 ret void45}46 47define amdgpu_ps void @buffer_store_immoffs(<4 x i32> inreg, <4 x float>) {48; GFX68-LABEL: buffer_store_immoffs:49; GFX68: ; %bb.0: ; %main_body50; GFX68-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:4251; GFX68-NEXT: s_endpgm52;53; GFX11-LABEL: buffer_store_immoffs:54; GFX11: ; %bb.0: ; %main_body55; GFX11-NEXT: buffer_store_b128 v[0:3], off, s[0:3], 0 offset:4256; GFX11-NEXT: s_endpgm57;58; GFX1200-LABEL: buffer_store_immoffs:59; GFX1200: ; %bb.0: ; %main_body60; GFX1200-NEXT: buffer_store_b128 v[0:3], off, s[0:3], null offset:4261; GFX1200-NEXT: s_endpgm62;63; GFX1250-LABEL: buffer_store_immoffs:64; GFX1250: ; %bb.0: ; %main_body65; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 166; GFX1250-NEXT: buffer_store_b128 v[0:3], off, s[0:3], null offset:4267; GFX1250-NEXT: s_endpgm68main_body:69 call void @llvm.amdgcn.raw.buffer.store.v4f32(<4 x float> %1, <4 x i32> %0, i32 42, i32 0, i32 0)70 ret void71}72 73define amdgpu_ps void @buffer_store_ofs(<4 x i32> inreg, <4 x float>, i32) {74; GFX68-LABEL: buffer_store_ofs:75; GFX68: ; %bb.0: ; %main_body76; GFX68-NEXT: buffer_store_dwordx4 v[0:3], v4, s[0:3], 0 offen77; GFX68-NEXT: s_endpgm78;79; GFX11-LABEL: buffer_store_ofs:80; GFX11: ; %bb.0: ; %main_body81; GFX11-NEXT: buffer_store_b128 v[0:3], v4, s[0:3], 0 offen82; GFX11-NEXT: s_endpgm83;84; GFX1200-LABEL: buffer_store_ofs:85; GFX1200: ; %bb.0: ; %main_body86; GFX1200-NEXT: buffer_store_b128 v[0:3], v4, s[0:3], null offen87; GFX1200-NEXT: s_endpgm88;89; GFX1250-LABEL: buffer_store_ofs:90; GFX1250: ; %bb.0: ; %main_body91; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 192; GFX1250-NEXT: buffer_store_b128 v[0:3], v4, s[0:3], null offen93; GFX1250-NEXT: s_endpgm94main_body:95 call void @llvm.amdgcn.raw.buffer.store.v4f32(<4 x float> %1, <4 x i32> %0, i32 %2, i32 0, i32 0)96 ret void97}98 99; Ideally, the register allocator would avoid the wait here100define amdgpu_ps void @buffer_store_wait(<4 x i32> inreg, <4 x float>, i32, i32, i32) {101; VERDE-LABEL: buffer_store_wait:102; VERDE: ; %bb.0: ; %main_body103; VERDE-NEXT: buffer_store_dwordx4 v[0:3], v4, s[0:3], 0 offen104; VERDE-NEXT: s_waitcnt expcnt(0)105; VERDE-NEXT: buffer_load_dwordx4 v[0:3], v5, s[0:3], 0 offen106; VERDE-NEXT: s_waitcnt vmcnt(0)107; VERDE-NEXT: buffer_store_dwordx4 v[0:3], v6, s[0:3], 0 offen108; VERDE-NEXT: s_endpgm109;110; GFX8-LABEL: buffer_store_wait:111; GFX8: ; %bb.0: ; %main_body112; GFX8-NEXT: buffer_store_dwordx4 v[0:3], v4, s[0:3], 0 offen113; GFX8-NEXT: buffer_load_dwordx4 v[0:3], v5, s[0:3], 0 offen114; GFX8-NEXT: s_waitcnt vmcnt(0)115; GFX8-NEXT: buffer_store_dwordx4 v[0:3], v6, s[0:3], 0 offen116; GFX8-NEXT: s_endpgm117;118; GFX11-LABEL: buffer_store_wait:119; GFX11: ; %bb.0: ; %main_body120; GFX11-NEXT: buffer_store_b128 v[0:3], v4, s[0:3], 0 offen121; GFX11-NEXT: buffer_load_b128 v[0:3], v5, s[0:3], 0 offen122; GFX11-NEXT: s_waitcnt vmcnt(0)123; GFX11-NEXT: buffer_store_b128 v[0:3], v6, s[0:3], 0 offen124; GFX11-NEXT: s_endpgm125;126; GFX1200-LABEL: buffer_store_wait:127; GFX1200: ; %bb.0: ; %main_body128; GFX1200-NEXT: buffer_store_b128 v[0:3], v4, s[0:3], null offen129; GFX1200-NEXT: buffer_load_b128 v[0:3], v5, s[0:3], null offen130; GFX1200-NEXT: s_wait_loadcnt 0x0131; GFX1200-NEXT: buffer_store_b128 v[0:3], v6, s[0:3], null offen132; GFX1200-NEXT: s_endpgm133;134; GFX1250-LABEL: buffer_store_wait:135; GFX1250: ; %bb.0: ; %main_body136; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1137; GFX1250-NEXT: s_clause 0x1138; GFX1250-NEXT: buffer_store_b128 v[0:3], v4, s[0:3], null offen139; GFX1250-NEXT: buffer_load_b128 v[0:3], v5, s[0:3], null offen140; GFX1250-NEXT: s_wait_loadcnt 0x0141; GFX1250-NEXT: buffer_store_b128 v[0:3], v6, s[0:3], null offen142; GFX1250-NEXT: s_endpgm143main_body:144 call void @llvm.amdgcn.raw.buffer.store.v4f32(<4 x float> %1, <4 x i32> %0, i32 %2, i32 0, i32 0)145 %data = call <4 x float> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32> %0, i32 %3, i32 0, i32 0)146 call void @llvm.amdgcn.raw.buffer.store.v4f32(<4 x float> %data, <4 x i32> %0, i32 %4, i32 0, i32 0)147 ret void148}149 150define amdgpu_ps void @buffer_store_x1(<4 x i32> inreg %rsrc, float %data, i32 %offset) {151; GFX68-LABEL: buffer_store_x1:152; GFX68: ; %bb.0: ; %main_body153; GFX68-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen154; GFX68-NEXT: s_endpgm155;156; GFX11-LABEL: buffer_store_x1:157; GFX11: ; %bb.0: ; %main_body158; GFX11-NEXT: buffer_store_b32 v0, v1, s[0:3], 0 offen159; GFX11-NEXT: s_endpgm160;161; GFX1200-LABEL: buffer_store_x1:162; GFX1200: ; %bb.0: ; %main_body163; GFX1200-NEXT: buffer_store_b32 v0, v1, s[0:3], null offen164; GFX1200-NEXT: s_endpgm165;166; GFX1250-LABEL: buffer_store_x1:167; GFX1250: ; %bb.0: ; %main_body168; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1169; GFX1250-NEXT: buffer_store_b32 v0, v1, s[0:3], null offen170; GFX1250-NEXT: s_endpgm171main_body:172 call void @llvm.amdgcn.raw.buffer.store.f32(float %data, <4 x i32> %rsrc, i32 %offset, i32 0, i32 0)173 ret void174}175 176define amdgpu_ps void @buffer_store_x2(<4 x i32> inreg %rsrc, <2 x float> %data, i32 %offset) #0 {177; GFX68-LABEL: buffer_store_x2:178; GFX68: ; %bb.0: ; %main_body179; GFX68-NEXT: buffer_store_dwordx2 v[0:1], v2, s[0:3], 0 offen180; GFX68-NEXT: s_endpgm181;182; GFX11-LABEL: buffer_store_x2:183; GFX11: ; %bb.0: ; %main_body184; GFX11-NEXT: buffer_store_b64 v[0:1], v2, s[0:3], 0 offen185; GFX11-NEXT: s_endpgm186;187; GFX1200-LABEL: buffer_store_x2:188; GFX1200: ; %bb.0: ; %main_body189; GFX1200-NEXT: buffer_store_b64 v[0:1], v2, s[0:3], null offen190; GFX1200-NEXT: s_endpgm191;192; GFX1250-LABEL: buffer_store_x2:193; GFX1250: ; %bb.0: ; %main_body194; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1195; GFX1250-NEXT: buffer_store_b64 v[0:1], v2, s[0:3], null offen196; GFX1250-NEXT: s_endpgm197main_body:198 call void @llvm.amdgcn.raw.buffer.store.v2f32(<2 x float> %data, <4 x i32> %rsrc, i32 %offset, i32 0, i32 0)199 ret void200}201 202define amdgpu_ps void @buffer_store_x1_offen_merged_and(<4 x i32> inreg %rsrc, i32 %a, float %v1, float %v2, float %v3, float %v4, float %v5, float %v6) {203; GFX68-LABEL: buffer_store_x1_offen_merged_and:204; GFX68: ; %bb.0:205; GFX68-NEXT: buffer_store_dwordx4 v[1:4], v0, s[0:3], 0 offen offset:4206; GFX68-NEXT: buffer_store_dwordx2 v[5:6], v0, s[0:3], 0 offen offset:28207; GFX68-NEXT: s_endpgm208;209; GFX11-LABEL: buffer_store_x1_offen_merged_and:210; GFX11: ; %bb.0:211; GFX11-NEXT: s_clause 0x1212; GFX11-NEXT: buffer_store_b128 v[1:4], v0, s[0:3], 0 offen offset:4213; GFX11-NEXT: buffer_store_b64 v[5:6], v0, s[0:3], 0 offen offset:28214; GFX11-NEXT: s_endpgm215;216; GFX1200-LABEL: buffer_store_x1_offen_merged_and:217; GFX1200: ; %bb.0:218; GFX1200-NEXT: s_clause 0x1219; GFX1200-NEXT: buffer_store_b128 v[1:4], v0, s[0:3], null offen offset:4220; GFX1200-NEXT: buffer_store_b64 v[5:6], v0, s[0:3], null offen offset:28221; GFX1200-NEXT: s_endpgm222;223; GFX1250-LABEL: buffer_store_x1_offen_merged_and:224; GFX1250: ; %bb.0:225; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1226; GFX1250-NEXT: v_dual_add_nc_u32 v7, 4, v0 :: v_dual_add_nc_u32 v8, 8, v0227; GFX1250-NEXT: v_dual_add_nc_u32 v9, 12, v0 :: v_dual_add_nc_u32 v10, 16, v0228; GFX1250-NEXT: v_dual_add_nc_u32 v11, 28, v0 :: v_dual_add_nc_u32 v0, 32, v0229; GFX1250-NEXT: s_clause 0x5230; GFX1250-NEXT: buffer_store_b32 v1, v7, s[0:3], null offen231; GFX1250-NEXT: buffer_store_b32 v2, v8, s[0:3], null offen232; GFX1250-NEXT: buffer_store_b32 v3, v9, s[0:3], null offen233; GFX1250-NEXT: buffer_store_b32 v4, v10, s[0:3], null offen234; GFX1250-NEXT: buffer_store_b32 v5, v11, s[0:3], null offen235; GFX1250-NEXT: buffer_store_b32 v6, v0, s[0:3], null offen236; GFX1250-NEXT: s_endpgm237 %a1 = add i32 %a, 4238 %a2 = add i32 %a, 8239 %a3 = add i32 %a, 12240 %a4 = add i32 %a, 16241 %a5 = add i32 %a, 28242 %a6 = add i32 %a, 32243 call void @llvm.amdgcn.raw.buffer.store.f32(float %v1, <4 x i32> %rsrc, i32 %a1, i32 0, i32 0)244 call void @llvm.amdgcn.raw.buffer.store.f32(float %v2, <4 x i32> %rsrc, i32 %a2, i32 0, i32 0)245 call void @llvm.amdgcn.raw.buffer.store.f32(float %v3, <4 x i32> %rsrc, i32 %a3, i32 0, i32 0)246 call void @llvm.amdgcn.raw.buffer.store.f32(float %v4, <4 x i32> %rsrc, i32 %a4, i32 0, i32 0)247 call void @llvm.amdgcn.raw.buffer.store.f32(float %v5, <4 x i32> %rsrc, i32 %a5, i32 0, i32 0)248 call void @llvm.amdgcn.raw.buffer.store.f32(float %v6, <4 x i32> %rsrc, i32 %a6, i32 0, i32 0)249 ret void250}251 252define amdgpu_ps void @buffer_store_x1_offen_merged_or(<4 x i32> inreg %rsrc, i32 %inp, float %v1, float %v2, float %v3, float %v4, float %v5, float %v6) {253; GFX68-LABEL: buffer_store_x1_offen_merged_or:254; GFX68: ; %bb.0:255; GFX68-NEXT: v_lshlrev_b32_e32 v0, 6, v0256; GFX68-NEXT: buffer_store_dwordx4 v[1:4], v0, s[0:3], 0 offen offset:4257; GFX68-NEXT: buffer_store_dwordx2 v[5:6], v0, s[0:3], 0 offen offset:28258; GFX68-NEXT: s_endpgm259;260; GFX11-LABEL: buffer_store_x1_offen_merged_or:261; GFX11: ; %bb.0:262; GFX11-NEXT: v_lshlrev_b32_e32 v0, 6, v0263; GFX11-NEXT: s_clause 0x1264; GFX11-NEXT: buffer_store_b128 v[1:4], v0, s[0:3], 0 offen offset:4265; GFX11-NEXT: buffer_store_b64 v[5:6], v0, s[0:3], 0 offen offset:28266; GFX11-NEXT: s_endpgm267;268; GFX1200-LABEL: buffer_store_x1_offen_merged_or:269; GFX1200: ; %bb.0:270; GFX1200-NEXT: v_lshlrev_b32_e32 v0, 6, v0271; GFX1200-NEXT: s_clause 0x1272; GFX1200-NEXT: buffer_store_b128 v[1:4], v0, s[0:3], null offen offset:4273; GFX1200-NEXT: buffer_store_b64 v[5:6], v0, s[0:3], null offen offset:28274; GFX1200-NEXT: s_endpgm275;276; GFX1250-LABEL: buffer_store_x1_offen_merged_or:277; GFX1250: ; %bb.0:278; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1279; GFX1250-NEXT: v_dual_mov_b32 v7, v6 :: v_dual_mov_b32 v6, v5280; GFX1250-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3281; GFX1250-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1282; GFX1250-NEXT: v_lshlrev_b32_e32 v0, 6, v0283; GFX1250-NEXT: s_clause 0x1284; GFX1250-NEXT: buffer_store_b128 v[2:5], v0, s[0:3], null offen offset:4285; GFX1250-NEXT: buffer_store_b64 v[6:7], v0, s[0:3], null offen offset:28286; GFX1250-NEXT: s_endpgm287 %a = shl i32 %inp, 6288 %a1 = add i32 %a, 4289 %a2 = add i32 %a, 8290 %a3 = add i32 %a, 12291 %a4 = add i32 %a, 16292 %a5 = add i32 %a, 28293 %a6 = add i32 %a, 32294 call void @llvm.amdgcn.raw.buffer.store.f32(float %v1, <4 x i32> %rsrc, i32 %a1, i32 0, i32 0)295 call void @llvm.amdgcn.raw.buffer.store.f32(float %v2, <4 x i32> %rsrc, i32 %a2, i32 0, i32 0)296 call void @llvm.amdgcn.raw.buffer.store.f32(float %v3, <4 x i32> %rsrc, i32 %a3, i32 0, i32 0)297 call void @llvm.amdgcn.raw.buffer.store.f32(float %v4, <4 x i32> %rsrc, i32 %a4, i32 0, i32 0)298 call void @llvm.amdgcn.raw.buffer.store.f32(float %v5, <4 x i32> %rsrc, i32 %a5, i32 0, i32 0)299 call void @llvm.amdgcn.raw.buffer.store.f32(float %v6, <4 x i32> %rsrc, i32 %a6, i32 0, i32 0)300 ret void301}302 303define amdgpu_ps void @buffer_store_x1_offen_merged_glc_slc(<4 x i32> inreg %rsrc, i32 %a, float %v1, float %v2, float %v3, float %v4, float %v5, float %v6) {304; GFX68-LABEL: buffer_store_x1_offen_merged_glc_slc:305; GFX68: ; %bb.0:306; GFX68-NEXT: buffer_store_dwordx2 v[1:2], v0, s[0:3], 0 offen offset:4307; GFX68-NEXT: buffer_store_dwordx2 v[3:4], v0, s[0:3], 0 offen offset:12 glc308; GFX68-NEXT: buffer_store_dwordx2 v[5:6], v0, s[0:3], 0 offen offset:28 glc slc309; GFX68-NEXT: s_endpgm310;311; GFX11-LABEL: buffer_store_x1_offen_merged_glc_slc:312; GFX11: ; %bb.0:313; GFX11-NEXT: s_clause 0x2314; GFX11-NEXT: buffer_store_b64 v[1:2], v0, s[0:3], 0 offen offset:4315; GFX11-NEXT: buffer_store_b64 v[3:4], v0, s[0:3], 0 offen offset:12 glc316; GFX11-NEXT: buffer_store_b64 v[5:6], v0, s[0:3], 0 offen offset:28 glc slc317; GFX11-NEXT: s_endpgm318;319; GFX1200-LABEL: buffer_store_x1_offen_merged_glc_slc:320; GFX1200: ; %bb.0:321; GFX1200-NEXT: s_clause 0x2322; GFX1200-NEXT: buffer_store_b64 v[1:2], v0, s[0:3], null offen offset:4323; GFX1200-NEXT: buffer_store_b64 v[3:4], v0, s[0:3], null offen offset:12 th:TH_STORE_NT324; GFX1200-NEXT: buffer_store_b64 v[5:6], v0, s[0:3], null offen offset:28 th:TH_STORE_WB325; GFX1200-NEXT: s_endpgm326;327; GFX1250-LABEL: buffer_store_x1_offen_merged_glc_slc:328; GFX1250: ; %bb.0:329; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1330; GFX1250-NEXT: v_dual_add_nc_u32 v7, 4, v0 :: v_dual_add_nc_u32 v8, 8, v0331; GFX1250-NEXT: v_dual_add_nc_u32 v9, 12, v0 :: v_dual_add_nc_u32 v10, 16, v0332; GFX1250-NEXT: v_dual_add_nc_u32 v11, 28, v0 :: v_dual_add_nc_u32 v0, 32, v0333; GFX1250-NEXT: s_clause 0x5334; GFX1250-NEXT: buffer_store_b32 v1, v7, s[0:3], null offen335; GFX1250-NEXT: buffer_store_b32 v2, v8, s[0:3], null offen336; GFX1250-NEXT: buffer_store_b32 v3, v9, s[0:3], null offen th:TH_STORE_NT337; GFX1250-NEXT: buffer_store_b32 v4, v10, s[0:3], null offen th:TH_STORE_NT338; GFX1250-NEXT: buffer_store_b32 v5, v11, s[0:3], null offen th:TH_STORE_WB339; GFX1250-NEXT: buffer_store_b32 v6, v0, s[0:3], null offen th:TH_STORE_WB340; GFX1250-NEXT: s_endpgm341 %a1 = add i32 %a, 4342 %a2 = add i32 %a, 8343 %a3 = add i32 %a, 12344 %a4 = add i32 %a, 16345 %a5 = add i32 %a, 28346 %a6 = add i32 %a, 32347 call void @llvm.amdgcn.raw.buffer.store.f32(float %v1, <4 x i32> %rsrc, i32 %a1, i32 0, i32 0)348 call void @llvm.amdgcn.raw.buffer.store.f32(float %v2, <4 x i32> %rsrc, i32 %a2, i32 0, i32 0)349 call void @llvm.amdgcn.raw.buffer.store.f32(float %v3, <4 x i32> %rsrc, i32 %a3, i32 0, i32 1)350 call void @llvm.amdgcn.raw.buffer.store.f32(float %v4, <4 x i32> %rsrc, i32 %a4, i32 0, i32 1)351 call void @llvm.amdgcn.raw.buffer.store.f32(float %v5, <4 x i32> %rsrc, i32 %a5, i32 0, i32 3)352 call void @llvm.amdgcn.raw.buffer.store.f32(float %v6, <4 x i32> %rsrc, i32 %a6, i32 0, i32 3)353 ret void354}355 356define amdgpu_ps void @buffer_store_x2_offen_merged_and(<4 x i32> inreg %rsrc, i32 %a, <2 x float> %v1, <2 x float> %v2) {357; GFX68-LABEL: buffer_store_x2_offen_merged_and:358; GFX68: ; %bb.0:359; GFX68-NEXT: buffer_store_dwordx4 v[1:4], v0, s[0:3], 0 offen offset:4360; GFX68-NEXT: s_endpgm361;362; GFX11-LABEL: buffer_store_x2_offen_merged_and:363; GFX11: ; %bb.0:364; GFX11-NEXT: buffer_store_b128 v[1:4], v0, s[0:3], 0 offen offset:4365; GFX11-NEXT: s_endpgm366;367; GFX1200-LABEL: buffer_store_x2_offen_merged_and:368; GFX1200: ; %bb.0:369; GFX1200-NEXT: buffer_store_b128 v[1:4], v0, s[0:3], null offen offset:4370; GFX1200-NEXT: s_endpgm371;372; GFX1250-LABEL: buffer_store_x2_offen_merged_and:373; GFX1250: ; %bb.0:374; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1375; GFX1250-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3376; GFX1250-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1377; GFX1250-NEXT: v_dual_add_nc_u32 v1, 4, v0 :: v_dual_add_nc_u32 v0, 12, v0378; GFX1250-NEXT: s_clause 0x1379; GFX1250-NEXT: buffer_store_b64 v[2:3], v1, s[0:3], null offen380; GFX1250-NEXT: buffer_store_b64 v[4:5], v0, s[0:3], null offen381; GFX1250-NEXT: s_endpgm382 %a1 = add i32 %a, 4383 %a2 = add i32 %a, 12384 call void @llvm.amdgcn.raw.buffer.store.v2f32(<2 x float> %v1, <4 x i32> %rsrc, i32 %a1, i32 0, i32 0)385 call void @llvm.amdgcn.raw.buffer.store.v2f32(<2 x float> %v2, <4 x i32> %rsrc, i32 %a2, i32 0, i32 0)386 ret void387}388 389define amdgpu_ps void @buffer_store_x2_offen_merged_or(<4 x i32> inreg %rsrc, i32 %inp, <2 x float> %v1, <2 x float> %v2) {390; GFX68-LABEL: buffer_store_x2_offen_merged_or:391; GFX68: ; %bb.0:392; GFX68-NEXT: v_lshlrev_b32_e32 v0, 4, v0393; GFX68-NEXT: buffer_store_dwordx4 v[1:4], v0, s[0:3], 0 offen offset:4394; GFX68-NEXT: s_endpgm395;396; GFX11-LABEL: buffer_store_x2_offen_merged_or:397; GFX11: ; %bb.0:398; GFX11-NEXT: v_lshlrev_b32_e32 v0, 4, v0399; GFX11-NEXT: buffer_store_b128 v[1:4], v0, s[0:3], 0 offen offset:4400; GFX11-NEXT: s_endpgm401;402; GFX1200-LABEL: buffer_store_x2_offen_merged_or:403; GFX1200: ; %bb.0:404; GFX1200-NEXT: v_lshlrev_b32_e32 v0, 4, v0405; GFX1200-NEXT: buffer_store_b128 v[1:4], v0, s[0:3], null offen offset:4406; GFX1200-NEXT: s_endpgm407;408; GFX1250-LABEL: buffer_store_x2_offen_merged_or:409; GFX1250: ; %bb.0:410; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1411; GFX1250-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3412; GFX1250-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1413; GFX1250-NEXT: v_lshlrev_b32_e32 v0, 4, v0414; GFX1250-NEXT: buffer_store_b128 v[2:5], v0, s[0:3], null offen offset:4415; GFX1250-NEXT: s_endpgm416 %a = shl i32 %inp, 4417 %a1 = add i32 %a, 4418 %a2 = add i32 %a, 12419 call void @llvm.amdgcn.raw.buffer.store.v2f32(<2 x float> %v1, <4 x i32> %rsrc, i32 %a1, i32 0, i32 0)420 call void @llvm.amdgcn.raw.buffer.store.v2f32(<2 x float> %v2, <4 x i32> %rsrc, i32 %a2, i32 0, i32 0)421 ret void422}423 424define amdgpu_ps void @buffer_store_x1_offset_merged(<4 x i32> inreg %rsrc, float %v1, float %v2, float %v3, float %v4, float %v5, float %v6) {425; GFX68-LABEL: buffer_store_x1_offset_merged:426; GFX68: ; %bb.0:427; GFX68-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:4428; GFX68-NEXT: buffer_store_dwordx2 v[4:5], off, s[0:3], 0 offset:28429; GFX68-NEXT: s_endpgm430;431; GFX11-LABEL: buffer_store_x1_offset_merged:432; GFX11: ; %bb.0:433; GFX11-NEXT: s_clause 0x1434; GFX11-NEXT: buffer_store_b128 v[0:3], off, s[0:3], 0 offset:4435; GFX11-NEXT: buffer_store_b64 v[4:5], off, s[0:3], 0 offset:28436; GFX11-NEXT: s_endpgm437;438; GFX1200-LABEL: buffer_store_x1_offset_merged:439; GFX1200: ; %bb.0:440; GFX1200-NEXT: s_clause 0x1441; GFX1200-NEXT: buffer_store_b128 v[0:3], off, s[0:3], null offset:4442; GFX1200-NEXT: buffer_store_b64 v[4:5], off, s[0:3], null offset:28443; GFX1200-NEXT: s_endpgm444;445; GFX1250-LABEL: buffer_store_x1_offset_merged:446; GFX1250: ; %bb.0:447; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1448; GFX1250-NEXT: s_clause 0x1449; GFX1250-NEXT: buffer_store_b128 v[0:3], off, s[0:3], null offset:4450; GFX1250-NEXT: buffer_store_b64 v[4:5], off, s[0:3], null offset:28451; GFX1250-NEXT: s_endpgm452 call void @llvm.amdgcn.raw.buffer.store.f32(float %v1, <4 x i32> %rsrc, i32 4, i32 0, i32 0)453 call void @llvm.amdgcn.raw.buffer.store.f32(float %v2, <4 x i32> %rsrc, i32 8, i32 0, i32 0)454 call void @llvm.amdgcn.raw.buffer.store.f32(float %v3, <4 x i32> %rsrc, i32 12, i32 0, i32 0)455 call void @llvm.amdgcn.raw.buffer.store.f32(float %v4, <4 x i32> %rsrc, i32 16, i32 0, i32 0)456 call void @llvm.amdgcn.raw.buffer.store.f32(float %v5, <4 x i32> %rsrc, i32 28, i32 0, i32 0)457 call void @llvm.amdgcn.raw.buffer.store.f32(float %v6, <4 x i32> %rsrc, i32 32, i32 0, i32 0)458 ret void459}460 461define amdgpu_ps void @buffer_store_x2_offset_merged(<4 x i32> inreg %rsrc, <2 x float> %v1,<2 x float> %v2) {462; GFX68-LABEL: buffer_store_x2_offset_merged:463; GFX68: ; %bb.0:464; GFX68-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:4465; GFX68-NEXT: s_endpgm466;467; GFX11-LABEL: buffer_store_x2_offset_merged:468; GFX11: ; %bb.0:469; GFX11-NEXT: buffer_store_b128 v[0:3], off, s[0:3], 0 offset:4470; GFX11-NEXT: s_endpgm471;472; GFX1200-LABEL: buffer_store_x2_offset_merged:473; GFX1200: ; %bb.0:474; GFX1200-NEXT: buffer_store_b128 v[0:3], off, s[0:3], null offset:4475; GFX1200-NEXT: s_endpgm476;477; GFX1250-LABEL: buffer_store_x2_offset_merged:478; GFX1250: ; %bb.0:479; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1480; GFX1250-NEXT: buffer_store_b128 v[0:3], off, s[0:3], null offset:4481; GFX1250-NEXT: s_endpgm482 call void @llvm.amdgcn.raw.buffer.store.v2f32(<2 x float> %v1, <4 x i32> %rsrc, i32 4, i32 0, i32 0)483 call void @llvm.amdgcn.raw.buffer.store.v2f32(<2 x float> %v2, <4 x i32> %rsrc, i32 12, i32 0, i32 0)484 ret void485}486 487define amdgpu_ps void @buffer_store_int(<4 x i32> inreg, <4 x i32>, <2 x i32>, i32) {488; GFX68-LABEL: buffer_store_int:489; GFX68: ; %bb.0: ; %main_body490; GFX68-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0491; GFX68-NEXT: buffer_store_dwordx2 v[4:5], off, s[0:3], 0 glc492; GFX68-NEXT: buffer_store_dword v6, off, s[0:3], 0 slc493; GFX68-NEXT: s_endpgm494;495; GFX11-LABEL: buffer_store_int:496; GFX11: ; %bb.0: ; %main_body497; GFX11-NEXT: s_clause 0x2498; GFX11-NEXT: buffer_store_b128 v[0:3], off, s[0:3], 0499; GFX11-NEXT: buffer_store_b64 v[4:5], off, s[0:3], 0 glc500; GFX11-NEXT: buffer_store_b32 v6, off, s[0:3], 0 slc501; GFX11-NEXT: s_endpgm502;503; GFX1200-LABEL: buffer_store_int:504; GFX1200: ; %bb.0: ; %main_body505; GFX1200-NEXT: s_clause 0x2506; GFX1200-NEXT: buffer_store_b128 v[0:3], off, s[0:3], null507; GFX1200-NEXT: buffer_store_b64 v[4:5], off, s[0:3], null th:TH_STORE_NT508; GFX1200-NEXT: buffer_store_b32 v6, off, s[0:3], null th:TH_STORE_HT509; GFX1200-NEXT: s_endpgm510;511; GFX1250-LABEL: buffer_store_int:512; GFX1250: ; %bb.0: ; %main_body513; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1514; GFX1250-NEXT: s_clause 0x2515; GFX1250-NEXT: buffer_store_b128 v[0:3], off, s[0:3], null516; GFX1250-NEXT: buffer_store_b64 v[4:5], off, s[0:3], null th:TH_STORE_NT517; GFX1250-NEXT: buffer_store_b32 v6, off, s[0:3], null th:TH_STORE_HT518; GFX1250-NEXT: s_endpgm519main_body:520 call void @llvm.amdgcn.raw.buffer.store.v4i32(<4 x i32> %1, <4 x i32> %0, i32 0, i32 0, i32 0)521 call void @llvm.amdgcn.raw.buffer.store.v2i32(<2 x i32> %2, <4 x i32> %0, i32 0, i32 0, i32 1)522 call void @llvm.amdgcn.raw.buffer.store.i32(i32 %3, <4 x i32> %0, i32 0, i32 0, i32 2)523 ret void524}525 526define amdgpu_ps void @raw_buffer_store_byte(<4 x i32> inreg %rsrc, float %v1) {527; GFX68-LABEL: raw_buffer_store_byte:528; GFX68: ; %bb.0: ; %main_body529; GFX68-NEXT: v_cvt_u32_f32_e32 v0, v0530; GFX68-NEXT: buffer_store_byte v0, off, s[0:3], 0531; GFX68-NEXT: s_endpgm532;533; GFX11-LABEL: raw_buffer_store_byte:534; GFX11: ; %bb.0: ; %main_body535; GFX11-NEXT: v_cvt_u32_f32_e32 v0, v0536; GFX11-NEXT: buffer_store_b8 v0, off, s[0:3], 0537; GFX11-NEXT: s_endpgm538;539; GFX1200-LABEL: raw_buffer_store_byte:540; GFX1200: ; %bb.0: ; %main_body541; GFX1200-NEXT: v_cvt_u32_f32_e32 v0, v0542; GFX1200-NEXT: buffer_store_b8 v0, off, s[0:3], null543; GFX1200-NEXT: s_endpgm544;545; GFX1250-LABEL: raw_buffer_store_byte:546; GFX1250: ; %bb.0: ; %main_body547; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1548; GFX1250-NEXT: v_cvt_u32_f32_e32 v0, v0549; GFX1250-NEXT: buffer_store_b8 v0, off, s[0:3], null550; GFX1250-NEXT: s_endpgm551main_body:552 %v2 = fptoui float %v1 to i32553 %v3 = trunc i32 %v2 to i8554 call void @llvm.amdgcn.raw.buffer.store.i8(i8 %v3, <4 x i32> %rsrc, i32 0, i32 0, i32 0)555 ret void556}557 558define amdgpu_ps void @raw_buffer_store_short(<4 x i32> inreg %rsrc, float %v1) {559; GFX68-LABEL: raw_buffer_store_short:560; GFX68: ; %bb.0: ; %main_body561; GFX68-NEXT: v_cvt_u32_f32_e32 v0, v0562; GFX68-NEXT: buffer_store_short v0, off, s[0:3], 0563; GFX68-NEXT: s_endpgm564;565; GFX11-LABEL: raw_buffer_store_short:566; GFX11: ; %bb.0: ; %main_body567; GFX11-NEXT: v_cvt_u32_f32_e32 v0, v0568; GFX11-NEXT: buffer_store_b16 v0, off, s[0:3], 0569; GFX11-NEXT: s_endpgm570;571; GFX1200-LABEL: raw_buffer_store_short:572; GFX1200: ; %bb.0: ; %main_body573; GFX1200-NEXT: v_cvt_u32_f32_e32 v0, v0574; GFX1200-NEXT: buffer_store_b16 v0, off, s[0:3], null575; GFX1200-NEXT: s_endpgm576;577; GFX1250-LABEL: raw_buffer_store_short:578; GFX1250: ; %bb.0: ; %main_body579; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1580; GFX1250-NEXT: v_cvt_u32_f32_e32 v0, v0581; GFX1250-NEXT: buffer_store_b16 v0, off, s[0:3], null582; GFX1250-NEXT: s_endpgm583main_body:584 %v2 = fptoui float %v1 to i32585 %v3 = trunc i32 %v2 to i16586 call void @llvm.amdgcn.raw.buffer.store.i16(i16 %v3, <4 x i32> %rsrc, i32 0, i32 0, i32 0)587 ret void588}589 590define amdgpu_ps void @raw_buffer_store_f16(<4 x i32> inreg %rsrc, i32 %v1) {591; GFX68-LABEL: raw_buffer_store_f16:592; GFX68: ; %bb.0: ; %main_body593; GFX68-NEXT: buffer_store_short v0, off, s[0:3], 0594; GFX68-NEXT: s_endpgm595;596; GFX11-LABEL: raw_buffer_store_f16:597; GFX11: ; %bb.0: ; %main_body598; GFX11-NEXT: buffer_store_b16 v0, off, s[0:3], 0599; GFX11-NEXT: s_endpgm600;601; GFX1200-LABEL: raw_buffer_store_f16:602; GFX1200: ; %bb.0: ; %main_body603; GFX1200-NEXT: buffer_store_b16 v0, off, s[0:3], null604; GFX1200-NEXT: s_endpgm605;606; GFX1250-LABEL: raw_buffer_store_f16:607; GFX1250: ; %bb.0: ; %main_body608; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1609; GFX1250-NEXT: buffer_store_b16 v0, off, s[0:3], null610; GFX1250-NEXT: s_endpgm611main_body:612 %trunc = trunc i32 %v1 to i16613 %cast = bitcast i16 %trunc to half614 call void @llvm.amdgcn.raw.buffer.store.f16(half %cast, <4 x i32> %rsrc, i32 0, i32 0, i32 0)615 ret void616}617 618define amdgpu_ps void @buffer_store_v2f16(<4 x i32> inreg %rsrc, <2 x half> %data, i32 %offset) {619; VERDE-LABEL: buffer_store_v2f16:620; VERDE: ; %bb.0: ; %main_body621; VERDE-NEXT: v_cvt_f16_f32_e32 v1, v1622; VERDE-NEXT: v_cvt_f16_f32_e32 v0, v0623; VERDE-NEXT: v_lshlrev_b32_e32 v1, 16, v1624; VERDE-NEXT: v_or_b32_e32 v0, v0, v1625; VERDE-NEXT: buffer_store_dword v0, v2, s[0:3], 0 offen626; VERDE-NEXT: s_endpgm627;628; GFX8-LABEL: buffer_store_v2f16:629; GFX8: ; %bb.0: ; %main_body630; GFX8-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen631; GFX8-NEXT: s_endpgm632;633; GFX11-LABEL: buffer_store_v2f16:634; GFX11: ; %bb.0: ; %main_body635; GFX11-NEXT: buffer_store_b32 v0, v1, s[0:3], 0 offen636; GFX11-NEXT: s_endpgm637;638; GFX1200-LABEL: buffer_store_v2f16:639; GFX1200: ; %bb.0: ; %main_body640; GFX1200-NEXT: buffer_store_b32 v0, v1, s[0:3], null offen641; GFX1200-NEXT: s_endpgm642;643; GFX1250-LABEL: buffer_store_v2f16:644; GFX1250: ; %bb.0: ; %main_body645; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1646; GFX1250-NEXT: buffer_store_b32 v0, v1, s[0:3], null offen647; GFX1250-NEXT: s_endpgm648main_body:649 call void @llvm.amdgcn.raw.buffer.store.v2f16(<2 x half> %data, <4 x i32> %rsrc, i32 %offset, i32 0, i32 0)650 ret void651}652 653define amdgpu_ps void @buffer_store_v4f16(<4 x i32> inreg %rsrc, <4 x half> %data, i32 %offset) #0 {654; VERDE-LABEL: buffer_store_v4f16:655; VERDE: ; %bb.0: ; %main_body656; VERDE-NEXT: v_cvt_f16_f32_e32 v3, v3657; VERDE-NEXT: v_cvt_f16_f32_e32 v2, v2658; VERDE-NEXT: v_cvt_f16_f32_e32 v5, v1659; VERDE-NEXT: v_cvt_f16_f32_e32 v0, v0660; VERDE-NEXT: v_lshlrev_b32_e32 v1, 16, v3661; VERDE-NEXT: v_or_b32_e32 v1, v2, v1662; VERDE-NEXT: v_lshlrev_b32_e32 v2, 16, v5663; VERDE-NEXT: v_or_b32_e32 v0, v0, v2664; VERDE-NEXT: buffer_store_dwordx2 v[0:1], v4, s[0:3], 0 offen665; VERDE-NEXT: s_endpgm666;667; GFX8-LABEL: buffer_store_v4f16:668; GFX8: ; %bb.0: ; %main_body669; GFX8-NEXT: buffer_store_dwordx2 v[0:1], v2, s[0:3], 0 offen670; GFX8-NEXT: s_endpgm671;672; GFX11-LABEL: buffer_store_v4f16:673; GFX11: ; %bb.0: ; %main_body674; GFX11-NEXT: buffer_store_b64 v[0:1], v2, s[0:3], 0 offen675; GFX11-NEXT: s_endpgm676;677; GFX1200-LABEL: buffer_store_v4f16:678; GFX1200: ; %bb.0: ; %main_body679; GFX1200-NEXT: buffer_store_b64 v[0:1], v2, s[0:3], null offen680; GFX1200-NEXT: s_endpgm681;682; GFX1250-LABEL: buffer_store_v4f16:683; GFX1250: ; %bb.0: ; %main_body684; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1685; GFX1250-NEXT: buffer_store_b64 v[0:1], v2, s[0:3], null offen686; GFX1250-NEXT: s_endpgm687main_body:688 call void @llvm.amdgcn.raw.buffer.store.v4f16(<4 x half> %data, <4 x i32> %rsrc, i32 %offset, i32 0, i32 0)689 ret void690}691 692define amdgpu_ps void @raw_buffer_store_i16(<4 x i32> inreg %rsrc, i32 %v1) {693; GFX68-LABEL: raw_buffer_store_i16:694; GFX68: ; %bb.0: ; %main_body695; GFX68-NEXT: buffer_store_short v0, off, s[0:3], 0696; GFX68-NEXT: s_endpgm697;698; GFX11-LABEL: raw_buffer_store_i16:699; GFX11: ; %bb.0: ; %main_body700; GFX11-NEXT: buffer_store_b16 v0, off, s[0:3], 0701; GFX11-NEXT: s_endpgm702;703; GFX1200-LABEL: raw_buffer_store_i16:704; GFX1200: ; %bb.0: ; %main_body705; GFX1200-NEXT: buffer_store_b16 v0, off, s[0:3], null706; GFX1200-NEXT: s_endpgm707;708; GFX1250-LABEL: raw_buffer_store_i16:709; GFX1250: ; %bb.0: ; %main_body710; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1711; GFX1250-NEXT: buffer_store_b16 v0, off, s[0:3], null712; GFX1250-NEXT: s_endpgm713main_body:714 %trunc = trunc i32 %v1 to i16715 call void @llvm.amdgcn.raw.buffer.store.i16(i16 %trunc, <4 x i32> %rsrc, i32 0, i32 0, i32 0)716 ret void717}718 719define amdgpu_ps void @buffer_store_v2i16(<4 x i32> inreg %rsrc, <2 x i16> %data, i32 %offset) {720; VERDE-LABEL: buffer_store_v2i16:721; VERDE: ; %bb.0: ; %main_body722; VERDE-NEXT: v_lshlrev_b32_e32 v1, 16, v1723; VERDE-NEXT: v_and_b32_e32 v0, 0xffff, v0724; VERDE-NEXT: v_or_b32_e32 v0, v0, v1725; VERDE-NEXT: buffer_store_dword v0, v2, s[0:3], 0 offen726; VERDE-NEXT: s_endpgm727;728; GFX8-LABEL: buffer_store_v2i16:729; GFX8: ; %bb.0: ; %main_body730; GFX8-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen731; GFX8-NEXT: s_endpgm732;733; GFX11-LABEL: buffer_store_v2i16:734; GFX11: ; %bb.0: ; %main_body735; GFX11-NEXT: buffer_store_b32 v0, v1, s[0:3], 0 offen736; GFX11-NEXT: s_endpgm737;738; GFX1200-LABEL: buffer_store_v2i16:739; GFX1200: ; %bb.0: ; %main_body740; GFX1200-NEXT: buffer_store_b32 v0, v1, s[0:3], null offen741; GFX1200-NEXT: s_endpgm742;743; GFX1250-LABEL: buffer_store_v2i16:744; GFX1250: ; %bb.0: ; %main_body745; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1746; GFX1250-NEXT: buffer_store_b32 v0, v1, s[0:3], null offen747; GFX1250-NEXT: s_endpgm748main_body:749 call void @llvm.amdgcn.raw.buffer.store.v2i16(<2 x i16> %data, <4 x i32> %rsrc, i32 %offset, i32 0, i32 0)750 ret void751}752 753define amdgpu_ps void @buffer_store_v4i16(<4 x i32> inreg %rsrc, <4 x i16> %data, i32 %offset) #0 {754; VERDE-LABEL: buffer_store_v4i16:755; VERDE: ; %bb.0: ; %main_body756; VERDE-NEXT: v_lshlrev_b32_e32 v3, 16, v3757; VERDE-NEXT: v_and_b32_e32 v2, 0xffff, v2758; VERDE-NEXT: v_lshlrev_b32_e32 v1, 16, v1759; VERDE-NEXT: v_and_b32_e32 v0, 0xffff, v0760; VERDE-NEXT: v_or_b32_e32 v2, v2, v3761; VERDE-NEXT: v_or_b32_e32 v1, v0, v1762; VERDE-NEXT: buffer_store_dwordx2 v[1:2], v4, s[0:3], 0 offen763; VERDE-NEXT: s_endpgm764;765; GFX8-LABEL: buffer_store_v4i16:766; GFX8: ; %bb.0: ; %main_body767; GFX8-NEXT: buffer_store_dwordx2 v[0:1], v2, s[0:3], 0 offen768; GFX8-NEXT: s_endpgm769;770; GFX11-LABEL: buffer_store_v4i16:771; GFX11: ; %bb.0: ; %main_body772; GFX11-NEXT: buffer_store_b64 v[0:1], v2, s[0:3], 0 offen773; GFX11-NEXT: s_endpgm774;775; GFX1200-LABEL: buffer_store_v4i16:776; GFX1200: ; %bb.0: ; %main_body777; GFX1200-NEXT: buffer_store_b64 v[0:1], v2, s[0:3], null offen778; GFX1200-NEXT: s_endpgm779;780; GFX1250-LABEL: buffer_store_v4i16:781; GFX1250: ; %bb.0: ; %main_body782; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1783; GFX1250-NEXT: buffer_store_b64 v[0:1], v2, s[0:3], null offen784; GFX1250-NEXT: s_endpgm785main_body:786 call void @llvm.amdgcn.raw.buffer.store.v4i16(<4 x i16> %data, <4 x i32> %rsrc, i32 %offset, i32 0, i32 0)787 ret void788}789 790define amdgpu_ps void @raw_buffer_store_x1_offset_merged(<4 x i32> inreg %rsrc, float %v1, float %v2, float %v3, float %v4, float %v5, float %v6) {791; GFX68-LABEL: raw_buffer_store_x1_offset_merged:792; GFX68: ; %bb.0:793; GFX68-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:4794; GFX68-NEXT: buffer_store_dwordx2 v[4:5], off, s[0:3], 0 offset:28795; GFX68-NEXT: s_endpgm796;797; GFX11-LABEL: raw_buffer_store_x1_offset_merged:798; GFX11: ; %bb.0:799; GFX11-NEXT: s_clause 0x1800; GFX11-NEXT: buffer_store_b128 v[0:3], off, s[0:3], 0 offset:4801; GFX11-NEXT: buffer_store_b64 v[4:5], off, s[0:3], 0 offset:28802; GFX11-NEXT: s_endpgm803;804; GFX1200-LABEL: raw_buffer_store_x1_offset_merged:805; GFX1200: ; %bb.0:806; GFX1200-NEXT: s_clause 0x1807; GFX1200-NEXT: buffer_store_b128 v[0:3], off, s[0:3], null offset:4808; GFX1200-NEXT: buffer_store_b64 v[4:5], off, s[0:3], null offset:28809; GFX1200-NEXT: s_endpgm810;811; GFX1250-LABEL: raw_buffer_store_x1_offset_merged:812; GFX1250: ; %bb.0:813; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1814; GFX1250-NEXT: s_clause 0x1815; GFX1250-NEXT: buffer_store_b128 v[0:3], off, s[0:3], null offset:4816; GFX1250-NEXT: buffer_store_b64 v[4:5], off, s[0:3], null offset:28817; GFX1250-NEXT: s_endpgm818 call void @llvm.amdgcn.raw.buffer.store.f32(float %v1, <4 x i32> %rsrc, i32 4, i32 0, i32 0)819 call void @llvm.amdgcn.raw.buffer.store.f32(float %v2, <4 x i32> %rsrc, i32 8, i32 0, i32 0)820 call void @llvm.amdgcn.raw.buffer.store.f32(float %v3, <4 x i32> %rsrc, i32 12, i32 0, i32 0)821 call void @llvm.amdgcn.raw.buffer.store.f32(float %v4, <4 x i32> %rsrc, i32 16, i32 0, i32 0)822 call void @llvm.amdgcn.raw.buffer.store.f32(float %v5, <4 x i32> %rsrc, i32 28, i32 0, i32 0)823 call void @llvm.amdgcn.raw.buffer.store.f32(float %v6, <4 x i32> %rsrc, i32 32, i32 0, i32 0)824 ret void825}826 827define amdgpu_ps void @raw_buffer_store_x1_offset_swizzled_not_merged_pregfx12(<4 x i32> inreg %rsrc, float %v1, float %v2, float %v3, float %v4, float %v5, float %v6) {828; GFX68-LABEL: raw_buffer_store_x1_offset_swizzled_not_merged_pregfx12:829; GFX68: ; %bb.0:830; GFX68-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:4831; GFX68-NEXT: buffer_store_dword v1, off, s[0:3], 0 offset:8832; GFX68-NEXT: buffer_store_dword v2, off, s[0:3], 0 offset:12833; GFX68-NEXT: buffer_store_dword v3, off, s[0:3], 0 offset:16834; GFX68-NEXT: buffer_store_dword v4, off, s[0:3], 0 offset:28835; GFX68-NEXT: buffer_store_dword v5, off, s[0:3], 0 offset:32836; GFX68-NEXT: s_endpgm837;838; GFX11-LABEL: raw_buffer_store_x1_offset_swizzled_not_merged_pregfx12:839; GFX11: ; %bb.0:840; GFX11-NEXT: s_clause 0x5841; GFX11-NEXT: buffer_store_b32 v0, off, s[0:3], 0 offset:4842; GFX11-NEXT: buffer_store_b32 v1, off, s[0:3], 0 offset:8843; GFX11-NEXT: buffer_store_b32 v2, off, s[0:3], 0 offset:12844; GFX11-NEXT: buffer_store_b32 v3, off, s[0:3], 0 offset:16845; GFX11-NEXT: buffer_store_b32 v4, off, s[0:3], 0 offset:28846; GFX11-NEXT: buffer_store_b32 v5, off, s[0:3], 0 offset:32847; GFX11-NEXT: s_endpgm848;849; GFX1200-LABEL: raw_buffer_store_x1_offset_swizzled_not_merged_pregfx12:850; GFX1200: ; %bb.0:851; GFX1200-NEXT: s_clause 0x1852; GFX1200-NEXT: buffer_store_b128 v[0:3], off, s[0:3], null offset:4 scope:SCOPE_SE853; GFX1200-NEXT: buffer_store_b64 v[4:5], off, s[0:3], null offset:28 scope:SCOPE_SE854; GFX1200-NEXT: s_endpgm855;856; GFX1250-LABEL: raw_buffer_store_x1_offset_swizzled_not_merged_pregfx12:857; GFX1250: ; %bb.0:858; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1859; GFX1250-NEXT: s_clause 0x1860; GFX1250-NEXT: buffer_store_b128 v[0:3], off, s[0:3], null offset:4 scope:SCOPE_SE861; GFX1250-NEXT: buffer_store_b64 v[4:5], off, s[0:3], null offset:28 scope:SCOPE_SE862; GFX1250-NEXT: s_endpgm863 call void @llvm.amdgcn.raw.buffer.store.f32(float %v1, <4 x i32> %rsrc, i32 4, i32 0, i32 8)864 call void @llvm.amdgcn.raw.buffer.store.f32(float %v2, <4 x i32> %rsrc, i32 8, i32 0, i32 8)865 call void @llvm.amdgcn.raw.buffer.store.f32(float %v3, <4 x i32> %rsrc, i32 12, i32 0, i32 8)866 call void @llvm.amdgcn.raw.buffer.store.f32(float %v4, <4 x i32> %rsrc, i32 16, i32 0, i32 8)867 call void @llvm.amdgcn.raw.buffer.store.f32(float %v5, <4 x i32> %rsrc, i32 28, i32 0, i32 8)868 call void @llvm.amdgcn.raw.buffer.store.f32(float %v6, <4 x i32> %rsrc, i32 32, i32 0, i32 8)869 ret void870}871 872define amdgpu_ps void @raw_buffer_store_x1_offset_swizzled_not_merged(<4 x i32> inreg %rsrc, float %v1, float %v2, float %v3, float %v4, float %v5, float %v6) {873; GFX68-LABEL: raw_buffer_store_x1_offset_swizzled_not_merged:874; GFX68: ; %bb.0:875; GFX68-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:4876; GFX68-NEXT: buffer_store_dwordx2 v[4:5], off, s[0:3], 0 offset:28877; GFX68-NEXT: s_endpgm878;879; GFX11-LABEL: raw_buffer_store_x1_offset_swizzled_not_merged:880; GFX11: ; %bb.0:881; GFX11-NEXT: s_clause 0x1882; GFX11-NEXT: buffer_store_b128 v[0:3], off, s[0:3], 0 offset:4883; GFX11-NEXT: buffer_store_b64 v[4:5], off, s[0:3], 0 offset:28884; GFX11-NEXT: s_endpgm885;886; GFX1200-LABEL: raw_buffer_store_x1_offset_swizzled_not_merged:887; GFX1200: ; %bb.0:888; GFX1200-NEXT: s_clause 0x5889; GFX1200-NEXT: buffer_store_b32 v0, off, s[0:3], null offset:4890; GFX1200-NEXT: buffer_store_b32 v1, off, s[0:3], null offset:8891; GFX1200-NEXT: buffer_store_b32 v2, off, s[0:3], null offset:12892; GFX1200-NEXT: buffer_store_b32 v3, off, s[0:3], null offset:16893; GFX1200-NEXT: buffer_store_b32 v4, off, s[0:3], null offset:28894; GFX1200-NEXT: buffer_store_b32 v5, off, s[0:3], null offset:32895; GFX1200-NEXT: s_endpgm896;897; GFX1250-LABEL: raw_buffer_store_x1_offset_swizzled_not_merged:898; GFX1250: ; %bb.0:899; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1900; GFX1250-NEXT: s_clause 0x5901; GFX1250-NEXT: buffer_store_b32 v0, off, s[0:3], null offset:4902; GFX1250-NEXT: buffer_store_b32 v1, off, s[0:3], null offset:8903; GFX1250-NEXT: buffer_store_b32 v2, off, s[0:3], null offset:12904; GFX1250-NEXT: buffer_store_b32 v3, off, s[0:3], null offset:16905; GFX1250-NEXT: buffer_store_b32 v4, off, s[0:3], null offset:28906; GFX1250-NEXT: buffer_store_b32 v5, off, s[0:3], null offset:32907; GFX1250-NEXT: s_endpgm908 call void @llvm.amdgcn.raw.buffer.store.f32(float %v1, <4 x i32> %rsrc, i32 4, i32 0, i32 64)909 call void @llvm.amdgcn.raw.buffer.store.f32(float %v2, <4 x i32> %rsrc, i32 8, i32 0, i32 64)910 call void @llvm.amdgcn.raw.buffer.store.f32(float %v3, <4 x i32> %rsrc, i32 12, i32 0, i32 64)911 call void @llvm.amdgcn.raw.buffer.store.f32(float %v4, <4 x i32> %rsrc, i32 16, i32 0, i32 64)912 call void @llvm.amdgcn.raw.buffer.store.f32(float %v5, <4 x i32> %rsrc, i32 28, i32 0, i32 64)913 call void @llvm.amdgcn.raw.buffer.store.f32(float %v6, <4 x i32> %rsrc, i32 32, i32 0, i32 64)914 ret void915}916 917declare void @llvm.amdgcn.raw.buffer.store.f32(float, <4 x i32>, i32, i32, i32) #0918declare void @llvm.amdgcn.raw.buffer.store.v2f32(<2 x float>, <4 x i32>, i32, i32, i32) #0919declare void @llvm.amdgcn.raw.buffer.store.v4f32(<4 x float>, <4 x i32>, i32, i32, i32) #0920declare void @llvm.amdgcn.raw.buffer.store.i32(i32, <4 x i32>, i32, i32, i32) #0921declare void @llvm.amdgcn.raw.buffer.store.v2i32(<2 x i32>, <4 x i32>, i32, i32, i32) #0922declare void @llvm.amdgcn.raw.buffer.store.v4i32(<4 x i32>, <4 x i32>, i32, i32, i32) #0923declare <4 x float> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32>, i32, i32, i32) #1924declare void @llvm.amdgcn.raw.buffer.store.i8(i8, <4 x i32>, i32, i32, i32) #0925declare void @llvm.amdgcn.raw.buffer.store.f16(half, <4 x i32>, i32, i32, i32) #0926declare void @llvm.amdgcn.raw.buffer.store.v2f16(<2 x half>, <4 x i32>, i32, i32, i32) #0927declare void @llvm.amdgcn.raw.buffer.store.v4f16(<4 x half>, <4 x i32>, i32, i32, i32) #0928declare void @llvm.amdgcn.raw.buffer.store.i16(i16, <4 x i32>, i32, i32, i32) #0929declare void @llvm.amdgcn.raw.buffer.store.v2i16(<2 x i16>, <4 x i32>, i32, i32, i32) #0930declare void @llvm.amdgcn.raw.buffer.store.v4i16(<4 x i16>, <4 x i32>, i32, i32, i32) #0931 932attributes #0 = { nounwind }933attributes #1 = { nounwind readonly }934