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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx90a < %s | FileCheck -check-prefix=GFX90A %s3; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx942 < %s | FileCheck -check-prefix=GFX942 %s4; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1200 < %s | FileCheck -check-prefix=GFX1200 %s5; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1250 < %s | FileCheck -check-prefix=GFX1250 %s6 7define float @raw_ptr_buffer_atomic_add_f32_rtn__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset(float %val, ptr addrspace(8) inreg %rsrc, i32 %voffset, i32 inreg %soffset) #0 {8; GFX90A-LABEL: raw_ptr_buffer_atomic_add_f32_rtn__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset:9; GFX90A: ; %bb.0:10; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)11; GFX90A-NEXT: buffer_atomic_add_f32 v0, v1, s[16:19], s20 offen glc scc12; GFX90A-NEXT: s_waitcnt vmcnt(0)13; GFX90A-NEXT: s_setpc_b64 s[30:31]14;15; GFX942-LABEL: raw_ptr_buffer_atomic_add_f32_rtn__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset:16; GFX942: ; %bb.0:17; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)18; GFX942-NEXT: buffer_atomic_add_f32 v0, v1, s[0:3], s16 offen sc0 sc119; GFX942-NEXT: s_waitcnt vmcnt(0)20; GFX942-NEXT: s_setpc_b64 s[30:31]21;22; GFX1200-LABEL: raw_ptr_buffer_atomic_add_f32_rtn__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset:23; GFX1200: ; %bb.0:24; GFX1200-NEXT: s_wait_loadcnt_dscnt 0x025; GFX1200-NEXT: s_wait_expcnt 0x026; GFX1200-NEXT: s_wait_samplecnt 0x027; GFX1200-NEXT: s_wait_bvhcnt 0x028; GFX1200-NEXT: s_wait_kmcnt 0x029; GFX1200-NEXT: buffer_atomic_add_f32 v0, v1, s[0:3], s16 offen th:TH_ATOMIC_RETURN scope:SCOPE_SYS30; GFX1200-NEXT: s_wait_loadcnt 0x031; GFX1200-NEXT: s_setpc_b64 s[30:31]32;33; GFX1250-LABEL: raw_ptr_buffer_atomic_add_f32_rtn__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset:34; GFX1250: ; %bb.0:35; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x036; GFX1250-NEXT: s_wait_kmcnt 0x037; GFX1250-NEXT: buffer_atomic_add_f32 v0, v1, s[0:3], s16 offen th:TH_ATOMIC_RETURN scope:SCOPE_SYS38; GFX1250-NEXT: s_wait_loadcnt 0x039; GFX1250-NEXT: s_set_pc_i64 s[30:31]40 %ret = call float @llvm.amdgcn.raw.ptr.buffer.atomic.fadd.f32(float %val, ptr addrspace(8) %rsrc, i32 %voffset, i32 %soffset, i32 24)41 ret float %ret42}43 44define float @raw_ptr_buffer_atomic_add_f32_rtn__vgpr_val__sgpr_rsrc__0_voffset__sgpr_soffset(float %val, ptr addrspace(8) inreg %rsrc, i32 inreg %soffset) #0 {45; GFX90A-LABEL: raw_ptr_buffer_atomic_add_f32_rtn__vgpr_val__sgpr_rsrc__0_voffset__sgpr_soffset:46; GFX90A: ; %bb.0:47; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)48; GFX90A-NEXT: buffer_atomic_add_f32 v0, off, s[16:19], s20 glc49; GFX90A-NEXT: s_waitcnt vmcnt(0)50; GFX90A-NEXT: s_setpc_b64 s[30:31]51;52; GFX942-LABEL: raw_ptr_buffer_atomic_add_f32_rtn__vgpr_val__sgpr_rsrc__0_voffset__sgpr_soffset:53; GFX942: ; %bb.0:54; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)55; GFX942-NEXT: buffer_atomic_add_f32 v0, off, s[0:3], s16 sc056; GFX942-NEXT: s_waitcnt vmcnt(0)57; GFX942-NEXT: s_setpc_b64 s[30:31]58;59; GFX1200-LABEL: raw_ptr_buffer_atomic_add_f32_rtn__vgpr_val__sgpr_rsrc__0_voffset__sgpr_soffset:60; GFX1200: ; %bb.0:61; GFX1200-NEXT: s_wait_loadcnt_dscnt 0x062; GFX1200-NEXT: s_wait_expcnt 0x063; GFX1200-NEXT: s_wait_samplecnt 0x064; GFX1200-NEXT: s_wait_bvhcnt 0x065; GFX1200-NEXT: s_wait_kmcnt 0x066; GFX1200-NEXT: buffer_atomic_add_f32 v0, off, s[0:3], s16 th:TH_ATOMIC_RETURN67; GFX1200-NEXT: s_wait_loadcnt 0x068; GFX1200-NEXT: s_setpc_b64 s[30:31]69;70; GFX1250-LABEL: raw_ptr_buffer_atomic_add_f32_rtn__vgpr_val__sgpr_rsrc__0_voffset__sgpr_soffset:71; GFX1250: ; %bb.0:72; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x073; GFX1250-NEXT: s_wait_kmcnt 0x074; GFX1250-NEXT: buffer_atomic_add_f32 v0, off, s[0:3], s16 th:TH_ATOMIC_RETURN75; GFX1250-NEXT: s_wait_loadcnt 0x076; GFX1250-NEXT: s_set_pc_i64 s[30:31]77 %ret = call float @llvm.amdgcn.raw.ptr.buffer.atomic.fadd.f32(float %val, ptr addrspace(8) %rsrc, i32 0, i32 %soffset, i32 0)78 ret float %ret79}80 81define <2 x half> @raw_ptr_buffer_atomic_add_v2f16_rtn__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset(<2 x half> %val, ptr addrspace(8) inreg %rsrc, i32 %voffset, i32 inreg %soffset) #0 {82; GFX90A-LABEL: raw_ptr_buffer_atomic_add_v2f16_rtn__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset:83; GFX90A: ; %bb.0:84; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)85; GFX90A-NEXT: buffer_atomic_pk_add_f16 v0, v1, s[16:19], s20 offen glc86; GFX90A-NEXT: s_waitcnt vmcnt(0)87; GFX90A-NEXT: s_setpc_b64 s[30:31]88;89; GFX942-LABEL: raw_ptr_buffer_atomic_add_v2f16_rtn__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset:90; GFX942: ; %bb.0:91; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)92; GFX942-NEXT: buffer_atomic_pk_add_f16 v0, v1, s[0:3], s16 offen sc093; GFX942-NEXT: s_waitcnt vmcnt(0)94; GFX942-NEXT: s_setpc_b64 s[30:31]95;96; GFX1200-LABEL: raw_ptr_buffer_atomic_add_v2f16_rtn__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset:97; GFX1200: ; %bb.0:98; GFX1200-NEXT: s_wait_loadcnt_dscnt 0x099; GFX1200-NEXT: s_wait_expcnt 0x0100; GFX1200-NEXT: s_wait_samplecnt 0x0101; GFX1200-NEXT: s_wait_bvhcnt 0x0102; GFX1200-NEXT: s_wait_kmcnt 0x0103; GFX1200-NEXT: buffer_atomic_pk_add_f16 v0, v1, s[0:3], s16 offen th:TH_ATOMIC_RETURN104; GFX1200-NEXT: s_wait_loadcnt 0x0105; GFX1200-NEXT: s_setpc_b64 s[30:31]106;107; GFX1250-LABEL: raw_ptr_buffer_atomic_add_v2f16_rtn__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset:108; GFX1250: ; %bb.0:109; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0110; GFX1250-NEXT: s_wait_kmcnt 0x0111; GFX1250-NEXT: buffer_atomic_pk_add_f16 v0, v1, s[0:3], s16 offen th:TH_ATOMIC_RETURN112; GFX1250-NEXT: s_wait_loadcnt 0x0113; GFX1250-NEXT: s_set_pc_i64 s[30:31]114 %ret = call <2 x half> @llvm.amdgcn.raw.ptr.buffer.atomic.fadd.v2f16(<2 x half> %val, ptr addrspace(8) %rsrc, i32 %voffset, i32 %soffset, i32 0)115 ret <2 x half> %ret116}117 118define <2 x half> @raw_ptr_buffer_atomic_add_v2f16_rtn__vgpr_val__sgpr_rsrc__0_voffset__sgpr_soffset(<2 x half> %val, ptr addrspace(8) inreg %rsrc, i32 %voffset, i32 inreg %soffset) #0 {119; GFX90A-LABEL: raw_ptr_buffer_atomic_add_v2f16_rtn__vgpr_val__sgpr_rsrc__0_voffset__sgpr_soffset:120; GFX90A: ; %bb.0:121; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)122; GFX90A-NEXT: buffer_atomic_pk_add_f16 v0, off, s[16:19], s20 offset:92 glc123; GFX90A-NEXT: s_waitcnt vmcnt(0)124; GFX90A-NEXT: s_setpc_b64 s[30:31]125;126; GFX942-LABEL: raw_ptr_buffer_atomic_add_v2f16_rtn__vgpr_val__sgpr_rsrc__0_voffset__sgpr_soffset:127; GFX942: ; %bb.0:128; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)129; GFX942-NEXT: buffer_atomic_pk_add_f16 v0, off, s[0:3], s16 offset:92 sc0130; GFX942-NEXT: s_waitcnt vmcnt(0)131; GFX942-NEXT: s_setpc_b64 s[30:31]132;133; GFX1200-LABEL: raw_ptr_buffer_atomic_add_v2f16_rtn__vgpr_val__sgpr_rsrc__0_voffset__sgpr_soffset:134; GFX1200: ; %bb.0:135; GFX1200-NEXT: s_wait_loadcnt_dscnt 0x0136; GFX1200-NEXT: s_wait_expcnt 0x0137; GFX1200-NEXT: s_wait_samplecnt 0x0138; GFX1200-NEXT: s_wait_bvhcnt 0x0139; GFX1200-NEXT: s_wait_kmcnt 0x0140; GFX1200-NEXT: buffer_atomic_pk_add_f16 v0, off, s[0:3], s16 offset:92 th:TH_ATOMIC_RETURN141; GFX1200-NEXT: s_wait_loadcnt 0x0142; GFX1200-NEXT: s_setpc_b64 s[30:31]143;144; GFX1250-LABEL: raw_ptr_buffer_atomic_add_v2f16_rtn__vgpr_val__sgpr_rsrc__0_voffset__sgpr_soffset:145; GFX1250: ; %bb.0:146; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0147; GFX1250-NEXT: s_wait_kmcnt 0x0148; GFX1250-NEXT: buffer_atomic_pk_add_f16 v0, off, s[0:3], s16 offset:92 th:TH_ATOMIC_RETURN149; GFX1250-NEXT: s_wait_loadcnt 0x0150; GFX1250-NEXT: s_set_pc_i64 s[30:31]151 %ret = call <2 x half> @llvm.amdgcn.raw.ptr.buffer.atomic.fadd.v2f16(<2 x half> %val, ptr addrspace(8) %rsrc, i32 92, i32 %soffset, i32 0)152 ret <2 x half> %ret153}154 155define float @raw_ptr_buffer_atomic_add_f32_rtn__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc(float %val, ptr addrspace(8) inreg %rsrc, i32 %voffset, i32 inreg %soffset) #0 {156; GFX90A-LABEL: raw_ptr_buffer_atomic_add_f32_rtn__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc:157; GFX90A: ; %bb.0:158; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)159; GFX90A-NEXT: buffer_atomic_add_f32 v0, v1, s[16:19], s20 offen glc slc160; GFX90A-NEXT: s_waitcnt vmcnt(0)161; GFX90A-NEXT: s_setpc_b64 s[30:31]162;163; GFX942-LABEL: raw_ptr_buffer_atomic_add_f32_rtn__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc:164; GFX942: ; %bb.0:165; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)166; GFX942-NEXT: buffer_atomic_add_f32 v0, v1, s[0:3], s16 offen sc0 nt167; GFX942-NEXT: s_waitcnt vmcnt(0)168; GFX942-NEXT: s_setpc_b64 s[30:31]169;170; GFX1200-LABEL: raw_ptr_buffer_atomic_add_f32_rtn__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc:171; GFX1200: ; %bb.0:172; GFX1200-NEXT: s_wait_loadcnt_dscnt 0x0173; GFX1200-NEXT: s_wait_expcnt 0x0174; GFX1200-NEXT: s_wait_samplecnt 0x0175; GFX1200-NEXT: s_wait_bvhcnt 0x0176; GFX1200-NEXT: s_wait_kmcnt 0x0177; GFX1200-NEXT: buffer_atomic_add_f32 v0, v1, s[0:3], s16 offen th:TH_ATOMIC_NT_RETURN178; GFX1200-NEXT: s_wait_loadcnt 0x0179; GFX1200-NEXT: s_setpc_b64 s[30:31]180;181; GFX1250-LABEL: raw_ptr_buffer_atomic_add_f32_rtn__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc:182; GFX1250: ; %bb.0:183; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0184; GFX1250-NEXT: s_wait_kmcnt 0x0185; GFX1250-NEXT: buffer_atomic_add_f32 v0, v1, s[0:3], s16 offen th:TH_ATOMIC_NT_RETURN186; GFX1250-NEXT: s_wait_loadcnt 0x0187; GFX1250-NEXT: s_set_pc_i64 s[30:31]188 %ret = call float @llvm.amdgcn.raw.ptr.buffer.atomic.fadd.f32(float %val, ptr addrspace(8) %rsrc, i32 %voffset, i32 %soffset, i32 2)189 ret float %ret190}191 192declare float @llvm.amdgcn.raw.ptr.buffer.atomic.fadd.f32(float, ptr addrspace(8), i32, i32, i32 immarg)193declare <2 x half> @llvm.amdgcn.raw.ptr.buffer.atomic.fadd.v2f16(<2 x half>, ptr addrspace(8), i32, i32, i32 immarg)194 195attributes #0 = { nounwind }196