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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 -mattr=+real-true16 %s -o - | FileCheck -check-prefix=SDAG-REAL16 %s3; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 -mattr=-real-true16 %s -o - | FileCheck -check-prefix=SDAG-FAKE16 %s4; xUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 -mattr=+real-true16 %s -o - | FileCheck -check-prefix=GISEL-REAL16 %s5; xUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 -mattr=-real-true16 %s -o - | FileCheck -check-prefix=GISEL-FAKE16 %s6 7; FIXME: GlobalISel does not work with bf168 9declare bfloat @llvm.amdgcn.rsq.bf16(bfloat) #010 11define amdgpu_kernel void @rsq_bf16(ptr addrspace(1) %out, bfloat %src) #1 {12; SDAG-REAL16-LABEL: rsq_bf16:13; SDAG-REAL16: ; %bb.0:14; SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 115; SDAG-REAL16-NEXT: s_load_b96 s[0:2], s[4:5], 0x016; SDAG-REAL16-NEXT: v_mov_b32_e32 v1, 017; SDAG-REAL16-NEXT: s_wait_kmcnt 0x018; SDAG-REAL16-NEXT: v_rsq_bf16_e32 v0.l, s219; SDAG-REAL16-NEXT: global_store_b16 v1, v0, s[0:1]20; SDAG-REAL16-NEXT: s_endpgm21;22; SDAG-FAKE16-LABEL: rsq_bf16:23; SDAG-FAKE16: ; %bb.0:24; SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 125; SDAG-FAKE16-NEXT: s_load_b96 s[0:2], s[4:5], 0x026; SDAG-FAKE16-NEXT: v_mov_b32_e32 v1, 027; SDAG-FAKE16-NEXT: s_wait_kmcnt 0x028; SDAG-FAKE16-NEXT: v_rsq_bf16_e32 v0, s229; SDAG-FAKE16-NEXT: global_store_b16 v1, v0, s[0:1]30; SDAG-FAKE16-NEXT: s_endpgm31 %rsq = call bfloat @llvm.amdgcn.rsq.bf16(bfloat %src) #032 store bfloat %rsq, ptr addrspace(1) %out, align 233 ret void34}35 36define amdgpu_kernel void @rsq_bf16_constant_4(ptr addrspace(1) %out) #1 {37; SDAG-REAL16-LABEL: rsq_bf16_constant_4:38; SDAG-REAL16: ; %bb.0:39; SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 140; SDAG-REAL16-NEXT: s_load_b64 s[0:1], s[4:5], 0x041; SDAG-REAL16-NEXT: v_rsq_bf16_e32 v0.l, 4.042; SDAG-REAL16-NEXT: v_mov_b32_e32 v1, 043; SDAG-REAL16-NEXT: s_wait_kmcnt 0x044; SDAG-REAL16-NEXT: global_store_b16 v1, v0, s[0:1]45; SDAG-REAL16-NEXT: s_endpgm46;47; SDAG-FAKE16-LABEL: rsq_bf16_constant_4:48; SDAG-FAKE16: ; %bb.0:49; SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 150; SDAG-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x051; SDAG-FAKE16-NEXT: v_rsq_bf16_e32 v0, 4.052; SDAG-FAKE16-NEXT: v_mov_b32_e32 v1, 053; SDAG-FAKE16-NEXT: s_wait_kmcnt 0x054; SDAG-FAKE16-NEXT: global_store_b16 v1, v0, s[0:1]55; SDAG-FAKE16-NEXT: s_endpgm56 %rsq = call bfloat @llvm.amdgcn.rsq.bf16(bfloat 4.0) #057 store bfloat %rsq, ptr addrspace(1) %out, align 258 ret void59}60 61define amdgpu_kernel void @rsq_bf16_constant_100(ptr addrspace(1) %out) #1 {62; SDAG-REAL16-LABEL: rsq_bf16_constant_100:63; SDAG-REAL16: ; %bb.0:64; SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 165; SDAG-REAL16-NEXT: s_load_b64 s[0:1], s[4:5], 0x066; SDAG-REAL16-NEXT: v_rsq_bf16_e32 v0.l, 0x42c867; SDAG-REAL16-NEXT: v_mov_b32_e32 v1, 068; SDAG-REAL16-NEXT: s_wait_kmcnt 0x069; SDAG-REAL16-NEXT: global_store_b16 v1, v0, s[0:1]70; SDAG-REAL16-NEXT: s_endpgm71;72; SDAG-FAKE16-LABEL: rsq_bf16_constant_100:73; SDAG-FAKE16: ; %bb.0:74; SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 175; SDAG-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x076; SDAG-FAKE16-NEXT: v_rsq_bf16_e32 v0, 0x42c877; SDAG-FAKE16-NEXT: v_mov_b32_e32 v1, 078; SDAG-FAKE16-NEXT: s_wait_kmcnt 0x079; SDAG-FAKE16-NEXT: global_store_b16 v1, v0, s[0:1]80; SDAG-FAKE16-NEXT: s_endpgm81 %rsq = call bfloat @llvm.amdgcn.rsq.bf16(bfloat 100.0) #082 store bfloat %rsq, ptr addrspace(1) %out, align 283 ret void84}85 86define amdgpu_kernel void @rsq_undef_bf16(ptr addrspace(1) %out) #1 {87; SDAG-REAL16-LABEL: rsq_undef_bf16:88; SDAG-REAL16: ; %bb.0:89; SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 190; SDAG-REAL16-NEXT: s_endpgm91;92; SDAG-FAKE16-LABEL: rsq_undef_bf16:93; SDAG-FAKE16: ; %bb.0:94; SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 195; SDAG-FAKE16-NEXT: s_endpgm96 %rsq = call bfloat @llvm.amdgcn.rsq.bf16(bfloat undef)97 store bfloat %rsq, ptr addrspace(1) %out, align 298 ret void99}100 101attributes #0 = { nounwind readnone }102attributes #1 = { nounwind }103