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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GFX12-SDAG %s3; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GFX12-GISEL %s4 5define i1 @func1() {6; GFX12-SDAG-LABEL: func1:7; GFX12-SDAG: ; %bb.0:8; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x09; GFX12-SDAG-NEXT: s_wait_expcnt 0x010; GFX12-SDAG-NEXT: s_wait_samplecnt 0x011; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x012; GFX12-SDAG-NEXT: s_wait_kmcnt 0x013; GFX12-SDAG-NEXT: s_cmp_eq_u32 0, 014; GFX12-SDAG-NEXT: s_barrier_signal_isfirst -115; GFX12-SDAG-NEXT: s_wait_kmcnt 0x016; GFX12-SDAG-NEXT: s_cselect_b32 s0, -1, 017; GFX12-SDAG-NEXT: s_wait_alu depctr_sa_sdst(0)18; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, s019; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]20;21; GFX12-GISEL-LABEL: func1:22; GFX12-GISEL: ; %bb.0:23; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x024; GFX12-GISEL-NEXT: s_wait_expcnt 0x025; GFX12-GISEL-NEXT: s_wait_samplecnt 0x026; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x027; GFX12-GISEL-NEXT: s_wait_kmcnt 0x028; GFX12-GISEL-NEXT: s_cmp_eq_u32 0, 029; GFX12-GISEL-NEXT: s_barrier_signal_isfirst -130; GFX12-GISEL-NEXT: s_wait_kmcnt 0x031; GFX12-GISEL-NEXT: s_cselect_b32 s0, 1, 032; GFX12-GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)33; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, s034; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]35 %r = call i1 @llvm.amdgcn.s.barrier.signal.isfirst(i32 -1)36 ret i1 %r37}38 39define i1 @signal_isfirst_same_barrier_wait() {40; GFX12-SDAG-LABEL: signal_isfirst_same_barrier_wait:41; GFX12-SDAG: ; %bb.0:42; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x043; GFX12-SDAG-NEXT: s_wait_expcnt 0x044; GFX12-SDAG-NEXT: s_wait_samplecnt 0x045; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x046; GFX12-SDAG-NEXT: s_wait_kmcnt 0x047; GFX12-SDAG-NEXT: s_cmp_eq_u32 0, 048; GFX12-SDAG-NEXT: s_barrier_signal_isfirst -149; GFX12-SDAG-NEXT: s_barrier_wait -150; GFX12-SDAG-NEXT: s_cselect_b32 s0, -1, 051; GFX12-SDAG-NEXT: s_wait_alu depctr_sa_sdst(0)52; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, s053; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]54;55; GFX12-GISEL-LABEL: signal_isfirst_same_barrier_wait:56; GFX12-GISEL: ; %bb.0:57; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x058; GFX12-GISEL-NEXT: s_wait_expcnt 0x059; GFX12-GISEL-NEXT: s_wait_samplecnt 0x060; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x061; GFX12-GISEL-NEXT: s_wait_kmcnt 0x062; GFX12-GISEL-NEXT: s_cmp_eq_u32 0, 063; GFX12-GISEL-NEXT: s_barrier_signal_isfirst -164; GFX12-GISEL-NEXT: s_barrier_wait -165; GFX12-GISEL-NEXT: s_cselect_b32 s0, 1, 066; GFX12-GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)67; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, s068; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]69 %r = call i1 @llvm.amdgcn.s.barrier.signal.isfirst(i32 -1)70 call void @llvm.amdgcn.s.barrier.wait(i16 -1)71 ret i1 %r72}73 74define i1 @signal_isfirst_different_barrier_wait() {75; GFX12-SDAG-LABEL: signal_isfirst_different_barrier_wait:76; GFX12-SDAG: ; %bb.0:77; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x078; GFX12-SDAG-NEXT: s_wait_expcnt 0x079; GFX12-SDAG-NEXT: s_wait_samplecnt 0x080; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x081; GFX12-SDAG-NEXT: s_wait_kmcnt 0x082; GFX12-SDAG-NEXT: s_cmp_eq_u32 0, 083; GFX12-SDAG-NEXT: s_barrier_signal_isfirst -184; GFX12-SDAG-NEXT: s_barrier_wait 085; GFX12-SDAG-NEXT: s_wait_kmcnt 0x086; GFX12-SDAG-NEXT: s_cselect_b32 s0, -1, 087; GFX12-SDAG-NEXT: s_wait_alu depctr_sa_sdst(0)88; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, s089; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]90;91; GFX12-GISEL-LABEL: signal_isfirst_different_barrier_wait:92; GFX12-GISEL: ; %bb.0:93; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x094; GFX12-GISEL-NEXT: s_wait_expcnt 0x095; GFX12-GISEL-NEXT: s_wait_samplecnt 0x096; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x097; GFX12-GISEL-NEXT: s_wait_kmcnt 0x098; GFX12-GISEL-NEXT: s_cmp_eq_u32 0, 099; GFX12-GISEL-NEXT: s_barrier_signal_isfirst -1100; GFX12-GISEL-NEXT: s_barrier_wait 0101; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0102; GFX12-GISEL-NEXT: s_cselect_b32 s0, 1, 0103; GFX12-GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)104; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, s0105; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]106 %r = call i1 @llvm.amdgcn.s.barrier.signal.isfirst(i32 -1)107 call void @llvm.amdgcn.s.barrier.wait(i16 0)108 ret i1 %r109}110 111declare void @llvm.amdgcn.s.barrier.wait(i16)112declare i1 @llvm.amdgcn.s.barrier.signal.isfirst(i32)113