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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn -mcpu=verde -show-mc-encoding < %s | FileCheck -check-prefixes=GFX6 %s3; RUN: llc -mtriple=amdgcn -mcpu=tonga -show-mc-encoding < %s | FileCheck -check-prefixes=GFX789 %s4; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -show-mc-encoding < %s | FileCheck -check-prefixes=GFX789 %s5; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -show-mc-encoding < %s | FileCheck -check-prefixes=GFX10 %s6; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -show-mc-encoding < %s | FileCheck -check-prefixes=GFX11 %s7 8; FIXME: This copy of the test is a subset of the -global-isel version, since the VGPR case doesn't work.9 10; Immediate values:11; (mode register ID = 1) | (Offset << 6) | ((Width - 1) << 11)12; Offset: fp_round = 0, fp_denorm = 4, dx10_clamp = 8, ieee_mode = 913 14 15; Set FP32 fp_round to round to zero16define amdgpu_kernel void @test_setreg_f32_round_mode_rtz() {17; GFX6-LABEL: test_setreg_f32_round_mode_rtz:18; GFX6: ; %bb.0:19; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 2), 3 ; encoding: [0x01,0x08,0x80,0xba,0x03,0x00,0x00,0x00]20; GFX6-NEXT: ;;#ASMSTART21; GFX6-NEXT: ;;#ASMEND22; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]23;24; GFX789-LABEL: test_setreg_f32_round_mode_rtz:25; GFX789: ; %bb.0:26; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 2), 3 ; encoding: [0x01,0x08,0x00,0xba,0x03,0x00,0x00,0x00]27; GFX789-NEXT: ;;#ASMSTART28; GFX789-NEXT: ;;#ASMEND29; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]30;31; GFX10-LABEL: test_setreg_f32_round_mode_rtz:32; GFX10: ; %bb.0:33; GFX10-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 2), 3 ; encoding: [0x01,0x08,0x80,0xba,0x03,0x00,0x00,0x00]34; GFX10-NEXT: ;;#ASMSTART35; GFX10-NEXT: ;;#ASMEND36; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]37;38; GFX11-LABEL: test_setreg_f32_round_mode_rtz:39; GFX11: ; %bb.0:40; GFX11-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 2), 3 ; encoding: [0x01,0x08,0x80,0xb9,0x03,0x00,0x00,0x00]41; GFX11-NEXT: ;;#ASMSTART42; GFX11-NEXT: ;;#ASMEND43; GFX11-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]44 call void @llvm.amdgcn.s.setreg(i32 2049, i32 3)45 call void asm sideeffect "", ""()46 ret void47}48 49; Set FP64/FP16 fp_round to round to zero50define amdgpu_kernel void @test_setreg_f64_round_mode_rtz() {51; GFX6-LABEL: test_setreg_f64_round_mode_rtz:52; GFX6: ; %bb.0:53; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 3 ; encoding: [0x81,0x08,0x80,0xba,0x03,0x00,0x00,0x00]54; GFX6-NEXT: ;;#ASMSTART55; GFX6-NEXT: ;;#ASMEND56; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]57;58; GFX789-LABEL: test_setreg_f64_round_mode_rtz:59; GFX789: ; %bb.0:60; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 3 ; encoding: [0x81,0x08,0x00,0xba,0x03,0x00,0x00,0x00]61; GFX789-NEXT: ;;#ASMSTART62; GFX789-NEXT: ;;#ASMEND63; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]64;65; GFX10-LABEL: test_setreg_f64_round_mode_rtz:66; GFX10: ; %bb.0:67; GFX10-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 3 ; encoding: [0x81,0x08,0x80,0xba,0x03,0x00,0x00,0x00]68; GFX10-NEXT: ;;#ASMSTART69; GFX10-NEXT: ;;#ASMEND70; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]71;72; GFX11-LABEL: test_setreg_f64_round_mode_rtz:73; GFX11: ; %bb.0:74; GFX11-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 3 ; encoding: [0x81,0x08,0x80,0xb9,0x03,0x00,0x00,0x00]75; GFX11-NEXT: ;;#ASMSTART76; GFX11-NEXT: ;;#ASMEND77; GFX11-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]78 call void @llvm.amdgcn.s.setreg(i32 2177, i32 3)79 call void asm sideeffect "", ""()80 ret void81}82 83; Set all fp_round to round to zero84define amdgpu_kernel void @test_setreg_all_round_mode_rtz() {85; GFX6-LABEL: test_setreg_all_round_mode_rtz:86; GFX6: ; %bb.0:87; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 4), 7 ; encoding: [0x81,0x18,0x80,0xba,0x07,0x00,0x00,0x00]88; GFX6-NEXT: ;;#ASMSTART89; GFX6-NEXT: ;;#ASMEND90; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]91;92; GFX789-LABEL: test_setreg_all_round_mode_rtz:93; GFX789: ; %bb.0:94; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 4), 7 ; encoding: [0x81,0x18,0x00,0xba,0x07,0x00,0x00,0x00]95; GFX789-NEXT: ;;#ASMSTART96; GFX789-NEXT: ;;#ASMEND97; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]98;99; GFX10-LABEL: test_setreg_all_round_mode_rtz:100; GFX10: ; %bb.0:101; GFX10-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 4), 7 ; encoding: [0x81,0x18,0x80,0xba,0x07,0x00,0x00,0x00]102; GFX10-NEXT: ;;#ASMSTART103; GFX10-NEXT: ;;#ASMEND104; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]105;106; GFX11-LABEL: test_setreg_all_round_mode_rtz:107; GFX11: ; %bb.0:108; GFX11-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 4), 7 ; encoding: [0x81,0x18,0x80,0xb9,0x07,0x00,0x00,0x00]109; GFX11-NEXT: ;;#ASMSTART110; GFX11-NEXT: ;;#ASMEND111; GFX11-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]112 call void @llvm.amdgcn.s.setreg(i32 6273, i32 7)113 call void asm sideeffect "", ""()114 ret void115}116 117; Set FP32 fp_round to dynamic mode118define amdgpu_cs void @test_setreg_roundingmode_var(i32 inreg %var.mode) {119; GFX6-LABEL: test_setreg_roundingmode_var:120; GFX6: ; %bb.0:121; GFX6-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 2), s0 ; encoding: [0x01,0x08,0x80,0xb9]122; GFX6-NEXT: ;;#ASMSTART123; GFX6-NEXT: ;;#ASMEND124; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]125;126; GFX789-LABEL: test_setreg_roundingmode_var:127; GFX789: ; %bb.0:128; GFX789-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 2), s0 ; encoding: [0x01,0x08,0x00,0xb9]129; GFX789-NEXT: ;;#ASMSTART130; GFX789-NEXT: ;;#ASMEND131; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]132;133; GFX10-LABEL: test_setreg_roundingmode_var:134; GFX10: ; %bb.0:135; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 2), s0 ; encoding: [0x01,0x08,0x80,0xb9]136; GFX10-NEXT: ;;#ASMSTART137; GFX10-NEXT: ;;#ASMEND138; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]139;140; GFX11-LABEL: test_setreg_roundingmode_var:141; GFX11: ; %bb.0:142; GFX11-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 2), s0 ; encoding: [0x01,0x08,0x00,0xb9]143; GFX11-NEXT: ;;#ASMSTART144; GFX11-NEXT: ;;#ASMEND145; GFX11-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]146 call void @llvm.amdgcn.s.setreg(i32 2049, i32 %var.mode)147 call void asm sideeffect "", ""()148 ret void149}150 151define amdgpu_kernel void @test_setreg_ieee_mode_off() {152; GFX6-LABEL: test_setreg_ieee_mode_off:153; GFX6: ; %bb.0:154; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 9, 1), 0 ; encoding: [0x41,0x02,0x80,0xba,0x00,0x00,0x00,0x00]155; GFX6-NEXT: ;;#ASMSTART156; GFX6-NEXT: ;;#ASMEND157; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]158;159; GFX789-LABEL: test_setreg_ieee_mode_off:160; GFX789: ; %bb.0:161; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 9, 1), 0 ; encoding: [0x41,0x02,0x00,0xba,0x00,0x00,0x00,0x00]162; GFX789-NEXT: ;;#ASMSTART163; GFX789-NEXT: ;;#ASMEND164; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]165;166; GFX10-LABEL: test_setreg_ieee_mode_off:167; GFX10: ; %bb.0:168; GFX10-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 9, 1), 0 ; encoding: [0x41,0x02,0x80,0xba,0x00,0x00,0x00,0x00]169; GFX10-NEXT: ;;#ASMSTART170; GFX10-NEXT: ;;#ASMEND171; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]172;173; GFX11-LABEL: test_setreg_ieee_mode_off:174; GFX11: ; %bb.0:175; GFX11-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 9, 1), 0 ; encoding: [0x41,0x02,0x80,0xb9,0x00,0x00,0x00,0x00]176; GFX11-NEXT: ;;#ASMSTART177; GFX11-NEXT: ;;#ASMEND178; GFX11-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]179 call void @llvm.amdgcn.s.setreg(i32 577, i32 0)180 call void asm sideeffect "", ""()181 ret void182}183 184define amdgpu_kernel void @test_setreg_ieee_mode_on() {185; GFX6-LABEL: test_setreg_ieee_mode_on:186; GFX6: ; %bb.0:187; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 9, 1), 1 ; encoding: [0x41,0x02,0x80,0xba,0x01,0x00,0x00,0x00]188; GFX6-NEXT: ;;#ASMSTART189; GFX6-NEXT: ;;#ASMEND190; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]191;192; GFX789-LABEL: test_setreg_ieee_mode_on:193; GFX789: ; %bb.0:194; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 9, 1), 1 ; encoding: [0x41,0x02,0x00,0xba,0x01,0x00,0x00,0x00]195; GFX789-NEXT: ;;#ASMSTART196; GFX789-NEXT: ;;#ASMEND197; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]198;199; GFX10-LABEL: test_setreg_ieee_mode_on:200; GFX10: ; %bb.0:201; GFX10-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 9, 1), 1 ; encoding: [0x41,0x02,0x80,0xba,0x01,0x00,0x00,0x00]202; GFX10-NEXT: ;;#ASMSTART203; GFX10-NEXT: ;;#ASMEND204; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]205;206; GFX11-LABEL: test_setreg_ieee_mode_on:207; GFX11: ; %bb.0:208; GFX11-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 9, 1), 1 ; encoding: [0x41,0x02,0x80,0xb9,0x01,0x00,0x00,0x00]209; GFX11-NEXT: ;;#ASMSTART210; GFX11-NEXT: ;;#ASMEND211; GFX11-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]212 call void @llvm.amdgcn.s.setreg(i32 577, i32 1)213 call void asm sideeffect "", ""()214 ret void215}216 217define amdgpu_kernel void @test_setreg_dx10_clamp_off() {218; GFX6-LABEL: test_setreg_dx10_clamp_off:219; GFX6: ; %bb.0:220; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 8, 1), 0 ; encoding: [0x01,0x02,0x80,0xba,0x00,0x00,0x00,0x00]221; GFX6-NEXT: ;;#ASMSTART222; GFX6-NEXT: ;;#ASMEND223; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]224;225; GFX789-LABEL: test_setreg_dx10_clamp_off:226; GFX789: ; %bb.0:227; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 8, 1), 0 ; encoding: [0x01,0x02,0x00,0xba,0x00,0x00,0x00,0x00]228; GFX789-NEXT: ;;#ASMSTART229; GFX789-NEXT: ;;#ASMEND230; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]231;232; GFX10-LABEL: test_setreg_dx10_clamp_off:233; GFX10: ; %bb.0:234; GFX10-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 8, 1), 0 ; encoding: [0x01,0x02,0x80,0xba,0x00,0x00,0x00,0x00]235; GFX10-NEXT: ;;#ASMSTART236; GFX10-NEXT: ;;#ASMEND237; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]238;239; GFX11-LABEL: test_setreg_dx10_clamp_off:240; GFX11: ; %bb.0:241; GFX11-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 8, 1), 0 ; encoding: [0x01,0x02,0x80,0xb9,0x00,0x00,0x00,0x00]242; GFX11-NEXT: ;;#ASMSTART243; GFX11-NEXT: ;;#ASMEND244; GFX11-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]245 call void @llvm.amdgcn.s.setreg(i32 513, i32 0)246 call void asm sideeffect "", ""()247 ret void248}249 250define amdgpu_kernel void @test_setreg_dx10_clamp_on() {251; GFX6-LABEL: test_setreg_dx10_clamp_on:252; GFX6: ; %bb.0:253; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 8, 1), 1 ; encoding: [0x01,0x02,0x80,0xba,0x01,0x00,0x00,0x00]254; GFX6-NEXT: ;;#ASMSTART255; GFX6-NEXT: ;;#ASMEND256; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]257;258; GFX789-LABEL: test_setreg_dx10_clamp_on:259; GFX789: ; %bb.0:260; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 8, 1), 1 ; encoding: [0x01,0x02,0x00,0xba,0x01,0x00,0x00,0x00]261; GFX789-NEXT: ;;#ASMSTART262; GFX789-NEXT: ;;#ASMEND263; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]264;265; GFX10-LABEL: test_setreg_dx10_clamp_on:266; GFX10: ; %bb.0:267; GFX10-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 8, 1), 1 ; encoding: [0x01,0x02,0x80,0xba,0x01,0x00,0x00,0x00]268; GFX10-NEXT: ;;#ASMSTART269; GFX10-NEXT: ;;#ASMEND270; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]271;272; GFX11-LABEL: test_setreg_dx10_clamp_on:273; GFX11: ; %bb.0:274; GFX11-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 8, 1), 1 ; encoding: [0x01,0x02,0x80,0xb9,0x01,0x00,0x00,0x00]275; GFX11-NEXT: ;;#ASMSTART276; GFX11-NEXT: ;;#ASMEND277; GFX11-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]278 call void @llvm.amdgcn.s.setreg(i32 513, i32 1)279 call void asm sideeffect "", ""()280 ret void281}282 283; Sets full width of fp round and fp denorm fields, to a variable284define amdgpu_cs void @test_setreg_full_both_round_mode_and_denorm_mode(i32 inreg %mode) {285; GFX6-LABEL: test_setreg_full_both_round_mode_and_denorm_mode:286; GFX6: ; %bb.0:287; GFX6-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 8), s0 ; encoding: [0x01,0x38,0x80,0xb9]288; GFX6-NEXT: ;;#ASMSTART289; GFX6-NEXT: ;;#ASMEND290; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]291;292; GFX789-LABEL: test_setreg_full_both_round_mode_and_denorm_mode:293; GFX789: ; %bb.0:294; GFX789-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 8), s0 ; encoding: [0x01,0x38,0x00,0xb9]295; GFX789-NEXT: ;;#ASMSTART296; GFX789-NEXT: ;;#ASMEND297; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]298;299; GFX10-LABEL: test_setreg_full_both_round_mode_and_denorm_mode:300; GFX10: ; %bb.0:301; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 8), s0 ; encoding: [0x01,0x38,0x80,0xb9]302; GFX10-NEXT: ;;#ASMSTART303; GFX10-NEXT: ;;#ASMEND304; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]305;306; GFX11-LABEL: test_setreg_full_both_round_mode_and_denorm_mode:307; GFX11: ; %bb.0:308; GFX11-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 8), s0 ; encoding: [0x01,0x38,0x00,0xb9]309; GFX11-NEXT: ;;#ASMSTART310; GFX11-NEXT: ;;#ASMEND311; GFX11-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]312 call void @llvm.amdgcn.s.setreg(i32 14337, i32 inreg %mode)313 call void asm sideeffect "", ""()314 ret void315}316 317; Does not cover last bit of denorm field318define amdgpu_cs void @test_setreg_most_both_round_mode_and_denorm_mode() {319; GFX6-LABEL: test_setreg_most_both_round_mode_and_denorm_mode:320; GFX6: ; %bb.0:321; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 7), 6 ; encoding: [0x01,0x30,0x80,0xba,0x06,0x00,0x00,0x00]322; GFX6-NEXT: ;;#ASMSTART323; GFX6-NEXT: ;;#ASMEND324; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]325;326; GFX789-LABEL: test_setreg_most_both_round_mode_and_denorm_mode:327; GFX789: ; %bb.0:328; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 7), 6 ; encoding: [0x01,0x30,0x00,0xba,0x06,0x00,0x00,0x00]329; GFX789-NEXT: ;;#ASMSTART330; GFX789-NEXT: ;;#ASMEND331; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]332;333; GFX10-LABEL: test_setreg_most_both_round_mode_and_denorm_mode:334; GFX10: ; %bb.0:335; GFX10-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 7), 6 ; encoding: [0x01,0x30,0x80,0xba,0x06,0x00,0x00,0x00]336; GFX10-NEXT: ;;#ASMSTART337; GFX10-NEXT: ;;#ASMEND338; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]339;340; GFX11-LABEL: test_setreg_most_both_round_mode_and_denorm_mode:341; GFX11: ; %bb.0:342; GFX11-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 7), 6 ; encoding: [0x01,0x30,0x80,0xb9,0x06,0x00,0x00,0x00]343; GFX11-NEXT: ;;#ASMSTART344; GFX11-NEXT: ;;#ASMEND345; GFX11-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]346 call void @llvm.amdgcn.s.setreg(i32 12289, i32 6)347 call void asm sideeffect "", ""()348 ret void349}350 351; Does not cover first bit of denorm field352define amdgpu_cs void @test_setreg_most_both_round_mode_and_denorm_mode_6() {353; GFX6-LABEL: test_setreg_most_both_round_mode_and_denorm_mode_6:354; GFX6: ; %bb.0:355; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 1, 3), 6 ; encoding: [0x41,0x10,0x80,0xba,0x06,0x00,0x00,0x00]356; GFX6-NEXT: ;;#ASMSTART357; GFX6-NEXT: ;;#ASMEND358; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]359;360; GFX789-LABEL: test_setreg_most_both_round_mode_and_denorm_mode_6:361; GFX789: ; %bb.0:362; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 1, 3), 6 ; encoding: [0x41,0x10,0x00,0xba,0x06,0x00,0x00,0x00]363; GFX789-NEXT: ;;#ASMSTART364; GFX789-NEXT: ;;#ASMEND365; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]366;367; GFX10-LABEL: test_setreg_most_both_round_mode_and_denorm_mode_6:368; GFX10: ; %bb.0:369; GFX10-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 1, 3), 6 ; encoding: [0x41,0x10,0x80,0xba,0x06,0x00,0x00,0x00]370; GFX10-NEXT: ;;#ASMSTART371; GFX10-NEXT: ;;#ASMEND372; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]373;374; GFX11-LABEL: test_setreg_most_both_round_mode_and_denorm_mode_6:375; GFX11: ; %bb.0:376; GFX11-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 1, 3), 6 ; encoding: [0x41,0x10,0x80,0xb9,0x06,0x00,0x00,0x00]377; GFX11-NEXT: ;;#ASMSTART378; GFX11-NEXT: ;;#ASMEND379; GFX11-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]380 call void @llvm.amdgcn.s.setreg(i32 4161, i32 6)381 call void asm sideeffect "", ""()382 ret void383}384 385define amdgpu_cs void @test_setreg_f32_denorm_mode(i32 inreg %val) {386; GFX6-LABEL: test_setreg_f32_denorm_mode:387; GFX6: ; %bb.0:388; GFX6-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s0 ; encoding: [0x01,0x09,0x80,0xb9]389; GFX6-NEXT: ;;#ASMSTART390; GFX6-NEXT: ;;#ASMEND391; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]392;393; GFX789-LABEL: test_setreg_f32_denorm_mode:394; GFX789: ; %bb.0:395; GFX789-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s0 ; encoding: [0x01,0x09,0x00,0xb9]396; GFX789-NEXT: ;;#ASMSTART397; GFX789-NEXT: ;;#ASMEND398; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]399;400; GFX10-LABEL: test_setreg_f32_denorm_mode:401; GFX10: ; %bb.0:402; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s0 ; encoding: [0x01,0x09,0x80,0xb9]403; GFX10-NEXT: ;;#ASMSTART404; GFX10-NEXT: ;;#ASMEND405; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]406;407; GFX11-LABEL: test_setreg_f32_denorm_mode:408; GFX11: ; %bb.0:409; GFX11-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s0 ; encoding: [0x01,0x09,0x00,0xb9]410; GFX11-NEXT: ;;#ASMSTART411; GFX11-NEXT: ;;#ASMEND412; GFX11-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]413 call void @llvm.amdgcn.s.setreg(i32 2305, i32 %val)414 call void asm sideeffect "", ""()415 ret void416}417 418define amdgpu_cs void @test_setreg_f64_denorm_mode(i32 inreg %val) {419; GFX6-LABEL: test_setreg_f64_denorm_mode:420; GFX6: ; %bb.0:421; GFX6-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 6, 2), s0 ; encoding: [0x81,0x09,0x80,0xb9]422; GFX6-NEXT: ;;#ASMSTART423; GFX6-NEXT: ;;#ASMEND424; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]425;426; GFX789-LABEL: test_setreg_f64_denorm_mode:427; GFX789: ; %bb.0:428; GFX789-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 6, 2), s0 ; encoding: [0x81,0x09,0x00,0xb9]429; GFX789-NEXT: ;;#ASMSTART430; GFX789-NEXT: ;;#ASMEND431; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]432;433; GFX10-LABEL: test_setreg_f64_denorm_mode:434; GFX10: ; %bb.0:435; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 6, 2), s0 ; encoding: [0x81,0x09,0x80,0xb9]436; GFX10-NEXT: ;;#ASMSTART437; GFX10-NEXT: ;;#ASMEND438; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]439;440; GFX11-LABEL: test_setreg_f64_denorm_mode:441; GFX11: ; %bb.0:442; GFX11-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 6, 2), s0 ; encoding: [0x81,0x09,0x00,0xb9]443; GFX11-NEXT: ;;#ASMSTART444; GFX11-NEXT: ;;#ASMEND445; GFX11-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]446 call void @llvm.amdgcn.s.setreg(i32 2433, i32 %val)447 call void asm sideeffect "", ""()448 ret void449}450 451define amdgpu_cs void @test_setreg_full_denorm_mode(i32 inreg %val) {452; GFX6-LABEL: test_setreg_full_denorm_mode:453; GFX6: ; %bb.0:454; GFX6-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s0 ; encoding: [0x01,0x18,0x80,0xb9]455; GFX6-NEXT: ;;#ASMSTART456; GFX6-NEXT: ;;#ASMEND457; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]458;459; GFX789-LABEL: test_setreg_full_denorm_mode:460; GFX789: ; %bb.0:461; GFX789-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s0 ; encoding: [0x01,0x18,0x00,0xb9]462; GFX789-NEXT: ;;#ASMSTART463; GFX789-NEXT: ;;#ASMEND464; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]465;466; GFX10-LABEL: test_setreg_full_denorm_mode:467; GFX10: ; %bb.0:468; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s0 ; encoding: [0x01,0x18,0x80,0xb9]469; GFX10-NEXT: ;;#ASMSTART470; GFX10-NEXT: ;;#ASMEND471; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]472;473; GFX11-LABEL: test_setreg_full_denorm_mode:474; GFX11: ; %bb.0:475; GFX11-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s0 ; encoding: [0x01,0x18,0x00,0xb9]476; GFX11-NEXT: ;;#ASMSTART477; GFX11-NEXT: ;;#ASMEND478; GFX11-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]479 call void @llvm.amdgcn.s.setreg(i32 6145, i32 %val)480 call void asm sideeffect "", ""()481 ret void482}483 484define amdgpu_kernel void @test_setreg_full_round_mode_0() {485; GFX6-LABEL: test_setreg_full_round_mode_0:486; GFX6: ; %bb.0:487; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 0 ; encoding: [0x01,0x18,0x80,0xba,0x00,0x00,0x00,0x00]488; GFX6-NEXT: ;;#ASMSTART489; GFX6-NEXT: ;;#ASMEND490; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]491;492; GFX789-LABEL: test_setreg_full_round_mode_0:493; GFX789: ; %bb.0:494; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 0 ; encoding: [0x01,0x18,0x00,0xba,0x00,0x00,0x00,0x00]495; GFX789-NEXT: ;;#ASMSTART496; GFX789-NEXT: ;;#ASMEND497; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]498;499; GFX10-LABEL: test_setreg_full_round_mode_0:500; GFX10: ; %bb.0:501; GFX10-NEXT: s_round_mode 0x0 ; encoding: [0x00,0x00,0xa4,0xbf]502; GFX10-NEXT: ;;#ASMSTART503; GFX10-NEXT: ;;#ASMEND504; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]505;506; GFX11-LABEL: test_setreg_full_round_mode_0:507; GFX11: ; %bb.0:508; GFX11-NEXT: s_round_mode 0x0 ; encoding: [0x00,0x00,0x91,0xbf]509; GFX11-NEXT: ;;#ASMSTART510; GFX11-NEXT: ;;#ASMEND511; GFX11-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]512 call void @llvm.amdgcn.s.setreg(i32 6145, i32 0)513 call void asm sideeffect "", ""()514 ret void515}516 517define amdgpu_kernel void @test_setreg_full_round_mode_1() {518; GFX6-LABEL: test_setreg_full_round_mode_1:519; GFX6: ; %bb.0:520; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 1 ; encoding: [0x01,0x18,0x80,0xba,0x01,0x00,0x00,0x00]521; GFX6-NEXT: ;;#ASMSTART522; GFX6-NEXT: ;;#ASMEND523; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]524;525; GFX789-LABEL: test_setreg_full_round_mode_1:526; GFX789: ; %bb.0:527; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 1 ; encoding: [0x01,0x18,0x00,0xba,0x01,0x00,0x00,0x00]528; GFX789-NEXT: ;;#ASMSTART529; GFX789-NEXT: ;;#ASMEND530; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]531;532; GFX10-LABEL: test_setreg_full_round_mode_1:533; GFX10: ; %bb.0:534; GFX10-NEXT: s_round_mode 0x1 ; encoding: [0x01,0x00,0xa4,0xbf]535; GFX10-NEXT: ;;#ASMSTART536; GFX10-NEXT: ;;#ASMEND537; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]538;539; GFX11-LABEL: test_setreg_full_round_mode_1:540; GFX11: ; %bb.0:541; GFX11-NEXT: s_round_mode 0x1 ; encoding: [0x01,0x00,0x91,0xbf]542; GFX11-NEXT: ;;#ASMSTART543; GFX11-NEXT: ;;#ASMEND544; GFX11-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]545 call void @llvm.amdgcn.s.setreg(i32 6145, i32 1)546 call void asm sideeffect "", ""()547 ret void548}549 550define amdgpu_kernel void @test_setreg_full_round_mode_2() {551; GFX6-LABEL: test_setreg_full_round_mode_2:552; GFX6: ; %bb.0:553; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 2 ; encoding: [0x01,0x18,0x80,0xba,0x02,0x00,0x00,0x00]554; GFX6-NEXT: ;;#ASMSTART555; GFX6-NEXT: ;;#ASMEND556; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]557;558; GFX789-LABEL: test_setreg_full_round_mode_2:559; GFX789: ; %bb.0:560; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 2 ; encoding: [0x01,0x18,0x00,0xba,0x02,0x00,0x00,0x00]561; GFX789-NEXT: ;;#ASMSTART562; GFX789-NEXT: ;;#ASMEND563; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]564;565; GFX10-LABEL: test_setreg_full_round_mode_2:566; GFX10: ; %bb.0:567; GFX10-NEXT: s_round_mode 0x2 ; encoding: [0x02,0x00,0xa4,0xbf]568; GFX10-NEXT: ;;#ASMSTART569; GFX10-NEXT: ;;#ASMEND570; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]571;572; GFX11-LABEL: test_setreg_full_round_mode_2:573; GFX11: ; %bb.0:574; GFX11-NEXT: s_round_mode 0x2 ; encoding: [0x02,0x00,0x91,0xbf]575; GFX11-NEXT: ;;#ASMSTART576; GFX11-NEXT: ;;#ASMEND577; GFX11-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]578 call void @llvm.amdgcn.s.setreg(i32 6145, i32 2)579 call void asm sideeffect "", ""()580 ret void581}582 583define amdgpu_kernel void @test_setreg_full_round_mode_4() {584; GFX6-LABEL: test_setreg_full_round_mode_4:585; GFX6: ; %bb.0:586; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 4 ; encoding: [0x01,0x18,0x80,0xba,0x04,0x00,0x00,0x00]587; GFX6-NEXT: ;;#ASMSTART588; GFX6-NEXT: ;;#ASMEND589; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]590;591; GFX789-LABEL: test_setreg_full_round_mode_4:592; GFX789: ; %bb.0:593; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 4 ; encoding: [0x01,0x18,0x00,0xba,0x04,0x00,0x00,0x00]594; GFX789-NEXT: ;;#ASMSTART595; GFX789-NEXT: ;;#ASMEND596; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]597;598; GFX10-LABEL: test_setreg_full_round_mode_4:599; GFX10: ; %bb.0:600; GFX10-NEXT: s_round_mode 0x4 ; encoding: [0x04,0x00,0xa4,0xbf]601; GFX10-NEXT: ;;#ASMSTART602; GFX10-NEXT: ;;#ASMEND603; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]604;605; GFX11-LABEL: test_setreg_full_round_mode_4:606; GFX11: ; %bb.0:607; GFX11-NEXT: s_round_mode 0x4 ; encoding: [0x04,0x00,0x91,0xbf]608; GFX11-NEXT: ;;#ASMSTART609; GFX11-NEXT: ;;#ASMEND610; GFX11-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]611 call void @llvm.amdgcn.s.setreg(i32 6145, i32 4)612 call void asm sideeffect "", ""()613 ret void614}615 616define amdgpu_kernel void @test_setreg_full_round_mode_8() {617; GFX6-LABEL: test_setreg_full_round_mode_8:618; GFX6: ; %bb.0:619; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 8 ; encoding: [0x01,0x18,0x80,0xba,0x08,0x00,0x00,0x00]620; GFX6-NEXT: ;;#ASMSTART621; GFX6-NEXT: ;;#ASMEND622; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]623;624; GFX789-LABEL: test_setreg_full_round_mode_8:625; GFX789: ; %bb.0:626; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 8 ; encoding: [0x01,0x18,0x00,0xba,0x08,0x00,0x00,0x00]627; GFX789-NEXT: ;;#ASMSTART628; GFX789-NEXT: ;;#ASMEND629; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]630;631; GFX10-LABEL: test_setreg_full_round_mode_8:632; GFX10: ; %bb.0:633; GFX10-NEXT: s_round_mode 0x8 ; encoding: [0x08,0x00,0xa4,0xbf]634; GFX10-NEXT: ;;#ASMSTART635; GFX10-NEXT: ;;#ASMEND636; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]637;638; GFX11-LABEL: test_setreg_full_round_mode_8:639; GFX11: ; %bb.0:640; GFX11-NEXT: s_round_mode 0x8 ; encoding: [0x08,0x00,0x91,0xbf]641; GFX11-NEXT: ;;#ASMSTART642; GFX11-NEXT: ;;#ASMEND643; GFX11-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]644 call void @llvm.amdgcn.s.setreg(i32 6145, i32 8)645 call void asm sideeffect "", ""()646 ret void647}648 649define amdgpu_kernel void @test_setreg_full_round_mode_15() {650; GFX6-LABEL: test_setreg_full_round_mode_15:651; GFX6: ; %bb.0:652; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 15 ; encoding: [0x01,0x18,0x80,0xba,0x0f,0x00,0x00,0x00]653; GFX6-NEXT: ;;#ASMSTART654; GFX6-NEXT: ;;#ASMEND655; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]656;657; GFX789-LABEL: test_setreg_full_round_mode_15:658; GFX789: ; %bb.0:659; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 15 ; encoding: [0x01,0x18,0x00,0xba,0x0f,0x00,0x00,0x00]660; GFX789-NEXT: ;;#ASMSTART661; GFX789-NEXT: ;;#ASMEND662; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]663;664; GFX10-LABEL: test_setreg_full_round_mode_15:665; GFX10: ; %bb.0:666; GFX10-NEXT: s_round_mode 0xf ; encoding: [0x0f,0x00,0xa4,0xbf]667; GFX10-NEXT: ;;#ASMSTART668; GFX10-NEXT: ;;#ASMEND669; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]670;671; GFX11-LABEL: test_setreg_full_round_mode_15:672; GFX11: ; %bb.0:673; GFX11-NEXT: s_round_mode 0xf ; encoding: [0x0f,0x00,0x91,0xbf]674; GFX11-NEXT: ;;#ASMSTART675; GFX11-NEXT: ;;#ASMEND676; GFX11-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]677 call void @llvm.amdgcn.s.setreg(i32 6145, i32 15)678 call void asm sideeffect "", ""()679 ret void680}681 682; Should truncate set immediate value683define amdgpu_kernel void @test_setreg_full_round_mode_42() {684; GFX6-LABEL: test_setreg_full_round_mode_42:685; GFX6: ; %bb.0:686; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 42 ; encoding: [0x01,0x18,0x80,0xba,0x2a,0x00,0x00,0x00]687; GFX6-NEXT: ;;#ASMSTART688; GFX6-NEXT: ;;#ASMEND689; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]690;691; GFX789-LABEL: test_setreg_full_round_mode_42:692; GFX789: ; %bb.0:693; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 42 ; encoding: [0x01,0x18,0x00,0xba,0x2a,0x00,0x00,0x00]694; GFX789-NEXT: ;;#ASMSTART695; GFX789-NEXT: ;;#ASMEND696; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]697;698; GFX10-LABEL: test_setreg_full_round_mode_42:699; GFX10: ; %bb.0:700; GFX10-NEXT: s_round_mode 0xa ; encoding: [0x0a,0x00,0xa4,0xbf]701; GFX10-NEXT: ;;#ASMSTART702; GFX10-NEXT: ;;#ASMEND703; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]704;705; GFX11-LABEL: test_setreg_full_round_mode_42:706; GFX11: ; %bb.0:707; GFX11-NEXT: s_round_mode 0xa ; encoding: [0x0a,0x00,0x91,0xbf]708; GFX11-NEXT: ;;#ASMSTART709; GFX11-NEXT: ;;#ASMEND710; GFX11-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]711 call void @llvm.amdgcn.s.setreg(i32 6145, i32 42)712 call void asm sideeffect "", ""()713 ret void714}715 716define amdgpu_kernel void @test_setreg_full_denorm_mode_0() {717; GFX6-LABEL: test_setreg_full_denorm_mode_0:718; GFX6: ; %bb.0:719; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 4), 0 ; encoding: [0x01,0x19,0x80,0xba,0x00,0x00,0x00,0x00]720; GFX6-NEXT: ;;#ASMSTART721; GFX6-NEXT: ;;#ASMEND722; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]723;724; GFX789-LABEL: test_setreg_full_denorm_mode_0:725; GFX789: ; %bb.0:726; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 4), 0 ; encoding: [0x01,0x19,0x00,0xba,0x00,0x00,0x00,0x00]727; GFX789-NEXT: ;;#ASMSTART728; GFX789-NEXT: ;;#ASMEND729; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]730;731; GFX10-LABEL: test_setreg_full_denorm_mode_0:732; GFX10: ; %bb.0:733; GFX10-NEXT: s_denorm_mode 0 ; encoding: [0x00,0x00,0xa5,0xbf]734; GFX10-NEXT: ;;#ASMSTART735; GFX10-NEXT: ;;#ASMEND736; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]737;738; GFX11-LABEL: test_setreg_full_denorm_mode_0:739; GFX11: ; %bb.0:740; GFX11-NEXT: s_denorm_mode 0 ; encoding: [0x00,0x00,0x92,0xbf]741; GFX11-NEXT: ;;#ASMSTART742; GFX11-NEXT: ;;#ASMEND743; GFX11-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]744 call void @llvm.amdgcn.s.setreg(i32 6401, i32 0)745 call void asm sideeffect "", ""()746 ret void747}748 749define amdgpu_kernel void @test_setreg_full_denorm_mode_1() {750; GFX6-LABEL: test_setreg_full_denorm_mode_1:751; GFX6: ; %bb.0:752; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 4), 1 ; encoding: [0x01,0x19,0x80,0xba,0x01,0x00,0x00,0x00]753; GFX6-NEXT: ;;#ASMSTART754; GFX6-NEXT: ;;#ASMEND755; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]756;757; GFX789-LABEL: test_setreg_full_denorm_mode_1:758; GFX789: ; %bb.0:759; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 4), 1 ; encoding: [0x01,0x19,0x00,0xba,0x01,0x00,0x00,0x00]760; GFX789-NEXT: ;;#ASMSTART761; GFX789-NEXT: ;;#ASMEND762; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]763;764; GFX10-LABEL: test_setreg_full_denorm_mode_1:765; GFX10: ; %bb.0:766; GFX10-NEXT: s_denorm_mode 1 ; encoding: [0x01,0x00,0xa5,0xbf]767; GFX10-NEXT: ;;#ASMSTART768; GFX10-NEXT: ;;#ASMEND769; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]770;771; GFX11-LABEL: test_setreg_full_denorm_mode_1:772; GFX11: ; %bb.0:773; GFX11-NEXT: s_denorm_mode 1 ; encoding: [0x01,0x00,0x92,0xbf]774; GFX11-NEXT: ;;#ASMSTART775; GFX11-NEXT: ;;#ASMEND776; GFX11-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]777 call void @llvm.amdgcn.s.setreg(i32 6401, i32 1)778 call void asm sideeffect "", ""()779 ret void780}781 782 783define amdgpu_kernel void @test_setreg_full_denorm_mode_2() {784; GFX6-LABEL: test_setreg_full_denorm_mode_2:785; GFX6: ; %bb.0:786; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 4), 2 ; encoding: [0x01,0x19,0x80,0xba,0x02,0x00,0x00,0x00]787; GFX6-NEXT: ;;#ASMSTART788; GFX6-NEXT: ;;#ASMEND789; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]790;791; GFX789-LABEL: test_setreg_full_denorm_mode_2:792; GFX789: ; %bb.0:793; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 4), 2 ; encoding: [0x01,0x19,0x00,0xba,0x02,0x00,0x00,0x00]794; GFX789-NEXT: ;;#ASMSTART795; GFX789-NEXT: ;;#ASMEND796; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]797;798; GFX10-LABEL: test_setreg_full_denorm_mode_2:799; GFX10: ; %bb.0:800; GFX10-NEXT: s_denorm_mode 2 ; encoding: [0x02,0x00,0xa5,0xbf]801; GFX10-NEXT: ;;#ASMSTART802; GFX10-NEXT: ;;#ASMEND803; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]804;805; GFX11-LABEL: test_setreg_full_denorm_mode_2:806; GFX11: ; %bb.0:807; GFX11-NEXT: s_denorm_mode 2 ; encoding: [0x02,0x00,0x92,0xbf]808; GFX11-NEXT: ;;#ASMSTART809; GFX11-NEXT: ;;#ASMEND810; GFX11-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]811 call void @llvm.amdgcn.s.setreg(i32 6401, i32 2)812 call void asm sideeffect "", ""()813 ret void814}815 816define amdgpu_kernel void @test_setreg_full_denorm_mode_4() {817; GFX6-LABEL: test_setreg_full_denorm_mode_4:818; GFX6: ; %bb.0:819; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 4), 4 ; encoding: [0x01,0x19,0x80,0xba,0x04,0x00,0x00,0x00]820; GFX6-NEXT: ;;#ASMSTART821; GFX6-NEXT: ;;#ASMEND822; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]823;824; GFX789-LABEL: test_setreg_full_denorm_mode_4:825; GFX789: ; %bb.0:826; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 4), 4 ; encoding: [0x01,0x19,0x00,0xba,0x04,0x00,0x00,0x00]827; GFX789-NEXT: ;;#ASMSTART828; GFX789-NEXT: ;;#ASMEND829; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]830;831; GFX10-LABEL: test_setreg_full_denorm_mode_4:832; GFX10: ; %bb.0:833; GFX10-NEXT: s_denorm_mode 4 ; encoding: [0x04,0x00,0xa5,0xbf]834; GFX10-NEXT: ;;#ASMSTART835; GFX10-NEXT: ;;#ASMEND836; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]837;838; GFX11-LABEL: test_setreg_full_denorm_mode_4:839; GFX11: ; %bb.0:840; GFX11-NEXT: s_denorm_mode 4 ; encoding: [0x04,0x00,0x92,0xbf]841; GFX11-NEXT: ;;#ASMSTART842; GFX11-NEXT: ;;#ASMEND843; GFX11-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]844 call void @llvm.amdgcn.s.setreg(i32 6401, i32 4)845 call void asm sideeffect "", ""()846 ret void847}848 849define amdgpu_kernel void @test_setreg_full_denorm_mode_8() {850; GFX6-LABEL: test_setreg_full_denorm_mode_8:851; GFX6: ; %bb.0:852; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 4), 8 ; encoding: [0x01,0x19,0x80,0xba,0x08,0x00,0x00,0x00]853; GFX6-NEXT: ;;#ASMSTART854; GFX6-NEXT: ;;#ASMEND855; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]856;857; GFX789-LABEL: test_setreg_full_denorm_mode_8:858; GFX789: ; %bb.0:859; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 4), 8 ; encoding: [0x01,0x19,0x00,0xba,0x08,0x00,0x00,0x00]860; GFX789-NEXT: ;;#ASMSTART861; GFX789-NEXT: ;;#ASMEND862; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]863;864; GFX10-LABEL: test_setreg_full_denorm_mode_8:865; GFX10: ; %bb.0:866; GFX10-NEXT: s_denorm_mode 8 ; encoding: [0x08,0x00,0xa5,0xbf]867; GFX10-NEXT: ;;#ASMSTART868; GFX10-NEXT: ;;#ASMEND869; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]870;871; GFX11-LABEL: test_setreg_full_denorm_mode_8:872; GFX11: ; %bb.0:873; GFX11-NEXT: s_denorm_mode 8 ; encoding: [0x08,0x00,0x92,0xbf]874; GFX11-NEXT: ;;#ASMSTART875; GFX11-NEXT: ;;#ASMEND876; GFX11-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]877 call void @llvm.amdgcn.s.setreg(i32 6401, i32 8)878 call void asm sideeffect "", ""()879 ret void880}881 882define amdgpu_kernel void @test_setreg_full_denorm_mode_15() {883; GFX6-LABEL: test_setreg_full_denorm_mode_15:884; GFX6: ; %bb.0:885; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 4), 15 ; encoding: [0x01,0x19,0x80,0xba,0x0f,0x00,0x00,0x00]886; GFX6-NEXT: ;;#ASMSTART887; GFX6-NEXT: ;;#ASMEND888; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]889;890; GFX789-LABEL: test_setreg_full_denorm_mode_15:891; GFX789: ; %bb.0:892; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 4), 15 ; encoding: [0x01,0x19,0x00,0xba,0x0f,0x00,0x00,0x00]893; GFX789-NEXT: ;;#ASMSTART894; GFX789-NEXT: ;;#ASMEND895; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]896;897; GFX10-LABEL: test_setreg_full_denorm_mode_15:898; GFX10: ; %bb.0:899; GFX10-NEXT: s_denorm_mode 15 ; encoding: [0x0f,0x00,0xa5,0xbf]900; GFX10-NEXT: ;;#ASMSTART901; GFX10-NEXT: ;;#ASMEND902; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]903;904; GFX11-LABEL: test_setreg_full_denorm_mode_15:905; GFX11: ; %bb.0:906; GFX11-NEXT: s_denorm_mode 15 ; encoding: [0x0f,0x00,0x92,0xbf]907; GFX11-NEXT: ;;#ASMSTART908; GFX11-NEXT: ;;#ASMEND909; GFX11-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]910 call void @llvm.amdgcn.s.setreg(i32 6401, i32 15)911 call void asm sideeffect "", ""()912 ret void913}914 915define amdgpu_kernel void @test_setreg_full_denorm_mode_42() {916; GFX6-LABEL: test_setreg_full_denorm_mode_42:917; GFX6: ; %bb.0:918; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 4), 42 ; encoding: [0x01,0x19,0x80,0xba,0x2a,0x00,0x00,0x00]919; GFX6-NEXT: ;;#ASMSTART920; GFX6-NEXT: ;;#ASMEND921; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]922;923; GFX789-LABEL: test_setreg_full_denorm_mode_42:924; GFX789: ; %bb.0:925; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 4), 42 ; encoding: [0x01,0x19,0x00,0xba,0x2a,0x00,0x00,0x00]926; GFX789-NEXT: ;;#ASMSTART927; GFX789-NEXT: ;;#ASMEND928; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]929;930; GFX10-LABEL: test_setreg_full_denorm_mode_42:931; GFX10: ; %bb.0:932; GFX10-NEXT: s_denorm_mode 10 ; encoding: [0x0a,0x00,0xa5,0xbf]933; GFX10-NEXT: ;;#ASMSTART934; GFX10-NEXT: ;;#ASMEND935; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]936;937; GFX11-LABEL: test_setreg_full_denorm_mode_42:938; GFX11: ; %bb.0:939; GFX11-NEXT: s_denorm_mode 10 ; encoding: [0x0a,0x00,0x92,0xbf]940; GFX11-NEXT: ;;#ASMSTART941; GFX11-NEXT: ;;#ASMEND942; GFX11-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]943 call void @llvm.amdgcn.s.setreg(i32 6401, i32 42)944 call void asm sideeffect "", ""()945 ret void946}947 948; Sets all fp round and fp denorm bits.949define amdgpu_kernel void @test_setreg_full_both_round_mode_and_denorm_mode_0() {950; GFX6-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_0:951; GFX6: ; %bb.0:952; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 0 ; encoding: [0x01,0x38,0x80,0xba,0x00,0x00,0x00,0x00]953; GFX6-NEXT: ;;#ASMSTART954; GFX6-NEXT: ;;#ASMEND955; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]956;957; GFX789-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_0:958; GFX789: ; %bb.0:959; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 0 ; encoding: [0x01,0x38,0x00,0xba,0x00,0x00,0x00,0x00]960; GFX789-NEXT: ;;#ASMSTART961; GFX789-NEXT: ;;#ASMEND962; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]963;964; GFX10-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_0:965; GFX10: ; %bb.0:966; GFX10-NEXT: s_round_mode 0x0 ; encoding: [0x00,0x00,0xa4,0xbf]967; GFX10-NEXT: ;;#ASMSTART968; GFX10-NEXT: ;;#ASMEND969; GFX10-NEXT: s_denorm_mode 0 ; encoding: [0x00,0x00,0xa5,0xbf]970; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]971;972; GFX11-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_0:973; GFX11: ; %bb.0:974; GFX11-NEXT: s_round_mode 0x0 ; encoding: [0x00,0x00,0x91,0xbf]975; GFX11-NEXT: ;;#ASMSTART976; GFX11-NEXT: ;;#ASMEND977; GFX11-NEXT: s_denorm_mode 0 ; encoding: [0x00,0x00,0x92,0xbf]978; GFX11-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]979 call void @llvm.amdgcn.s.setreg(i32 14337, i32 0)980 call void asm sideeffect "", ""()981 ret void982}983 984define amdgpu_kernel void @test_setreg_full_both_round_mode_and_denorm_mode_1() {985; GFX6-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_1:986; GFX6: ; %bb.0:987; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 1 ; encoding: [0x01,0x38,0x80,0xba,0x01,0x00,0x00,0x00]988; GFX6-NEXT: ;;#ASMSTART989; GFX6-NEXT: ;;#ASMEND990; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]991;992; GFX789-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_1:993; GFX789: ; %bb.0:994; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 1 ; encoding: [0x01,0x38,0x00,0xba,0x01,0x00,0x00,0x00]995; GFX789-NEXT: ;;#ASMSTART996; GFX789-NEXT: ;;#ASMEND997; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]998;999; GFX10-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_1:1000; GFX10: ; %bb.0:1001; GFX10-NEXT: s_round_mode 0x1 ; encoding: [0x01,0x00,0xa4,0xbf]1002; GFX10-NEXT: ;;#ASMSTART1003; GFX10-NEXT: ;;#ASMEND1004; GFX10-NEXT: s_denorm_mode 0 ; encoding: [0x00,0x00,0xa5,0xbf]1005; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]1006;1007; GFX11-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_1:1008; GFX11: ; %bb.0:1009; GFX11-NEXT: s_round_mode 0x1 ; encoding: [0x01,0x00,0x91,0xbf]1010; GFX11-NEXT: ;;#ASMSTART1011; GFX11-NEXT: ;;#ASMEND1012; GFX11-NEXT: s_denorm_mode 0 ; encoding: [0x00,0x00,0x92,0xbf]1013; GFX11-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]1014 call void @llvm.amdgcn.s.setreg(i32 14337, i32 1)1015 call void asm sideeffect "", ""()1016 ret void1017}1018 1019define amdgpu_kernel void @test_setreg_full_both_round_mode_and_denorm_mode_2() {1020; GFX6-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_2:1021; GFX6: ; %bb.0:1022; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 2 ; encoding: [0x01,0x38,0x80,0xba,0x02,0x00,0x00,0x00]1023; GFX6-NEXT: ;;#ASMSTART1024; GFX6-NEXT: ;;#ASMEND1025; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]1026;1027; GFX789-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_2:1028; GFX789: ; %bb.0:1029; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 2 ; encoding: [0x01,0x38,0x00,0xba,0x02,0x00,0x00,0x00]1030; GFX789-NEXT: ;;#ASMSTART1031; GFX789-NEXT: ;;#ASMEND1032; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]1033;1034; GFX10-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_2:1035; GFX10: ; %bb.0:1036; GFX10-NEXT: s_round_mode 0x2 ; encoding: [0x02,0x00,0xa4,0xbf]1037; GFX10-NEXT: ;;#ASMSTART1038; GFX10-NEXT: ;;#ASMEND1039; GFX10-NEXT: s_denorm_mode 0 ; encoding: [0x00,0x00,0xa5,0xbf]1040; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]1041;1042; GFX11-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_2:1043; GFX11: ; %bb.0:1044; GFX11-NEXT: s_round_mode 0x2 ; encoding: [0x02,0x00,0x91,0xbf]1045; GFX11-NEXT: ;;#ASMSTART1046; GFX11-NEXT: ;;#ASMEND1047; GFX11-NEXT: s_denorm_mode 0 ; encoding: [0x00,0x00,0x92,0xbf]1048; GFX11-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]1049 call void @llvm.amdgcn.s.setreg(i32 14337, i32 2)1050 call void asm sideeffect "", ""()1051 ret void1052}1053 1054define amdgpu_kernel void @test_setreg_full_both_round_mode_and_denorm_mode_4() {1055; GFX6-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_4:1056; GFX6: ; %bb.0:1057; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 4 ; encoding: [0x01,0x38,0x80,0xba,0x04,0x00,0x00,0x00]1058; GFX6-NEXT: ;;#ASMSTART1059; GFX6-NEXT: ;;#ASMEND1060; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]1061;1062; GFX789-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_4:1063; GFX789: ; %bb.0:1064; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 4 ; encoding: [0x01,0x38,0x00,0xba,0x04,0x00,0x00,0x00]1065; GFX789-NEXT: ;;#ASMSTART1066; GFX789-NEXT: ;;#ASMEND1067; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]1068;1069; GFX10-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_4:1070; GFX10: ; %bb.0:1071; GFX10-NEXT: s_round_mode 0x4 ; encoding: [0x04,0x00,0xa4,0xbf]1072; GFX10-NEXT: ;;#ASMSTART1073; GFX10-NEXT: ;;#ASMEND1074; GFX10-NEXT: s_denorm_mode 0 ; encoding: [0x00,0x00,0xa5,0xbf]1075; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]1076;1077; GFX11-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_4:1078; GFX11: ; %bb.0:1079; GFX11-NEXT: s_round_mode 0x4 ; encoding: [0x04,0x00,0x91,0xbf]1080; GFX11-NEXT: ;;#ASMSTART1081; GFX11-NEXT: ;;#ASMEND1082; GFX11-NEXT: s_denorm_mode 0 ; encoding: [0x00,0x00,0x92,0xbf]1083; GFX11-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]1084 call void @llvm.amdgcn.s.setreg(i32 14337, i32 4)1085 call void asm sideeffect "", ""()1086 ret void1087}1088 1089define amdgpu_kernel void @test_setreg_full_both_round_mode_and_denorm_mode_8() {1090; GFX6-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_8:1091; GFX6: ; %bb.0:1092; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 8 ; encoding: [0x01,0x38,0x80,0xba,0x08,0x00,0x00,0x00]1093; GFX6-NEXT: ;;#ASMSTART1094; GFX6-NEXT: ;;#ASMEND1095; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]1096;1097; GFX789-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_8:1098; GFX789: ; %bb.0:1099; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 8 ; encoding: [0x01,0x38,0x00,0xba,0x08,0x00,0x00,0x00]1100; GFX789-NEXT: ;;#ASMSTART1101; GFX789-NEXT: ;;#ASMEND1102; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]1103;1104; GFX10-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_8:1105; GFX10: ; %bb.0:1106; GFX10-NEXT: s_round_mode 0x8 ; encoding: [0x08,0x00,0xa4,0xbf]1107; GFX10-NEXT: ;;#ASMSTART1108; GFX10-NEXT: ;;#ASMEND1109; GFX10-NEXT: s_denorm_mode 0 ; encoding: [0x00,0x00,0xa5,0xbf]1110; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]1111;1112; GFX11-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_8:1113; GFX11: ; %bb.0:1114; GFX11-NEXT: s_round_mode 0x8 ; encoding: [0x08,0x00,0x91,0xbf]1115; GFX11-NEXT: ;;#ASMSTART1116; GFX11-NEXT: ;;#ASMEND1117; GFX11-NEXT: s_denorm_mode 0 ; encoding: [0x00,0x00,0x92,0xbf]1118; GFX11-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]1119 call void @llvm.amdgcn.s.setreg(i32 14337, i32 8)1120 call void asm sideeffect "", ""()1121 ret void1122}1123 1124define amdgpu_kernel void @test_setreg_full_both_round_mode_and_denorm_mode_16() {1125; GFX6-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_16:1126; GFX6: ; %bb.0:1127; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 16 ; encoding: [0x01,0x38,0x80,0xba,0x10,0x00,0x00,0x00]1128; GFX6-NEXT: ;;#ASMSTART1129; GFX6-NEXT: ;;#ASMEND1130; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]1131;1132; GFX789-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_16:1133; GFX789: ; %bb.0:1134; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 16 ; encoding: [0x01,0x38,0x00,0xba,0x10,0x00,0x00,0x00]1135; GFX789-NEXT: ;;#ASMSTART1136; GFX789-NEXT: ;;#ASMEND1137; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]1138;1139; GFX10-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_16:1140; GFX10: ; %bb.0:1141; GFX10-NEXT: s_round_mode 0x0 ; encoding: [0x00,0x00,0xa4,0xbf]1142; GFX10-NEXT: ;;#ASMSTART1143; GFX10-NEXT: ;;#ASMEND1144; GFX10-NEXT: s_denorm_mode 1 ; encoding: [0x01,0x00,0xa5,0xbf]1145; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]1146;1147; GFX11-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_16:1148; GFX11: ; %bb.0:1149; GFX11-NEXT: s_round_mode 0x0 ; encoding: [0x00,0x00,0x91,0xbf]1150; GFX11-NEXT: ;;#ASMSTART1151; GFX11-NEXT: ;;#ASMEND1152; GFX11-NEXT: s_denorm_mode 1 ; encoding: [0x01,0x00,0x92,0xbf]1153; GFX11-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]1154 call void @llvm.amdgcn.s.setreg(i32 14337, i32 16)1155 call void asm sideeffect "", ""()1156 ret void1157}1158 1159define amdgpu_kernel void @test_setreg_full_both_round_mode_and_denorm_mode_32() {1160; GFX6-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_32:1161; GFX6: ; %bb.0:1162; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 32 ; encoding: [0x01,0x38,0x80,0xba,0x20,0x00,0x00,0x00]1163; GFX6-NEXT: ;;#ASMSTART1164; GFX6-NEXT: ;;#ASMEND1165; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]1166;1167; GFX789-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_32:1168; GFX789: ; %bb.0:1169; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 32 ; encoding: [0x01,0x38,0x00,0xba,0x20,0x00,0x00,0x00]1170; GFX789-NEXT: ;;#ASMSTART1171; GFX789-NEXT: ;;#ASMEND1172; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]1173;1174; GFX10-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_32:1175; GFX10: ; %bb.0:1176; GFX10-NEXT: s_round_mode 0x0 ; encoding: [0x00,0x00,0xa4,0xbf]1177; GFX10-NEXT: ;;#ASMSTART1178; GFX10-NEXT: ;;#ASMEND1179; GFX10-NEXT: s_denorm_mode 2 ; encoding: [0x02,0x00,0xa5,0xbf]1180; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]1181;1182; GFX11-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_32:1183; GFX11: ; %bb.0:1184; GFX11-NEXT: s_round_mode 0x0 ; encoding: [0x00,0x00,0x91,0xbf]1185; GFX11-NEXT: ;;#ASMSTART1186; GFX11-NEXT: ;;#ASMEND1187; GFX11-NEXT: s_denorm_mode 2 ; encoding: [0x02,0x00,0x92,0xbf]1188; GFX11-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]1189 call void @llvm.amdgcn.s.setreg(i32 14337, i32 32)1190 call void asm sideeffect "", ""()1191 ret void1192}1193 1194define amdgpu_kernel void @test_setreg_full_both_round_mode_and_denorm_mode_64() {1195; GFX6-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_64:1196; GFX6: ; %bb.0:1197; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 64 ; encoding: [0x01,0x38,0x80,0xba,0x40,0x00,0x00,0x00]1198; GFX6-NEXT: ;;#ASMSTART1199; GFX6-NEXT: ;;#ASMEND1200; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]1201;1202; GFX789-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_64:1203; GFX789: ; %bb.0:1204; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 64 ; encoding: [0x01,0x38,0x00,0xba,0x40,0x00,0x00,0x00]1205; GFX789-NEXT: ;;#ASMSTART1206; GFX789-NEXT: ;;#ASMEND1207; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]1208;1209; GFX10-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_64:1210; GFX10: ; %bb.0:1211; GFX10-NEXT: s_round_mode 0x0 ; encoding: [0x00,0x00,0xa4,0xbf]1212; GFX10-NEXT: ;;#ASMSTART1213; GFX10-NEXT: ;;#ASMEND1214; GFX10-NEXT: s_denorm_mode 4 ; encoding: [0x04,0x00,0xa5,0xbf]1215; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]1216;1217; GFX11-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_64:1218; GFX11: ; %bb.0:1219; GFX11-NEXT: s_round_mode 0x0 ; encoding: [0x00,0x00,0x91,0xbf]1220; GFX11-NEXT: ;;#ASMSTART1221; GFX11-NEXT: ;;#ASMEND1222; GFX11-NEXT: s_denorm_mode 4 ; encoding: [0x04,0x00,0x92,0xbf]1223; GFX11-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]1224 call void @llvm.amdgcn.s.setreg(i32 14337, i32 64)1225 call void asm sideeffect "", ""()1226 ret void1227}1228 1229define amdgpu_kernel void @test_setreg_full_both_round_mode_and_denorm_mode_128() {1230; GFX6-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_128:1231; GFX6: ; %bb.0:1232; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 0x80 ; encoding: [0x01,0x38,0x80,0xba,0x80,0x00,0x00,0x00]1233; GFX6-NEXT: ;;#ASMSTART1234; GFX6-NEXT: ;;#ASMEND1235; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]1236;1237; GFX789-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_128:1238; GFX789: ; %bb.0:1239; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 0x80 ; encoding: [0x01,0x38,0x00,0xba,0x80,0x00,0x00,0x00]1240; GFX789-NEXT: ;;#ASMSTART1241; GFX789-NEXT: ;;#ASMEND1242; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]1243;1244; GFX10-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_128:1245; GFX10: ; %bb.0:1246; GFX10-NEXT: s_round_mode 0x0 ; encoding: [0x00,0x00,0xa4,0xbf]1247; GFX10-NEXT: ;;#ASMSTART1248; GFX10-NEXT: ;;#ASMEND1249; GFX10-NEXT: s_denorm_mode 8 ; encoding: [0x08,0x00,0xa5,0xbf]1250; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]1251;1252; GFX11-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_128:1253; GFX11: ; %bb.0:1254; GFX11-NEXT: s_round_mode 0x0 ; encoding: [0x00,0x00,0x91,0xbf]1255; GFX11-NEXT: ;;#ASMSTART1256; GFX11-NEXT: ;;#ASMEND1257; GFX11-NEXT: s_denorm_mode 8 ; encoding: [0x08,0x00,0x92,0xbf]1258; GFX11-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]1259 call void @llvm.amdgcn.s.setreg(i32 14337, i32 128)1260 call void asm sideeffect "", ""()1261 ret void1262}1263 1264define amdgpu_kernel void @test_setreg_full_both_round_mode_and_denorm_mode_15() {1265; GFX6-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_15:1266; GFX6: ; %bb.0:1267; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 15 ; encoding: [0x01,0x38,0x80,0xba,0x0f,0x00,0x00,0x00]1268; GFX6-NEXT: ;;#ASMSTART1269; GFX6-NEXT: ;;#ASMEND1270; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]1271;1272; GFX789-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_15:1273; GFX789: ; %bb.0:1274; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 15 ; encoding: [0x01,0x38,0x00,0xba,0x0f,0x00,0x00,0x00]1275; GFX789-NEXT: ;;#ASMSTART1276; GFX789-NEXT: ;;#ASMEND1277; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]1278;1279; GFX10-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_15:1280; GFX10: ; %bb.0:1281; GFX10-NEXT: s_round_mode 0xf ; encoding: [0x0f,0x00,0xa4,0xbf]1282; GFX10-NEXT: ;;#ASMSTART1283; GFX10-NEXT: ;;#ASMEND1284; GFX10-NEXT: s_denorm_mode 0 ; encoding: [0x00,0x00,0xa5,0xbf]1285; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]1286;1287; GFX11-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_15:1288; GFX11: ; %bb.0:1289; GFX11-NEXT: s_round_mode 0xf ; encoding: [0x0f,0x00,0x91,0xbf]1290; GFX11-NEXT: ;;#ASMSTART1291; GFX11-NEXT: ;;#ASMEND1292; GFX11-NEXT: s_denorm_mode 0 ; encoding: [0x00,0x00,0x92,0xbf]1293; GFX11-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]1294 call void @llvm.amdgcn.s.setreg(i32 14337, i32 15)1295 call void asm sideeffect "", ""()1296 ret void1297}1298 1299define amdgpu_kernel void @test_setreg_full_both_round_mode_and_denorm_mode_255() {1300; GFX6-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_255:1301; GFX6: ; %bb.0:1302; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 0xff ; encoding: [0x01,0x38,0x80,0xba,0xff,0x00,0x00,0x00]1303; GFX6-NEXT: ;;#ASMSTART1304; GFX6-NEXT: ;;#ASMEND1305; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]1306;1307; GFX789-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_255:1308; GFX789: ; %bb.0:1309; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 0xff ; encoding: [0x01,0x38,0x00,0xba,0xff,0x00,0x00,0x00]1310; GFX789-NEXT: ;;#ASMSTART1311; GFX789-NEXT: ;;#ASMEND1312; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]1313;1314; GFX10-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_255:1315; GFX10: ; %bb.0:1316; GFX10-NEXT: s_round_mode 0xf ; encoding: [0x0f,0x00,0xa4,0xbf]1317; GFX10-NEXT: ;;#ASMSTART1318; GFX10-NEXT: ;;#ASMEND1319; GFX10-NEXT: s_denorm_mode 15 ; encoding: [0x0f,0x00,0xa5,0xbf]1320; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]1321;1322; GFX11-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_255:1323; GFX11: ; %bb.0:1324; GFX11-NEXT: s_round_mode 0xf ; encoding: [0x0f,0x00,0x91,0xbf]1325; GFX11-NEXT: ;;#ASMSTART1326; GFX11-NEXT: ;;#ASMEND1327; GFX11-NEXT: s_denorm_mode 15 ; encoding: [0x0f,0x00,0x92,0xbf]1328; GFX11-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]1329 call void @llvm.amdgcn.s.setreg(i32 14337, i32 255)1330 call void asm sideeffect "", ""()1331 ret void1332}1333 1334; Truncate extra high bit1335define amdgpu_kernel void @test_setreg_full_both_round_mode_and_denorm_mode_597() {1336; GFX6-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_597:1337; GFX6: ; %bb.0:1338; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 0x255 ; encoding: [0x01,0x38,0x80,0xba,0x55,0x02,0x00,0x00]1339; GFX6-NEXT: ;;#ASMSTART1340; GFX6-NEXT: ;;#ASMEND1341; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]1342;1343; GFX789-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_597:1344; GFX789: ; %bb.0:1345; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 0x255 ; encoding: [0x01,0x38,0x00,0xba,0x55,0x02,0x00,0x00]1346; GFX789-NEXT: ;;#ASMSTART1347; GFX789-NEXT: ;;#ASMEND1348; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]1349;1350; GFX10-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_597:1351; GFX10: ; %bb.0:1352; GFX10-NEXT: s_round_mode 0x5 ; encoding: [0x05,0x00,0xa4,0xbf]1353; GFX10-NEXT: ;;#ASMSTART1354; GFX10-NEXT: ;;#ASMEND1355; GFX10-NEXT: s_denorm_mode 5 ; encoding: [0x05,0x00,0xa5,0xbf]1356; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]1357;1358; GFX11-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_597:1359; GFX11: ; %bb.0:1360; GFX11-NEXT: s_round_mode 0x5 ; encoding: [0x05,0x00,0x91,0xbf]1361; GFX11-NEXT: ;;#ASMSTART1362; GFX11-NEXT: ;;#ASMEND1363; GFX11-NEXT: s_denorm_mode 5 ; encoding: [0x05,0x00,0x92,0xbf]1364; GFX11-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]1365 call void @llvm.amdgcn.s.setreg(i32 14337, i32 597)1366 call void asm sideeffect "", ""()1367 ret void1368}1369 1370define amdgpu_kernel void @test_setreg_set_8_bits_straddles_round_and_denorm() {1371; GFX6-LABEL: test_setreg_set_8_bits_straddles_round_and_denorm:1372; GFX6: ; %bb.0:1373; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 8), 0xff ; encoding: [0x81,0x38,0x80,0xba,0xff,0x00,0x00,0x00]1374; GFX6-NEXT: ;;#ASMSTART1375; GFX6-NEXT: ;;#ASMEND1376; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]1377;1378; GFX789-LABEL: test_setreg_set_8_bits_straddles_round_and_denorm:1379; GFX789: ; %bb.0:1380; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 8), 0xff ; encoding: [0x81,0x38,0x00,0xba,0xff,0x00,0x00,0x00]1381; GFX789-NEXT: ;;#ASMSTART1382; GFX789-NEXT: ;;#ASMEND1383; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]1384;1385; GFX10-LABEL: test_setreg_set_8_bits_straddles_round_and_denorm:1386; GFX10: ; %bb.0:1387; GFX10-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 8), 0xff ; encoding: [0x81,0x38,0x80,0xba,0xff,0x00,0x00,0x00]1388; GFX10-NEXT: ;;#ASMSTART1389; GFX10-NEXT: ;;#ASMEND1390; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]1391;1392; GFX11-LABEL: test_setreg_set_8_bits_straddles_round_and_denorm:1393; GFX11: ; %bb.0:1394; GFX11-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 8), 0xff ; encoding: [0x81,0x38,0x80,0xb9,0xff,0x00,0x00,0x00]1395; GFX11-NEXT: ;;#ASMSTART1396; GFX11-NEXT: ;;#ASMEND1397; GFX11-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]1398 call void @llvm.amdgcn.s.setreg(i32 14465, i32 255)1399 call void asm sideeffect "", ""()1400 ret void1401}1402 1403define amdgpu_kernel void @test_setreg_set_4_bits_straddles_round_and_denorm() {1404; GFX6-LABEL: test_setreg_set_4_bits_straddles_round_and_denorm:1405; GFX6: ; %bb.0:1406; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 4), 15 ; encoding: [0x81,0x18,0x80,0xba,0x0f,0x00,0x00,0x00]1407; GFX6-NEXT: ;;#ASMSTART1408; GFX6-NEXT: ;;#ASMEND1409; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]1410;1411; GFX789-LABEL: test_setreg_set_4_bits_straddles_round_and_denorm:1412; GFX789: ; %bb.0:1413; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 4), 15 ; encoding: [0x81,0x18,0x00,0xba,0x0f,0x00,0x00,0x00]1414; GFX789-NEXT: ;;#ASMSTART1415; GFX789-NEXT: ;;#ASMEND1416; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]1417;1418; GFX10-LABEL: test_setreg_set_4_bits_straddles_round_and_denorm:1419; GFX10: ; %bb.0:1420; GFX10-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 4), 15 ; encoding: [0x81,0x18,0x80,0xba,0x0f,0x00,0x00,0x00]1421; GFX10-NEXT: ;;#ASMSTART1422; GFX10-NEXT: ;;#ASMEND1423; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]1424;1425; GFX11-LABEL: test_setreg_set_4_bits_straddles_round_and_denorm:1426; GFX11: ; %bb.0:1427; GFX11-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 4), 15 ; encoding: [0x81,0x18,0x80,0xb9,0x0f,0x00,0x00,0x00]1428; GFX11-NEXT: ;;#ASMSTART1429; GFX11-NEXT: ;;#ASMEND1430; GFX11-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]1431 call void @llvm.amdgcn.s.setreg(i32 6273, i32 15)1432 call void asm sideeffect "", ""()1433 ret void1434}1435 1436define amdgpu_ps void @test_63489(i32 inreg %var.mode) {1437; GFX6-LABEL: test_63489:1438; GFX6: ; %bb.0:1439; GFX6-NEXT: s_setreg_b32 hwreg(HW_REG_MODE), s0 ; encoding: [0x01,0xf8,0x80,0xb9]1440; GFX6-NEXT: ;;#ASMSTART1441; GFX6-NEXT: ;;#ASMEND1442; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]1443;1444; GFX789-LABEL: test_63489:1445; GFX789: ; %bb.0:1446; GFX789-NEXT: s_setreg_b32 hwreg(HW_REG_MODE), s0 ; encoding: [0x01,0xf8,0x00,0xb9]1447; GFX789-NEXT: ;;#ASMSTART1448; GFX789-NEXT: ;;#ASMEND1449; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]1450;1451; GFX10-LABEL: test_63489:1452; GFX10: ; %bb.0:1453; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_MODE), s0 ; encoding: [0x01,0xf8,0x80,0xb9]1454; GFX10-NEXT: ;;#ASMSTART1455; GFX10-NEXT: ;;#ASMEND1456; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]1457;1458; GFX11-LABEL: test_63489:1459; GFX11: ; %bb.0:1460; GFX11-NEXT: s_setreg_b32 hwreg(HW_REG_MODE), s0 ; encoding: [0x01,0xf8,0x00,0xb9]1461; GFX11-NEXT: ;;#ASMSTART1462; GFX11-NEXT: ;;#ASMEND1463; GFX11-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]1464 call void @llvm.amdgcn.s.setreg(i32 63489, i32 %var.mode)1465 call void asm sideeffect "", ""()1466 ret void1467}1468 1469define amdgpu_ps void @test_minus_2047(i32 inreg %var.mode) {1470; GFX6-LABEL: test_minus_2047:1471; GFX6: ; %bb.0:1472; GFX6-NEXT: s_setreg_b32 hwreg(HW_REG_MODE), s0 ; encoding: [0x01,0xf8,0x80,0xb9]1473; GFX6-NEXT: ;;#ASMSTART1474; GFX6-NEXT: ;;#ASMEND1475; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]1476;1477; GFX789-LABEL: test_minus_2047:1478; GFX789: ; %bb.0:1479; GFX789-NEXT: s_setreg_b32 hwreg(HW_REG_MODE), s0 ; encoding: [0x01,0xf8,0x00,0xb9]1480; GFX789-NEXT: ;;#ASMSTART1481; GFX789-NEXT: ;;#ASMEND1482; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]1483;1484; GFX10-LABEL: test_minus_2047:1485; GFX10: ; %bb.0:1486; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_MODE), s0 ; encoding: [0x01,0xf8,0x80,0xb9]1487; GFX10-NEXT: ;;#ASMSTART1488; GFX10-NEXT: ;;#ASMEND1489; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]1490;1491; GFX11-LABEL: test_minus_2047:1492; GFX11: ; %bb.0:1493; GFX11-NEXT: s_setreg_b32 hwreg(HW_REG_MODE), s0 ; encoding: [0x01,0xf8,0x00,0xb9]1494; GFX11-NEXT: ;;#ASMSTART1495; GFX11-NEXT: ;;#ASMEND1496; GFX11-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]1497 call void @llvm.amdgcn.s.setreg(i32 -2047, i32 %var.mode)1498 call void asm sideeffect "", ""()1499 ret void1500}1501 1502; FIXME: Broken for DAG1503; define void @test_setreg_roundingmode_var_vgpr(i32 %var.mode) {1504; call void @llvm.amdgcn.s.setreg(i32 4097, i32 %var.mode)1505; call void asm sideeffect "", ""()1506; ret void1507; }1508 1509declare void @llvm.amdgcn.s.setreg(i32 immarg, i32) #01510 1511attributes #0 = { nounwind }1512