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1; RUN: llc -mtriple=amdgcn -mcpu=gfx906 < %s | FileCheck %s --check-prefixes=GCN,GFX9062; RUN: llc -mtriple=amdgcn -mcpu=gfx908 < %s | FileCheck %s --check-prefixes=GCN,GFX9083; RUN: llc -mtriple=amdgcn -mcpu=gfx1011 < %s | FileCheck %s --check-prefixes=GCN,GFX104; RUN: llc -mtriple=amdgcn -mcpu=gfx1012 < %s | FileCheck %s --check-prefixes=GCN,GFX105 6declare i32 @llvm.amdgcn.sdot2(<2 x i16> %a, <2 x i16> %b, i32 %c, i1 %clamp)7 8; GCN-LABEL: {{^}}test_llvm_amdgcn_sdot2_clamp9; GFX906: v_dot2_i32_i16 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} clamp{{$}}10; GFX908: v_dot2_i32_i16 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} clamp{{$}}11; GFX10: v_dot2_i32_i16 v{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}} clamp{{$}}12define amdgpu_kernel void @test_llvm_amdgcn_sdot2_clamp(13 ptr addrspace(1) %r,14 ptr addrspace(1) %a,15 ptr addrspace(1) %b,16 ptr addrspace(1) %c) {17entry:18 %a.val = load <2 x i16>, ptr addrspace(1) %a19 %b.val = load <2 x i16>, ptr addrspace(1) %b20 %c.val = load i32, ptr addrspace(1) %c21 %r.val = call i32 @llvm.amdgcn.sdot2(<2 x i16> %a.val, <2 x i16> %b.val, i32 %c.val, i1 1)22 store i32 %r.val, ptr addrspace(1) %r23 ret void24}25 26; GCN-LABEL: {{^}}test_llvm_amdgcn_sdot2_no_clamp27; GFX906: v_dot2_i32_i16 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}{{$}}28; GFX908: v_dot2c_i32_i16_e32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}{{$}}29; GFX10: v_dot2_i32_i16 v{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}{{$}}30define amdgpu_kernel void @test_llvm_amdgcn_sdot2_no_clamp(31 ptr addrspace(1) %r,32 ptr addrspace(1) %a,33 ptr addrspace(1) %b,34 ptr addrspace(1) %c) {35entry:36 %a.val = load <2 x i16>, ptr addrspace(1) %a37 %b.val = load <2 x i16>, ptr addrspace(1) %b38 %c.val = load i32, ptr addrspace(1) %c39 %r.val = call i32 @llvm.amdgcn.sdot2(<2 x i16> %a.val, <2 x i16> %b.val, i32 %c.val, i1 0)40 store i32 %r.val, ptr addrspace(1) %r41 ret void42}43