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1;RUN: llc < %s -mtriple=amdgcn -mcpu=verde | FileCheck %s2;RUN: llc < %s -mtriple=amdgcn -mcpu=tonga | FileCheck %s --check-prefixes=CHECK,VI3 4;CHECK-LABEL: {{^}}buffer_load:5;CHECK: buffer_load_dwordx4 v[0:3], {{v[0-9]+}}, s[0:3], 0 idxen6;CHECK: buffer_load_dwordx4 v[4:7], {{v[0-9]+}}, s[0:3], 0 idxen glc7;CHECK: buffer_load_dwordx4 v[8:11], {{v[0-9]+}}, s[0:3], 0 idxen slc8;CHECK: s_waitcnt9define amdgpu_ps {<4 x float>, <4 x float>, <4 x float>} @buffer_load(<4 x i32> inreg) {10main_body:11 %data = call <4 x float> @llvm.amdgcn.struct.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 0, i32 0, i32 0)12 %data_glc = call <4 x float> @llvm.amdgcn.struct.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 0, i32 0, i32 1)13 %data_slc = call <4 x float> @llvm.amdgcn.struct.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 0, i32 0, i32 2)14 %r0 = insertvalue {<4 x float>, <4 x float>, <4 x float>} poison, <4 x float> %data, 015 %r1 = insertvalue {<4 x float>, <4 x float>, <4 x float>} %r0, <4 x float> %data_glc, 116 %r2 = insertvalue {<4 x float>, <4 x float>, <4 x float>} %r1, <4 x float> %data_slc, 217 ret {<4 x float>, <4 x float>, <4 x float>} %r218}19 20;CHECK-LABEL: {{^}}buffer_load_immoffs:21;CHECK: buffer_load_dwordx4 v[0:3], {{v[0-9]+}}, s[0:3], 0 idxen offset:4022;CHECK: s_waitcnt23define amdgpu_ps <4 x float> @buffer_load_immoffs(<4 x i32> inreg) {24main_body:25 %data = call <4 x float> @llvm.amdgcn.struct.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 40, i32 0, i32 0)26 ret <4 x float> %data27}28 29;CHECK-LABEL: {{^}}buffer_load_immoffs_large:30;CHECK: s_movk_i32 [[OFFSET:s[0-9]+]], 0x1ffc31;CHECK: buffer_load_dwordx4 v[0:3], {{v[0-9]+}}, s[0:3], [[OFFSET]] idxen offset:432;CHECK: s_waitcnt33define amdgpu_ps <4 x float> @buffer_load_immoffs_large(<4 x i32> inreg) {34main_body:35 %data = call <4 x float> @llvm.amdgcn.struct.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 4, i32 8188, i32 0)36 ret <4 x float> %data37}38 39;CHECK-LABEL: {{^}}buffer_load_idx:40;CHECK: buffer_load_dwordx4 v[0:3], v0, s[0:3], 0 idxen41;CHECK: s_waitcnt42define amdgpu_ps <4 x float> @buffer_load_idx(<4 x i32> inreg, i32) {43main_body:44 %data = call <4 x float> @llvm.amdgcn.struct.buffer.load.v4f32(<4 x i32> %0, i32 %1, i32 0, i32 0, i32 0)45 ret <4 x float> %data46}47 48;CHECK-LABEL: {{^}}buffer_load_ofs:49;CHECK: buffer_load_dwordx4 v[0:3], v[0:1], s[0:3], 0 idxen offen50;CHECK: s_waitcnt51define amdgpu_ps <4 x float> @buffer_load_ofs(<4 x i32> inreg, i32) {52main_body:53 %data = call <4 x float> @llvm.amdgcn.struct.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 %1, i32 0, i32 0)54 ret <4 x float> %data55}56 57;CHECK-LABEL: {{^}}buffer_load_ofs_imm:58;CHECK: buffer_load_dwordx4 v[0:3], v[0:1], s[0:3], 0 idxen offen offset:6059;CHECK: s_waitcnt60define amdgpu_ps <4 x float> @buffer_load_ofs_imm(<4 x i32> inreg, i32) {61main_body:62 %ofs = add i32 %1, 6063 %data = call <4 x float> @llvm.amdgcn.struct.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 %ofs, i32 0, i32 0)64 ret <4 x float> %data65}66 67;CHECK-LABEL: {{^}}buffer_load_both:68;CHECK: buffer_load_dwordx4 v[0:3], v[0:1], s[0:3], 0 idxen offen69;CHECK: s_waitcnt70define amdgpu_ps <4 x float> @buffer_load_both(<4 x i32> inreg, i32, i32) {71main_body:72 %data = call <4 x float> @llvm.amdgcn.struct.buffer.load.v4f32(<4 x i32> %0, i32 %1, i32 %2, i32 0, i32 0)73 ret <4 x float> %data74}75 76;CHECK-LABEL: {{^}}buffer_load_both_reversed:77;CHECK: v_mov_b32_e32 v2, v078;CHECK: buffer_load_dwordx4 v[0:3], v[1:2], s[0:3], 0 idxen offen79;CHECK: s_waitcnt80define amdgpu_ps <4 x float> @buffer_load_both_reversed(<4 x i32> inreg, i32, i32) {81main_body:82 %data = call <4 x float> @llvm.amdgcn.struct.buffer.load.v4f32(<4 x i32> %0, i32 %2, i32 %1, i32 0, i32 0)83 ret <4 x float> %data84}85 86;CHECK-LABEL: {{^}}buffer_load_x1:87;CHECK: buffer_load_dword v0, v[0:1], s[0:3], 0 idxen offen88;CHECK: s_waitcnt89define amdgpu_ps float @buffer_load_x1(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) {90main_body:91 %data = call float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 0, i32 0)92 ret float %data93}94 95;CHECK-LABEL: {{^}}buffer_load_x2:96;CHECK: buffer_load_dwordx2 v[0:1], v[0:1], s[0:3], 0 idxen offen97;CHECK: s_waitcnt98define amdgpu_ps <2 x float> @buffer_load_x2(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) {99main_body:100 %data = call <2 x float> @llvm.amdgcn.struct.buffer.load.v2f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 0, i32 0)101 ret <2 x float> %data102}103 104;CHECK-LABEL: {{^}}buffer_load_negative_offset:105;CHECK: v_add_{{[iu]}}32_e32 {{v[0-9]+}}, vcc, -16, v0106;CHECK: buffer_load_dwordx4 v[0:3], {{v\[[0-9]+:[0-9]+\]}}, s[0:3], 0 idxen offen107define amdgpu_ps <4 x float> @buffer_load_negative_offset(<4 x i32> inreg, i32 %ofs) {108main_body:109 %ofs.1 = add i32 %ofs, -16110 %data = call <4 x float> @llvm.amdgcn.struct.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 %ofs.1, i32 0, i32 0)111 ret <4 x float> %data112}113 114; SI won't merge ds memory operations, because of the signed offset bug, so115; we only have check lines for VI.116; CHECK-LABEL: buffer_load_mmo:117; VI: v_mov_b32_e32 [[ZERO:v[0-9]+]], 0118; VI: ds_write2_b32 v{{[0-9]+}}, [[ZERO]], [[ZERO]] offset1:4119define amdgpu_ps float @buffer_load_mmo(<4 x i32> inreg %rsrc, ptr addrspace(3) %lds) {120entry:121 store float 0.0, ptr addrspace(3) %lds122 %val = call float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32> %rsrc, i32 0, i32 0, i32 0, i32 0)123 %tmp2 = getelementptr float, ptr addrspace(3) %lds, i32 4124 store float 0.0, ptr addrspace(3) %tmp2125 ret float %val126}127 128;CHECK-LABEL: {{^}}buffer_load_int:129;CHECK: buffer_load_dwordx4 v[0:3], {{v[0-9]+}}, s[0:3], 0 idxen130;CHECK: buffer_load_dwordx2 v[4:5], {{v[0-9]+}}, s[0:3], 0 idxen glc131;CHECK: buffer_load_dword v6, {{v[0-9]+}}, s[0:3], 0 idxen slc132;CHECK: s_waitcnt133define amdgpu_ps {<4 x float>, <2 x float>, float} @buffer_load_int(<4 x i32> inreg) {134main_body:135 %data = call <4 x i32> @llvm.amdgcn.struct.buffer.load.v4i32(<4 x i32> %0, i32 0, i32 0, i32 0, i32 0)136 %data_glc = call <2 x i32> @llvm.amdgcn.struct.buffer.load.v2i32(<4 x i32> %0, i32 0, i32 0, i32 0, i32 1)137 %data_slc = call i32 @llvm.amdgcn.struct.buffer.load.i32(<4 x i32> %0, i32 0, i32 0, i32 0, i32 2)138 %fdata = bitcast <4 x i32> %data to <4 x float>139 %fdata_glc = bitcast <2 x i32> %data_glc to <2 x float>140 %fdata_slc = bitcast i32 %data_slc to float141 %r0 = insertvalue {<4 x float>, <2 x float>, float} poison, <4 x float> %fdata, 0142 %r1 = insertvalue {<4 x float>, <2 x float>, float} %r0, <2 x float> %fdata_glc, 1143 %r2 = insertvalue {<4 x float>, <2 x float>, float} %r1, float %fdata_slc, 2144 ret {<4 x float>, <2 x float>, float} %r2145}146 147;CHECK-LABEL: {{^}}struct_buffer_load_ubyte:148;CHECK-NEXT: %bb.149;CHECK-NEXT: buffer_load_ubyte v{{[0-9]}}, v[0:1], s[0:3], 0 idxen offen150;CHECK: s_waitcnt vmcnt(0)151;CHECK-NEXT: v_cvt_f32_ubyte0_e32 v0, v0152;CHECK-NEXT: ; return to shader part epilog153define amdgpu_ps float @struct_buffer_load_ubyte(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) {154main_body:155 %tmp = call i8 @llvm.amdgcn.struct.buffer.load.i8(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 0, i32 0)156 %tmp2 = zext i8 %tmp to i32157 %val = uitofp i32 %tmp2 to float158 ret float %val159}160 161;CHECK-LABEL: {{^}}struct_buffer_load_ushort:162;CHECK-NEXT: %bb.163;CHECK-NEXT: buffer_load_ushort v{{[0-9]}}, v[0:1], s[0:3], 0 idxen offen164;CHECK-NEXT: s_waitcnt vmcnt(0)165;CHECK-NEXT: v_cvt_f32_u32_e32 v0, v0166;CHECK-NEXT: ; return to shader part epilog167define amdgpu_ps float @struct_buffer_load_ushort(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) {168main_body:169 %tmp = call i16 @llvm.amdgcn.struct.buffer.load.i16(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 0, i32 0)170 %tmp2 = zext i16 %tmp to i32171 %val = uitofp i32 %tmp2 to float172 ret float %val173}174 175;CHECK-LABEL: {{^}}struct_buffer_load_sbyte:176;CHECK-NEXT: %bb.177;CHECK-NEXT: buffer_load_sbyte v{{[0-9]}}, v[0:1], s[0:3], 0 idxen offen178;CHECK-NEXT: s_waitcnt vmcnt(0)179;CHECK-NEXT: v_cvt_f32_i32_e32 v0, v0180;CHECK-NEXT: ; return to shader part epilog181define amdgpu_ps float @struct_buffer_load_sbyte(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) {182main_body:183 %tmp = call i8 @llvm.amdgcn.struct.buffer.load.i8(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 0, i32 0)184 %tmp2 = sext i8 %tmp to i32185 %val = sitofp i32 %tmp2 to float186 ret float %val187}188 189;CHECK-LABEL: {{^}}struct_buffer_load_sshort:190;CHECK-NEXT: %bb.191;CHECK-NEXT: buffer_load_sshort v{{[0-9]}}, v[0:1], s[0:3], 0 idxen offen192;CHECK-NEXT: s_waitcnt vmcnt(0)193;CHECK-NEXT: v_cvt_f32_i32_e32 v0, v0194;CHECK-NEXT: ; return to shader part epilog195define amdgpu_ps float @struct_buffer_load_sshort(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) {196main_body:197 %tmp = call i16 @llvm.amdgcn.struct.buffer.load.i16(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 0, i32 0)198 %tmp2 = sext i16 %tmp to i32199 %val = sitofp i32 %tmp2 to float200 ret float %val201}202 203;CHECK-LABEL: {{^}}struct_buffer_load_f16:204;CHECK-NEXT: %bb.205;CHECK-NEXT: buffer_load_ushort [[VAL:v[0-9]+]], v1, s[0:3], 0 idxen206;CHECK: s_waitcnt vmcnt(0)207;CHECK: ds_write_b16 v0, [[VAL]]208define amdgpu_ps void @struct_buffer_load_f16(<4 x i32> inreg %rsrc, ptr addrspace(3) %ptr, i32 %idx) {209main_body:210 %val = call half @llvm.amdgcn.struct.buffer.load.f16(<4 x i32> %rsrc, i32 %idx, i32 0, i32 0, i32 0)211 store half %val, ptr addrspace(3) %ptr212 ret void213}214 215;CHECK-LABEL: {{^}}struct_buffer_load_v2f16:216;CHECK-NEXT: %bb.217;CHECK-NEXT: buffer_load_dword [[VAL:v[0-9]+]], v1, s[0:3], 0 idxen218;CHECK: s_waitcnt vmcnt(0)219;CHECK: ds_write_b32 v0, [[VAL]]220define amdgpu_ps void @struct_buffer_load_v2f16(<4 x i32> inreg %rsrc, ptr addrspace(3) %ptr, i32 %idx) {221main_body:222 %val = call <2 x half> @llvm.amdgcn.struct.buffer.load.v2f16(<4 x i32> %rsrc, i32 %idx, i32 0, i32 0, i32 0)223 store <2 x half> %val, ptr addrspace(3) %ptr224 ret void225}226 227;CHECK-LABEL: {{^}}struct_buffer_load_v4f16:228;CHECK-NEXT: %bb.229;CHECK-NEXT: buffer_load_dwordx2 [[VAL:v\[[0-9]+:[0-9]+\]]], v1, s[0:3], 0 idxen230;CHECK: s_waitcnt vmcnt(0)231;CHECK: ds_write_b64 v0, [[VAL]]232define amdgpu_ps void @struct_buffer_load_v4f16(<4 x i32> inreg %rsrc, ptr addrspace(3) %ptr, i32 %idx) {233main_body:234 %val = call <4 x half> @llvm.amdgcn.struct.buffer.load.v4f16(<4 x i32> %rsrc, i32 %idx, i32 0, i32 0, i32 0)235 store <4 x half> %val, ptr addrspace(3) %ptr236 ret void237}238 239;CHECK-LABEL: {{^}}struct_buffer_load_i16:240;CHECK-NEXT: %bb.241;CHECK-NEXT: buffer_load_ushort [[VAL:v[0-9]+]], v1, s[0:3], 0 idxen242;CHECK: s_waitcnt vmcnt(0)243;CHECK: ds_write_b16 v0, [[VAL]]244define amdgpu_ps void @struct_buffer_load_i16(<4 x i32> inreg %rsrc, ptr addrspace(3) %ptr, i32 %idx) {245main_body:246 %val = call i16 @llvm.amdgcn.struct.buffer.load.i16(<4 x i32> %rsrc, i32 %idx, i32 0, i32 0, i32 0)247 store i16 %val, ptr addrspace(3) %ptr248 ret void249}250 251;CHECK-LABEL: {{^}}struct_buffer_load_v2i16:252;CHECK-NEXT: %bb.253;CHECK-NEXT: buffer_load_dword [[VAL:v[0-9]+]], v1, s[0:3], 0 idxen254;CHECK: s_waitcnt vmcnt(0)255;CHECK: ds_write_b32 v0, [[VAL]]256define amdgpu_ps void @struct_buffer_load_v2i16(<4 x i32> inreg %rsrc, ptr addrspace(3) %ptr, i32 %idx) {257main_body:258 %val = call <2 x i16> @llvm.amdgcn.struct.buffer.load.v2i16(<4 x i32> %rsrc, i32 %idx, i32 0, i32 0, i32 0)259 store <2 x i16> %val, ptr addrspace(3) %ptr260 ret void261}262 263;CHECK-LABEL: {{^}}struct_buffer_load_v4i16:264;CHECK-NEXT: %bb.265;CHECK-NEXT: buffer_load_dwordx2 [[VAL:v\[[0-9]+:[0-9]+\]]], v1, s[0:3], 0 idxen266;CHECK: s_waitcnt vmcnt(0)267;CHECK: ds_write_b64 v0, [[VAL]]268define amdgpu_ps void @struct_buffer_load_v4i16(<4 x i32> inreg %rsrc, ptr addrspace(3) %ptr, i32 %idx) {269main_body:270 %val = call <4 x i16> @llvm.amdgcn.struct.buffer.load.v4i16(<4 x i32> %rsrc, i32 %idx, i32 0, i32 0, i32 0)271 store <4 x i16> %val, ptr addrspace(3) %ptr272 ret void273}274 275declare float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32>, i32, i32, i32, i32) #0276declare <2 x float> @llvm.amdgcn.struct.buffer.load.v2f32(<4 x i32>, i32, i32, i32, i32) #0277declare <4 x float> @llvm.amdgcn.struct.buffer.load.v4f32(<4 x i32>, i32, i32, i32, i32) #0278declare i32 @llvm.amdgcn.struct.buffer.load.i32(<4 x i32>, i32, i32, i32, i32) #0279declare <2 x i32> @llvm.amdgcn.struct.buffer.load.v2i32(<4 x i32>, i32, i32, i32, i32) #0280declare <4 x i32> @llvm.amdgcn.struct.buffer.load.v4i32(<4 x i32>, i32, i32, i32, i32) #0281declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #0282declare i8 @llvm.amdgcn.struct.buffer.load.i8(<4 x i32>, i32, i32, i32, i32) #0283 284declare half @llvm.amdgcn.struct.buffer.load.f16(<4 x i32>, i32, i32, i32, i32) #0285declare <2 x half> @llvm.amdgcn.struct.buffer.load.v2f16(<4 x i32>, i32, i32, i32, i32) #0286declare <4 x half> @llvm.amdgcn.struct.buffer.load.v4f16(<4 x i32>, i32, i32, i32, i32) #0287 288declare i16 @llvm.amdgcn.struct.buffer.load.i16(<4 x i32>, i32, i32, i32, i32) #0289declare <2 x i16> @llvm.amdgcn.struct.buffer.load.v2i16(<4 x i32>, i32, i32, i32, i32) #0290declare <4 x i16> @llvm.amdgcn.struct.buffer.load.v4i16(<4 x i32>, i32, i32, i32, i32) #0291 292attributes #0 = { nounwind readonly }293