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1;RUN: llc < %s -mtriple=amdgcn -mcpu=verde | FileCheck -check-prefix=VERDE %s2;RUN: llc < %s -mtriple=amdgcn -mcpu=tonga | FileCheck %s3 4;CHECK-LABEL: {{^}}buffer_store:5;CHECK-NOT: s_waitcnt6;CHECK: buffer_store_format_xyzw v[0:3], {{v[0-9]+}}, s[0:3], 0 idxen7;CHECK: buffer_store_format_xyzw v[4:7], {{v[0-9]+}}, s[0:3], 0 idxen glc8;CHECK: buffer_store_format_xyzw v[8:11], {{v[0-9]+}}, s[0:3], 0 idxen slc9define amdgpu_ps void @buffer_store(<4 x i32> inreg, <4 x float>, <4 x float>, <4 x float>) {10main_body:11 call void @llvm.amdgcn.struct.buffer.store.format.v4f32(<4 x float> %1, <4 x i32> %0, i32 0, i32 0, i32 0, i32 0)12 call void @llvm.amdgcn.struct.buffer.store.format.v4f32(<4 x float> %2, <4 x i32> %0, i32 0, i32 0, i32 0, i32 1)13 call void @llvm.amdgcn.struct.buffer.store.format.v4f32(<4 x float> %3, <4 x i32> %0, i32 0, i32 0, i32 0, i32 2)14 ret void15}16 17;CHECK-LABEL: {{^}}buffer_store_immoffs:18;CHECK-NOT: s_waitcnt19;CHECK: buffer_store_format_xyzw v[0:3], {{v[0-9]+}}, s[0:3], 0 idxen offset:4220define amdgpu_ps void @buffer_store_immoffs(<4 x i32> inreg, <4 x float>) {21main_body:22 call void @llvm.amdgcn.struct.buffer.store.format.v4f32(<4 x float> %1, <4 x i32> %0, i32 0, i32 42, i32 0, i32 0)23 ret void24}25 26;CHECK-LABEL: {{^}}buffer_store_idx:27;CHECK-NOT: s_waitcnt28;CHECK: buffer_store_format_xyzw v[0:3], v4, s[0:3], 0 idxen29define amdgpu_ps void @buffer_store_idx(<4 x i32> inreg, <4 x float>, i32) {30main_body:31 call void @llvm.amdgcn.struct.buffer.store.format.v4f32(<4 x float> %1, <4 x i32> %0, i32 %2, i32 0, i32 0, i32 0)32 ret void33}34 35;CHECK-LABEL: {{^}}buffer_store_ofs:36;CHECK-NOT: s_waitcnt37;CHECK: buffer_store_format_xyzw v[0:3], v[4:5], s[0:3], 0 idxen offen38define amdgpu_ps void @buffer_store_ofs(<4 x i32> inreg, <4 x float>, i32) {39main_body:40 call void @llvm.amdgcn.struct.buffer.store.format.v4f32(<4 x float> %1, <4 x i32> %0, i32 0, i32 %2, i32 0, i32 0)41 ret void42}43 44;CHECK-LABEL: {{^}}buffer_store_both:45;CHECK-NOT: s_waitcnt46;CHECK: buffer_store_format_xyzw v[0:3], v[4:5], s[0:3], 0 idxen offen47define amdgpu_ps void @buffer_store_both(<4 x i32> inreg, <4 x float>, i32, i32) {48main_body:49 call void @llvm.amdgcn.struct.buffer.store.format.v4f32(<4 x float> %1, <4 x i32> %0, i32 %2, i32 %3, i32 0, i32 0)50 ret void51}52 53;CHECK-LABEL: {{^}}buffer_store_both_reversed:54;CHECK: v_mov_b32_e32 v6, v455;CHECK-NOT: s_waitcnt56;CHECK: buffer_store_format_xyzw v[0:3], v[5:6], s[0:3], 0 idxen offen57define amdgpu_ps void @buffer_store_both_reversed(<4 x i32> inreg, <4 x float>, i32, i32) {58main_body:59 call void @llvm.amdgcn.struct.buffer.store.format.v4f32(<4 x float> %1, <4 x i32> %0, i32 %3, i32 %2, i32 0, i32 0)60 ret void61}62 63; Ideally, the register allocator would avoid the wait here64;65;CHECK-LABEL: {{^}}buffer_store_wait:66;CHECK-NOT: s_waitcnt67;CHECK: buffer_store_format_xyzw v[0:3], v4, s[0:3], 0 idxen68;VERDE: s_waitcnt expcnt(0)69;CHECK: buffer_load_format_xyzw v[0:3], v5, s[0:3], 0 idxen70;CHECK: s_waitcnt vmcnt(0)71;CHECK: buffer_store_format_xyzw v[0:3], v6, s[0:3], 0 idxen72define amdgpu_ps void @buffer_store_wait(<4 x i32> inreg, <4 x float>, i32, i32, i32) {73main_body:74 call void @llvm.amdgcn.struct.buffer.store.format.v4f32(<4 x float> %1, <4 x i32> %0, i32 %2, i32 0, i32 0, i32 0)75 %data = call <4 x float> @llvm.amdgcn.struct.buffer.load.format.v4f32(<4 x i32> %0, i32 %3, i32 0, i32 0, i32 0)76 call void @llvm.amdgcn.struct.buffer.store.format.v4f32(<4 x float> %data, <4 x i32> %0, i32 %4, i32 0, i32 0, i32 0)77 ret void78}79 80;CHECK-LABEL: {{^}}buffer_store_x1:81;CHECK-NOT: s_waitcnt82;CHECK: buffer_store_format_x v0, v1, s[0:3], 0 idxen83define amdgpu_ps void @buffer_store_x1(<4 x i32> inreg %rsrc, float %data, i32 %index) {84main_body:85 call void @llvm.amdgcn.struct.buffer.store.format.f32(float %data, <4 x i32> %rsrc, i32 %index, i32 0, i32 0, i32 0)86 ret void87}88 89;CHECK-LABEL: {{^}}buffer_store_x1_i32:90;CHECK-NOT: s_waitcnt91;CHECK: buffer_store_format_x v0, v1, s[0:3], 0 idxen92define amdgpu_ps void @buffer_store_x1_i32(<4 x i32> inreg %rsrc, i32 %data, i32 %index) {93main_body:94 call void @llvm.amdgcn.struct.buffer.store.format.i32(i32 %data, <4 x i32> %rsrc, i32 %index, i32 0, i32 0, i32 0)95 ret void96}97 98;CHECK-LABEL: {{^}}buffer_store_x2:99;CHECK-NOT: s_waitcnt100;CHECK: buffer_store_format_xy v[0:1], v2, s[0:3], 0 idxen101define amdgpu_ps void @buffer_store_x2(<4 x i32> inreg %rsrc, <2 x float> %data, i32 %index) {102main_body:103 call void @llvm.amdgcn.struct.buffer.store.format.v2f32(<2 x float> %data, <4 x i32> %rsrc, i32 %index, i32 0, i32 0, i32 0)104 ret void105}106 107declare void @llvm.amdgcn.struct.buffer.store.format.f32(float, <4 x i32>, i32, i32, i32, i32) #0108declare void @llvm.amdgcn.struct.buffer.store.format.v2f32(<2 x float>, <4 x i32>, i32, i32, i32, i32) #0109declare void @llvm.amdgcn.struct.buffer.store.format.v4f32(<4 x float>, <4 x i32>, i32, i32, i32, i32) #0110declare void @llvm.amdgcn.struct.buffer.store.format.i32(i32, <4 x i32>, i32, i32, i32, i32) #0111declare <4 x float> @llvm.amdgcn.struct.buffer.load.format.v4f32(<4 x i32>, i32, i32, i32, i32) #1112 113attributes #0 = { nounwind }114attributes #1 = { nounwind readonly }115