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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 22; RUN: llc < %s -mtriple=amdgcn -mcpu=verde | FileCheck -check-prefixes=GFX68,VERDE %s3; RUN: llc < %s -mtriple=amdgcn -mcpu=tonga | FileCheck -check-prefixes=GFX68,GFX8 %s4; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s5; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s6; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1250 -mattr=+real-true16 | FileCheck -check-prefixes=GFX12,GFX12-TRUE16 %s7; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1250 -mattr=-real-true16 | FileCheck -check-prefixes=GFX12,GFX12-FAKE16 %s8 9define amdgpu_ps void @buffer_store(<4 x i32> inreg, <4 x float>, <4 x float>, <4 x float>) {10; GFX68-LABEL: buffer_store:11; GFX68: ; %bb.0: ; %main_body12; GFX68-NEXT: v_mov_b32_e32 v12, 013; GFX68-NEXT: buffer_store_dwordx4 v[0:3], v12, s[0:3], 0 idxen14; GFX68-NEXT: buffer_store_dwordx4 v[4:7], v12, s[0:3], 0 idxen glc15; GFX68-NEXT: buffer_store_dwordx4 v[8:11], v12, s[0:3], 0 idxen slc16; GFX68-NEXT: s_endpgm17;18; GFX11-LABEL: buffer_store:19; GFX11: ; %bb.0: ; %main_body20; GFX11-NEXT: v_mov_b32_e32 v12, 021; GFX11-NEXT: s_clause 0x222; GFX11-NEXT: buffer_store_b128 v[0:3], v12, s[0:3], 0 idxen23; GFX11-NEXT: buffer_store_b128 v[4:7], v12, s[0:3], 0 idxen glc24; GFX11-NEXT: buffer_store_b128 v[8:11], v12, s[0:3], 0 idxen slc25; GFX11-NEXT: s_endpgm26;27; GFX12-LABEL: buffer_store:28; GFX12: ; %bb.0: ; %main_body29; GFX12-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 130; GFX12-NEXT: v_mov_b32_e32 v12, 031; GFX12-NEXT: s_clause 0x232; GFX12-NEXT: buffer_store_b128 v[0:3], v12, s[0:3], null idxen33; GFX12-NEXT: buffer_store_b128 v[4:7], v12, s[0:3], null idxen th:TH_STORE_NT34; GFX12-NEXT: buffer_store_b128 v[8:11], v12, s[0:3], null idxen th:TH_STORE_HT35; GFX12-NEXT: s_endpgm36main_body:37 call void @llvm.amdgcn.struct.buffer.store.v4f32(<4 x float> %1, <4 x i32> %0, i32 0, i32 0, i32 0, i32 0)38 call void @llvm.amdgcn.struct.buffer.store.v4f32(<4 x float> %2, <4 x i32> %0, i32 0, i32 0, i32 0, i32 1)39 call void @llvm.amdgcn.struct.buffer.store.v4f32(<4 x float> %3, <4 x i32> %0, i32 0, i32 0, i32 0, i32 2)40 ret void41}42 43define amdgpu_ps void @buffer_store_immoffs(<4 x i32> inreg, <4 x float>) {44; GFX68-LABEL: buffer_store_immoffs:45; GFX68: ; %bb.0: ; %main_body46; GFX68-NEXT: v_mov_b32_e32 v4, 047; GFX68-NEXT: buffer_store_dwordx4 v[0:3], v4, s[0:3], 0 idxen offset:4248; GFX68-NEXT: s_endpgm49;50; GFX11-LABEL: buffer_store_immoffs:51; GFX11: ; %bb.0: ; %main_body52; GFX11-NEXT: v_mov_b32_e32 v4, 053; GFX11-NEXT: buffer_store_b128 v[0:3], v4, s[0:3], 0 idxen offset:4254; GFX11-NEXT: s_endpgm55;56; GFX12-LABEL: buffer_store_immoffs:57; GFX12: ; %bb.0: ; %main_body58; GFX12-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 159; GFX12-NEXT: v_mov_b32_e32 v4, 060; GFX12-NEXT: buffer_store_b128 v[0:3], v4, s[0:3], null idxen offset:4261; GFX12-NEXT: s_endpgm62main_body:63 call void @llvm.amdgcn.struct.buffer.store.v4f32(<4 x float> %1, <4 x i32> %0, i32 0, i32 42, i32 0, i32 0)64 ret void65}66 67define amdgpu_ps void @buffer_store_idx(<4 x i32> inreg, <4 x float>, i32) {68; GFX68-LABEL: buffer_store_idx:69; GFX68: ; %bb.0: ; %main_body70; GFX68-NEXT: buffer_store_dwordx4 v[0:3], v4, s[0:3], 0 idxen71; GFX68-NEXT: s_endpgm72;73; GFX11-LABEL: buffer_store_idx:74; GFX11: ; %bb.0: ; %main_body75; GFX11-NEXT: buffer_store_b128 v[0:3], v4, s[0:3], 0 idxen76; GFX11-NEXT: s_endpgm77;78; GFX12-LABEL: buffer_store_idx:79; GFX12: ; %bb.0: ; %main_body80; GFX12-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 181; GFX12-NEXT: buffer_store_b128 v[0:3], v4, s[0:3], null idxen82; GFX12-NEXT: s_endpgm83main_body:84 call void @llvm.amdgcn.struct.buffer.store.v4f32(<4 x float> %1, <4 x i32> %0, i32 %2, i32 0, i32 0, i32 0)85 ret void86}87 88define amdgpu_ps void @buffer_store_ofs(<4 x i32> inreg, <4 x float>, i32) {89; GFX68-LABEL: buffer_store_ofs:90; GFX68: ; %bb.0: ; %main_body91; GFX68-NEXT: s_mov_b32 s4, 092; GFX68-NEXT: v_mov_b32_e32 v5, v493; GFX68-NEXT: v_mov_b32_e32 v4, s494; GFX68-NEXT: buffer_store_dwordx4 v[0:3], v[4:5], s[0:3], 0 idxen offen95; GFX68-NEXT: s_endpgm96;97; GFX11-LABEL: buffer_store_ofs:98; GFX11: ; %bb.0: ; %main_body99; GFX11-NEXT: s_mov_b32 s4, 0100; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)101; GFX11-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, s4102; GFX11-NEXT: buffer_store_b128 v[0:3], v[4:5], s[0:3], 0 idxen offen103; GFX11-NEXT: s_endpgm104;105; GFX12-LABEL: buffer_store_ofs:106; GFX12: ; %bb.0: ; %main_body107; GFX12-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1108; GFX12-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, 0109; GFX12-NEXT: buffer_store_b128 v[0:3], v[4:5], s[0:3], null idxen offen110; GFX12-NEXT: s_endpgm111main_body:112 call void @llvm.amdgcn.struct.buffer.store.v4f32(<4 x float> %1, <4 x i32> %0, i32 0, i32 %2, i32 0, i32 0)113 ret void114}115 116define amdgpu_ps void @buffer_store_both(<4 x i32> inreg, <4 x float>, i32, i32) {117; GFX68-LABEL: buffer_store_both:118; GFX68: ; %bb.0: ; %main_body119; GFX68-NEXT: buffer_store_dwordx4 v[0:3], v[4:5], s[0:3], 0 idxen offen120; GFX68-NEXT: s_endpgm121;122; GFX11-LABEL: buffer_store_both:123; GFX11: ; %bb.0: ; %main_body124; GFX11-NEXT: buffer_store_b128 v[0:3], v[4:5], s[0:3], 0 idxen offen125; GFX11-NEXT: s_endpgm126;127; GFX12-LABEL: buffer_store_both:128; GFX12: ; %bb.0: ; %main_body129; GFX12-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1130; GFX12-NEXT: buffer_store_b128 v[0:3], v[4:5], s[0:3], null idxen offen131; GFX12-NEXT: s_endpgm132main_body:133 call void @llvm.amdgcn.struct.buffer.store.v4f32(<4 x float> %1, <4 x i32> %0, i32 %2, i32 %3, i32 0, i32 0)134 ret void135}136 137define amdgpu_ps void @buffer_store_both_reversed(<4 x i32> inreg, <4 x float>, i32, i32) {138; GFX68-LABEL: buffer_store_both_reversed:139; GFX68: ; %bb.0: ; %main_body140; GFX68-NEXT: v_mov_b32_e32 v6, v4141; GFX68-NEXT: buffer_store_dwordx4 v[0:3], v[5:6], s[0:3], 0 idxen offen142; GFX68-NEXT: s_endpgm143;144; GFX11-LABEL: buffer_store_both_reversed:145; GFX11: ; %bb.0: ; %main_body146; GFX11-NEXT: v_mov_b32_e32 v6, v4147; GFX11-NEXT: buffer_store_b128 v[0:3], v[5:6], s[0:3], 0 idxen offen148; GFX11-NEXT: s_endpgm149;150; GFX12-LABEL: buffer_store_both_reversed:151; GFX12: ; %bb.0: ; %main_body152; GFX12-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1153; GFX12-NEXT: v_dual_mov_b32 v6, v5 :: v_dual_mov_b32 v7, v4154; GFX12-NEXT: buffer_store_b128 v[0:3], v[6:7], s[0:3], null idxen offen155; GFX12-NEXT: s_endpgm156main_body:157 call void @llvm.amdgcn.struct.buffer.store.v4f32(<4 x float> %1, <4 x i32> %0, i32 %3, i32 %2, i32 0, i32 0)158 ret void159}160 161; Ideally, the register allocator would avoid the wait here162define amdgpu_ps void @buffer_store_wait(<4 x i32> inreg, <4 x float>, i32, i32, i32) {163; VERDE-LABEL: buffer_store_wait:164; VERDE: ; %bb.0: ; %main_body165; VERDE-NEXT: buffer_store_dwordx4 v[0:3], v4, s[0:3], 0 idxen166; VERDE-NEXT: s_waitcnt expcnt(0)167; VERDE-NEXT: buffer_load_dwordx4 v[0:3], v5, s[0:3], 0 idxen168; VERDE-NEXT: s_waitcnt vmcnt(0)169; VERDE-NEXT: buffer_store_dwordx4 v[0:3], v6, s[0:3], 0 idxen170; VERDE-NEXT: s_endpgm171;172; GFX8-LABEL: buffer_store_wait:173; GFX8: ; %bb.0: ; %main_body174; GFX8-NEXT: buffer_store_dwordx4 v[0:3], v4, s[0:3], 0 idxen175; GFX8-NEXT: buffer_load_dwordx4 v[0:3], v5, s[0:3], 0 idxen176; GFX8-NEXT: s_waitcnt vmcnt(0)177; GFX8-NEXT: buffer_store_dwordx4 v[0:3], v6, s[0:3], 0 idxen178; GFX8-NEXT: s_endpgm179;180; GFX11-LABEL: buffer_store_wait:181; GFX11: ; %bb.0: ; %main_body182; GFX11-NEXT: buffer_store_b128 v[0:3], v4, s[0:3], 0 idxen183; GFX11-NEXT: buffer_load_b128 v[0:3], v5, s[0:3], 0 idxen184; GFX11-NEXT: s_waitcnt vmcnt(0)185; GFX11-NEXT: buffer_store_b128 v[0:3], v6, s[0:3], 0 idxen186; GFX11-NEXT: s_endpgm187;188; GFX12-LABEL: buffer_store_wait:189; GFX12: ; %bb.0: ; %main_body190; GFX12-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1191; GFX12-NEXT: s_clause 0x1192; GFX12-NEXT: buffer_store_b128 v[0:3], v4, s[0:3], null idxen193; GFX12-NEXT: buffer_load_b128 v[0:3], v5, s[0:3], null idxen194; GFX12-NEXT: s_wait_loadcnt 0x0195; GFX12-NEXT: buffer_store_b128 v[0:3], v6, s[0:3], null idxen196; GFX12-NEXT: s_endpgm197main_body:198 call void @llvm.amdgcn.struct.buffer.store.v4f32(<4 x float> %1, <4 x i32> %0, i32 %2, i32 0, i32 0, i32 0)199 %data = call <4 x float> @llvm.amdgcn.struct.buffer.load.v4f32(<4 x i32> %0, i32 %3, i32 0, i32 0, i32 0)200 call void @llvm.amdgcn.struct.buffer.store.v4f32(<4 x float> %data, <4 x i32> %0, i32 %4, i32 0, i32 0, i32 0)201 ret void202}203 204define amdgpu_ps void @buffer_store_x1(<4 x i32> inreg %rsrc, float %data, i32 %index) {205; GFX68-LABEL: buffer_store_x1:206; GFX68: ; %bb.0: ; %main_body207; GFX68-NEXT: buffer_store_dword v0, v1, s[0:3], 0 idxen208; GFX68-NEXT: s_endpgm209;210; GFX11-LABEL: buffer_store_x1:211; GFX11: ; %bb.0: ; %main_body212; GFX11-NEXT: buffer_store_b32 v0, v1, s[0:3], 0 idxen213; GFX11-NEXT: s_endpgm214;215; GFX12-LABEL: buffer_store_x1:216; GFX12: ; %bb.0: ; %main_body217; GFX12-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1218; GFX12-NEXT: buffer_store_b32 v0, v1, s[0:3], null idxen219; GFX12-NEXT: s_endpgm220main_body:221 call void @llvm.amdgcn.struct.buffer.store.f32(float %data, <4 x i32> %rsrc, i32 %index, i32 0, i32 0, i32 0)222 ret void223}224 225define amdgpu_ps void @buffer_store_x2(<4 x i32> inreg %rsrc, <2 x float> %data, i32 %index) #0 {226; GFX68-LABEL: buffer_store_x2:227; GFX68: ; %bb.0: ; %main_body228; GFX68-NEXT: buffer_store_dwordx2 v[0:1], v2, s[0:3], 0 idxen229; GFX68-NEXT: s_endpgm230;231; GFX11-LABEL: buffer_store_x2:232; GFX11: ; %bb.0: ; %main_body233; GFX11-NEXT: buffer_store_b64 v[0:1], v2, s[0:3], 0 idxen234; GFX11-NEXT: s_endpgm235;236; GFX12-LABEL: buffer_store_x2:237; GFX12: ; %bb.0: ; %main_body238; GFX12-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1239; GFX12-NEXT: buffer_store_b64 v[0:1], v2, s[0:3], null idxen240; GFX12-NEXT: s_endpgm241main_body:242 call void @llvm.amdgcn.struct.buffer.store.v2f32(<2 x float> %data, <4 x i32> %rsrc, i32 %index, i32 0, i32 0, i32 0)243 ret void244}245 246define amdgpu_ps void @buffer_store_int(<4 x i32> inreg, <4 x i32>, <2 x i32>, i32) {247; GFX68-LABEL: buffer_store_int:248; GFX68: ; %bb.0: ; %main_body249; GFX68-NEXT: v_mov_b32_e32 v7, 0250; GFX68-NEXT: buffer_store_dwordx4 v[0:3], v7, s[0:3], 0 idxen251; GFX68-NEXT: buffer_store_dwordx2 v[4:5], v7, s[0:3], 0 idxen glc252; GFX68-NEXT: buffer_store_dword v6, v7, s[0:3], 0 idxen slc253; GFX68-NEXT: s_endpgm254;255; GFX11-LABEL: buffer_store_int:256; GFX11: ; %bb.0: ; %main_body257; GFX11-NEXT: v_mov_b32_e32 v7, 0258; GFX11-NEXT: s_clause 0x2259; GFX11-NEXT: buffer_store_b128 v[0:3], v7, s[0:3], 0 idxen260; GFX11-NEXT: buffer_store_b64 v[4:5], v7, s[0:3], 0 idxen glc261; GFX11-NEXT: buffer_store_b32 v6, v7, s[0:3], 0 idxen slc262; GFX11-NEXT: s_endpgm263;264; GFX12-LABEL: buffer_store_int:265; GFX12: ; %bb.0: ; %main_body266; GFX12-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1267; GFX12-NEXT: v_mov_b32_e32 v7, 0268; GFX12-NEXT: s_clause 0x2269; GFX12-NEXT: buffer_store_b128 v[0:3], v7, s[0:3], null idxen270; GFX12-NEXT: buffer_store_b64 v[4:5], v7, s[0:3], null idxen th:TH_STORE_NT271; GFX12-NEXT: buffer_store_b32 v6, v7, s[0:3], null idxen th:TH_STORE_HT272; GFX12-NEXT: s_endpgm273main_body:274 call void @llvm.amdgcn.struct.buffer.store.v4i32(<4 x i32> %1, <4 x i32> %0, i32 0, i32 0, i32 0, i32 0)275 call void @llvm.amdgcn.struct.buffer.store.v2i32(<2 x i32> %2, <4 x i32> %0, i32 0, i32 0, i32 0, i32 1)276 call void @llvm.amdgcn.struct.buffer.store.i32(i32 %3, <4 x i32> %0, i32 0, i32 0, i32 0, i32 2)277 ret void278}279 280define amdgpu_ps void @struct_buffer_store_byte(<4 x i32> inreg %rsrc, float %v1, i32 %index) {281; GFX68-LABEL: struct_buffer_store_byte:282; GFX68: ; %bb.0: ; %main_body283; GFX68-NEXT: v_cvt_u32_f32_e32 v0, v0284; GFX68-NEXT: buffer_store_byte v0, v1, s[0:3], 0 idxen285; GFX68-NEXT: s_endpgm286;287; GFX11-LABEL: struct_buffer_store_byte:288; GFX11: ; %bb.0: ; %main_body289; GFX11-NEXT: v_cvt_u32_f32_e32 v0, v0290; GFX11-NEXT: buffer_store_b8 v0, v1, s[0:3], 0 idxen291; GFX11-NEXT: s_endpgm292;293; GFX12-LABEL: struct_buffer_store_byte:294; GFX12: ; %bb.0: ; %main_body295; GFX12-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1296; GFX12-NEXT: v_cvt_u32_f32_e32 v0, v0297; GFX12-NEXT: buffer_store_b8 v0, v1, s[0:3], null idxen298; GFX12-NEXT: s_endpgm299main_body:300 %v2 = fptoui float %v1 to i32301 %v3 = trunc i32 %v2 to i8302 call void @llvm.amdgcn.struct.buffer.store.i8(i8 %v3, <4 x i32> %rsrc, i32 %index, i32 0, i32 0, i32 0)303 ret void304}305 306define amdgpu_ps void @struct_buffer_store_f16(<4 x i32> inreg %rsrc, float %v1, i32 %index) {307; GFX68-LABEL: struct_buffer_store_f16:308; GFX68: ; %bb.0:309; GFX68-NEXT: v_cvt_f16_f32_e32 v0, v0310; GFX68-NEXT: buffer_store_short v0, v1, s[0:3], 0 idxen311; GFX68-NEXT: s_endpgm312;313; GFX11-TRUE16-LABEL: struct_buffer_store_f16:314; GFX11-TRUE16: ; %bb.0:315; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0316; GFX11-TRUE16-NEXT: buffer_store_b16 v0, v1, s[0:3], 0 idxen317; GFX11-TRUE16-NEXT: s_endpgm318;319; GFX11-FAKE16-LABEL: struct_buffer_store_f16:320; GFX11-FAKE16: ; %bb.0:321; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0322; GFX11-FAKE16-NEXT: buffer_store_b16 v0, v1, s[0:3], 0 idxen323; GFX11-FAKE16-NEXT: s_endpgm324;325; GFX12-TRUE16-LABEL: struct_buffer_store_f16:326; GFX12-TRUE16: ; %bb.0:327; GFX12-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1328; GFX12-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0329; GFX12-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0330; GFX12-TRUE16-NEXT: buffer_store_b16 v0, v1, s[0:3], null idxen331; GFX12-TRUE16-NEXT: s_endpgm332;333; GFX12-FAKE16-LABEL: struct_buffer_store_f16:334; GFX12-FAKE16: ; %bb.0:335; GFX12-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1336; GFX12-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0337; GFX12-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0338; GFX12-FAKE16-NEXT: buffer_store_b16 v0, v1, s[0:3], null idxen339; GFX12-FAKE16-NEXT: s_endpgm340 %v2 = fptrunc float %v1 to half341 call void @llvm.amdgcn.struct.buffer.store.f16(half %v2, <4 x i32> %rsrc, i32 %index, i32 0, i32 0, i32 0)342 ret void343}344 345define amdgpu_ps void @struct_buffer_store_v2f16(<4 x i32> inreg %rsrc, <2 x half> %v1, i32 %index) {346; VERDE-LABEL: struct_buffer_store_v2f16:347; VERDE: ; %bb.0:348; VERDE-NEXT: v_cvt_f16_f32_e32 v1, v1349; VERDE-NEXT: v_cvt_f16_f32_e32 v0, v0350; VERDE-NEXT: v_lshlrev_b32_e32 v1, 16, v1351; VERDE-NEXT: v_or_b32_e32 v0, v0, v1352; VERDE-NEXT: buffer_store_dword v0, v2, s[0:3], 0 idxen353; VERDE-NEXT: s_endpgm354;355; GFX8-LABEL: struct_buffer_store_v2f16:356; GFX8: ; %bb.0:357; GFX8-NEXT: buffer_store_dword v0, v1, s[0:3], 0 idxen358; GFX8-NEXT: s_endpgm359;360; GFX11-LABEL: struct_buffer_store_v2f16:361; GFX11: ; %bb.0:362; GFX11-NEXT: buffer_store_b32 v0, v1, s[0:3], 0 idxen363; GFX11-NEXT: s_endpgm364;365; GFX12-LABEL: struct_buffer_store_v2f16:366; GFX12: ; %bb.0:367; GFX12-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1368; GFX12-NEXT: buffer_store_b32 v0, v1, s[0:3], null idxen369; GFX12-NEXT: s_endpgm370 call void @llvm.amdgcn.struct.buffer.store.v2f16(<2 x half> %v1, <4 x i32> %rsrc, i32 %index, i32 0, i32 0, i32 0)371 ret void372}373 374define amdgpu_ps void @struct_buffer_store_v4f16(<4 x i32> inreg %rsrc, <4 x half> %v1, i32 %index) {375; VERDE-LABEL: struct_buffer_store_v4f16:376; VERDE: ; %bb.0:377; VERDE-NEXT: v_cvt_f16_f32_e32 v3, v3378; VERDE-NEXT: v_cvt_f16_f32_e32 v2, v2379; VERDE-NEXT: v_cvt_f16_f32_e32 v5, v1380; VERDE-NEXT: v_cvt_f16_f32_e32 v0, v0381; VERDE-NEXT: v_lshlrev_b32_e32 v1, 16, v3382; VERDE-NEXT: v_or_b32_e32 v1, v2, v1383; VERDE-NEXT: v_lshlrev_b32_e32 v2, 16, v5384; VERDE-NEXT: v_or_b32_e32 v0, v0, v2385; VERDE-NEXT: buffer_store_dwordx2 v[0:1], v4, s[0:3], 0 idxen386; VERDE-NEXT: s_endpgm387;388; GFX8-LABEL: struct_buffer_store_v4f16:389; GFX8: ; %bb.0:390; GFX8-NEXT: buffer_store_dwordx2 v[0:1], v2, s[0:3], 0 idxen391; GFX8-NEXT: s_endpgm392;393; GFX11-LABEL: struct_buffer_store_v4f16:394; GFX11: ; %bb.0:395; GFX11-NEXT: buffer_store_b64 v[0:1], v2, s[0:3], 0 idxen396; GFX11-NEXT: s_endpgm397;398; GFX12-LABEL: struct_buffer_store_v4f16:399; GFX12: ; %bb.0:400; GFX12-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1401; GFX12-NEXT: buffer_store_b64 v[0:1], v2, s[0:3], null idxen402; GFX12-NEXT: s_endpgm403 call void @llvm.amdgcn.struct.buffer.store.v4f16(<4 x half> %v1, <4 x i32> %rsrc, i32 %index, i32 0, i32 0, i32 0)404 ret void405}406 407define amdgpu_ps void @struct_buffer_store_i16(<4 x i32> inreg %rsrc, float %v1, i32 %index) {408; GFX68-LABEL: struct_buffer_store_i16:409; GFX68: ; %bb.0: ; %main_body410; GFX68-NEXT: v_cvt_u32_f32_e32 v0, v0411; GFX68-NEXT: buffer_store_short v0, v1, s[0:3], 0 idxen412; GFX68-NEXT: s_endpgm413;414; GFX11-LABEL: struct_buffer_store_i16:415; GFX11: ; %bb.0: ; %main_body416; GFX11-NEXT: v_cvt_u32_f32_e32 v0, v0417; GFX11-NEXT: buffer_store_b16 v0, v1, s[0:3], 0 idxen418; GFX11-NEXT: s_endpgm419;420; GFX12-LABEL: struct_buffer_store_i16:421; GFX12: ; %bb.0: ; %main_body422; GFX12-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1423; GFX12-NEXT: v_cvt_u32_f32_e32 v0, v0424; GFX12-NEXT: buffer_store_b16 v0, v1, s[0:3], null idxen425; GFX12-NEXT: s_endpgm426main_body:427 %v2 = fptoui float %v1 to i32428 %v3 = trunc i32 %v2 to i16429 call void @llvm.amdgcn.struct.buffer.store.i16(i16 %v3, <4 x i32> %rsrc, i32 %index, i32 0, i32 0, i32 0)430 ret void431}432 433define amdgpu_ps void @struct_buffer_store_vif16(<4 x i32> inreg %rsrc, <2 x i16> %v1, i32 %index) {434; VERDE-LABEL: struct_buffer_store_vif16:435; VERDE: ; %bb.0:436; VERDE-NEXT: v_lshlrev_b32_e32 v1, 16, v1437; VERDE-NEXT: v_and_b32_e32 v0, 0xffff, v0438; VERDE-NEXT: v_or_b32_e32 v0, v0, v1439; VERDE-NEXT: buffer_store_dword v0, v2, s[0:3], 0 idxen440; VERDE-NEXT: s_endpgm441;442; GFX8-LABEL: struct_buffer_store_vif16:443; GFX8: ; %bb.0:444; GFX8-NEXT: buffer_store_dword v0, v1, s[0:3], 0 idxen445; GFX8-NEXT: s_endpgm446;447; GFX11-LABEL: struct_buffer_store_vif16:448; GFX11: ; %bb.0:449; GFX11-NEXT: buffer_store_b32 v0, v1, s[0:3], 0 idxen450; GFX11-NEXT: s_endpgm451;452; GFX12-LABEL: struct_buffer_store_vif16:453; GFX12: ; %bb.0:454; GFX12-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1455; GFX12-NEXT: buffer_store_b32 v0, v1, s[0:3], null idxen456; GFX12-NEXT: s_endpgm457 call void @llvm.amdgcn.struct.buffer.store.v2i16(<2 x i16> %v1, <4 x i32> %rsrc, i32 %index, i32 0, i32 0, i32 0)458 ret void459}460 461define amdgpu_ps void @struct_buffer_store_v4i16(<4 x i32> inreg %rsrc, <4 x i16> %v1, i32 %index) {462; VERDE-LABEL: struct_buffer_store_v4i16:463; VERDE: ; %bb.0:464; VERDE-NEXT: v_lshlrev_b32_e32 v3, 16, v3465; VERDE-NEXT: v_and_b32_e32 v2, 0xffff, v2466; VERDE-NEXT: v_lshlrev_b32_e32 v1, 16, v1467; VERDE-NEXT: v_and_b32_e32 v0, 0xffff, v0468; VERDE-NEXT: v_or_b32_e32 v2, v2, v3469; VERDE-NEXT: v_or_b32_e32 v1, v0, v1470; VERDE-NEXT: buffer_store_dwordx2 v[1:2], v4, s[0:3], 0 idxen471; VERDE-NEXT: s_endpgm472;473; GFX8-LABEL: struct_buffer_store_v4i16:474; GFX8: ; %bb.0:475; GFX8-NEXT: buffer_store_dwordx2 v[0:1], v2, s[0:3], 0 idxen476; GFX8-NEXT: s_endpgm477;478; GFX11-LABEL: struct_buffer_store_v4i16:479; GFX11: ; %bb.0:480; GFX11-NEXT: buffer_store_b64 v[0:1], v2, s[0:3], 0 idxen481; GFX11-NEXT: s_endpgm482;483; GFX12-LABEL: struct_buffer_store_v4i16:484; GFX12: ; %bb.0:485; GFX12-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1486; GFX12-NEXT: buffer_store_b64 v[0:1], v2, s[0:3], null idxen487; GFX12-NEXT: s_endpgm488 call void @llvm.amdgcn.struct.buffer.store.v4i16(<4 x i16> %v1, <4 x i32> %rsrc, i32 %index, i32 0, i32 0, i32 0)489 ret void490}491 492declare void @llvm.amdgcn.struct.buffer.store.f32(float, <4 x i32>, i32, i32, i32, i32) #0493declare void @llvm.amdgcn.struct.buffer.store.v2f32(<2 x float>, <4 x i32>, i32, i32, i32, i32) #0494declare void @llvm.amdgcn.struct.buffer.store.v4f32(<4 x float>, <4 x i32>, i32, i32, i32, i32) #0495declare void @llvm.amdgcn.struct.buffer.store.i32(i32, <4 x i32>, i32, i32, i32, i32) #0496declare void @llvm.amdgcn.struct.buffer.store.v2i32(<2 x i32>, <4 x i32>, i32, i32, i32, i32) #0497declare void @llvm.amdgcn.struct.buffer.store.v4i32(<4 x i32>, <4 x i32>, i32, i32, i32, i32) #0498declare <4 x float> @llvm.amdgcn.struct.buffer.load.v4f32(<4 x i32>, i32, i32, i32, i32) #1499declare void @llvm.amdgcn.struct.buffer.store.i8(i8, <4 x i32>, i32, i32, i32, i32) #0500declare void @llvm.amdgcn.struct.buffer.store.i16(i16, <4 x i32>, i32, i32, i32, i32) #0501declare void @llvm.amdgcn.struct.buffer.store.v2i16(<2 x i16>, <4 x i32>, i32, i32, i32, i32) #0502declare void @llvm.amdgcn.struct.buffer.store.v4i16(<4 x i16>, <4 x i32>, i32, i32, i32, i32) #0503declare void @llvm.amdgcn.struct.buffer.store.f16(half, <4 x i32>, i32, i32, i32, i32) #0504declare void @llvm.amdgcn.struct.buffer.store.v2f16(<2 x half>, <4 x i32>, i32, i32, i32, i32) #0505declare void @llvm.amdgcn.struct.buffer.store.v4f16(<4 x half>, <4 x i32>, i32, i32, i32, i32) #0506 507attributes #0 = { nounwind }508attributes #1 = { nounwind readonly }509