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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti < %s | FileCheck -check-prefix=GFX6 %s3; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=hawaii < %s | FileCheck -check-prefix=GFX7 %s4; Not supported in gfx8 or gfx95; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s6; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 < %s | FileCheck -check-prefix=GFX11 %s7; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1200 < %s | FileCheck -check-prefix=GFX1200 %s8; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1250 < %s | FileCheck -check-prefix=GFX1250 %s9 10define float @struct_ptr_buffer_atomic_add_f32_ret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset(float %val, ptr addrspace(8) inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {11; GFX6-LABEL: struct_ptr_buffer_atomic_add_f32_ret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset:12; GFX6: ; %bb.0:13; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)14; GFX6-NEXT: buffer_atomic_fmax v0, v[1:2], s[16:19], s20 idxen offen glc15; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0)16; GFX6-NEXT: s_setpc_b64 s[30:31]17;18; GFX7-LABEL: struct_ptr_buffer_atomic_add_f32_ret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset:19; GFX7: ; %bb.0:20; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)21; GFX7-NEXT: buffer_atomic_fmax v0, v[1:2], s[16:19], s20 idxen offen glc22; GFX7-NEXT: s_waitcnt vmcnt(0)23; GFX7-NEXT: s_setpc_b64 s[30:31]24;25; GFX10-LABEL: struct_ptr_buffer_atomic_add_f32_ret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset:26; GFX10: ; %bb.0:27; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)28; GFX10-NEXT: buffer_atomic_fmax v0, v[1:2], s[16:19], s20 idxen offen glc29; GFX10-NEXT: s_waitcnt vmcnt(0)30; GFX10-NEXT: s_setpc_b64 s[30:31]31;32; GFX11-LABEL: struct_ptr_buffer_atomic_add_f32_ret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset:33; GFX11: ; %bb.0:34; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)35; GFX11-NEXT: buffer_atomic_max_f32 v0, v[1:2], s[0:3], s16 idxen offen glc36; GFX11-NEXT: s_waitcnt vmcnt(0)37; GFX11-NEXT: s_setpc_b64 s[30:31]38;39; GFX1200-LABEL: struct_ptr_buffer_atomic_add_f32_ret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset:40; GFX1200: ; %bb.0:41; GFX1200-NEXT: s_wait_loadcnt_dscnt 0x042; GFX1200-NEXT: s_wait_expcnt 0x043; GFX1200-NEXT: s_wait_samplecnt 0x044; GFX1200-NEXT: s_wait_bvhcnt 0x045; GFX1200-NEXT: s_wait_kmcnt 0x046; GFX1200-NEXT: buffer_atomic_max_num_f32 v0, v[1:2], s[0:3], s16 idxen offen th:TH_ATOMIC_RETURN47; GFX1200-NEXT: s_wait_loadcnt 0x048; GFX1200-NEXT: s_setpc_b64 s[30:31]49;50; GFX1250-LABEL: struct_ptr_buffer_atomic_add_f32_ret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset:51; GFX1250: ; %bb.0:52; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x053; GFX1250-NEXT: s_wait_kmcnt 0x054; GFX1250-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v155; GFX1250-NEXT: buffer_atomic_max_num_f32 v0, v[2:3], s[0:3], s16 idxen offen th:TH_ATOMIC_RETURN56; GFX1250-NEXT: s_wait_loadcnt 0x057; GFX1250-NEXT: s_set_pc_i64 s[30:31]58 %ret = call float @llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f32(float %val, ptr addrspace(8) %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)59 ret float %ret60}61 62define float @struct_ptr_buffer_atomic_add_f32_ret__vgpr_val__sgpr_rsrc__vgpr_voffset_add__sgpr_soffset(float %val, ptr addrspace(8) inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {63; GFX6-LABEL: struct_ptr_buffer_atomic_add_f32_ret__vgpr_val__sgpr_rsrc__vgpr_voffset_add__sgpr_soffset:64; GFX6: ; %bb.0:65; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)66; GFX6-NEXT: buffer_atomic_fmax v0, v[1:2], s[16:19], s20 idxen offen offset:256 glc67; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0)68; GFX6-NEXT: s_setpc_b64 s[30:31]69;70; GFX7-LABEL: struct_ptr_buffer_atomic_add_f32_ret__vgpr_val__sgpr_rsrc__vgpr_voffset_add__sgpr_soffset:71; GFX7: ; %bb.0:72; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)73; GFX7-NEXT: buffer_atomic_fmax v0, v[1:2], s[16:19], s20 idxen offen offset:256 glc74; GFX7-NEXT: s_waitcnt vmcnt(0)75; GFX7-NEXT: s_setpc_b64 s[30:31]76;77; GFX10-LABEL: struct_ptr_buffer_atomic_add_f32_ret__vgpr_val__sgpr_rsrc__vgpr_voffset_add__sgpr_soffset:78; GFX10: ; %bb.0:79; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)80; GFX10-NEXT: buffer_atomic_fmax v0, v[1:2], s[16:19], s20 idxen offen offset:256 glc81; GFX10-NEXT: s_waitcnt vmcnt(0)82; GFX10-NEXT: s_setpc_b64 s[30:31]83;84; GFX11-LABEL: struct_ptr_buffer_atomic_add_f32_ret__vgpr_val__sgpr_rsrc__vgpr_voffset_add__sgpr_soffset:85; GFX11: ; %bb.0:86; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)87; GFX11-NEXT: buffer_atomic_max_f32 v0, v[1:2], s[0:3], s16 idxen offen offset:256 glc88; GFX11-NEXT: s_waitcnt vmcnt(0)89; GFX11-NEXT: s_setpc_b64 s[30:31]90;91; GFX1200-LABEL: struct_ptr_buffer_atomic_add_f32_ret__vgpr_val__sgpr_rsrc__vgpr_voffset_add__sgpr_soffset:92; GFX1200: ; %bb.0:93; GFX1200-NEXT: s_wait_loadcnt_dscnt 0x094; GFX1200-NEXT: s_wait_expcnt 0x095; GFX1200-NEXT: s_wait_samplecnt 0x096; GFX1200-NEXT: s_wait_bvhcnt 0x097; GFX1200-NEXT: s_wait_kmcnt 0x098; GFX1200-NEXT: buffer_atomic_max_num_f32 v0, v[1:2], s[0:3], s16 idxen offen offset:256 th:TH_ATOMIC_RETURN99; GFX1200-NEXT: s_wait_loadcnt 0x0100; GFX1200-NEXT: s_setpc_b64 s[30:31]101;102; GFX1250-LABEL: struct_ptr_buffer_atomic_add_f32_ret__vgpr_val__sgpr_rsrc__vgpr_voffset_add__sgpr_soffset:103; GFX1250: ; %bb.0:104; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0105; GFX1250-NEXT: s_wait_kmcnt 0x0106; GFX1250-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_add_nc_u32 v5, 0x100, v2107; GFX1250-NEXT: buffer_atomic_max_num_f32 v0, v[4:5], s[0:3], s16 idxen offen th:TH_ATOMIC_RETURN108; GFX1250-NEXT: s_wait_loadcnt 0x0109; GFX1250-NEXT: s_set_pc_i64 s[30:31]110 %voffset.add = add i32 %voffset, 256111 %ret = call float @llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f32(float %val, ptr addrspace(8) %rsrc, i32 %vindex, i32 %voffset.add, i32 %soffset, i32 0)112 ret float %ret113}114 115define float @struct_ptr_buffer_atomic_add_f32_ret__vgpr_val__sgpr_rsrc__0_voffset__sgpr_soffset(float %val, ptr addrspace(8) inreg %rsrc, i32 %vindex, i32 inreg %soffset) {116; GFX6-LABEL: struct_ptr_buffer_atomic_add_f32_ret__vgpr_val__sgpr_rsrc__0_voffset__sgpr_soffset:117; GFX6: ; %bb.0:118; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)119; GFX6-NEXT: buffer_atomic_fmax v0, v1, s[16:19], s20 idxen glc120; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0)121; GFX6-NEXT: s_setpc_b64 s[30:31]122;123; GFX7-LABEL: struct_ptr_buffer_atomic_add_f32_ret__vgpr_val__sgpr_rsrc__0_voffset__sgpr_soffset:124; GFX7: ; %bb.0:125; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)126; GFX7-NEXT: buffer_atomic_fmax v0, v1, s[16:19], s20 idxen glc127; GFX7-NEXT: s_waitcnt vmcnt(0)128; GFX7-NEXT: s_setpc_b64 s[30:31]129;130; GFX10-LABEL: struct_ptr_buffer_atomic_add_f32_ret__vgpr_val__sgpr_rsrc__0_voffset__sgpr_soffset:131; GFX10: ; %bb.0:132; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)133; GFX10-NEXT: buffer_atomic_fmax v0, v1, s[16:19], s20 idxen glc134; GFX10-NEXT: s_waitcnt vmcnt(0)135; GFX10-NEXT: s_setpc_b64 s[30:31]136;137; GFX11-LABEL: struct_ptr_buffer_atomic_add_f32_ret__vgpr_val__sgpr_rsrc__0_voffset__sgpr_soffset:138; GFX11: ; %bb.0:139; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)140; GFX11-NEXT: buffer_atomic_max_f32 v0, v1, s[0:3], s16 idxen glc141; GFX11-NEXT: s_waitcnt vmcnt(0)142; GFX11-NEXT: s_setpc_b64 s[30:31]143;144; GFX1200-LABEL: struct_ptr_buffer_atomic_add_f32_ret__vgpr_val__sgpr_rsrc__0_voffset__sgpr_soffset:145; GFX1200: ; %bb.0:146; GFX1200-NEXT: s_wait_loadcnt_dscnt 0x0147; GFX1200-NEXT: s_wait_expcnt 0x0148; GFX1200-NEXT: s_wait_samplecnt 0x0149; GFX1200-NEXT: s_wait_bvhcnt 0x0150; GFX1200-NEXT: s_wait_kmcnt 0x0151; GFX1200-NEXT: buffer_atomic_max_num_f32 v0, v1, s[0:3], s16 idxen th:TH_ATOMIC_RETURN152; GFX1200-NEXT: s_wait_loadcnt 0x0153; GFX1200-NEXT: s_setpc_b64 s[30:31]154;155; GFX1250-LABEL: struct_ptr_buffer_atomic_add_f32_ret__vgpr_val__sgpr_rsrc__0_voffset__sgpr_soffset:156; GFX1250: ; %bb.0:157; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0158; GFX1250-NEXT: s_wait_kmcnt 0x0159; GFX1250-NEXT: buffer_atomic_max_num_f32 v0, v1, s[0:3], s16 idxen th:TH_ATOMIC_RETURN160; GFX1250-NEXT: s_wait_loadcnt 0x0161; GFX1250-NEXT: s_set_pc_i64 s[30:31]162 %ret = call float @llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f32(float %val, ptr addrspace(8) %rsrc, i32 %vindex, i32 0, i32 %soffset, i32 0)163 ret float %ret164}165 166define float @struct_ptr_buffer_atomic_add_f32_ret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc(float %val, ptr addrspace(8) inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {167; GFX6-LABEL: struct_ptr_buffer_atomic_add_f32_ret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc:168; GFX6: ; %bb.0:169; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)170; GFX6-NEXT: buffer_atomic_fmax v0, v[1:2], s[16:19], s20 idxen offen glc slc171; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0)172; GFX6-NEXT: s_setpc_b64 s[30:31]173;174; GFX7-LABEL: struct_ptr_buffer_atomic_add_f32_ret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc:175; GFX7: ; %bb.0:176; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)177; GFX7-NEXT: buffer_atomic_fmax v0, v[1:2], s[16:19], s20 idxen offen glc slc178; GFX7-NEXT: s_waitcnt vmcnt(0)179; GFX7-NEXT: s_setpc_b64 s[30:31]180;181; GFX10-LABEL: struct_ptr_buffer_atomic_add_f32_ret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc:182; GFX10: ; %bb.0:183; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)184; GFX10-NEXT: buffer_atomic_fmax v0, v[1:2], s[16:19], s20 idxen offen glc slc185; GFX10-NEXT: s_waitcnt vmcnt(0)186; GFX10-NEXT: s_setpc_b64 s[30:31]187;188; GFX11-LABEL: struct_ptr_buffer_atomic_add_f32_ret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc:189; GFX11: ; %bb.0:190; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)191; GFX11-NEXT: buffer_atomic_max_f32 v0, v[1:2], s[0:3], s16 idxen offen glc slc192; GFX11-NEXT: s_waitcnt vmcnt(0)193; GFX11-NEXT: s_setpc_b64 s[30:31]194;195; GFX1200-LABEL: struct_ptr_buffer_atomic_add_f32_ret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc:196; GFX1200: ; %bb.0:197; GFX1200-NEXT: s_wait_loadcnt_dscnt 0x0198; GFX1200-NEXT: s_wait_expcnt 0x0199; GFX1200-NEXT: s_wait_samplecnt 0x0200; GFX1200-NEXT: s_wait_bvhcnt 0x0201; GFX1200-NEXT: s_wait_kmcnt 0x0202; GFX1200-NEXT: buffer_atomic_max_num_f32 v0, v[1:2], s[0:3], s16 idxen offen th:TH_ATOMIC_NT_RETURN203; GFX1200-NEXT: s_wait_loadcnt 0x0204; GFX1200-NEXT: s_setpc_b64 s[30:31]205;206; GFX1250-LABEL: struct_ptr_buffer_atomic_add_f32_ret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc:207; GFX1250: ; %bb.0:208; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0209; GFX1250-NEXT: s_wait_kmcnt 0x0210; GFX1250-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1211; GFX1250-NEXT: buffer_atomic_max_num_f32 v0, v[2:3], s[0:3], s16 idxen offen th:TH_ATOMIC_NT_RETURN212; GFX1250-NEXT: s_wait_loadcnt 0x0213; GFX1250-NEXT: s_set_pc_i64 s[30:31]214 %ret = call float @llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f32(float %val, ptr addrspace(8) %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 2)215 ret float %ret216}217 218define void @struct_ptr_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset(float %val, ptr addrspace(8) inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {219; GFX6-LABEL: struct_ptr_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset:220; GFX6: ; %bb.0:221; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)222; GFX6-NEXT: buffer_atomic_fmax v0, v[1:2], s[16:19], s20 idxen offen223; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0)224; GFX6-NEXT: s_setpc_b64 s[30:31]225;226; GFX7-LABEL: struct_ptr_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset:227; GFX7: ; %bb.0:228; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)229; GFX7-NEXT: buffer_atomic_fmax v0, v[1:2], s[16:19], s20 idxen offen230; GFX7-NEXT: s_waitcnt vmcnt(0)231; GFX7-NEXT: s_setpc_b64 s[30:31]232;233; GFX10-LABEL: struct_ptr_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset:234; GFX10: ; %bb.0:235; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)236; GFX10-NEXT: buffer_atomic_fmax v0, v[1:2], s[16:19], s20 idxen offen237; GFX10-NEXT: s_setpc_b64 s[30:31]238;239; GFX11-LABEL: struct_ptr_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset:240; GFX11: ; %bb.0:241; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)242; GFX11-NEXT: buffer_atomic_max_f32 v0, v[1:2], s[0:3], s16 idxen offen243; GFX11-NEXT: s_setpc_b64 s[30:31]244;245; GFX1200-LABEL: struct_ptr_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset:246; GFX1200: ; %bb.0:247; GFX1200-NEXT: s_wait_loadcnt_dscnt 0x0248; GFX1200-NEXT: s_wait_expcnt 0x0249; GFX1200-NEXT: s_wait_samplecnt 0x0250; GFX1200-NEXT: s_wait_bvhcnt 0x0251; GFX1200-NEXT: s_wait_kmcnt 0x0252; GFX1200-NEXT: buffer_atomic_max_num_f32 v0, v[1:2], s[0:3], s16 idxen offen253; GFX1200-NEXT: s_setpc_b64 s[30:31]254;255; GFX1250-LABEL: struct_ptr_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset:256; GFX1250: ; %bb.0:257; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0258; GFX1250-NEXT: s_wait_kmcnt 0x0259; GFX1250-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1260; GFX1250-NEXT: buffer_atomic_max_num_f32 v0, v[2:3], s[0:3], s16 idxen offen261; GFX1250-NEXT: s_set_pc_i64 s[30:31]262 %ret = call float @llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f32(float %val, ptr addrspace(8) %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)263 ret void264}265 266define void @struct_ptr_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset_add__sgpr_soffset(float %val, ptr addrspace(8) inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {267; GFX6-LABEL: struct_ptr_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset_add__sgpr_soffset:268; GFX6: ; %bb.0:269; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)270; GFX6-NEXT: buffer_atomic_fmax v0, v[1:2], s[16:19], s20 idxen offen offset:256271; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0)272; GFX6-NEXT: s_setpc_b64 s[30:31]273;274; GFX7-LABEL: struct_ptr_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset_add__sgpr_soffset:275; GFX7: ; %bb.0:276; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)277; GFX7-NEXT: buffer_atomic_fmax v0, v[1:2], s[16:19], s20 idxen offen offset:256278; GFX7-NEXT: s_waitcnt vmcnt(0)279; GFX7-NEXT: s_setpc_b64 s[30:31]280;281; GFX10-LABEL: struct_ptr_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset_add__sgpr_soffset:282; GFX10: ; %bb.0:283; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)284; GFX10-NEXT: buffer_atomic_fmax v0, v[1:2], s[16:19], s20 idxen offen offset:256285; GFX10-NEXT: s_setpc_b64 s[30:31]286;287; GFX11-LABEL: struct_ptr_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset_add__sgpr_soffset:288; GFX11: ; %bb.0:289; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)290; GFX11-NEXT: buffer_atomic_max_f32 v0, v[1:2], s[0:3], s16 idxen offen offset:256291; GFX11-NEXT: s_setpc_b64 s[30:31]292;293; GFX1200-LABEL: struct_ptr_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset_add__sgpr_soffset:294; GFX1200: ; %bb.0:295; GFX1200-NEXT: s_wait_loadcnt_dscnt 0x0296; GFX1200-NEXT: s_wait_expcnt 0x0297; GFX1200-NEXT: s_wait_samplecnt 0x0298; GFX1200-NEXT: s_wait_bvhcnt 0x0299; GFX1200-NEXT: s_wait_kmcnt 0x0300; GFX1200-NEXT: buffer_atomic_max_num_f32 v0, v[1:2], s[0:3], s16 idxen offen offset:256301; GFX1200-NEXT: s_setpc_b64 s[30:31]302;303; GFX1250-LABEL: struct_ptr_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset_add__sgpr_soffset:304; GFX1250: ; %bb.0:305; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0306; GFX1250-NEXT: s_wait_kmcnt 0x0307; GFX1250-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_add_nc_u32 v5, 0x100, v2308; GFX1250-NEXT: buffer_atomic_max_num_f32 v0, v[4:5], s[0:3], s16 idxen offen309; GFX1250-NEXT: s_set_pc_i64 s[30:31]310 %voffset.add = add i32 %voffset, 256311 %ret = call float @llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f32(float %val, ptr addrspace(8) %rsrc, i32 %vindex, i32 %voffset.add, i32 %soffset, i32 0)312 ret void313}314 315; Natural mapping, no voffset316define void @struct_ptr_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__0_voffset__sgpr_soffset(float %val, ptr addrspace(8) inreg %rsrc, i32 %vindex, i32 inreg %soffset) {317; GFX6-LABEL: struct_ptr_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__0_voffset__sgpr_soffset:318; GFX6: ; %bb.0:319; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)320; GFX6-NEXT: buffer_atomic_fmax v0, v1, s[16:19], s20 idxen321; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0)322; GFX6-NEXT: s_setpc_b64 s[30:31]323;324; GFX7-LABEL: struct_ptr_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__0_voffset__sgpr_soffset:325; GFX7: ; %bb.0:326; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)327; GFX7-NEXT: buffer_atomic_fmax v0, v1, s[16:19], s20 idxen328; GFX7-NEXT: s_waitcnt vmcnt(0)329; GFX7-NEXT: s_setpc_b64 s[30:31]330;331; GFX10-LABEL: struct_ptr_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__0_voffset__sgpr_soffset:332; GFX10: ; %bb.0:333; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)334; GFX10-NEXT: buffer_atomic_fmax v0, v1, s[16:19], s20 idxen335; GFX10-NEXT: s_setpc_b64 s[30:31]336;337; GFX11-LABEL: struct_ptr_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__0_voffset__sgpr_soffset:338; GFX11: ; %bb.0:339; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)340; GFX11-NEXT: buffer_atomic_max_f32 v0, v1, s[0:3], s16 idxen341; GFX11-NEXT: s_setpc_b64 s[30:31]342;343; GFX1200-LABEL: struct_ptr_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__0_voffset__sgpr_soffset:344; GFX1200: ; %bb.0:345; GFX1200-NEXT: s_wait_loadcnt_dscnt 0x0346; GFX1200-NEXT: s_wait_expcnt 0x0347; GFX1200-NEXT: s_wait_samplecnt 0x0348; GFX1200-NEXT: s_wait_bvhcnt 0x0349; GFX1200-NEXT: s_wait_kmcnt 0x0350; GFX1200-NEXT: buffer_atomic_max_num_f32 v0, v1, s[0:3], s16 idxen351; GFX1200-NEXT: s_setpc_b64 s[30:31]352;353; GFX1250-LABEL: struct_ptr_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__0_voffset__sgpr_soffset:354; GFX1250: ; %bb.0:355; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0356; GFX1250-NEXT: s_wait_kmcnt 0x0357; GFX1250-NEXT: buffer_atomic_max_num_f32 v0, v1, s[0:3], s16 idxen358; GFX1250-NEXT: s_set_pc_i64 s[30:31]359 %ret = call float @llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f32(float %val, ptr addrspace(8) %rsrc, i32 %vindex, i32 0, i32 %soffset, i32 0)360 ret void361}362 363define void @struct_ptr_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc(float %val, ptr addrspace(8) inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {364; GFX6-LABEL: struct_ptr_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc:365; GFX6: ; %bb.0:366; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)367; GFX6-NEXT: buffer_atomic_fmax v0, v[1:2], s[16:19], s20 idxen offen slc368; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0)369; GFX6-NEXT: s_setpc_b64 s[30:31]370;371; GFX7-LABEL: struct_ptr_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc:372; GFX7: ; %bb.0:373; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)374; GFX7-NEXT: buffer_atomic_fmax v0, v[1:2], s[16:19], s20 idxen offen slc375; GFX7-NEXT: s_waitcnt vmcnt(0)376; GFX7-NEXT: s_setpc_b64 s[30:31]377;378; GFX10-LABEL: struct_ptr_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc:379; GFX10: ; %bb.0:380; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)381; GFX10-NEXT: buffer_atomic_fmax v0, v[1:2], s[16:19], s20 idxen offen slc382; GFX10-NEXT: s_setpc_b64 s[30:31]383;384; GFX11-LABEL: struct_ptr_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc:385; GFX11: ; %bb.0:386; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)387; GFX11-NEXT: buffer_atomic_max_f32 v0, v[1:2], s[0:3], s16 idxen offen slc388; GFX11-NEXT: s_setpc_b64 s[30:31]389;390; GFX1200-LABEL: struct_ptr_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc:391; GFX1200: ; %bb.0:392; GFX1200-NEXT: s_wait_loadcnt_dscnt 0x0393; GFX1200-NEXT: s_wait_expcnt 0x0394; GFX1200-NEXT: s_wait_samplecnt 0x0395; GFX1200-NEXT: s_wait_bvhcnt 0x0396; GFX1200-NEXT: s_wait_kmcnt 0x0397; GFX1200-NEXT: buffer_atomic_max_num_f32 v0, v[1:2], s[0:3], s16 idxen offen th:TH_ATOMIC_NT398; GFX1200-NEXT: s_setpc_b64 s[30:31]399;400; GFX1250-LABEL: struct_ptr_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc:401; GFX1250: ; %bb.0:402; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0403; GFX1250-NEXT: s_wait_kmcnt 0x0404; GFX1250-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1405; GFX1250-NEXT: buffer_atomic_max_num_f32 v0, v[2:3], s[0:3], s16 idxen offen th:TH_ATOMIC_NT406; GFX1250-NEXT: s_set_pc_i64 s[30:31]407 %ret = call float @llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f32(float %val, ptr addrspace(8) %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 2)408 ret void409}410 411; Test waterfall loop on resource412define float @struct_ptr_buffer_atomic_add_f32_ret__vgpr_val__vgpr_rsrc__vgpr_voffset_add__sgpr_soffset(float %val, ptr addrspace(8) %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {413; GFX6-LABEL: struct_ptr_buffer_atomic_add_f32_ret__vgpr_val__vgpr_rsrc__vgpr_voffset_add__sgpr_soffset:414; GFX6: ; %bb.0:415; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)416; GFX6-NEXT: s_mov_b64 s[6:7], exec417; GFX6-NEXT: .LBB8_1: ; =>This Inner Loop Header: Depth=1418; GFX6-NEXT: v_readfirstlane_b32 s8, v1419; GFX6-NEXT: v_readfirstlane_b32 s9, v2420; GFX6-NEXT: v_readfirstlane_b32 s10, v3421; GFX6-NEXT: v_readfirstlane_b32 s11, v4422; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, s[8:9], v[1:2]423; GFX6-NEXT: v_cmp_eq_u64_e64 s[4:5], s[10:11], v[3:4]424; GFX6-NEXT: s_and_b64 s[4:5], vcc, s[4:5]425; GFX6-NEXT: s_and_saveexec_b64 s[4:5], s[4:5]426; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0)427; GFX6-NEXT: buffer_atomic_fmax v0, v[5:6], s[8:11], s16 idxen offen offset:256 glc428; GFX6-NEXT: ; implicit-def: $vgpr1_vgpr2_vgpr3_vgpr4429; GFX6-NEXT: ; implicit-def: $vgpr5_vgpr6430; GFX6-NEXT: s_xor_b64 exec, exec, s[4:5]431; GFX6-NEXT: s_cbranch_execnz .LBB8_1432; GFX6-NEXT: ; %bb.2:433; GFX6-NEXT: s_mov_b64 exec, s[6:7]434; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0)435; GFX6-NEXT: s_setpc_b64 s[30:31]436;437; GFX7-LABEL: struct_ptr_buffer_atomic_add_f32_ret__vgpr_val__vgpr_rsrc__vgpr_voffset_add__sgpr_soffset:438; GFX7: ; %bb.0:439; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)440; GFX7-NEXT: s_mov_b64 s[6:7], exec441; GFX7-NEXT: .LBB8_1: ; =>This Inner Loop Header: Depth=1442; GFX7-NEXT: v_readfirstlane_b32 s8, v1443; GFX7-NEXT: v_readfirstlane_b32 s9, v2444; GFX7-NEXT: v_readfirstlane_b32 s10, v3445; GFX7-NEXT: v_readfirstlane_b32 s11, v4446; GFX7-NEXT: v_cmp_eq_u64_e32 vcc, s[8:9], v[1:2]447; GFX7-NEXT: v_cmp_eq_u64_e64 s[4:5], s[10:11], v[3:4]448; GFX7-NEXT: s_and_b64 s[4:5], vcc, s[4:5]449; GFX7-NEXT: s_and_saveexec_b64 s[4:5], s[4:5]450; GFX7-NEXT: s_waitcnt vmcnt(0)451; GFX7-NEXT: buffer_atomic_fmax v0, v[5:6], s[8:11], s16 idxen offen offset:256 glc452; GFX7-NEXT: ; implicit-def: $vgpr1_vgpr2_vgpr3_vgpr4453; GFX7-NEXT: ; implicit-def: $vgpr5_vgpr6454; GFX7-NEXT: s_xor_b64 exec, exec, s[4:5]455; GFX7-NEXT: s_cbranch_execnz .LBB8_1456; GFX7-NEXT: ; %bb.2:457; GFX7-NEXT: s_mov_b64 exec, s[6:7]458; GFX7-NEXT: s_waitcnt vmcnt(0)459; GFX7-NEXT: s_setpc_b64 s[30:31]460;461; GFX10-LABEL: struct_ptr_buffer_atomic_add_f32_ret__vgpr_val__vgpr_rsrc__vgpr_voffset_add__sgpr_soffset:462; GFX10: ; %bb.0:463; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)464; GFX10-NEXT: s_mov_b32 s5, exec_lo465; GFX10-NEXT: .LBB8_1: ; =>This Inner Loop Header: Depth=1466; GFX10-NEXT: v_readfirstlane_b32 s8, v1467; GFX10-NEXT: v_readfirstlane_b32 s9, v2468; GFX10-NEXT: v_readfirstlane_b32 s10, v3469; GFX10-NEXT: v_readfirstlane_b32 s11, v4470; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[8:9], v[1:2]471; GFX10-NEXT: v_cmp_eq_u64_e64 s4, s[10:11], v[3:4]472; GFX10-NEXT: s_and_b32 s4, vcc_lo, s4473; GFX10-NEXT: s_and_saveexec_b32 s4, s4474; GFX10-NEXT: s_waitcnt vmcnt(0)475; GFX10-NEXT: buffer_atomic_fmax v0, v[5:6], s[8:11], s16 idxen offen offset:256 glc476; GFX10-NEXT: ; implicit-def: $vgpr1_vgpr2_vgpr3_vgpr4477; GFX10-NEXT: ; implicit-def: $vgpr5_vgpr6478; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)479; GFX10-NEXT: s_xor_b32 exec_lo, exec_lo, s4480; GFX10-NEXT: s_cbranch_execnz .LBB8_1481; GFX10-NEXT: ; %bb.2:482; GFX10-NEXT: s_mov_b32 exec_lo, s5483; GFX10-NEXT: s_waitcnt vmcnt(0)484; GFX10-NEXT: s_setpc_b64 s[30:31]485;486; GFX11-LABEL: struct_ptr_buffer_atomic_add_f32_ret__vgpr_val__vgpr_rsrc__vgpr_voffset_add__sgpr_soffset:487; GFX11: ; %bb.0:488; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)489; GFX11-NEXT: s_mov_b32 s2, exec_lo490; GFX11-NEXT: .LBB8_1: ; =>This Inner Loop Header: Depth=1491; GFX11-NEXT: v_readfirstlane_b32 s4, v1492; GFX11-NEXT: v_readfirstlane_b32 s5, v2493; GFX11-NEXT: v_readfirstlane_b32 s6, v3494; GFX11-NEXT: v_readfirstlane_b32 s7, v4495; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)496; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[1:2]497; GFX11-NEXT: v_cmp_eq_u64_e64 s1, s[6:7], v[3:4]498; GFX11-NEXT: s_and_b32 s1, vcc_lo, s1499; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)500; GFX11-NEXT: s_and_saveexec_b32 s1, s1501; GFX11-NEXT: s_waitcnt vmcnt(0)502; GFX11-NEXT: buffer_atomic_max_f32 v0, v[5:6], s[4:7], s0 idxen offen offset:256 glc503; GFX11-NEXT: ; implicit-def: $vgpr1_vgpr2_vgpr3_vgpr4504; GFX11-NEXT: ; implicit-def: $vgpr5_vgpr6505; GFX11-NEXT: s_xor_b32 exec_lo, exec_lo, s1506; GFX11-NEXT: s_cbranch_execnz .LBB8_1507; GFX11-NEXT: ; %bb.2:508; GFX11-NEXT: s_mov_b32 exec_lo, s2509; GFX11-NEXT: s_waitcnt vmcnt(0)510; GFX11-NEXT: s_setpc_b64 s[30:31]511;512; GFX1200-LABEL: struct_ptr_buffer_atomic_add_f32_ret__vgpr_val__vgpr_rsrc__vgpr_voffset_add__sgpr_soffset:513; GFX1200: ; %bb.0:514; GFX1200-NEXT: s_wait_loadcnt_dscnt 0x0515; GFX1200-NEXT: s_wait_expcnt 0x0516; GFX1200-NEXT: s_wait_samplecnt 0x0517; GFX1200-NEXT: s_wait_bvhcnt 0x0518; GFX1200-NEXT: s_wait_kmcnt 0x0519; GFX1200-NEXT: s_mov_b32 s2, exec_lo520; GFX1200-NEXT: .LBB8_1: ; =>This Inner Loop Header: Depth=1521; GFX1200-NEXT: v_readfirstlane_b32 s4, v1522; GFX1200-NEXT: v_readfirstlane_b32 s5, v2523; GFX1200-NEXT: v_readfirstlane_b32 s6, v3524; GFX1200-NEXT: v_readfirstlane_b32 s7, v4525; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)526; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)527; GFX1200-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[1:2]528; GFX1200-NEXT: v_cmp_eq_u64_e64 s1, s[6:7], v[3:4]529; GFX1200-NEXT: s_and_b32 s1, vcc_lo, s1530; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)531; GFX1200-NEXT: s_and_saveexec_b32 s1, s1532; GFX1200-NEXT: s_wait_loadcnt 0x0533; GFX1200-NEXT: buffer_atomic_max_num_f32 v0, v[5:6], s[4:7], s0 idxen offen offset:256 th:TH_ATOMIC_RETURN534; GFX1200-NEXT: ; implicit-def: $vgpr1_vgpr2_vgpr3_vgpr4535; GFX1200-NEXT: ; implicit-def: $vgpr5_vgpr6536; GFX1200-NEXT: s_xor_b32 exec_lo, exec_lo, s1537; GFX1200-NEXT: s_cbranch_execnz .LBB8_1538; GFX1200-NEXT: ; %bb.2:539; GFX1200-NEXT: s_mov_b32 exec_lo, s2540; GFX1200-NEXT: s_wait_loadcnt 0x0541; GFX1200-NEXT: s_setpc_b64 s[30:31]542;543; GFX1250-LABEL: struct_ptr_buffer_atomic_add_f32_ret__vgpr_val__vgpr_rsrc__vgpr_voffset_add__sgpr_soffset:544; GFX1250: ; %bb.0:545; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0546; GFX1250-NEXT: s_wait_kmcnt 0x0547; GFX1250-NEXT: v_dual_mov_b32 v8, v5 :: v_dual_mov_b32 v5, v4548; GFX1250-NEXT: v_dual_mov_b32 v4, v3 :: v_dual_mov_b32 v3, v2549; GFX1250-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_add_nc_u32 v9, 0x100, v6550; GFX1250-NEXT: s_mov_b32 s2, exec_lo551; GFX1250-NEXT: .LBB8_1: ; =>This Inner Loop Header: Depth=1552; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)553; GFX1250-NEXT: v_readfirstlane_b32 s4, v2554; GFX1250-NEXT: v_readfirstlane_b32 s5, v3555; GFX1250-NEXT: v_readfirstlane_b32 s6, v4556; GFX1250-NEXT: v_readfirstlane_b32 s7, v5557; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)558; GFX1250-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[2:3]559; GFX1250-NEXT: v_cmp_eq_u64_e64 s1, s[6:7], v[4:5]560; GFX1250-NEXT: s_and_b32 s1, vcc_lo, s1561; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)562; GFX1250-NEXT: s_and_saveexec_b32 s1, s1563; GFX1250-NEXT: s_wait_loadcnt 0x0564; GFX1250-NEXT: buffer_atomic_max_num_f32 v0, v[8:9], s[4:7], s0 idxen offen th:TH_ATOMIC_RETURN565; GFX1250-NEXT: ; implicit-def: $vgpr2_vgpr3_vgpr4_vgpr5566; GFX1250-NEXT: ; implicit-def: $vgpr8_vgpr9567; GFX1250-NEXT: s_wait_xcnt 0x0568; GFX1250-NEXT: s_xor_b32 exec_lo, exec_lo, s1569; GFX1250-NEXT: s_cbranch_execnz .LBB8_1570; GFX1250-NEXT: ; %bb.2:571; GFX1250-NEXT: s_mov_b32 exec_lo, s2572; GFX1250-NEXT: s_wait_loadcnt 0x0573; GFX1250-NEXT: s_set_pc_i64 s[30:31]574 %voffset.add = add i32 %voffset, 256575 %ret = call float @llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f32(float %val, ptr addrspace(8) %rsrc, i32 %vindex, i32 %voffset.add, i32 %soffset, i32 0)576 ret float %ret577}578 579; Test waterfall loop on soffset580define float @struct_ptr_buffer_atomic_add_f32_ret__vgpr_val__sgpr_rsrc__vgpr_voffset_add__vgpr_soffset(float %val, ptr addrspace(8) %rsrc, i32 %vindex, i32 %voffset, i32 %soffset) {581; GFX6-LABEL: struct_ptr_buffer_atomic_add_f32_ret__vgpr_val__sgpr_rsrc__vgpr_voffset_add__vgpr_soffset:582; GFX6: ; %bb.0:583; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)584; GFX6-NEXT: s_mov_b64 s[6:7], exec585; GFX6-NEXT: .LBB9_1: ; =>This Inner Loop Header: Depth=1586; GFX6-NEXT: v_readfirstlane_b32 s8, v1587; GFX6-NEXT: v_readfirstlane_b32 s9, v2588; GFX6-NEXT: v_readfirstlane_b32 s10, v3589; GFX6-NEXT: v_readfirstlane_b32 s11, v4590; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, s[8:9], v[1:2]591; GFX6-NEXT: v_cmp_eq_u64_e64 s[4:5], s[10:11], v[3:4]592; GFX6-NEXT: v_readfirstlane_b32 s12, v7593; GFX6-NEXT: s_and_b64 s[4:5], vcc, s[4:5]594; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, s12, v7595; GFX6-NEXT: s_and_b64 s[4:5], s[4:5], vcc596; GFX6-NEXT: s_and_saveexec_b64 s[4:5], s[4:5]597; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0)598; GFX6-NEXT: buffer_atomic_fmax v0, v[5:6], s[8:11], s12 idxen offen offset:256 glc599; GFX6-NEXT: ; implicit-def: $vgpr1_vgpr2_vgpr3_vgpr4600; GFX6-NEXT: ; implicit-def: $vgpr7601; GFX6-NEXT: ; implicit-def: $vgpr5_vgpr6602; GFX6-NEXT: s_xor_b64 exec, exec, s[4:5]603; GFX6-NEXT: s_cbranch_execnz .LBB9_1604; GFX6-NEXT: ; %bb.2:605; GFX6-NEXT: s_mov_b64 exec, s[6:7]606; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0)607; GFX6-NEXT: s_setpc_b64 s[30:31]608;609; GFX7-LABEL: struct_ptr_buffer_atomic_add_f32_ret__vgpr_val__sgpr_rsrc__vgpr_voffset_add__vgpr_soffset:610; GFX7: ; %bb.0:611; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)612; GFX7-NEXT: s_mov_b64 s[6:7], exec613; GFX7-NEXT: .LBB9_1: ; =>This Inner Loop Header: Depth=1614; GFX7-NEXT: v_readfirstlane_b32 s8, v1615; GFX7-NEXT: v_readfirstlane_b32 s9, v2616; GFX7-NEXT: v_readfirstlane_b32 s10, v3617; GFX7-NEXT: v_readfirstlane_b32 s11, v4618; GFX7-NEXT: v_cmp_eq_u64_e32 vcc, s[8:9], v[1:2]619; GFX7-NEXT: v_cmp_eq_u64_e64 s[4:5], s[10:11], v[3:4]620; GFX7-NEXT: v_readfirstlane_b32 s12, v7621; GFX7-NEXT: s_and_b64 s[4:5], vcc, s[4:5]622; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, s12, v7623; GFX7-NEXT: s_and_b64 s[4:5], s[4:5], vcc624; GFX7-NEXT: s_and_saveexec_b64 s[4:5], s[4:5]625; GFX7-NEXT: s_waitcnt vmcnt(0)626; GFX7-NEXT: buffer_atomic_fmax v0, v[5:6], s[8:11], s12 idxen offen offset:256 glc627; GFX7-NEXT: ; implicit-def: $vgpr1_vgpr2_vgpr3_vgpr4628; GFX7-NEXT: ; implicit-def: $vgpr7629; GFX7-NEXT: ; implicit-def: $vgpr5_vgpr6630; GFX7-NEXT: s_xor_b64 exec, exec, s[4:5]631; GFX7-NEXT: s_cbranch_execnz .LBB9_1632; GFX7-NEXT: ; %bb.2:633; GFX7-NEXT: s_mov_b64 exec, s[6:7]634; GFX7-NEXT: s_waitcnt vmcnt(0)635; GFX7-NEXT: s_setpc_b64 s[30:31]636;637; GFX10-LABEL: struct_ptr_buffer_atomic_add_f32_ret__vgpr_val__sgpr_rsrc__vgpr_voffset_add__vgpr_soffset:638; GFX10: ; %bb.0:639; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)640; GFX10-NEXT: s_mov_b32 s6, exec_lo641; GFX10-NEXT: .LBB9_1: ; =>This Inner Loop Header: Depth=1642; GFX10-NEXT: v_readfirstlane_b32 s8, v1643; GFX10-NEXT: v_readfirstlane_b32 s9, v2644; GFX10-NEXT: v_readfirstlane_b32 s10, v3645; GFX10-NEXT: v_readfirstlane_b32 s11, v4646; GFX10-NEXT: v_readfirstlane_b32 s7, v7647; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[8:9], v[1:2]648; GFX10-NEXT: v_cmp_eq_u64_e64 s4, s[10:11], v[3:4]649; GFX10-NEXT: v_cmp_eq_u32_e64 s5, s7, v7650; GFX10-NEXT: s_and_b32 s4, vcc_lo, s4651; GFX10-NEXT: s_and_b32 s4, s4, s5652; GFX10-NEXT: s_and_saveexec_b32 s4, s4653; GFX10-NEXT: s_waitcnt vmcnt(0)654; GFX10-NEXT: buffer_atomic_fmax v0, v[5:6], s[8:11], s7 idxen offen offset:256 glc655; GFX10-NEXT: ; implicit-def: $vgpr1_vgpr2_vgpr3_vgpr4656; GFX10-NEXT: ; implicit-def: $vgpr7657; GFX10-NEXT: ; implicit-def: $vgpr5_vgpr6658; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)659; GFX10-NEXT: s_xor_b32 exec_lo, exec_lo, s4660; GFX10-NEXT: s_cbranch_execnz .LBB9_1661; GFX10-NEXT: ; %bb.2:662; GFX10-NEXT: s_mov_b32 exec_lo, s6663; GFX10-NEXT: s_waitcnt vmcnt(0)664; GFX10-NEXT: s_setpc_b64 s[30:31]665;666; GFX11-LABEL: struct_ptr_buffer_atomic_add_f32_ret__vgpr_val__sgpr_rsrc__vgpr_voffset_add__vgpr_soffset:667; GFX11: ; %bb.0:668; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)669; GFX11-NEXT: s_mov_b32 s2, exec_lo670; GFX11-NEXT: .LBB9_1: ; =>This Inner Loop Header: Depth=1671; GFX11-NEXT: v_readfirstlane_b32 s4, v1672; GFX11-NEXT: v_readfirstlane_b32 s5, v2673; GFX11-NEXT: v_readfirstlane_b32 s6, v3674; GFX11-NEXT: v_readfirstlane_b32 s7, v4675; GFX11-NEXT: v_readfirstlane_b32 s3, v7676; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)677; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[1:2]678; GFX11-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[3:4]679; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)680; GFX11-NEXT: v_cmp_eq_u32_e64 s1, s3, v7681; GFX11-NEXT: s_and_b32 s0, vcc_lo, s0682; GFX11-NEXT: s_and_b32 s0, s0, s1683; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)684; GFX11-NEXT: s_and_saveexec_b32 s0, s0685; GFX11-NEXT: s_waitcnt vmcnt(0)686; GFX11-NEXT: buffer_atomic_max_f32 v0, v[5:6], s[4:7], s3 idxen offen offset:256 glc687; GFX11-NEXT: ; implicit-def: $vgpr1_vgpr2_vgpr3_vgpr4688; GFX11-NEXT: ; implicit-def: $vgpr7689; GFX11-NEXT: ; implicit-def: $vgpr5_vgpr6690; GFX11-NEXT: s_xor_b32 exec_lo, exec_lo, s0691; GFX11-NEXT: s_cbranch_execnz .LBB9_1692; GFX11-NEXT: ; %bb.2:693; GFX11-NEXT: s_mov_b32 exec_lo, s2694; GFX11-NEXT: s_waitcnt vmcnt(0)695; GFX11-NEXT: s_setpc_b64 s[30:31]696;697; GFX1200-LABEL: struct_ptr_buffer_atomic_add_f32_ret__vgpr_val__sgpr_rsrc__vgpr_voffset_add__vgpr_soffset:698; GFX1200: ; %bb.0:699; GFX1200-NEXT: s_wait_loadcnt_dscnt 0x0700; GFX1200-NEXT: s_wait_expcnt 0x0701; GFX1200-NEXT: s_wait_samplecnt 0x0702; GFX1200-NEXT: s_wait_bvhcnt 0x0703; GFX1200-NEXT: s_wait_kmcnt 0x0704; GFX1200-NEXT: s_mov_b32 s2, exec_lo705; GFX1200-NEXT: .LBB9_1: ; =>This Inner Loop Header: Depth=1706; GFX1200-NEXT: v_readfirstlane_b32 s4, v1707; GFX1200-NEXT: v_readfirstlane_b32 s5, v2708; GFX1200-NEXT: v_readfirstlane_b32 s6, v3709; GFX1200-NEXT: v_readfirstlane_b32 s7, v4710; GFX1200-NEXT: v_readfirstlane_b32 s3, v7711; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)712; GFX1200-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[1:2]713; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)714; GFX1200-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[3:4]715; GFX1200-NEXT: v_cmp_eq_u32_e64 s1, s3, v7716; GFX1200-NEXT: s_and_b32 s0, vcc_lo, s0717; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)718; GFX1200-NEXT: s_and_b32 s0, s0, s1719; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)720; GFX1200-NEXT: s_and_saveexec_b32 s0, s0721; GFX1200-NEXT: s_wait_loadcnt 0x0722; GFX1200-NEXT: buffer_atomic_max_num_f32 v0, v[5:6], s[4:7], s3 idxen offen offset:256 th:TH_ATOMIC_RETURN723; GFX1200-NEXT: ; implicit-def: $vgpr1_vgpr2_vgpr3_vgpr4724; GFX1200-NEXT: ; implicit-def: $vgpr7725; GFX1200-NEXT: ; implicit-def: $vgpr5_vgpr6726; GFX1200-NEXT: s_xor_b32 exec_lo, exec_lo, s0727; GFX1200-NEXT: s_cbranch_execnz .LBB9_1728; GFX1200-NEXT: ; %bb.2:729; GFX1200-NEXT: s_mov_b32 exec_lo, s2730; GFX1200-NEXT: s_wait_loadcnt 0x0731; GFX1200-NEXT: s_setpc_b64 s[30:31]732;733; GFX1250-LABEL: struct_ptr_buffer_atomic_add_f32_ret__vgpr_val__sgpr_rsrc__vgpr_voffset_add__vgpr_soffset:734; GFX1250: ; %bb.0:735; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0736; GFX1250-NEXT: s_wait_kmcnt 0x0737; GFX1250-NEXT: v_dual_mov_b32 v8, v5 :: v_dual_mov_b32 v5, v4738; GFX1250-NEXT: v_dual_mov_b32 v4, v3 :: v_dual_mov_b32 v3, v2739; GFX1250-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_add_nc_u32 v9, 0x100, v6740; GFX1250-NEXT: s_mov_b32 s2, exec_lo741; GFX1250-NEXT: .LBB9_1: ; =>This Inner Loop Header: Depth=1742; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)743; GFX1250-NEXT: v_readfirstlane_b32 s4, v2744; GFX1250-NEXT: v_readfirstlane_b32 s5, v3745; GFX1250-NEXT: v_readfirstlane_b32 s6, v4746; GFX1250-NEXT: v_readfirstlane_b32 s7, v5747; GFX1250-NEXT: v_readfirstlane_b32 s3, v7748; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)749; GFX1250-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[2:3]750; GFX1250-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[4:5]751; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)752; GFX1250-NEXT: v_cmp_eq_u32_e64 s1, s3, v7753; GFX1250-NEXT: s_and_b32 s0, vcc_lo, s0754; GFX1250-NEXT: s_and_b32 s0, s0, s1755; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)756; GFX1250-NEXT: s_and_saveexec_b32 s0, s0757; GFX1250-NEXT: s_wait_loadcnt 0x0758; GFX1250-NEXT: buffer_atomic_max_num_f32 v0, v[8:9], s[4:7], s3 idxen offen th:TH_ATOMIC_RETURN759; GFX1250-NEXT: ; implicit-def: $vgpr2_vgpr3_vgpr4_vgpr5760; GFX1250-NEXT: ; implicit-def: $vgpr7761; GFX1250-NEXT: ; implicit-def: $vgpr8_vgpr9762; GFX1250-NEXT: s_wait_xcnt 0x0763; GFX1250-NEXT: s_xor_b32 exec_lo, exec_lo, s0764; GFX1250-NEXT: s_cbranch_execnz .LBB9_1765; GFX1250-NEXT: ; %bb.2:766; GFX1250-NEXT: s_mov_b32 exec_lo, s2767; GFX1250-NEXT: s_wait_loadcnt 0x0768; GFX1250-NEXT: s_set_pc_i64 s[30:31]769 %voffset.add = add i32 %voffset, 256770 %ret = call float @llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f32(float %val, ptr addrspace(8) %rsrc, i32 %vindex, i32 %voffset.add, i32 %soffset, i32 0)771 ret float %ret772}773 774declare float @llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f32(float, ptr addrspace(8), i32, i32, i32, i32 immarg)775