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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52;RUN: llc < %s -mtriple=amdgcn -mcpu=verde | FileCheck -check-prefixes=CHECK,SI %s3;RUN: llc < %s -mtriple=amdgcn -mcpu=tonga | FileCheck -check-prefixes=CHECK,VI %s4 5define amdgpu_ps void @buffer_store(ptr addrspace(8) inreg, <4 x float>, <4 x float>, <4 x float>) {6; CHECK-LABEL: buffer_store:7; CHECK: ; %bb.0: ; %main_body8; CHECK-NEXT: v_mov_b32_e32 v12, 09; CHECK-NEXT: buffer_store_format_xyzw v[0:3], v12, s[0:3], 0 idxen10; CHECK-NEXT: buffer_store_format_xyzw v[4:7], v12, s[0:3], 0 idxen glc11; CHECK-NEXT: buffer_store_format_xyzw v[8:11], v12, s[0:3], 0 idxen slc12; CHECK-NEXT: s_endpgm13main_body:14 call void @llvm.amdgcn.struct.ptr.buffer.store.format.v4f32(<4 x float> %1, ptr addrspace(8) %0, i32 0, i32 0, i32 0, i32 0)15 call void @llvm.amdgcn.struct.ptr.buffer.store.format.v4f32(<4 x float> %2, ptr addrspace(8) %0, i32 0, i32 0, i32 0, i32 1)16 call void @llvm.amdgcn.struct.ptr.buffer.store.format.v4f32(<4 x float> %3, ptr addrspace(8) %0, i32 0, i32 0, i32 0, i32 2)17 ret void18}19 20define amdgpu_ps void @buffer_store_immoffs(ptr addrspace(8) inreg, <4 x float>) {21; CHECK-LABEL: buffer_store_immoffs:22; CHECK: ; %bb.0: ; %main_body23; CHECK-NEXT: v_mov_b32_e32 v4, 024; CHECK-NEXT: buffer_store_format_xyzw v[0:3], v4, s[0:3], 0 idxen offset:4225; CHECK-NEXT: s_endpgm26main_body:27 call void @llvm.amdgcn.struct.ptr.buffer.store.format.v4f32(<4 x float> %1, ptr addrspace(8) %0, i32 0, i32 42, i32 0, i32 0)28 ret void29}30 31define amdgpu_ps void @buffer_store_idx(ptr addrspace(8) inreg, <4 x float>, i32) {32; CHECK-LABEL: buffer_store_idx:33; CHECK: ; %bb.0: ; %main_body34; CHECK-NEXT: buffer_store_format_xyzw v[0:3], v4, s[0:3], 0 idxen35; CHECK-NEXT: s_endpgm36main_body:37 call void @llvm.amdgcn.struct.ptr.buffer.store.format.v4f32(<4 x float> %1, ptr addrspace(8) %0, i32 %2, i32 0, i32 0, i32 0)38 ret void39}40 41define amdgpu_ps void @buffer_store_ofs(ptr addrspace(8) inreg, <4 x float>, i32) {42; CHECK-LABEL: buffer_store_ofs:43; CHECK: ; %bb.0: ; %main_body44; CHECK-NEXT: s_mov_b32 s4, 045; CHECK-NEXT: v_mov_b32_e32 v5, v446; CHECK-NEXT: v_mov_b32_e32 v4, s447; CHECK-NEXT: buffer_store_format_xyzw v[0:3], v[4:5], s[0:3], 0 idxen offen48; CHECK-NEXT: s_endpgm49main_body:50 call void @llvm.amdgcn.struct.ptr.buffer.store.format.v4f32(<4 x float> %1, ptr addrspace(8) %0, i32 0, i32 %2, i32 0, i32 0)51 ret void52}53 54define amdgpu_ps void @buffer_store_both(ptr addrspace(8) inreg, <4 x float>, i32, i32) {55; CHECK-LABEL: buffer_store_both:56; CHECK: ; %bb.0: ; %main_body57; CHECK-NEXT: buffer_store_format_xyzw v[0:3], v[4:5], s[0:3], 0 idxen offen58; CHECK-NEXT: s_endpgm59main_body:60 call void @llvm.amdgcn.struct.ptr.buffer.store.format.v4f32(<4 x float> %1, ptr addrspace(8) %0, i32 %2, i32 %3, i32 0, i32 0)61 ret void62}63 64define amdgpu_ps void @buffer_store_both_reversed(ptr addrspace(8) inreg, <4 x float>, i32, i32) {65; CHECK-LABEL: buffer_store_both_reversed:66; CHECK: ; %bb.0: ; %main_body67; CHECK-NEXT: v_mov_b32_e32 v6, v468; CHECK-NEXT: buffer_store_format_xyzw v[0:3], v[5:6], s[0:3], 0 idxen offen69; CHECK-NEXT: s_endpgm70main_body:71 call void @llvm.amdgcn.struct.ptr.buffer.store.format.v4f32(<4 x float> %1, ptr addrspace(8) %0, i32 %3, i32 %2, i32 0, i32 0)72 ret void73}74 75; Ideally, the register allocator would avoid the wait here76;77define amdgpu_ps void @buffer_store_wait(ptr addrspace(8) inreg, <4 x float>, i32, i32, i32) {78; SI-LABEL: buffer_store_wait:79; SI: ; %bb.0: ; %main_body80; SI-NEXT: buffer_store_format_xyzw v[0:3], v4, s[0:3], 0 idxen81; SI-NEXT: s_waitcnt expcnt(0)82; SI-NEXT: buffer_load_format_xyzw v[0:3], v5, s[0:3], 0 idxen83; SI-NEXT: s_waitcnt vmcnt(0)84; SI-NEXT: buffer_store_format_xyzw v[0:3], v6, s[0:3], 0 idxen85; SI-NEXT: s_endpgm86;87; VI-LABEL: buffer_store_wait:88; VI: ; %bb.0: ; %main_body89; VI-NEXT: buffer_store_format_xyzw v[0:3], v4, s[0:3], 0 idxen90; VI-NEXT: buffer_load_format_xyzw v[0:3], v5, s[0:3], 0 idxen91; VI-NEXT: s_waitcnt vmcnt(0)92; VI-NEXT: buffer_store_format_xyzw v[0:3], v6, s[0:3], 0 idxen93; VI-NEXT: s_endpgm94main_body:95 call void @llvm.amdgcn.struct.ptr.buffer.store.format.v4f32(<4 x float> %1, ptr addrspace(8) %0, i32 %2, i32 0, i32 0, i32 0)96 %data = call <4 x float> @llvm.amdgcn.struct.ptr.buffer.load.format.v4f32(ptr addrspace(8) %0, i32 %3, i32 0, i32 0, i32 0)97 call void @llvm.amdgcn.struct.ptr.buffer.store.format.v4f32(<4 x float> %data, ptr addrspace(8) %0, i32 %4, i32 0, i32 0, i32 0)98 ret void99}100 101define amdgpu_ps void @buffer_store_x1(ptr addrspace(8) inreg %rsrc, float %data, i32 %index) {102; CHECK-LABEL: buffer_store_x1:103; CHECK: ; %bb.0: ; %main_body104; CHECK-NEXT: buffer_store_format_x v0, v1, s[0:3], 0 idxen105; CHECK-NEXT: s_endpgm106main_body:107 call void @llvm.amdgcn.struct.ptr.buffer.store.format.f32(float %data, ptr addrspace(8) %rsrc, i32 %index, i32 0, i32 0, i32 0)108 ret void109}110 111define amdgpu_ps void @buffer_store_x1_i32(ptr addrspace(8) inreg %rsrc, i32 %data, i32 %index) {112; CHECK-LABEL: buffer_store_x1_i32:113; CHECK: ; %bb.0: ; %main_body114; CHECK-NEXT: buffer_store_format_x v0, v1, s[0:3], 0 idxen115; CHECK-NEXT: s_endpgm116main_body:117 call void @llvm.amdgcn.struct.ptr.buffer.store.format.i32(i32 %data, ptr addrspace(8) %rsrc, i32 %index, i32 0, i32 0, i32 0)118 ret void119}120 121define amdgpu_ps void @buffer_store_x2(ptr addrspace(8) inreg %rsrc, <2 x float> %data, i32 %index) {122; CHECK-LABEL: buffer_store_x2:123; CHECK: ; %bb.0: ; %main_body124; CHECK-NEXT: buffer_store_format_xy v[0:1], v2, s[0:3], 0 idxen125; CHECK-NEXT: s_endpgm126main_body:127 call void @llvm.amdgcn.struct.ptr.buffer.store.format.v2f32(<2 x float> %data, ptr addrspace(8) %rsrc, i32 %index, i32 0, i32 0, i32 0)128 ret void129}130 131declare void @llvm.amdgcn.struct.ptr.buffer.store.format.f32(float, ptr addrspace(8), i32, i32, i32, i32) #0132declare void @llvm.amdgcn.struct.ptr.buffer.store.format.v2f32(<2 x float>, ptr addrspace(8), i32, i32, i32, i32) #0133declare void @llvm.amdgcn.struct.ptr.buffer.store.format.v4f32(<4 x float>, ptr addrspace(8), i32, i32, i32, i32) #0134declare void @llvm.amdgcn.struct.ptr.buffer.store.format.i32(i32, ptr addrspace(8), i32, i32, i32, i32) #0135declare <4 x float> @llvm.amdgcn.struct.ptr.buffer.load.format.v4f32(ptr addrspace(8), i32, i32, i32, i32) #1136 137attributes #0 = { nounwind }138attributes #1 = { nounwind readonly }139