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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52;RUN: llc < %s -mtriple=amdgcn -mcpu=verde | FileCheck -check-prefixes=CHECK,SI %s3;RUN: llc < %s -mtriple=amdgcn -mcpu=tonga | FileCheck -check-prefixes=CHECK,VI %s4 5define amdgpu_ps void @buffer_store(ptr addrspace(8) inreg, <4 x float>, <4 x float>, <4 x float>) {6; CHECK-LABEL: buffer_store:7; CHECK: ; %bb.0: ; %main_body8; CHECK-NEXT: v_mov_b32_e32 v12, 09; CHECK-NEXT: buffer_store_dwordx4 v[0:3], v12, s[0:3], 0 idxen10; CHECK-NEXT: buffer_store_dwordx4 v[4:7], v12, s[0:3], 0 idxen glc11; CHECK-NEXT: buffer_store_dwordx4 v[8:11], v12, s[0:3], 0 idxen slc12; CHECK-NEXT: s_endpgm13main_body:14 call void @llvm.amdgcn.struct.ptr.buffer.store.v4f32(<4 x float> %1, ptr addrspace(8) %0, i32 0, i32 0, i32 0, i32 0)15 call void @llvm.amdgcn.struct.ptr.buffer.store.v4f32(<4 x float> %2, ptr addrspace(8) %0, i32 0, i32 0, i32 0, i32 1)16 call void @llvm.amdgcn.struct.ptr.buffer.store.v4f32(<4 x float> %3, ptr addrspace(8) %0, i32 0, i32 0, i32 0, i32 2)17 ret void18}19 20define amdgpu_ps void @buffer_store_immoffs(ptr addrspace(8) inreg, <4 x float>) {21; CHECK-LABEL: buffer_store_immoffs:22; CHECK: ; %bb.0: ; %main_body23; CHECK-NEXT: v_mov_b32_e32 v4, 024; CHECK-NEXT: buffer_store_dwordx4 v[0:3], v4, s[0:3], 0 idxen offset:4225; CHECK-NEXT: s_endpgm26main_body:27 call void @llvm.amdgcn.struct.ptr.buffer.store.v4f32(<4 x float> %1, ptr addrspace(8) %0, i32 0, i32 42, i32 0, i32 0)28 ret void29}30 31define amdgpu_ps void @buffer_store_idx(ptr addrspace(8) inreg, <4 x float>, i32) {32; CHECK-LABEL: buffer_store_idx:33; CHECK: ; %bb.0: ; %main_body34; CHECK-NEXT: buffer_store_dwordx4 v[0:3], v4, s[0:3], 0 idxen35; CHECK-NEXT: s_endpgm36main_body:37 call void @llvm.amdgcn.struct.ptr.buffer.store.v4f32(<4 x float> %1, ptr addrspace(8) %0, i32 %2, i32 0, i32 0, i32 0)38 ret void39}40 41define amdgpu_ps void @buffer_store_ofs(ptr addrspace(8) inreg, <4 x float>, i32) {42; CHECK-LABEL: buffer_store_ofs:43; CHECK: ; %bb.0: ; %main_body44; CHECK-NEXT: s_mov_b32 s4, 045; CHECK-NEXT: v_mov_b32_e32 v5, v446; CHECK-NEXT: v_mov_b32_e32 v4, s447; CHECK-NEXT: buffer_store_dwordx4 v[0:3], v[4:5], s[0:3], 0 idxen offen48; CHECK-NEXT: s_endpgm49main_body:50 call void @llvm.amdgcn.struct.ptr.buffer.store.v4f32(<4 x float> %1, ptr addrspace(8) %0, i32 0, i32 %2, i32 0, i32 0)51 ret void52}53 54define amdgpu_ps void @buffer_store_both(ptr addrspace(8) inreg, <4 x float>, i32, i32) {55; CHECK-LABEL: buffer_store_both:56; CHECK: ; %bb.0: ; %main_body57; CHECK-NEXT: buffer_store_dwordx4 v[0:3], v[4:5], s[0:3], 0 idxen offen58; CHECK-NEXT: s_endpgm59main_body:60 call void @llvm.amdgcn.struct.ptr.buffer.store.v4f32(<4 x float> %1, ptr addrspace(8) %0, i32 %2, i32 %3, i32 0, i32 0)61 ret void62}63 64define amdgpu_ps void @buffer_store_both_reversed(ptr addrspace(8) inreg, <4 x float>, i32, i32) {65; CHECK-LABEL: buffer_store_both_reversed:66; CHECK: ; %bb.0: ; %main_body67; CHECK-NEXT: v_mov_b32_e32 v6, v468; CHECK-NEXT: buffer_store_dwordx4 v[0:3], v[5:6], s[0:3], 0 idxen offen69; CHECK-NEXT: s_endpgm70main_body:71 call void @llvm.amdgcn.struct.ptr.buffer.store.v4f32(<4 x float> %1, ptr addrspace(8) %0, i32 %3, i32 %2, i32 0, i32 0)72 ret void73}74 75; Ideally, the register allocator would avoid the wait here76define amdgpu_ps void @buffer_store_wait(ptr addrspace(8) inreg, <4 x float>, i32, i32, i32) {77; SI-LABEL: buffer_store_wait:78; SI: ; %bb.0: ; %main_body79; SI-NEXT: buffer_store_dwordx4 v[0:3], v4, s[0:3], 0 idxen80; SI-NEXT: s_waitcnt expcnt(0)81; SI-NEXT: buffer_load_dwordx4 v[0:3], v5, s[0:3], 0 idxen82; SI-NEXT: s_waitcnt vmcnt(0)83; SI-NEXT: buffer_store_dwordx4 v[0:3], v6, s[0:3], 0 idxen84; SI-NEXT: s_endpgm85;86; VI-LABEL: buffer_store_wait:87; VI: ; %bb.0: ; %main_body88; VI-NEXT: buffer_store_dwordx4 v[0:3], v4, s[0:3], 0 idxen89; VI-NEXT: buffer_load_dwordx4 v[0:3], v5, s[0:3], 0 idxen90; VI-NEXT: s_waitcnt vmcnt(0)91; VI-NEXT: buffer_store_dwordx4 v[0:3], v6, s[0:3], 0 idxen92; VI-NEXT: s_endpgm93main_body:94 call void @llvm.amdgcn.struct.ptr.buffer.store.v4f32(<4 x float> %1, ptr addrspace(8) %0, i32 %2, i32 0, i32 0, i32 0)95 %data = call <4 x float> @llvm.amdgcn.struct.ptr.buffer.load.v4f32(ptr addrspace(8) %0, i32 %3, i32 0, i32 0, i32 0)96 call void @llvm.amdgcn.struct.ptr.buffer.store.v4f32(<4 x float> %data, ptr addrspace(8) %0, i32 %4, i32 0, i32 0, i32 0)97 ret void98}99 100define amdgpu_ps void @buffer_store_x1(ptr addrspace(8) inreg %rsrc, float %data, i32 %index) {101; CHECK-LABEL: buffer_store_x1:102; CHECK: ; %bb.0: ; %main_body103; CHECK-NEXT: buffer_store_dword v0, v1, s[0:3], 0 idxen104; CHECK-NEXT: s_endpgm105main_body:106 call void @llvm.amdgcn.struct.ptr.buffer.store.f32(float %data, ptr addrspace(8) %rsrc, i32 %index, i32 0, i32 0, i32 0)107 ret void108}109 110define amdgpu_ps void @buffer_store_x2(ptr addrspace(8) inreg %rsrc, <2 x float> %data, i32 %index) #0 {111; CHECK-LABEL: buffer_store_x2:112; CHECK: ; %bb.0: ; %main_body113; CHECK-NEXT: buffer_store_dwordx2 v[0:1], v2, s[0:3], 0 idxen114; CHECK-NEXT: s_endpgm115main_body:116 call void @llvm.amdgcn.struct.ptr.buffer.store.v2f32(<2 x float> %data, ptr addrspace(8) %rsrc, i32 %index, i32 0, i32 0, i32 0)117 ret void118}119 120define amdgpu_ps void @buffer_store_int(ptr addrspace(8) inreg, <4 x i32>, <2 x i32>, i32) {121; CHECK-LABEL: buffer_store_int:122; CHECK: ; %bb.0: ; %main_body123; CHECK-NEXT: v_mov_b32_e32 v7, 0124; CHECK-NEXT: buffer_store_dwordx4 v[0:3], v7, s[0:3], 0 idxen125; CHECK-NEXT: buffer_store_dwordx2 v[4:5], v7, s[0:3], 0 idxen glc126; CHECK-NEXT: buffer_store_dword v6, v7, s[0:3], 0 idxen slc127; CHECK-NEXT: s_endpgm128main_body:129 call void @llvm.amdgcn.struct.ptr.buffer.store.v4i32(<4 x i32> %1, ptr addrspace(8) %0, i32 0, i32 0, i32 0, i32 0)130 call void @llvm.amdgcn.struct.ptr.buffer.store.v2i32(<2 x i32> %2, ptr addrspace(8) %0, i32 0, i32 0, i32 0, i32 1)131 call void @llvm.amdgcn.struct.ptr.buffer.store.i32(i32 %3, ptr addrspace(8) %0, i32 0, i32 0, i32 0, i32 2)132 ret void133}134 135define amdgpu_ps void @struct_ptr_buffer_store_byte(ptr addrspace(8) inreg %rsrc, float %v1, i32 %index) {136; CHECK-LABEL: struct_ptr_buffer_store_byte:137; CHECK: ; %bb.0: ; %main_body138; CHECK-NEXT: v_cvt_u32_f32_e32 v0, v0139; CHECK-NEXT: buffer_store_byte v0, v1, s[0:3], 0 idxen140; CHECK-NEXT: s_endpgm141main_body:142 %v2 = fptoui float %v1 to i32143 %v3 = trunc i32 %v2 to i8144 call void @llvm.amdgcn.struct.ptr.buffer.store.i8(i8 %v3, ptr addrspace(8) %rsrc, i32 %index, i32 0, i32 0, i32 0)145 ret void146}147 148define amdgpu_ps void @struct_ptr_buffer_store_f16(ptr addrspace(8) inreg %rsrc, float %v1, i32 %index) {149; CHECK-LABEL: struct_ptr_buffer_store_f16:150; CHECK: ; %bb.0:151; CHECK-NEXT: v_cvt_f16_f32_e32 v0, v0152; CHECK-NEXT: buffer_store_short v0, v1, s[0:3], 0 idxen153; CHECK-NEXT: s_endpgm154 %v2 = fptrunc float %v1 to half155 call void @llvm.amdgcn.struct.ptr.buffer.store.f16(half %v2, ptr addrspace(8) %rsrc, i32 %index, i32 0, i32 0, i32 0)156 ret void157}158 159define amdgpu_ps void @struct_ptr_buffer_store_v2f16(ptr addrspace(8) inreg %rsrc, <2 x half> %v1, i32 %index) {160; SI-LABEL: struct_ptr_buffer_store_v2f16:161; SI: ; %bb.0:162; SI-NEXT: v_cvt_f16_f32_e32 v1, v1163; SI-NEXT: v_cvt_f16_f32_e32 v0, v0164; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1165; SI-NEXT: v_or_b32_e32 v0, v0, v1166; SI-NEXT: buffer_store_dword v0, v2, s[0:3], 0 idxen167; SI-NEXT: s_endpgm168;169; VI-LABEL: struct_ptr_buffer_store_v2f16:170; VI: ; %bb.0:171; VI-NEXT: buffer_store_dword v0, v1, s[0:3], 0 idxen172; VI-NEXT: s_endpgm173 call void @llvm.amdgcn.struct.ptr.buffer.store.v2f16(<2 x half> %v1, ptr addrspace(8) %rsrc, i32 %index, i32 0, i32 0, i32 0)174 ret void175}176 177define amdgpu_ps void @struct_ptr_buffer_store_v4f16(ptr addrspace(8) inreg %rsrc, <4 x half> %v1, i32 %index) {178; SI-LABEL: struct_ptr_buffer_store_v4f16:179; SI: ; %bb.0:180; SI-NEXT: v_cvt_f16_f32_e32 v3, v3181; SI-NEXT: v_cvt_f16_f32_e32 v2, v2182; SI-NEXT: v_cvt_f16_f32_e32 v5, v1183; SI-NEXT: v_cvt_f16_f32_e32 v0, v0184; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v3185; SI-NEXT: v_or_b32_e32 v1, v2, v1186; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v5187; SI-NEXT: v_or_b32_e32 v0, v0, v2188; SI-NEXT: buffer_store_dwordx2 v[0:1], v4, s[0:3], 0 idxen189; SI-NEXT: s_endpgm190;191; VI-LABEL: struct_ptr_buffer_store_v4f16:192; VI: ; %bb.0:193; VI-NEXT: buffer_store_dwordx2 v[0:1], v2, s[0:3], 0 idxen194; VI-NEXT: s_endpgm195 call void @llvm.amdgcn.struct.ptr.buffer.store.v4f16(<4 x half> %v1, ptr addrspace(8) %rsrc, i32 %index, i32 0, i32 0, i32 0)196 ret void197}198 199define amdgpu_ps void @struct_ptr_buffer_store_i16(ptr addrspace(8) inreg %rsrc, float %v1, i32 %index) {200; CHECK-LABEL: struct_ptr_buffer_store_i16:201; CHECK: ; %bb.0: ; %main_body202; CHECK-NEXT: v_cvt_u32_f32_e32 v0, v0203; CHECK-NEXT: buffer_store_short v0, v1, s[0:3], 0 idxen204; CHECK-NEXT: s_endpgm205main_body:206 %v2 = fptoui float %v1 to i32207 %v3 = trunc i32 %v2 to i16208 call void @llvm.amdgcn.struct.ptr.buffer.store.i16(i16 %v3, ptr addrspace(8) %rsrc, i32 %index, i32 0, i32 0, i32 0)209 ret void210}211 212define amdgpu_ps void @struct_ptr_buffer_store_vif16(ptr addrspace(8) inreg %rsrc, <2 x i16> %v1, i32 %index) {213; SI-LABEL: struct_ptr_buffer_store_vif16:214; SI: ; %bb.0:215; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1216; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0217; SI-NEXT: v_or_b32_e32 v0, v0, v1218; SI-NEXT: buffer_store_dword v0, v2, s[0:3], 0 idxen219; SI-NEXT: s_endpgm220;221; VI-LABEL: struct_ptr_buffer_store_vif16:222; VI: ; %bb.0:223; VI-NEXT: buffer_store_dword v0, v1, s[0:3], 0 idxen224; VI-NEXT: s_endpgm225 call void @llvm.amdgcn.struct.ptr.buffer.store.v2i16(<2 x i16> %v1, ptr addrspace(8) %rsrc, i32 %index, i32 0, i32 0, i32 0)226 ret void227}228 229define amdgpu_ps void @struct_ptr_buffer_store_v4i16(ptr addrspace(8) inreg %rsrc, <4 x i16> %v1, i32 %index) {230; SI-LABEL: struct_ptr_buffer_store_v4i16:231; SI: ; %bb.0:232; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3233; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2234; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1235; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0236; SI-NEXT: v_or_b32_e32 v2, v2, v3237; SI-NEXT: v_or_b32_e32 v1, v0, v1238; SI-NEXT: buffer_store_dwordx2 v[1:2], v4, s[0:3], 0 idxen239; SI-NEXT: s_endpgm240;241; VI-LABEL: struct_ptr_buffer_store_v4i16:242; VI: ; %bb.0:243; VI-NEXT: buffer_store_dwordx2 v[0:1], v2, s[0:3], 0 idxen244; VI-NEXT: s_endpgm245 call void @llvm.amdgcn.struct.ptr.buffer.store.v4i16(<4 x i16> %v1, ptr addrspace(8) %rsrc, i32 %index, i32 0, i32 0, i32 0)246 ret void247}248 249declare void @llvm.amdgcn.struct.ptr.buffer.store.f32(float, ptr addrspace(8), i32, i32, i32, i32) #0250declare void @llvm.amdgcn.struct.ptr.buffer.store.v2f32(<2 x float>, ptr addrspace(8), i32, i32, i32, i32) #0251declare void @llvm.amdgcn.struct.ptr.buffer.store.v4f32(<4 x float>, ptr addrspace(8), i32, i32, i32, i32) #0252declare void @llvm.amdgcn.struct.ptr.buffer.store.i32(i32, ptr addrspace(8), i32, i32, i32, i32) #0253declare void @llvm.amdgcn.struct.ptr.buffer.store.v2i32(<2 x i32>, ptr addrspace(8), i32, i32, i32, i32) #0254declare void @llvm.amdgcn.struct.ptr.buffer.store.v4i32(<4 x i32>, ptr addrspace(8), i32, i32, i32, i32) #0255declare <4 x float> @llvm.amdgcn.struct.ptr.buffer.load.v4f32(ptr addrspace(8), i32, i32, i32, i32) #1256declare void @llvm.amdgcn.struct.ptr.buffer.store.i8(i8, ptr addrspace(8), i32, i32, i32, i32) #0257declare void @llvm.amdgcn.struct.ptr.buffer.store.i16(i16, ptr addrspace(8), i32, i32, i32, i32) #0258declare void @llvm.amdgcn.struct.ptr.buffer.store.v2i16(<2 x i16>, ptr addrspace(8), i32, i32, i32, i32) #0259declare void @llvm.amdgcn.struct.ptr.buffer.store.v4i16(<4 x i16>, ptr addrspace(8), i32, i32, i32, i32) #0260declare void @llvm.amdgcn.struct.ptr.buffer.store.f16(half, ptr addrspace(8), i32, i32, i32, i32) #0261declare void @llvm.amdgcn.struct.ptr.buffer.store.v2f16(<2 x half>, ptr addrspace(8), i32, i32, i32, i32) #0262declare void @llvm.amdgcn.struct.ptr.buffer.store.v4f16(<4 x half>, ptr addrspace(8), i32, i32, i32, i32) #0263 264 265attributes #0 = { nounwind }266attributes #1 = { nounwind readonly }267