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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 -mattr=+real-true16 %s -o - | FileCheck -check-prefix=SDAG-REAL16 %s3; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 -mattr=-real-true16 %s -o - | FileCheck -check-prefix=SDAG-FAKE16 %s4; xUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 -mattr=+real-true16 %s -o - | FileCheck -check-prefix=GISEL-REAL16 %s5; xUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 -mattr=-real-true16 %s -o - | FileCheck -check-prefix=GISEL-FAKE16 %s6 7; FIXME: GlobalISel does not work with bf168 9declare float @llvm.amdgcn.tanh.f32(float) #010declare half @llvm.amdgcn.tanh.f16(half) #011declare bfloat @llvm.amdgcn.tanh.bf16(bfloat) #012 13define amdgpu_kernel void @tanh_f32(ptr addrspace(1) %out, float %src) #1 {14; SDAG-REAL16-LABEL: tanh_f32:15; SDAG-REAL16: ; %bb.0:16; SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 117; SDAG-REAL16-NEXT: s_load_b96 s[0:2], s[4:5], 0x018; SDAG-REAL16-NEXT: v_mov_b32_e32 v1, 019; SDAG-REAL16-NEXT: s_wait_kmcnt 0x020; SDAG-REAL16-NEXT: v_tanh_f32_e32 v0, s221; SDAG-REAL16-NEXT: global_store_b32 v1, v0, s[0:1]22; SDAG-REAL16-NEXT: s_endpgm23;24; SDAG-FAKE16-LABEL: tanh_f32:25; SDAG-FAKE16: ; %bb.0:26; SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 127; SDAG-FAKE16-NEXT: s_load_b96 s[0:2], s[4:5], 0x028; SDAG-FAKE16-NEXT: v_mov_b32_e32 v1, 029; SDAG-FAKE16-NEXT: s_wait_kmcnt 0x030; SDAG-FAKE16-NEXT: v_tanh_f32_e32 v0, s231; SDAG-FAKE16-NEXT: global_store_b32 v1, v0, s[0:1]32; SDAG-FAKE16-NEXT: s_endpgm33 %tanh = call float @llvm.amdgcn.tanh.f32(float %src) #034 store float %tanh, ptr addrspace(1) %out, align 435 ret void36}37 38; TODO: Really these should be constant folded39define amdgpu_kernel void @tanh_f32_constant_4.0(ptr addrspace(1) %out) #1 {40; SDAG-REAL16-LABEL: tanh_f32_constant_4.0:41; SDAG-REAL16: ; %bb.0:42; SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 143; SDAG-REAL16-NEXT: s_load_b64 s[0:1], s[4:5], 0x044; SDAG-REAL16-NEXT: v_tanh_f32_e32 v0, 4.045; SDAG-REAL16-NEXT: v_mov_b32_e32 v1, 046; SDAG-REAL16-NEXT: s_wait_kmcnt 0x047; SDAG-REAL16-NEXT: global_store_b32 v1, v0, s[0:1]48; SDAG-REAL16-NEXT: s_endpgm49;50; SDAG-FAKE16-LABEL: tanh_f32_constant_4.0:51; SDAG-FAKE16: ; %bb.0:52; SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 153; SDAG-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x054; SDAG-FAKE16-NEXT: v_tanh_f32_e32 v0, 4.055; SDAG-FAKE16-NEXT: v_mov_b32_e32 v1, 056; SDAG-FAKE16-NEXT: s_wait_kmcnt 0x057; SDAG-FAKE16-NEXT: global_store_b32 v1, v0, s[0:1]58; SDAG-FAKE16-NEXT: s_endpgm59 %tanh = call float @llvm.amdgcn.tanh.f32(float 4.0) #060 store float %tanh, ptr addrspace(1) %out, align 461 ret void62}63 64define amdgpu_kernel void @tanh_f32_constant_100.0(ptr addrspace(1) %out) #1 {65; SDAG-REAL16-LABEL: tanh_f32_constant_100.0:66; SDAG-REAL16: ; %bb.0:67; SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 168; SDAG-REAL16-NEXT: s_load_b64 s[0:1], s[4:5], 0x069; SDAG-REAL16-NEXT: v_tanh_f32_e32 v0, 0x42c8000070; SDAG-REAL16-NEXT: v_mov_b32_e32 v1, 071; SDAG-REAL16-NEXT: s_wait_kmcnt 0x072; SDAG-REAL16-NEXT: global_store_b32 v1, v0, s[0:1]73; SDAG-REAL16-NEXT: s_endpgm74;75; SDAG-FAKE16-LABEL: tanh_f32_constant_100.0:76; SDAG-FAKE16: ; %bb.0:77; SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 178; SDAG-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x079; SDAG-FAKE16-NEXT: v_tanh_f32_e32 v0, 0x42c8000080; SDAG-FAKE16-NEXT: v_mov_b32_e32 v1, 081; SDAG-FAKE16-NEXT: s_wait_kmcnt 0x082; SDAG-FAKE16-NEXT: global_store_b32 v1, v0, s[0:1]83; SDAG-FAKE16-NEXT: s_endpgm84 %tanh = call float @llvm.amdgcn.tanh.f32(float 100.0) #085 store float %tanh, ptr addrspace(1) %out, align 486 ret void87}88 89define amdgpu_kernel void @tanh_undef_f32(ptr addrspace(1) %out) #1 {90; SDAG-REAL16-LABEL: tanh_undef_f32:91; SDAG-REAL16: ; %bb.0:92; SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 193; SDAG-REAL16-NEXT: s_endpgm94;95; SDAG-FAKE16-LABEL: tanh_undef_f32:96; SDAG-FAKE16: ; %bb.0:97; SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 198; SDAG-FAKE16-NEXT: s_endpgm99 %tanh = call float @llvm.amdgcn.tanh.f32(float undef)100 store float %tanh, ptr addrspace(1) %out, align 4101 ret void102}103 104define amdgpu_kernel void @tanh_f16(ptr addrspace(1) %out, half %src) #1 {105; SDAG-REAL16-LABEL: tanh_f16:106; SDAG-REAL16: ; %bb.0:107; SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1108; SDAG-REAL16-NEXT: s_load_b96 s[0:2], s[4:5], 0x0109; SDAG-REAL16-NEXT: v_mov_b32_e32 v1, 0110; SDAG-REAL16-NEXT: s_wait_kmcnt 0x0111; SDAG-REAL16-NEXT: v_tanh_f16_e32 v0.l, s2112; SDAG-REAL16-NEXT: global_store_b16 v1, v0, s[0:1]113; SDAG-REAL16-NEXT: s_endpgm114;115; SDAG-FAKE16-LABEL: tanh_f16:116; SDAG-FAKE16: ; %bb.0:117; SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1118; SDAG-FAKE16-NEXT: s_load_b96 s[0:2], s[4:5], 0x0119; SDAG-FAKE16-NEXT: v_mov_b32_e32 v1, 0120; SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0121; SDAG-FAKE16-NEXT: v_tanh_f16_e32 v0, s2122; SDAG-FAKE16-NEXT: global_store_b16 v1, v0, s[0:1]123; SDAG-FAKE16-NEXT: s_endpgm124 %tanh = call half @llvm.amdgcn.tanh.f16(half %src) #0125 store half %tanh, ptr addrspace(1) %out, align 2126 ret void127}128 129define amdgpu_kernel void @tanh_f16_constant_4.0(ptr addrspace(1) %out) #1 {130; SDAG-REAL16-LABEL: tanh_f16_constant_4.0:131; SDAG-REAL16: ; %bb.0:132; SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1133; SDAG-REAL16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0134; SDAG-REAL16-NEXT: v_tanh_f16_e32 v0.l, 4.0135; SDAG-REAL16-NEXT: v_mov_b32_e32 v1, 0136; SDAG-REAL16-NEXT: s_wait_kmcnt 0x0137; SDAG-REAL16-NEXT: global_store_b16 v1, v0, s[0:1]138; SDAG-REAL16-NEXT: s_endpgm139;140; SDAG-FAKE16-LABEL: tanh_f16_constant_4.0:141; SDAG-FAKE16: ; %bb.0:142; SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1143; SDAG-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0144; SDAG-FAKE16-NEXT: v_tanh_f16_e32 v0, 4.0145; SDAG-FAKE16-NEXT: v_mov_b32_e32 v1, 0146; SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0147; SDAG-FAKE16-NEXT: global_store_b16 v1, v0, s[0:1]148; SDAG-FAKE16-NEXT: s_endpgm149 %tanh = call half @llvm.amdgcn.tanh.f16(half 4.0) #0150 store half %tanh, ptr addrspace(1) %out, align 2151 ret void152}153 154define amdgpu_kernel void @tanh_f16_constant_100.0(ptr addrspace(1) %out) #1 {155; SDAG-REAL16-LABEL: tanh_f16_constant_100.0:156; SDAG-REAL16: ; %bb.0:157; SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1158; SDAG-REAL16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0159; SDAG-REAL16-NEXT: v_tanh_f16_e32 v0.l, 0x5640160; SDAG-REAL16-NEXT: v_mov_b32_e32 v1, 0161; SDAG-REAL16-NEXT: s_wait_kmcnt 0x0162; SDAG-REAL16-NEXT: global_store_b16 v1, v0, s[0:1]163; SDAG-REAL16-NEXT: s_endpgm164;165; SDAG-FAKE16-LABEL: tanh_f16_constant_100.0:166; SDAG-FAKE16: ; %bb.0:167; SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1168; SDAG-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0169; SDAG-FAKE16-NEXT: v_tanh_f16_e32 v0, 0x5640170; SDAG-FAKE16-NEXT: v_mov_b32_e32 v1, 0171; SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0172; SDAG-FAKE16-NEXT: global_store_b16 v1, v0, s[0:1]173; SDAG-FAKE16-NEXT: s_endpgm174 %tanh = call half @llvm.amdgcn.tanh.f16(half 100.0) #0175 store half %tanh, ptr addrspace(1) %out, align 2176 ret void177}178 179define amdgpu_kernel void @tanh_undef_f16(ptr addrspace(1) %out) #1 {180; SDAG-REAL16-LABEL: tanh_undef_f16:181; SDAG-REAL16: ; %bb.0:182; SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1183; SDAG-REAL16-NEXT: s_endpgm184;185; SDAG-FAKE16-LABEL: tanh_undef_f16:186; SDAG-FAKE16: ; %bb.0:187; SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1188; SDAG-FAKE16-NEXT: s_endpgm189 %tanh = call half @llvm.amdgcn.tanh.f16(half undef)190 store half %tanh, ptr addrspace(1) %out, align 2191 ret void192}193 194define amdgpu_kernel void @tanh_bf16(ptr addrspace(1) %out, bfloat %src) #1 {195; SDAG-REAL16-LABEL: tanh_bf16:196; SDAG-REAL16: ; %bb.0:197; SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1198; SDAG-REAL16-NEXT: s_load_b96 s[0:2], s[4:5], 0x0199; SDAG-REAL16-NEXT: v_mov_b32_e32 v1, 0200; SDAG-REAL16-NEXT: s_wait_kmcnt 0x0201; SDAG-REAL16-NEXT: v_tanh_bf16_e32 v0.l, s2202; SDAG-REAL16-NEXT: global_store_b16 v1, v0, s[0:1]203; SDAG-REAL16-NEXT: s_endpgm204;205; SDAG-FAKE16-LABEL: tanh_bf16:206; SDAG-FAKE16: ; %bb.0:207; SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1208; SDAG-FAKE16-NEXT: s_load_b96 s[0:2], s[4:5], 0x0209; SDAG-FAKE16-NEXT: v_mov_b32_e32 v1, 0210; SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0211; SDAG-FAKE16-NEXT: v_tanh_bf16_e32 v0, s2212; SDAG-FAKE16-NEXT: global_store_b16 v1, v0, s[0:1]213; SDAG-FAKE16-NEXT: s_endpgm214 %tanh = call bfloat @llvm.amdgcn.tanh.bf16(bfloat %src) #0215 store bfloat %tanh, ptr addrspace(1) %out, align 2216 ret void217}218 219define amdgpu_kernel void @tanh_bf16_constant_4(ptr addrspace(1) %out) #1 {220; SDAG-REAL16-LABEL: tanh_bf16_constant_4:221; SDAG-REAL16: ; %bb.0:222; SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1223; SDAG-REAL16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0224; SDAG-REAL16-NEXT: v_tanh_bf16_e32 v0.l, 4.0225; SDAG-REAL16-NEXT: v_mov_b32_e32 v1, 0226; SDAG-REAL16-NEXT: s_wait_kmcnt 0x0227; SDAG-REAL16-NEXT: global_store_b16 v1, v0, s[0:1]228; SDAG-REAL16-NEXT: s_endpgm229;230; SDAG-FAKE16-LABEL: tanh_bf16_constant_4:231; SDAG-FAKE16: ; %bb.0:232; SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1233; SDAG-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0234; SDAG-FAKE16-NEXT: v_tanh_bf16_e32 v0, 4.0235; SDAG-FAKE16-NEXT: v_mov_b32_e32 v1, 0236; SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0237; SDAG-FAKE16-NEXT: global_store_b16 v1, v0, s[0:1]238; SDAG-FAKE16-NEXT: s_endpgm239 %tanh = call bfloat @llvm.amdgcn.tanh.bf16(bfloat 4.0) #0240 store bfloat %tanh, ptr addrspace(1) %out, align 2241 ret void242}243 244define amdgpu_kernel void @tanh_bf16_constant_100(ptr addrspace(1) %out) #1 {245; SDAG-REAL16-LABEL: tanh_bf16_constant_100:246; SDAG-REAL16: ; %bb.0:247; SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1248; SDAG-REAL16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0249; SDAG-REAL16-NEXT: v_tanh_bf16_e32 v0.l, 0x42c8250; SDAG-REAL16-NEXT: v_mov_b32_e32 v1, 0251; SDAG-REAL16-NEXT: s_wait_kmcnt 0x0252; SDAG-REAL16-NEXT: global_store_b16 v1, v0, s[0:1]253; SDAG-REAL16-NEXT: s_endpgm254;255; SDAG-FAKE16-LABEL: tanh_bf16_constant_100:256; SDAG-FAKE16: ; %bb.0:257; SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1258; SDAG-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0259; SDAG-FAKE16-NEXT: v_tanh_bf16_e32 v0, 0x42c8260; SDAG-FAKE16-NEXT: v_mov_b32_e32 v1, 0261; SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0262; SDAG-FAKE16-NEXT: global_store_b16 v1, v0, s[0:1]263; SDAG-FAKE16-NEXT: s_endpgm264 %tanh = call bfloat @llvm.amdgcn.tanh.bf16(bfloat 100.0) #0265 store bfloat %tanh, ptr addrspace(1) %out, align 2266 ret void267}268 269define amdgpu_kernel void @tanh_undef_bf16(ptr addrspace(1) %out) #1 {270; SDAG-REAL16-LABEL: tanh_undef_bf16:271; SDAG-REAL16: ; %bb.0:272; SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1273; SDAG-REAL16-NEXT: s_endpgm274;275; SDAG-FAKE16-LABEL: tanh_undef_bf16:276; SDAG-FAKE16: ; %bb.0:277; SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1278; SDAG-FAKE16-NEXT: s_endpgm279 %tanh = call bfloat @llvm.amdgcn.tanh.bf16(bfloat undef)280 store bfloat %tanh, ptr addrspace(1) %out, align 2281 ret void282}283 284attributes #0 = { nounwind readnone }285attributes #1 = { nounwind }286