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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-SDAG %s3; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-GISEL %s4 5declare void @llvm.amdgcn.tensor.load.to.lds(<4 x i32> %D0, <8 x i32> %D1, <4 x i32> %D2, <4 x i32> %D3, i32 %cpol)6declare void @llvm.amdgcn.tensor.load.to.lds.d2(<4 x i32> %D0, <8 x i32> %D1, i32 %cpol)7declare void @llvm.amdgcn.tensor.store.from.lds(<4 x i32> %D0, <8 x i32> %D1, <4 x i32> %D2, <4 x i32> %D3, i32 %cpol)8declare void @llvm.amdgcn.tensor.store.from.lds.d2(<4 x i32> %D0, <8 x i32> %D1, i32 %cpol)9 10define amdgpu_ps void @tensor_load_to_lds(<4 x i32> inreg %D0, <8 x i32> inreg %D1, <4 x i32> inreg %D2, <4 x i32> inreg %D3) {11; GFX1250-LABEL: tensor_load_to_lds:12; GFX1250: ; %bb.0: ; %entry13; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 114; GFX1250-NEXT: tensor_load_to_lds s[0:3], s[4:11], s[12:15], s[16:19]15; GFX1250-NEXT: s_endpgm16entry:17 call void @llvm.amdgcn.tensor.load.to.lds(<4 x i32> %D0, <8 x i32> %D1, <4 x i32> %D2, <4 x i32> %D3, i32 0)18 ret void19}20 21define amdgpu_ps void @tensor_load_to_lds_vector(<4 x i32> %D0, <8 x i32> %D1, <4 x i32> %D2, <4 x i32> %D3) {22; GFX1250-SDAG-LABEL: tensor_load_to_lds_vector:23; GFX1250-SDAG: ; %bb.0: ; %entry24; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 125; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s0, v426; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s1, v527; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s2, v628; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s3, v729; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s4, v830; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s8, v031; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s9, v132; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s10, v233; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s11, v334; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s5, v935; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s6, v1036; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s7, v1137; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s12, v1238; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s13, v1339; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s14, v1440; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s15, v1541; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s16, v1642; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s17, v1743; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s18, v1844; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s19, v1945; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)46; GFX1250-SDAG-NEXT: tensor_load_to_lds s[8:11], s[0:7], s[12:15], s[16:19]47; GFX1250-SDAG-NEXT: s_endpgm48;49; GFX1250-GISEL-LABEL: tensor_load_to_lds_vector:50; GFX1250-GISEL: ; %bb.0: ; %entry51; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 152; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s8, v053; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s9, v154; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s10, v255; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s11, v356; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s0, v457; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s1, v558; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s2, v659; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s3, v760; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s4, v861; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s5, v962; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s6, v1063; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s7, v1164; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s12, v1265; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s13, v1366; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s14, v1467; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s15, v1568; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s16, v1669; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s17, v1770; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s18, v1871; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s19, v1972; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)73; GFX1250-GISEL-NEXT: tensor_load_to_lds s[8:11], s[0:7], s[12:15], s[16:19]74; GFX1250-GISEL-NEXT: s_endpgm75entry:76 call void @llvm.amdgcn.tensor.load.to.lds(<4 x i32> %D0, <8 x i32> %D1, <4 x i32> %D2, <4 x i32> %D3, i32 0)77 ret void78}79 80 81define amdgpu_ps void @tensor_load_to_lds_d2(<4 x i32> inreg %D0, <8 x i32> inreg %D1) {82; GFX1250-LABEL: tensor_load_to_lds_d2:83; GFX1250: ; %bb.0: ; %entry84; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 185; GFX1250-NEXT: tensor_load_to_lds s[0:3], s[4:11] th:TH_LOAD_BYPASS scope:SCOPE_SYS86; GFX1250-NEXT: s_endpgm87entry:88 call void @llvm.amdgcn.tensor.load.to.lds.d2(<4 x i32> %D0, <8 x i32> %D1, i32 27)89 ret void90}91 92define amdgpu_ps void @tensor_load_to_lds_d2_vector(<4 x i32> %D0, <8 x i32> %D1) {93; GFX1250-SDAG-LABEL: tensor_load_to_lds_d2_vector:94; GFX1250-SDAG: ; %bb.0: ; %entry95; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 196; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s0, v497; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s8, v098; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s9, v199; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s10, v2100; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s11, v3101; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s1, v5102; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s2, v6103; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s3, v7104; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s4, v8105; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s5, v9106; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s6, v10107; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s7, v11108; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)109; GFX1250-SDAG-NEXT: tensor_load_to_lds s[8:11], s[0:7] th:TH_LOAD_BYPASS scope:SCOPE_SYS110; GFX1250-SDAG-NEXT: s_endpgm111;112; GFX1250-GISEL-LABEL: tensor_load_to_lds_d2_vector:113; GFX1250-GISEL: ; %bb.0: ; %entry114; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1115; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s8, v0116; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s9, v1117; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s10, v2118; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s11, v3119; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s0, v4120; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s1, v5121; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s2, v6122; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s3, v7123; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s4, v8124; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s5, v9125; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s6, v10126; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s7, v11127; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)128; GFX1250-GISEL-NEXT: tensor_load_to_lds s[8:11], s[0:7] th:TH_LOAD_BYPASS scope:SCOPE_SYS129; GFX1250-GISEL-NEXT: s_endpgm130entry:131 call void @llvm.amdgcn.tensor.load.to.lds.d2(<4 x i32> %D0, <8 x i32> %D1, i32 27)132 ret void133}134 135define amdgpu_ps void @tensor_store_from_lds(<4 x i32> inreg %D0, <8 x i32> inreg %D1, <4 x i32> inreg %D2, <4 x i32> inreg %D3) {136; GFX1250-LABEL: tensor_store_from_lds:137; GFX1250: ; %bb.0: ; %entry138; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1139; GFX1250-NEXT: tensor_store_from_lds s[0:3], s[4:11], s[12:15], s[16:19] th:TH_STORE_NT_HT scope:SCOPE_DEV140; GFX1250-NEXT: s_endpgm141entry:142 call void @llvm.amdgcn.tensor.store.from.lds(<4 x i32> %D0, <8 x i32> %D1, <4 x i32> %D2, <4 x i32> %D3, i32 22)143 ret void144}145 146define amdgpu_ps void @tensor_store_from_lds_vector(<4 x i32> %D0, <8 x i32> %D1, <4 x i32> %D2, <4 x i32> %D3) {147; GFX1250-SDAG-LABEL: tensor_store_from_lds_vector:148; GFX1250-SDAG: ; %bb.0: ; %entry149; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1150; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s0, v4151; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s1, v5152; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s2, v6153; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s3, v7154; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s4, v8155; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s8, v0156; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s9, v1157; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s10, v2158; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s11, v3159; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s5, v9160; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s6, v10161; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s7, v11162; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s12, v12163; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s13, v13164; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s14, v14165; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s15, v15166; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s16, v16167; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s17, v17168; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s18, v18169; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s19, v19170; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)171; GFX1250-SDAG-NEXT: tensor_store_from_lds s[8:11], s[0:7], s[12:15], s[16:19] th:TH_STORE_NT_HT scope:SCOPE_DEV172; GFX1250-SDAG-NEXT: s_endpgm173;174; GFX1250-GISEL-LABEL: tensor_store_from_lds_vector:175; GFX1250-GISEL: ; %bb.0: ; %entry176; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1177; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s8, v0178; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s9, v1179; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s10, v2180; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s11, v3181; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s0, v4182; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s1, v5183; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s2, v6184; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s3, v7185; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s4, v8186; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s5, v9187; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s6, v10188; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s7, v11189; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s12, v12190; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s13, v13191; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s14, v14192; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s15, v15193; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s16, v16194; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s17, v17195; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s18, v18196; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s19, v19197; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)198; GFX1250-GISEL-NEXT: tensor_store_from_lds s[8:11], s[0:7], s[12:15], s[16:19] th:TH_STORE_NT_HT scope:SCOPE_DEV199; GFX1250-GISEL-NEXT: s_endpgm200entry:201 call void @llvm.amdgcn.tensor.store.from.lds(<4 x i32> %D0, <8 x i32> %D1, <4 x i32> %D2, <4 x i32> %D3, i32 22)202 ret void203}204 205define amdgpu_ps void @tensor_store_from_lds_d2(<4 x i32> inreg %D0, <8 x i32> inreg %D1) {206; GFX1250-LABEL: tensor_store_from_lds_d2:207; GFX1250: ; %bb.0: ; %entry208; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1209; GFX1250-NEXT: tensor_store_from_lds s[0:3], s[4:11]210; GFX1250-NEXT: s_endpgm211entry:212 call void @llvm.amdgcn.tensor.store.from.lds.d2(<4 x i32> %D0, <8 x i32> %D1, i32 0)213 ret void214}215 216define amdgpu_ps void @tensor_store_from_lds_d2_vector(<4 x i32> %D0, <8 x i32> %D1) {217; GFX1250-SDAG-LABEL: tensor_store_from_lds_d2_vector:218; GFX1250-SDAG: ; %bb.0: ; %entry219; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1220; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s0, v4221; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s8, v0222; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s9, v1223; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s10, v2224; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s11, v3225; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s1, v5226; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s2, v6227; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s3, v7228; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s4, v8229; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s5, v9230; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s6, v10231; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s7, v11232; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)233; GFX1250-SDAG-NEXT: tensor_store_from_lds s[8:11], s[0:7]234; GFX1250-SDAG-NEXT: s_endpgm235;236; GFX1250-GISEL-LABEL: tensor_store_from_lds_d2_vector:237; GFX1250-GISEL: ; %bb.0: ; %entry238; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1239; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s8, v0240; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s9, v1241; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s10, v2242; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s11, v3243; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s0, v4244; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s1, v5245; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s2, v6246; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s3, v7247; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s4, v8248; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s5, v9249; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s6, v10250; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s7, v11251; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)252; GFX1250-GISEL-NEXT: tensor_store_from_lds s[8:11], s[0:7]253; GFX1250-GISEL-NEXT: s_endpgm254entry:255 call void @llvm.amdgcn.tensor.store.from.lds.d2(<4 x i32> %D0, <8 x i32> %D1, i32 0)256 ret void257}258