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1; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn < %s | FileCheck -check-prefix=SI %s2; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -check-prefix=SI %s3 4declare double @llvm.amdgcn.trig.preop.f64(double, i32) nounwind readnone5 6; SI-LABEL: {{^}}test_trig_preop_f64:7; SI-DAG: buffer_load_dword [[SEG:v[0-9]+]]8; SI-DAG: buffer_load_dwordx2 [[SRC:v\[[0-9]+:[0-9]+\]]],9; SI: v_trig_preop_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[SRC]], [[SEG]]10; SI: buffer_store_dwordx2 [[RESULT]],11; SI: s_endpgm12define amdgpu_kernel void @test_trig_preop_f64(ptr addrspace(1) %out, ptr addrspace(1) %aptr, ptr addrspace(1) %bptr) nounwind {13 %a = load double, ptr addrspace(1) %aptr, align 814 %b = load i32, ptr addrspace(1) %bptr, align 415 %result = call double @llvm.amdgcn.trig.preop.f64(double %a, i32 %b) nounwind readnone16 store double %result, ptr addrspace(1) %out, align 817 ret void18}19 20; SI-LABEL: {{^}}test_trig_preop_f64_imm_segment:21; SI: buffer_load_dwordx2 [[SRC:v\[[0-9]+:[0-9]+\]]],22; SI: v_trig_preop_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[SRC]], 723; SI: buffer_store_dwordx2 [[RESULT]],24; SI: s_endpgm25define amdgpu_kernel void @test_trig_preop_f64_imm_segment(ptr addrspace(1) %out, ptr addrspace(1) %aptr) nounwind {26 %a = load double, ptr addrspace(1) %aptr, align 827 %result = call double @llvm.amdgcn.trig.preop.f64(double %a, i32 7) nounwind readnone28 store double %result, ptr addrspace(1) %out, align 829 ret void30}31