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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn < %s | FileCheck --check-prefix=SI %s3; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck --check-prefix=VI %s4 5define amdgpu_kernel void @bfe_u32_arg_arg_arg(ptr addrspace(1) %out, i32 %src0, i32 %src1, i32 %src2) #0 {6; SI-LABEL: bfe_u32_arg_arg_arg:7; SI: ; %bb.0:8; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x99; SI-NEXT: s_mov_b32 s7, 0xf00010; SI-NEXT: s_mov_b32 s6, -111; SI-NEXT: s_waitcnt lgkmcnt(0)12; SI-NEXT: s_mov_b32 s4, s013; SI-NEXT: s_mov_b32 s5, s114; SI-NEXT: v_mov_b32_e32 v0, s215; SI-NEXT: v_bfe_u32 v0, v0, s3, s316; SI-NEXT: buffer_store_dword v0, off, s[4:7], 017; SI-NEXT: s_endpgm18;19; VI-LABEL: bfe_u32_arg_arg_arg:20; VI: ; %bb.0:21; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2422; VI-NEXT: s_mov_b32 s7, 0xf00023; VI-NEXT: s_mov_b32 s6, -124; VI-NEXT: s_waitcnt lgkmcnt(0)25; VI-NEXT: v_mov_b32_e32 v0, s226; VI-NEXT: s_mov_b32 s4, s027; VI-NEXT: s_mov_b32 s5, s128; VI-NEXT: v_bfe_u32 v0, v0, s3, s329; VI-NEXT: buffer_store_dword v0, off, s[4:7], 030; VI-NEXT: s_endpgm31 %bfe_u32 = call i32 @llvm.amdgcn.ubfe.i32(i32 %src0, i32 %src1, i32 %src1)32 store i32 %bfe_u32, ptr addrspace(1) %out, align 433 ret void34}35 36define amdgpu_kernel void @bfe_u32_arg_arg_imm(ptr addrspace(1) %out, i32 %src0, i32 %src1) #0 {37; SI-LABEL: bfe_u32_arg_arg_imm:38; SI: ; %bb.0:39; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x940; SI-NEXT: s_mov_b32 s7, 0xf00041; SI-NEXT: s_mov_b32 s6, -142; SI-NEXT: v_mov_b32_e32 v0, 0x7b43; SI-NEXT: s_waitcnt lgkmcnt(0)44; SI-NEXT: s_mov_b32 s4, s045; SI-NEXT: s_mov_b32 s5, s146; SI-NEXT: v_mov_b32_e32 v1, s347; SI-NEXT: v_bfe_u32 v0, s2, v1, v048; SI-NEXT: buffer_store_dword v0, off, s[4:7], 049; SI-NEXT: s_endpgm50;51; VI-LABEL: bfe_u32_arg_arg_imm:52; VI: ; %bb.0:53; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2454; VI-NEXT: v_mov_b32_e32 v1, 0x7b55; VI-NEXT: s_mov_b32 s7, 0xf00056; VI-NEXT: s_mov_b32 s6, -157; VI-NEXT: s_waitcnt lgkmcnt(0)58; VI-NEXT: v_mov_b32_e32 v0, s359; VI-NEXT: s_mov_b32 s4, s060; VI-NEXT: s_mov_b32 s5, s161; VI-NEXT: v_bfe_u32 v0, s2, v0, v162; VI-NEXT: buffer_store_dword v0, off, s[4:7], 063; VI-NEXT: s_endpgm64 %bfe_u32 = call i32 @llvm.amdgcn.ubfe.i32(i32 %src0, i32 %src1, i32 123)65 store i32 %bfe_u32, ptr addrspace(1) %out, align 466 ret void67}68 69define amdgpu_kernel void @bfe_u32_arg_imm_arg(ptr addrspace(1) %out, i32 %src0, i32 %src2) #0 {70; SI-LABEL: bfe_u32_arg_imm_arg:71; SI: ; %bb.0:72; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x973; SI-NEXT: s_mov_b32 s7, 0xf00074; SI-NEXT: s_mov_b32 s6, -175; SI-NEXT: v_mov_b32_e32 v0, 0x7b76; SI-NEXT: s_waitcnt lgkmcnt(0)77; SI-NEXT: s_mov_b32 s4, s078; SI-NEXT: s_mov_b32 s5, s179; SI-NEXT: v_mov_b32_e32 v1, s380; SI-NEXT: v_bfe_u32 v0, s2, v0, v181; SI-NEXT: buffer_store_dword v0, off, s[4:7], 082; SI-NEXT: s_endpgm83;84; VI-LABEL: bfe_u32_arg_imm_arg:85; VI: ; %bb.0:86; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2487; VI-NEXT: v_mov_b32_e32 v0, 0x7b88; VI-NEXT: s_mov_b32 s7, 0xf00089; VI-NEXT: s_mov_b32 s6, -190; VI-NEXT: s_waitcnt lgkmcnt(0)91; VI-NEXT: v_mov_b32_e32 v1, s392; VI-NEXT: s_mov_b32 s4, s093; VI-NEXT: s_mov_b32 s5, s194; VI-NEXT: v_bfe_u32 v0, s2, v0, v195; VI-NEXT: buffer_store_dword v0, off, s[4:7], 096; VI-NEXT: s_endpgm97 %bfe_u32 = call i32 @llvm.amdgcn.ubfe.i32(i32 %src0, i32 123, i32 %src2)98 store i32 %bfe_u32, ptr addrspace(1) %out, align 499 ret void100}101 102define amdgpu_kernel void @bfe_u32_imm_arg_arg(ptr addrspace(1) %out, i32 %src1, i32 %src2) #0 {103; SI-LABEL: bfe_u32_imm_arg_arg:104; SI: ; %bb.0:105; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9106; SI-NEXT: s_mov_b32 s7, 0xf000107; SI-NEXT: s_mov_b32 s6, -1108; SI-NEXT: s_movk_i32 s8, 0x7b109; SI-NEXT: s_waitcnt lgkmcnt(0)110; SI-NEXT: s_mov_b32 s4, s0111; SI-NEXT: s_mov_b32 s5, s1112; SI-NEXT: v_mov_b32_e32 v0, s2113; SI-NEXT: v_mov_b32_e32 v1, s3114; SI-NEXT: v_bfe_u32 v0, s8, v0, v1115; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0116; SI-NEXT: s_endpgm117;118; VI-LABEL: bfe_u32_imm_arg_arg:119; VI: ; %bb.0:120; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24121; VI-NEXT: s_movk_i32 s8, 0x7b122; VI-NEXT: s_mov_b32 s7, 0xf000123; VI-NEXT: s_mov_b32 s6, -1124; VI-NEXT: s_waitcnt lgkmcnt(0)125; VI-NEXT: v_mov_b32_e32 v0, s2126; VI-NEXT: v_mov_b32_e32 v1, s3127; VI-NEXT: s_mov_b32 s4, s0128; VI-NEXT: s_mov_b32 s5, s1129; VI-NEXT: v_bfe_u32 v0, s8, v0, v1130; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0131; VI-NEXT: s_endpgm132 %bfe_u32 = call i32 @llvm.amdgcn.ubfe.i32(i32 123, i32 %src1, i32 %src2)133 store i32 %bfe_u32, ptr addrspace(1) %out, align 4134 ret void135}136 137define amdgpu_kernel void @bfe_u32_arg_0_width_reg_offset(ptr addrspace(1) %out, i32 %src0, i32 %src1) #0 {138; SI-LABEL: bfe_u32_arg_0_width_reg_offset:139; SI: ; %bb.0:140; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9141; SI-NEXT: s_mov_b32 s3, 0xf000142; SI-NEXT: s_mov_b32 s2, -1143; SI-NEXT: v_mov_b32_e32 v0, 0144; SI-NEXT: s_waitcnt lgkmcnt(0)145; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0146; SI-NEXT: s_endpgm147;148; VI-LABEL: bfe_u32_arg_0_width_reg_offset:149; VI: ; %bb.0:150; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24151; VI-NEXT: s_mov_b32 s3, 0xf000152; VI-NEXT: s_mov_b32 s2, -1153; VI-NEXT: v_mov_b32_e32 v0, 0154; VI-NEXT: s_waitcnt lgkmcnt(0)155; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0156; VI-NEXT: s_endpgm157 %bfe_u32 = call i32 @llvm.amdgcn.ubfe.i32(i32 %src0, i32 %src1, i32 0)158 store i32 %bfe_u32, ptr addrspace(1) %out, align 4159 ret void160}161 162define amdgpu_kernel void @bfe_u32_arg_0_width_imm_offset(ptr addrspace(1) %out, i32 %src0, i32 %src1) #0 {163; SI-LABEL: bfe_u32_arg_0_width_imm_offset:164; SI: ; %bb.0:165; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9166; SI-NEXT: s_mov_b32 s3, 0xf000167; SI-NEXT: s_mov_b32 s2, -1168; SI-NEXT: v_mov_b32_e32 v0, 0169; SI-NEXT: s_waitcnt lgkmcnt(0)170; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0171; SI-NEXT: s_endpgm172;173; VI-LABEL: bfe_u32_arg_0_width_imm_offset:174; VI: ; %bb.0:175; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24176; VI-NEXT: s_mov_b32 s3, 0xf000177; VI-NEXT: s_mov_b32 s2, -1178; VI-NEXT: v_mov_b32_e32 v0, 0179; VI-NEXT: s_waitcnt lgkmcnt(0)180; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0181; VI-NEXT: s_endpgm182 %bfe_u32 = call i32 @llvm.amdgcn.ubfe.i32(i32 %src0, i32 8, i32 0)183 store i32 %bfe_u32, ptr addrspace(1) %out, align 4184 ret void185}186 187define amdgpu_kernel void @bfe_u32_zextload_i8(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {188; SI-LABEL: bfe_u32_zextload_i8:189; SI: ; %bb.0:190; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9191; SI-NEXT: s_mov_b32 s7, 0xf000192; SI-NEXT: s_mov_b32 s6, -1193; SI-NEXT: s_mov_b32 s10, s6194; SI-NEXT: s_mov_b32 s11, s7195; SI-NEXT: s_waitcnt lgkmcnt(0)196; SI-NEXT: s_mov_b32 s8, s2197; SI-NEXT: s_mov_b32 s9, s3198; SI-NEXT: buffer_load_ubyte v0, off, s[8:11], 0199; SI-NEXT: s_mov_b32 s4, s0200; SI-NEXT: s_mov_b32 s5, s1201; SI-NEXT: s_waitcnt vmcnt(0)202; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0203; SI-NEXT: s_endpgm204;205; VI-LABEL: bfe_u32_zextload_i8:206; VI: ; %bb.0:207; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24208; VI-NEXT: s_mov_b32 s7, 0xf000209; VI-NEXT: s_mov_b32 s6, -1210; VI-NEXT: s_mov_b32 s10, s6211; VI-NEXT: s_mov_b32 s11, s7212; VI-NEXT: s_waitcnt lgkmcnt(0)213; VI-NEXT: s_mov_b32 s8, s2214; VI-NEXT: s_mov_b32 s9, s3215; VI-NEXT: buffer_load_ubyte v0, off, s[8:11], 0216; VI-NEXT: s_mov_b32 s4, s0217; VI-NEXT: s_mov_b32 s5, s1218; VI-NEXT: s_waitcnt vmcnt(0)219; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0220; VI-NEXT: s_endpgm221 %load = load i8, ptr addrspace(1) %in222 %ext = zext i8 %load to i32223 %bfe = call i32 @llvm.amdgcn.ubfe.i32(i32 %ext, i32 0, i32 8)224 store i32 %bfe, ptr addrspace(1) %out, align 4225 ret void226}227 228; FIXME: Should be using s_add_i32229define amdgpu_kernel void @bfe_u32_zext_in_reg_i8(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {230; SI-LABEL: bfe_u32_zext_in_reg_i8:231; SI: ; %bb.0:232; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9233; SI-NEXT: s_mov_b32 s7, 0xf000234; SI-NEXT: s_mov_b32 s6, -1235; SI-NEXT: s_mov_b32 s10, s6236; SI-NEXT: s_mov_b32 s11, s7237; SI-NEXT: s_waitcnt lgkmcnt(0)238; SI-NEXT: s_mov_b32 s8, s2239; SI-NEXT: s_mov_b32 s9, s3240; SI-NEXT: buffer_load_dword v0, off, s[8:11], 0241; SI-NEXT: s_mov_b32 s4, s0242; SI-NEXT: s_mov_b32 s5, s1243; SI-NEXT: s_waitcnt vmcnt(0)244; SI-NEXT: v_add_i32_e32 v0, vcc, 1, v0245; SI-NEXT: v_and_b32_e32 v0, 0xff, v0246; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0247; SI-NEXT: s_endpgm248;249; VI-LABEL: bfe_u32_zext_in_reg_i8:250; VI: ; %bb.0:251; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24252; VI-NEXT: s_mov_b32 s7, 0xf000253; VI-NEXT: s_mov_b32 s6, -1254; VI-NEXT: s_mov_b32 s10, s6255; VI-NEXT: s_mov_b32 s11, s7256; VI-NEXT: s_waitcnt lgkmcnt(0)257; VI-NEXT: s_mov_b32 s8, s2258; VI-NEXT: s_mov_b32 s9, s3259; VI-NEXT: buffer_load_dword v0, off, s[8:11], 0260; VI-NEXT: s_mov_b32 s4, s0261; VI-NEXT: s_mov_b32 s5, s1262; VI-NEXT: s_waitcnt vmcnt(0)263; VI-NEXT: v_add_u32_e32 v0, vcc, 1, v0264; VI-NEXT: v_and_b32_e32 v0, 0xff, v0265; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0266; VI-NEXT: s_endpgm267 %load = load i32, ptr addrspace(1) %in, align 4268 %add = add i32 %load, 1269 %ext = and i32 %add, 255270 %bfe = call i32 @llvm.amdgcn.ubfe.i32(i32 %ext, i32 0, i32 8)271 store i32 %bfe, ptr addrspace(1) %out, align 4272 ret void273}274 275define amdgpu_kernel void @bfe_u32_zext_in_reg_i16(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {276; SI-LABEL: bfe_u32_zext_in_reg_i16:277; SI: ; %bb.0:278; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9279; SI-NEXT: s_mov_b32 s7, 0xf000280; SI-NEXT: s_mov_b32 s6, -1281; SI-NEXT: s_mov_b32 s10, s6282; SI-NEXT: s_mov_b32 s11, s7283; SI-NEXT: s_waitcnt lgkmcnt(0)284; SI-NEXT: s_mov_b32 s8, s2285; SI-NEXT: s_mov_b32 s9, s3286; SI-NEXT: buffer_load_dword v0, off, s[8:11], 0287; SI-NEXT: s_mov_b32 s4, s0288; SI-NEXT: s_mov_b32 s5, s1289; SI-NEXT: s_waitcnt vmcnt(0)290; SI-NEXT: v_add_i32_e32 v0, vcc, 1, v0291; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0292; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0293; SI-NEXT: s_endpgm294;295; VI-LABEL: bfe_u32_zext_in_reg_i16:296; VI: ; %bb.0:297; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24298; VI-NEXT: s_mov_b32 s7, 0xf000299; VI-NEXT: s_mov_b32 s6, -1300; VI-NEXT: s_mov_b32 s10, s6301; VI-NEXT: s_mov_b32 s11, s7302; VI-NEXT: s_waitcnt lgkmcnt(0)303; VI-NEXT: s_mov_b32 s8, s2304; VI-NEXT: s_mov_b32 s9, s3305; VI-NEXT: buffer_load_dword v0, off, s[8:11], 0306; VI-NEXT: s_mov_b32 s4, s0307; VI-NEXT: s_mov_b32 s5, s1308; VI-NEXT: s_waitcnt vmcnt(0)309; VI-NEXT: v_add_u32_e32 v0, vcc, 1, v0310; VI-NEXT: v_and_b32_e32 v0, 0xffff, v0311; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0312; VI-NEXT: s_endpgm313 %load = load i32, ptr addrspace(1) %in, align 4314 %add = add i32 %load, 1315 %ext = and i32 %add, 65535316 %bfe = call i32 @llvm.amdgcn.ubfe.i32(i32 %ext, i32 0, i32 16)317 store i32 %bfe, ptr addrspace(1) %out, align 4318 ret void319}320 321define amdgpu_kernel void @bfe_u32_zext_in_reg_i8_offset_1(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {322; SI-LABEL: bfe_u32_zext_in_reg_i8_offset_1:323; SI: ; %bb.0:324; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9325; SI-NEXT: s_mov_b32 s7, 0xf000326; SI-NEXT: s_mov_b32 s6, -1327; SI-NEXT: s_mov_b32 s10, s6328; SI-NEXT: s_mov_b32 s11, s7329; SI-NEXT: s_waitcnt lgkmcnt(0)330; SI-NEXT: s_mov_b32 s8, s2331; SI-NEXT: s_mov_b32 s9, s3332; SI-NEXT: buffer_load_dword v0, off, s[8:11], 0333; SI-NEXT: s_mov_b32 s4, s0334; SI-NEXT: s_mov_b32 s5, s1335; SI-NEXT: s_waitcnt vmcnt(0)336; SI-NEXT: v_add_i32_e32 v0, vcc, 1, v0337; SI-NEXT: v_and_b32_e32 v0, 0xfe, v0338; SI-NEXT: v_bfe_u32 v0, v0, 1, 8339; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0340; SI-NEXT: s_endpgm341;342; VI-LABEL: bfe_u32_zext_in_reg_i8_offset_1:343; VI: ; %bb.0:344; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24345; VI-NEXT: s_mov_b32 s7, 0xf000346; VI-NEXT: s_mov_b32 s6, -1347; VI-NEXT: s_mov_b32 s10, s6348; VI-NEXT: s_mov_b32 s11, s7349; VI-NEXT: s_waitcnt lgkmcnt(0)350; VI-NEXT: s_mov_b32 s8, s2351; VI-NEXT: s_mov_b32 s9, s3352; VI-NEXT: buffer_load_dword v0, off, s[8:11], 0353; VI-NEXT: s_mov_b32 s4, s0354; VI-NEXT: s_mov_b32 s5, s1355; VI-NEXT: s_waitcnt vmcnt(0)356; VI-NEXT: v_add_u32_e32 v0, vcc, 1, v0357; VI-NEXT: v_and_b32_e32 v0, 0xfe, v0358; VI-NEXT: v_bfe_u32 v0, v0, 1, 8359; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0360; VI-NEXT: s_endpgm361 %load = load i32, ptr addrspace(1) %in, align 4362 %add = add i32 %load, 1363 %ext = and i32 %add, 255364 %bfe = call i32 @llvm.amdgcn.ubfe.i32(i32 %ext, i32 1, i32 8)365 store i32 %bfe, ptr addrspace(1) %out, align 4366 ret void367}368 369define amdgpu_kernel void @bfe_u32_zext_in_reg_i8_offset_3(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {370; SI-LABEL: bfe_u32_zext_in_reg_i8_offset_3:371; SI: ; %bb.0:372; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9373; SI-NEXT: s_mov_b32 s7, 0xf000374; SI-NEXT: s_mov_b32 s6, -1375; SI-NEXT: s_mov_b32 s10, s6376; SI-NEXT: s_mov_b32 s11, s7377; SI-NEXT: s_waitcnt lgkmcnt(0)378; SI-NEXT: s_mov_b32 s8, s2379; SI-NEXT: s_mov_b32 s9, s3380; SI-NEXT: buffer_load_dword v0, off, s[8:11], 0381; SI-NEXT: s_mov_b32 s4, s0382; SI-NEXT: s_mov_b32 s5, s1383; SI-NEXT: s_waitcnt vmcnt(0)384; SI-NEXT: v_add_i32_e32 v0, vcc, 1, v0385; SI-NEXT: v_and_b32_e32 v0, 0xf8, v0386; SI-NEXT: v_bfe_u32 v0, v0, 3, 8387; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0388; SI-NEXT: s_endpgm389;390; VI-LABEL: bfe_u32_zext_in_reg_i8_offset_3:391; VI: ; %bb.0:392; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24393; VI-NEXT: s_mov_b32 s7, 0xf000394; VI-NEXT: s_mov_b32 s6, -1395; VI-NEXT: s_mov_b32 s10, s6396; VI-NEXT: s_mov_b32 s11, s7397; VI-NEXT: s_waitcnt lgkmcnt(0)398; VI-NEXT: s_mov_b32 s8, s2399; VI-NEXT: s_mov_b32 s9, s3400; VI-NEXT: buffer_load_dword v0, off, s[8:11], 0401; VI-NEXT: s_mov_b32 s4, s0402; VI-NEXT: s_mov_b32 s5, s1403; VI-NEXT: s_waitcnt vmcnt(0)404; VI-NEXT: v_add_u32_e32 v0, vcc, 1, v0405; VI-NEXT: v_and_b32_e32 v0, 0xf8, v0406; VI-NEXT: v_bfe_u32 v0, v0, 3, 8407; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0408; VI-NEXT: s_endpgm409 %load = load i32, ptr addrspace(1) %in, align 4410 %add = add i32 %load, 1411 %ext = and i32 %add, 255412 %bfe = call i32 @llvm.amdgcn.ubfe.i32(i32 %ext, i32 3, i32 8)413 store i32 %bfe, ptr addrspace(1) %out, align 4414 ret void415}416 417define amdgpu_kernel void @bfe_u32_zext_in_reg_i8_offset_7(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {418; SI-LABEL: bfe_u32_zext_in_reg_i8_offset_7:419; SI: ; %bb.0:420; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9421; SI-NEXT: s_mov_b32 s7, 0xf000422; SI-NEXT: s_mov_b32 s6, -1423; SI-NEXT: s_mov_b32 s10, s6424; SI-NEXT: s_mov_b32 s11, s7425; SI-NEXT: s_waitcnt lgkmcnt(0)426; SI-NEXT: s_mov_b32 s8, s2427; SI-NEXT: s_mov_b32 s9, s3428; SI-NEXT: buffer_load_dword v0, off, s[8:11], 0429; SI-NEXT: s_mov_b32 s4, s0430; SI-NEXT: s_mov_b32 s5, s1431; SI-NEXT: s_waitcnt vmcnt(0)432; SI-NEXT: v_add_i32_e32 v0, vcc, 1, v0433; SI-NEXT: v_and_b32_e32 v0, 0x80, v0434; SI-NEXT: v_bfe_u32 v0, v0, 7, 8435; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0436; SI-NEXT: s_endpgm437;438; VI-LABEL: bfe_u32_zext_in_reg_i8_offset_7:439; VI: ; %bb.0:440; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24441; VI-NEXT: s_mov_b32 s7, 0xf000442; VI-NEXT: s_mov_b32 s6, -1443; VI-NEXT: s_mov_b32 s10, s6444; VI-NEXT: s_mov_b32 s11, s7445; VI-NEXT: s_waitcnt lgkmcnt(0)446; VI-NEXT: s_mov_b32 s8, s2447; VI-NEXT: s_mov_b32 s9, s3448; VI-NEXT: buffer_load_dword v0, off, s[8:11], 0449; VI-NEXT: s_mov_b32 s4, s0450; VI-NEXT: s_mov_b32 s5, s1451; VI-NEXT: s_waitcnt vmcnt(0)452; VI-NEXT: v_add_u32_e32 v0, vcc, 1, v0453; VI-NEXT: v_and_b32_e32 v0, 0x80, v0454; VI-NEXT: v_bfe_u32 v0, v0, 7, 8455; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0456; VI-NEXT: s_endpgm457 %load = load i32, ptr addrspace(1) %in, align 4458 %add = add i32 %load, 1459 %ext = and i32 %add, 255460 %bfe = call i32 @llvm.amdgcn.ubfe.i32(i32 %ext, i32 7, i32 8)461 store i32 %bfe, ptr addrspace(1) %out, align 4462 ret void463}464 465define amdgpu_kernel void @bfe_u32_zext_in_reg_i16_offset_8(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {466; SI-LABEL: bfe_u32_zext_in_reg_i16_offset_8:467; SI: ; %bb.0:468; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9469; SI-NEXT: s_mov_b32 s7, 0xf000470; SI-NEXT: s_mov_b32 s6, -1471; SI-NEXT: s_mov_b32 s10, s6472; SI-NEXT: s_mov_b32 s11, s7473; SI-NEXT: s_waitcnt lgkmcnt(0)474; SI-NEXT: s_mov_b32 s8, s2475; SI-NEXT: s_mov_b32 s9, s3476; SI-NEXT: buffer_load_dword v0, off, s[8:11], 0477; SI-NEXT: s_mov_b32 s4, s0478; SI-NEXT: s_mov_b32 s5, s1479; SI-NEXT: s_waitcnt vmcnt(0)480; SI-NEXT: v_add_i32_e32 v0, vcc, 1, v0481; SI-NEXT: v_bfe_u32 v0, v0, 8, 8482; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0483; SI-NEXT: s_endpgm484;485; VI-LABEL: bfe_u32_zext_in_reg_i16_offset_8:486; VI: ; %bb.0:487; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24488; VI-NEXT: s_mov_b32 s7, 0xf000489; VI-NEXT: s_mov_b32 s6, -1490; VI-NEXT: s_mov_b32 s10, s6491; VI-NEXT: s_mov_b32 s11, s7492; VI-NEXT: s_waitcnt lgkmcnt(0)493; VI-NEXT: s_mov_b32 s8, s2494; VI-NEXT: s_mov_b32 s9, s3495; VI-NEXT: buffer_load_dword v0, off, s[8:11], 0496; VI-NEXT: s_mov_b32 s4, s0497; VI-NEXT: s_mov_b32 s5, s1498; VI-NEXT: s_waitcnt vmcnt(0)499; VI-NEXT: v_add_u32_e32 v0, vcc, 1, v0500; VI-NEXT: v_bfe_u32 v0, v0, 8, 8501; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0502; VI-NEXT: s_endpgm503 %load = load i32, ptr addrspace(1) %in, align 4504 %add = add i32 %load, 1505 %ext = and i32 %add, 65535506 %bfe = call i32 @llvm.amdgcn.ubfe.i32(i32 %ext, i32 8, i32 8)507 store i32 %bfe, ptr addrspace(1) %out, align 4508 ret void509}510 511define amdgpu_kernel void @bfe_u32_test_1(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {512; SI-LABEL: bfe_u32_test_1:513; SI: ; %bb.0:514; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9515; SI-NEXT: s_mov_b32 s7, 0xf000516; SI-NEXT: s_mov_b32 s6, -1517; SI-NEXT: s_mov_b32 s10, s6518; SI-NEXT: s_mov_b32 s11, s7519; SI-NEXT: s_waitcnt lgkmcnt(0)520; SI-NEXT: s_mov_b32 s8, s2521; SI-NEXT: s_mov_b32 s9, s3522; SI-NEXT: buffer_load_dword v0, off, s[8:11], 0523; SI-NEXT: s_mov_b32 s4, s0524; SI-NEXT: s_mov_b32 s5, s1525; SI-NEXT: s_waitcnt vmcnt(0)526; SI-NEXT: v_and_b32_e32 v0, 1, v0527; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0528; SI-NEXT: s_endpgm529;530; VI-LABEL: bfe_u32_test_1:531; VI: ; %bb.0:532; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24533; VI-NEXT: s_mov_b32 s7, 0xf000534; VI-NEXT: s_mov_b32 s6, -1535; VI-NEXT: s_mov_b32 s10, s6536; VI-NEXT: s_mov_b32 s11, s7537; VI-NEXT: s_waitcnt lgkmcnt(0)538; VI-NEXT: s_mov_b32 s8, s2539; VI-NEXT: s_mov_b32 s9, s3540; VI-NEXT: buffer_load_dword v0, off, s[8:11], 0541; VI-NEXT: s_mov_b32 s4, s0542; VI-NEXT: s_mov_b32 s5, s1543; VI-NEXT: s_waitcnt vmcnt(0)544; VI-NEXT: v_and_b32_e32 v0, 1, v0545; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0546; VI-NEXT: s_endpgm547 %x = load i32, ptr addrspace(1) %in, align 4548 %bfe = call i32 @llvm.amdgcn.ubfe.i32(i32 %x, i32 0, i32 1)549 store i32 %bfe, ptr addrspace(1) %out, align 4550 ret void551}552 553define amdgpu_kernel void @bfe_u32_test_2(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {554; SI-LABEL: bfe_u32_test_2:555; SI: ; %bb.0:556; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9557; SI-NEXT: s_waitcnt lgkmcnt(0)558; SI-NEXT: s_mov_b32 s3, 0xf000559; SI-NEXT: s_mov_b32 s2, -1560; SI-NEXT: v_mov_b32_e32 v0, 0561; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0562; SI-NEXT: s_endpgm563;564; VI-LABEL: bfe_u32_test_2:565; VI: ; %bb.0:566; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24567; VI-NEXT: s_waitcnt lgkmcnt(0)568; VI-NEXT: s_mov_b32 s3, 0xf000569; VI-NEXT: s_mov_b32 s2, -1570; VI-NEXT: v_mov_b32_e32 v0, 0571; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0572; VI-NEXT: s_endpgm573 %x = load i32, ptr addrspace(1) %in, align 4574 %shl = shl i32 %x, 31575 %bfe = call i32 @llvm.amdgcn.ubfe.i32(i32 %shl, i32 0, i32 8)576 store i32 %bfe, ptr addrspace(1) %out, align 4577 ret void578}579 580define amdgpu_kernel void @bfe_u32_test_3(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {581; SI-LABEL: bfe_u32_test_3:582; SI: ; %bb.0:583; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9584; SI-NEXT: s_waitcnt lgkmcnt(0)585; SI-NEXT: s_mov_b32 s3, 0xf000586; SI-NEXT: s_mov_b32 s2, -1587; SI-NEXT: v_mov_b32_e32 v0, 0588; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0589; SI-NEXT: s_endpgm590;591; VI-LABEL: bfe_u32_test_3:592; VI: ; %bb.0:593; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24594; VI-NEXT: s_waitcnt lgkmcnt(0)595; VI-NEXT: s_mov_b32 s3, 0xf000596; VI-NEXT: s_mov_b32 s2, -1597; VI-NEXT: v_mov_b32_e32 v0, 0598; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0599; VI-NEXT: s_endpgm600 %x = load i32, ptr addrspace(1) %in, align 4601 %shl = shl i32 %x, 31602 %bfe = call i32 @llvm.amdgcn.ubfe.i32(i32 %shl, i32 0, i32 1)603 store i32 %bfe, ptr addrspace(1) %out, align 4604 ret void605}606 607define amdgpu_kernel void @bfe_u32_test_4(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {608; SI-LABEL: bfe_u32_test_4:609; SI: ; %bb.0:610; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9611; SI-NEXT: s_waitcnt lgkmcnt(0)612; SI-NEXT: s_mov_b32 s3, 0xf000613; SI-NEXT: s_mov_b32 s2, -1614; SI-NEXT: v_mov_b32_e32 v0, 0615; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0616; SI-NEXT: s_endpgm617;618; VI-LABEL: bfe_u32_test_4:619; VI: ; %bb.0:620; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24621; VI-NEXT: s_waitcnt lgkmcnt(0)622; VI-NEXT: s_mov_b32 s3, 0xf000623; VI-NEXT: s_mov_b32 s2, -1624; VI-NEXT: v_mov_b32_e32 v0, 0625; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0626; VI-NEXT: s_endpgm627 %x = load i32, ptr addrspace(1) %in, align 4628 %shl = shl i32 %x, 31629 %shr = lshr i32 %shl, 31630 %bfe = call i32 @llvm.amdgcn.ubfe.i32(i32 %shr, i32 31, i32 1)631 store i32 %bfe, ptr addrspace(1) %out, align 4632 ret void633}634 635define amdgpu_kernel void @bfe_u32_test_5(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {636; SI-LABEL: bfe_u32_test_5:637; SI: ; %bb.0:638; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9639; SI-NEXT: s_mov_b32 s7, 0xf000640; SI-NEXT: s_mov_b32 s6, -1641; SI-NEXT: s_mov_b32 s10, s6642; SI-NEXT: s_mov_b32 s11, s7643; SI-NEXT: s_waitcnt lgkmcnt(0)644; SI-NEXT: s_mov_b32 s8, s2645; SI-NEXT: s_mov_b32 s9, s3646; SI-NEXT: buffer_load_dword v0, off, s[8:11], 0647; SI-NEXT: s_mov_b32 s4, s0648; SI-NEXT: s_mov_b32 s5, s1649; SI-NEXT: s_waitcnt vmcnt(0)650; SI-NEXT: v_bfe_i32 v0, v0, 0, 1651; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0652; SI-NEXT: s_endpgm653;654; VI-LABEL: bfe_u32_test_5:655; VI: ; %bb.0:656; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24657; VI-NEXT: s_mov_b32 s7, 0xf000658; VI-NEXT: s_mov_b32 s6, -1659; VI-NEXT: s_mov_b32 s10, s6660; VI-NEXT: s_mov_b32 s11, s7661; VI-NEXT: s_waitcnt lgkmcnt(0)662; VI-NEXT: s_mov_b32 s8, s2663; VI-NEXT: s_mov_b32 s9, s3664; VI-NEXT: buffer_load_dword v0, off, s[8:11], 0665; VI-NEXT: s_mov_b32 s4, s0666; VI-NEXT: s_mov_b32 s5, s1667; VI-NEXT: s_waitcnt vmcnt(0)668; VI-NEXT: v_bfe_i32 v0, v0, 0, 1669; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0670; VI-NEXT: s_endpgm671 %x = load i32, ptr addrspace(1) %in, align 4672 %shl = shl i32 %x, 31673 %shr = ashr i32 %shl, 31674 %bfe = call i32 @llvm.amdgcn.ubfe.i32(i32 %shr, i32 0, i32 1)675 store i32 %bfe, ptr addrspace(1) %out, align 4676 ret void677}678 679define amdgpu_kernel void @bfe_u32_test_6(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {680; SI-LABEL: bfe_u32_test_6:681; SI: ; %bb.0:682; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9683; SI-NEXT: s_mov_b32 s7, 0xf000684; SI-NEXT: s_mov_b32 s6, -1685; SI-NEXT: s_mov_b32 s10, s6686; SI-NEXT: s_mov_b32 s11, s7687; SI-NEXT: s_waitcnt lgkmcnt(0)688; SI-NEXT: s_mov_b32 s8, s2689; SI-NEXT: s_mov_b32 s9, s3690; SI-NEXT: buffer_load_dword v0, off, s[8:11], 0691; SI-NEXT: s_mov_b32 s4, s0692; SI-NEXT: s_mov_b32 s5, s1693; SI-NEXT: s_waitcnt vmcnt(0)694; SI-NEXT: v_lshlrev_b32_e32 v0, 30, v0695; SI-NEXT: v_and_b32_e32 v0, 2.0, v0696; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0697; SI-NEXT: s_endpgm698;699; VI-LABEL: bfe_u32_test_6:700; VI: ; %bb.0:701; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24702; VI-NEXT: s_mov_b32 s7, 0xf000703; VI-NEXT: s_mov_b32 s6, -1704; VI-NEXT: s_mov_b32 s10, s6705; VI-NEXT: s_mov_b32 s11, s7706; VI-NEXT: s_waitcnt lgkmcnt(0)707; VI-NEXT: s_mov_b32 s8, s2708; VI-NEXT: s_mov_b32 s9, s3709; VI-NEXT: buffer_load_dword v0, off, s[8:11], 0710; VI-NEXT: s_mov_b32 s4, s0711; VI-NEXT: s_mov_b32 s5, s1712; VI-NEXT: s_waitcnt vmcnt(0)713; VI-NEXT: v_lshlrev_b32_e32 v0, 30, v0714; VI-NEXT: v_and_b32_e32 v0, 2.0, v0715; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0716; VI-NEXT: s_endpgm717 %x = load i32, ptr addrspace(1) %in, align 4718 %shl = shl i32 %x, 31719 %bfe = call i32 @llvm.amdgcn.ubfe.i32(i32 %shl, i32 1, i32 31)720 store i32 %bfe, ptr addrspace(1) %out, align 4721 ret void722}723 724define amdgpu_kernel void @bfe_u32_test_7(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {725; SI-LABEL: bfe_u32_test_7:726; SI: ; %bb.0:727; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9728; SI-NEXT: s_mov_b32 s7, 0xf000729; SI-NEXT: s_mov_b32 s6, -1730; SI-NEXT: s_mov_b32 s10, s6731; SI-NEXT: s_mov_b32 s11, s7732; SI-NEXT: s_waitcnt lgkmcnt(0)733; SI-NEXT: s_mov_b32 s8, s2734; SI-NEXT: s_mov_b32 s9, s3735; SI-NEXT: buffer_load_dword v0, off, s[8:11], 0736; SI-NEXT: s_mov_b32 s4, s0737; SI-NEXT: s_mov_b32 s5, s1738; SI-NEXT: s_waitcnt vmcnt(0)739; SI-NEXT: v_lshlrev_b32_e32 v0, 31, v0740; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0741; SI-NEXT: s_endpgm742;743; VI-LABEL: bfe_u32_test_7:744; VI: ; %bb.0:745; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24746; VI-NEXT: s_mov_b32 s7, 0xf000747; VI-NEXT: s_mov_b32 s6, -1748; VI-NEXT: s_mov_b32 s10, s6749; VI-NEXT: s_mov_b32 s11, s7750; VI-NEXT: s_waitcnt lgkmcnt(0)751; VI-NEXT: s_mov_b32 s8, s2752; VI-NEXT: s_mov_b32 s9, s3753; VI-NEXT: buffer_load_dword v0, off, s[8:11], 0754; VI-NEXT: s_mov_b32 s4, s0755; VI-NEXT: s_mov_b32 s5, s1756; VI-NEXT: s_waitcnt vmcnt(0)757; VI-NEXT: v_lshlrev_b32_e32 v0, 31, v0758; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0759; VI-NEXT: s_endpgm760 %x = load i32, ptr addrspace(1) %in, align 4761 %shl = shl i32 %x, 31762 %bfe = call i32 @llvm.amdgcn.ubfe.i32(i32 %shl, i32 0, i32 31)763 store i32 %bfe, ptr addrspace(1) %out, align 4764 ret void765}766 767define amdgpu_kernel void @bfe_u32_test_8(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {768; SI-LABEL: bfe_u32_test_8:769; SI: ; %bb.0:770; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9771; SI-NEXT: s_mov_b32 s7, 0xf000772; SI-NEXT: s_mov_b32 s6, -1773; SI-NEXT: s_mov_b32 s10, s6774; SI-NEXT: s_mov_b32 s11, s7775; SI-NEXT: s_waitcnt lgkmcnt(0)776; SI-NEXT: s_mov_b32 s8, s2777; SI-NEXT: s_mov_b32 s9, s3778; SI-NEXT: buffer_load_dword v0, off, s[8:11], 0779; SI-NEXT: s_mov_b32 s4, s0780; SI-NEXT: s_mov_b32 s5, s1781; SI-NEXT: s_waitcnt vmcnt(0)782; SI-NEXT: v_and_b32_e32 v0, 1, v0783; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0784; SI-NEXT: s_endpgm785;786; VI-LABEL: bfe_u32_test_8:787; VI: ; %bb.0:788; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24789; VI-NEXT: s_mov_b32 s7, 0xf000790; VI-NEXT: s_mov_b32 s6, -1791; VI-NEXT: s_mov_b32 s10, s6792; VI-NEXT: s_mov_b32 s11, s7793; VI-NEXT: s_waitcnt lgkmcnt(0)794; VI-NEXT: s_mov_b32 s8, s2795; VI-NEXT: s_mov_b32 s9, s3796; VI-NEXT: buffer_load_dword v0, off, s[8:11], 0797; VI-NEXT: s_mov_b32 s4, s0798; VI-NEXT: s_mov_b32 s5, s1799; VI-NEXT: s_waitcnt vmcnt(0)800; VI-NEXT: v_and_b32_e32 v0, 1, v0801; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0802; VI-NEXT: s_endpgm803 %x = load i32, ptr addrspace(1) %in, align 4804 %shl = shl i32 %x, 31805 %bfe = call i32 @llvm.amdgcn.ubfe.i32(i32 %shl, i32 31, i32 1)806 store i32 %bfe, ptr addrspace(1) %out, align 4807 ret void808}809 810define amdgpu_kernel void @bfe_u32_test_9(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {811; SI-LABEL: bfe_u32_test_9:812; SI: ; %bb.0:813; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9814; SI-NEXT: s_mov_b32 s7, 0xf000815; SI-NEXT: s_mov_b32 s6, -1816; SI-NEXT: s_mov_b32 s10, s6817; SI-NEXT: s_mov_b32 s11, s7818; SI-NEXT: s_waitcnt lgkmcnt(0)819; SI-NEXT: s_mov_b32 s8, s2820; SI-NEXT: s_mov_b32 s9, s3821; SI-NEXT: buffer_load_dword v0, off, s[8:11], 0822; SI-NEXT: s_mov_b32 s4, s0823; SI-NEXT: s_mov_b32 s5, s1824; SI-NEXT: s_waitcnt vmcnt(0)825; SI-NEXT: v_lshrrev_b32_e32 v0, 31, v0826; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0827; SI-NEXT: s_endpgm828;829; VI-LABEL: bfe_u32_test_9:830; VI: ; %bb.0:831; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24832; VI-NEXT: s_mov_b32 s7, 0xf000833; VI-NEXT: s_mov_b32 s6, -1834; VI-NEXT: s_mov_b32 s10, s6835; VI-NEXT: s_mov_b32 s11, s7836; VI-NEXT: s_waitcnt lgkmcnt(0)837; VI-NEXT: s_mov_b32 s8, s2838; VI-NEXT: s_mov_b32 s9, s3839; VI-NEXT: buffer_load_dword v0, off, s[8:11], 0840; VI-NEXT: s_mov_b32 s4, s0841; VI-NEXT: s_mov_b32 s5, s1842; VI-NEXT: s_waitcnt vmcnt(0)843; VI-NEXT: v_lshrrev_b32_e32 v0, 31, v0844; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0845; VI-NEXT: s_endpgm846 %x = load i32, ptr addrspace(1) %in, align 4847 %bfe = call i32 @llvm.amdgcn.ubfe.i32(i32 %x, i32 31, i32 1)848 store i32 %bfe, ptr addrspace(1) %out, align 4849 ret void850}851 852define amdgpu_kernel void @bfe_u32_test_10(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {853; SI-LABEL: bfe_u32_test_10:854; SI: ; %bb.0:855; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9856; SI-NEXT: s_mov_b32 s7, 0xf000857; SI-NEXT: s_mov_b32 s6, -1858; SI-NEXT: s_mov_b32 s10, s6859; SI-NEXT: s_mov_b32 s11, s7860; SI-NEXT: s_waitcnt lgkmcnt(0)861; SI-NEXT: s_mov_b32 s8, s2862; SI-NEXT: s_mov_b32 s9, s3863; SI-NEXT: buffer_load_dword v0, off, s[8:11], 0864; SI-NEXT: s_mov_b32 s4, s0865; SI-NEXT: s_mov_b32 s5, s1866; SI-NEXT: s_waitcnt vmcnt(0)867; SI-NEXT: v_lshrrev_b32_e32 v0, 1, v0868; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0869; SI-NEXT: s_endpgm870;871; VI-LABEL: bfe_u32_test_10:872; VI: ; %bb.0:873; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24874; VI-NEXT: s_mov_b32 s7, 0xf000875; VI-NEXT: s_mov_b32 s6, -1876; VI-NEXT: s_mov_b32 s10, s6877; VI-NEXT: s_mov_b32 s11, s7878; VI-NEXT: s_waitcnt lgkmcnt(0)879; VI-NEXT: s_mov_b32 s8, s2880; VI-NEXT: s_mov_b32 s9, s3881; VI-NEXT: buffer_load_dword v0, off, s[8:11], 0882; VI-NEXT: s_mov_b32 s4, s0883; VI-NEXT: s_mov_b32 s5, s1884; VI-NEXT: s_waitcnt vmcnt(0)885; VI-NEXT: v_lshrrev_b32_e32 v0, 1, v0886; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0887; VI-NEXT: s_endpgm888 %x = load i32, ptr addrspace(1) %in, align 4889 %bfe = call i32 @llvm.amdgcn.ubfe.i32(i32 %x, i32 1, i32 31)890 store i32 %bfe, ptr addrspace(1) %out, align 4891 ret void892}893 894define amdgpu_kernel void @bfe_u32_test_11(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {895; SI-LABEL: bfe_u32_test_11:896; SI: ; %bb.0:897; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9898; SI-NEXT: s_mov_b32 s7, 0xf000899; SI-NEXT: s_mov_b32 s6, -1900; SI-NEXT: s_mov_b32 s10, s6901; SI-NEXT: s_mov_b32 s11, s7902; SI-NEXT: s_waitcnt lgkmcnt(0)903; SI-NEXT: s_mov_b32 s8, s2904; SI-NEXT: s_mov_b32 s9, s3905; SI-NEXT: buffer_load_dword v0, off, s[8:11], 0906; SI-NEXT: s_mov_b32 s4, s0907; SI-NEXT: s_mov_b32 s5, s1908; SI-NEXT: s_waitcnt vmcnt(0)909; SI-NEXT: v_lshrrev_b32_e32 v0, 8, v0910; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0911; SI-NEXT: s_endpgm912;913; VI-LABEL: bfe_u32_test_11:914; VI: ; %bb.0:915; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24916; VI-NEXT: s_mov_b32 s7, 0xf000917; VI-NEXT: s_mov_b32 s6, -1918; VI-NEXT: s_mov_b32 s10, s6919; VI-NEXT: s_mov_b32 s11, s7920; VI-NEXT: s_waitcnt lgkmcnt(0)921; VI-NEXT: s_mov_b32 s8, s2922; VI-NEXT: s_mov_b32 s9, s3923; VI-NEXT: buffer_load_dword v0, off, s[8:11], 0924; VI-NEXT: s_mov_b32 s4, s0925; VI-NEXT: s_mov_b32 s5, s1926; VI-NEXT: s_waitcnt vmcnt(0)927; VI-NEXT: v_lshrrev_b32_e32 v0, 8, v0928; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0929; VI-NEXT: s_endpgm930 %x = load i32, ptr addrspace(1) %in, align 4931 %bfe = call i32 @llvm.amdgcn.ubfe.i32(i32 %x, i32 8, i32 24)932 store i32 %bfe, ptr addrspace(1) %out, align 4933 ret void934}935 936define amdgpu_kernel void @bfe_u32_test_12(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {937; SI-LABEL: bfe_u32_test_12:938; SI: ; %bb.0:939; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9940; SI-NEXT: s_mov_b32 s7, 0xf000941; SI-NEXT: s_mov_b32 s6, -1942; SI-NEXT: s_mov_b32 s10, s6943; SI-NEXT: s_mov_b32 s11, s7944; SI-NEXT: s_waitcnt lgkmcnt(0)945; SI-NEXT: s_mov_b32 s8, s2946; SI-NEXT: s_mov_b32 s9, s3947; SI-NEXT: buffer_load_dword v0, off, s[8:11], 0948; SI-NEXT: s_mov_b32 s4, s0949; SI-NEXT: s_mov_b32 s5, s1950; SI-NEXT: s_waitcnt vmcnt(0)951; SI-NEXT: v_lshrrev_b32_e32 v0, 24, v0952; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0953; SI-NEXT: s_endpgm954;955; VI-LABEL: bfe_u32_test_12:956; VI: ; %bb.0:957; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24958; VI-NEXT: s_mov_b32 s7, 0xf000959; VI-NEXT: s_mov_b32 s6, -1960; VI-NEXT: s_mov_b32 s10, s6961; VI-NEXT: s_mov_b32 s11, s7962; VI-NEXT: s_waitcnt lgkmcnt(0)963; VI-NEXT: s_mov_b32 s8, s2964; VI-NEXT: s_mov_b32 s9, s3965; VI-NEXT: buffer_load_dword v0, off, s[8:11], 0966; VI-NEXT: s_mov_b32 s4, s0967; VI-NEXT: s_mov_b32 s5, s1968; VI-NEXT: s_waitcnt vmcnt(0)969; VI-NEXT: v_lshrrev_b32_e32 v0, 24, v0970; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0971; VI-NEXT: s_endpgm972 %x = load i32, ptr addrspace(1) %in, align 4973 %bfe = call i32 @llvm.amdgcn.ubfe.i32(i32 %x, i32 24, i32 8)974 store i32 %bfe, ptr addrspace(1) %out, align 4975 ret void976}977 978; V_ASHRREV_U32_e32 {{v[0-9]+}}, 31, {{v[0-9]+}}979define amdgpu_kernel void @bfe_u32_test_13(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {980; SI-LABEL: bfe_u32_test_13:981; SI: ; %bb.0:982; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9983; SI-NEXT: s_mov_b32 s7, 0xf000984; SI-NEXT: s_mov_b32 s6, -1985; SI-NEXT: s_mov_b32 s10, s6986; SI-NEXT: s_mov_b32 s11, s7987; SI-NEXT: s_waitcnt lgkmcnt(0)988; SI-NEXT: s_mov_b32 s8, s2989; SI-NEXT: s_mov_b32 s9, s3990; SI-NEXT: buffer_load_dword v0, off, s[8:11], 0991; SI-NEXT: s_mov_b32 s4, s0992; SI-NEXT: s_mov_b32 s5, s1993; SI-NEXT: s_waitcnt vmcnt(0)994; SI-NEXT: v_lshrrev_b32_e32 v0, 31, v0995; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0996; SI-NEXT: s_endpgm997;998; VI-LABEL: bfe_u32_test_13:999; VI: ; %bb.0:1000; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241001; VI-NEXT: s_mov_b32 s7, 0xf0001002; VI-NEXT: s_mov_b32 s6, -11003; VI-NEXT: s_mov_b32 s10, s61004; VI-NEXT: s_mov_b32 s11, s71005; VI-NEXT: s_waitcnt lgkmcnt(0)1006; VI-NEXT: s_mov_b32 s8, s21007; VI-NEXT: s_mov_b32 s9, s31008; VI-NEXT: buffer_load_dword v0, off, s[8:11], 01009; VI-NEXT: s_mov_b32 s4, s01010; VI-NEXT: s_mov_b32 s5, s11011; VI-NEXT: s_waitcnt vmcnt(0)1012; VI-NEXT: v_lshrrev_b32_e32 v0, 31, v01013; VI-NEXT: buffer_store_dword v0, off, s[4:7], 01014; VI-NEXT: s_endpgm1015 %x = load i32, ptr addrspace(1) %in, align 41016 %shl = ashr i32 %x, 311017 %bfe = call i32 @llvm.amdgcn.ubfe.i32(i32 %shl, i32 31, i32 1)1018 store i32 %bfe, ptr addrspace(1) %out, align 4 ret void1019}1020 1021define amdgpu_kernel void @bfe_u32_test_14(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {1022; SI-LABEL: bfe_u32_test_14:1023; SI: ; %bb.0:1024; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91025; SI-NEXT: s_waitcnt lgkmcnt(0)1026; SI-NEXT: s_mov_b32 s3, 0xf0001027; SI-NEXT: s_mov_b32 s2, -11028; SI-NEXT: v_mov_b32_e32 v0, 01029; SI-NEXT: buffer_store_dword v0, off, s[0:3], 01030; SI-NEXT: s_endpgm1031;1032; VI-LABEL: bfe_u32_test_14:1033; VI: ; %bb.0:1034; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241035; VI-NEXT: s_waitcnt lgkmcnt(0)1036; VI-NEXT: s_mov_b32 s3, 0xf0001037; VI-NEXT: s_mov_b32 s2, -11038; VI-NEXT: v_mov_b32_e32 v0, 01039; VI-NEXT: buffer_store_dword v0, off, s[0:3], 01040; VI-NEXT: s_endpgm1041 %x = load i32, ptr addrspace(1) %in, align 41042 %shl = lshr i32 %x, 311043 %bfe = call i32 @llvm.amdgcn.ubfe.i32(i32 %shl, i32 31, i32 1)1044 store i32 %bfe, ptr addrspace(1) %out, align 4 ret void1045}1046 1047define amdgpu_kernel void @bfe_u32_constant_fold_test_0(ptr addrspace(1) %out) #0 {1048; SI-LABEL: bfe_u32_constant_fold_test_0:1049; SI: ; %bb.0:1050; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x91051; SI-NEXT: s_mov_b32 s3, 0xf0001052; SI-NEXT: s_mov_b32 s2, -11053; SI-NEXT: v_mov_b32_e32 v0, 01054; SI-NEXT: s_waitcnt lgkmcnt(0)1055; SI-NEXT: buffer_store_dword v0, off, s[0:3], 01056; SI-NEXT: s_endpgm1057;1058; VI-LABEL: bfe_u32_constant_fold_test_0:1059; VI: ; %bb.0:1060; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x241061; VI-NEXT: s_mov_b32 s3, 0xf0001062; VI-NEXT: s_mov_b32 s2, -11063; VI-NEXT: v_mov_b32_e32 v0, 01064; VI-NEXT: s_waitcnt lgkmcnt(0)1065; VI-NEXT: buffer_store_dword v0, off, s[0:3], 01066; VI-NEXT: s_endpgm1067 %bfe_u32 = call i32 @llvm.amdgcn.ubfe.i32(i32 0, i32 0, i32 0)1068 store i32 %bfe_u32, ptr addrspace(1) %out, align 41069 ret void1070}1071 1072define amdgpu_kernel void @bfe_u32_constant_fold_test_1(ptr addrspace(1) %out) #0 {1073; SI-LABEL: bfe_u32_constant_fold_test_1:1074; SI: ; %bb.0:1075; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x91076; SI-NEXT: s_mov_b32 s3, 0xf0001077; SI-NEXT: s_mov_b32 s2, -11078; SI-NEXT: v_mov_b32_e32 v0, 01079; SI-NEXT: s_waitcnt lgkmcnt(0)1080; SI-NEXT: buffer_store_dword v0, off, s[0:3], 01081; SI-NEXT: s_endpgm1082;1083; VI-LABEL: bfe_u32_constant_fold_test_1:1084; VI: ; %bb.0:1085; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x241086; VI-NEXT: s_mov_b32 s3, 0xf0001087; VI-NEXT: s_mov_b32 s2, -11088; VI-NEXT: v_mov_b32_e32 v0, 01089; VI-NEXT: s_waitcnt lgkmcnt(0)1090; VI-NEXT: buffer_store_dword v0, off, s[0:3], 01091; VI-NEXT: s_endpgm1092 %bfe_u32 = call i32 @llvm.amdgcn.ubfe.i32(i32 12334, i32 0, i32 0)1093 store i32 %bfe_u32, ptr addrspace(1) %out, align 41094 ret void1095}1096 1097define amdgpu_kernel void @bfe_u32_constant_fold_test_2(ptr addrspace(1) %out) #0 {1098; SI-LABEL: bfe_u32_constant_fold_test_2:1099; SI: ; %bb.0:1100; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x91101; SI-NEXT: s_mov_b32 s3, 0xf0001102; SI-NEXT: s_mov_b32 s2, -11103; SI-NEXT: v_mov_b32_e32 v0, 01104; SI-NEXT: s_waitcnt lgkmcnt(0)1105; SI-NEXT: buffer_store_dword v0, off, s[0:3], 01106; SI-NEXT: s_endpgm1107;1108; VI-LABEL: bfe_u32_constant_fold_test_2:1109; VI: ; %bb.0:1110; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x241111; VI-NEXT: s_mov_b32 s3, 0xf0001112; VI-NEXT: s_mov_b32 s2, -11113; VI-NEXT: v_mov_b32_e32 v0, 01114; VI-NEXT: s_waitcnt lgkmcnt(0)1115; VI-NEXT: buffer_store_dword v0, off, s[0:3], 01116; VI-NEXT: s_endpgm1117 %bfe_u32 = call i32 @llvm.amdgcn.ubfe.i32(i32 0, i32 0, i32 1)1118 store i32 %bfe_u32, ptr addrspace(1) %out, align 41119 ret void1120}1121 1122define amdgpu_kernel void @bfe_u32_constant_fold_test_3(ptr addrspace(1) %out) #0 {1123; SI-LABEL: bfe_u32_constant_fold_test_3:1124; SI: ; %bb.0:1125; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x91126; SI-NEXT: s_mov_b32 s3, 0xf0001127; SI-NEXT: s_mov_b32 s2, -11128; SI-NEXT: v_mov_b32_e32 v0, 11129; SI-NEXT: s_waitcnt lgkmcnt(0)1130; SI-NEXT: buffer_store_dword v0, off, s[0:3], 01131; SI-NEXT: s_endpgm1132;1133; VI-LABEL: bfe_u32_constant_fold_test_3:1134; VI: ; %bb.0:1135; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x241136; VI-NEXT: s_mov_b32 s3, 0xf0001137; VI-NEXT: s_mov_b32 s2, -11138; VI-NEXT: v_mov_b32_e32 v0, 11139; VI-NEXT: s_waitcnt lgkmcnt(0)1140; VI-NEXT: buffer_store_dword v0, off, s[0:3], 01141; VI-NEXT: s_endpgm1142 %bfe_u32 = call i32 @llvm.amdgcn.ubfe.i32(i32 1, i32 0, i32 1)1143 store i32 %bfe_u32, ptr addrspace(1) %out, align 41144 ret void1145}1146 1147define amdgpu_kernel void @bfe_u32_constant_fold_test_4(ptr addrspace(1) %out) #0 {1148; SI-LABEL: bfe_u32_constant_fold_test_4:1149; SI: ; %bb.0:1150; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x91151; SI-NEXT: s_mov_b32 s3, 0xf0001152; SI-NEXT: s_mov_b32 s2, -11153; SI-NEXT: v_mov_b32_e32 v0, -11154; SI-NEXT: s_waitcnt lgkmcnt(0)1155; SI-NEXT: buffer_store_dword v0, off, s[0:3], 01156; SI-NEXT: s_endpgm1157;1158; VI-LABEL: bfe_u32_constant_fold_test_4:1159; VI: ; %bb.0:1160; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x241161; VI-NEXT: s_mov_b32 s3, 0xf0001162; VI-NEXT: s_mov_b32 s2, -11163; VI-NEXT: v_mov_b32_e32 v0, -11164; VI-NEXT: s_waitcnt lgkmcnt(0)1165; VI-NEXT: buffer_store_dword v0, off, s[0:3], 01166; VI-NEXT: s_endpgm1167 %bfe_u32 = call i32 @llvm.amdgcn.ubfe.i32(i32 4294967295, i32 0, i32 1)1168 store i32 %bfe_u32, ptr addrspace(1) %out, align 41169 ret void1170}1171 1172define amdgpu_kernel void @bfe_u32_constant_fold_test_5(ptr addrspace(1) %out) #0 {1173; SI-LABEL: bfe_u32_constant_fold_test_5:1174; SI: ; %bb.0:1175; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x91176; SI-NEXT: s_mov_b32 s3, 0xf0001177; SI-NEXT: s_mov_b32 s2, -11178; SI-NEXT: v_mov_b32_e32 v0, 11179; SI-NEXT: s_waitcnt lgkmcnt(0)1180; SI-NEXT: buffer_store_dword v0, off, s[0:3], 01181; SI-NEXT: s_endpgm1182;1183; VI-LABEL: bfe_u32_constant_fold_test_5:1184; VI: ; %bb.0:1185; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x241186; VI-NEXT: s_mov_b32 s3, 0xf0001187; VI-NEXT: s_mov_b32 s2, -11188; VI-NEXT: v_mov_b32_e32 v0, 11189; VI-NEXT: s_waitcnt lgkmcnt(0)1190; VI-NEXT: buffer_store_dword v0, off, s[0:3], 01191; VI-NEXT: s_endpgm1192 %bfe_u32 = call i32 @llvm.amdgcn.ubfe.i32(i32 128, i32 7, i32 1)1193 store i32 %bfe_u32, ptr addrspace(1) %out, align 41194 ret void1195}1196 1197define amdgpu_kernel void @bfe_u32_constant_fold_test_6(ptr addrspace(1) %out) #0 {1198; SI-LABEL: bfe_u32_constant_fold_test_6:1199; SI: ; %bb.0:1200; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x91201; SI-NEXT: s_mov_b32 s3, 0xf0001202; SI-NEXT: s_mov_b32 s2, -11203; SI-NEXT: v_mov_b32_e32 v0, 0x801204; SI-NEXT: s_waitcnt lgkmcnt(0)1205; SI-NEXT: buffer_store_dword v0, off, s[0:3], 01206; SI-NEXT: s_endpgm1207;1208; VI-LABEL: bfe_u32_constant_fold_test_6:1209; VI: ; %bb.0:1210; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x241211; VI-NEXT: s_mov_b32 s3, 0xf0001212; VI-NEXT: s_mov_b32 s2, -11213; VI-NEXT: v_mov_b32_e32 v0, 0x801214; VI-NEXT: s_waitcnt lgkmcnt(0)1215; VI-NEXT: buffer_store_dword v0, off, s[0:3], 01216; VI-NEXT: s_endpgm1217 %bfe_u32 = call i32 @llvm.amdgcn.ubfe.i32(i32 128, i32 0, i32 8)1218 store i32 %bfe_u32, ptr addrspace(1) %out, align 41219 ret void1220}1221 1222define amdgpu_kernel void @bfe_u32_constant_fold_test_7(ptr addrspace(1) %out) #0 {1223; SI-LABEL: bfe_u32_constant_fold_test_7:1224; SI: ; %bb.0:1225; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x91226; SI-NEXT: s_mov_b32 s3, 0xf0001227; SI-NEXT: s_mov_b32 s2, -11228; SI-NEXT: v_mov_b32_e32 v0, 0x7f1229; SI-NEXT: s_waitcnt lgkmcnt(0)1230; SI-NEXT: buffer_store_dword v0, off, s[0:3], 01231; SI-NEXT: s_endpgm1232;1233; VI-LABEL: bfe_u32_constant_fold_test_7:1234; VI: ; %bb.0:1235; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x241236; VI-NEXT: s_mov_b32 s3, 0xf0001237; VI-NEXT: s_mov_b32 s2, -11238; VI-NEXT: v_mov_b32_e32 v0, 0x7f1239; VI-NEXT: s_waitcnt lgkmcnt(0)1240; VI-NEXT: buffer_store_dword v0, off, s[0:3], 01241; VI-NEXT: s_endpgm1242 %bfe_u32 = call i32 @llvm.amdgcn.ubfe.i32(i32 127, i32 0, i32 8)1243 store i32 %bfe_u32, ptr addrspace(1) %out, align 41244 ret void1245}1246 1247define amdgpu_kernel void @bfe_u32_constant_fold_test_8(ptr addrspace(1) %out) #0 {1248; SI-LABEL: bfe_u32_constant_fold_test_8:1249; SI: ; %bb.0:1250; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x91251; SI-NEXT: s_mov_b32 s3, 0xf0001252; SI-NEXT: s_mov_b32 s2, -11253; SI-NEXT: v_mov_b32_e32 v0, 11254; SI-NEXT: s_waitcnt lgkmcnt(0)1255; SI-NEXT: buffer_store_dword v0, off, s[0:3], 01256; SI-NEXT: s_endpgm1257;1258; VI-LABEL: bfe_u32_constant_fold_test_8:1259; VI: ; %bb.0:1260; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x241261; VI-NEXT: s_mov_b32 s3, 0xf0001262; VI-NEXT: s_mov_b32 s2, -11263; VI-NEXT: v_mov_b32_e32 v0, 11264; VI-NEXT: s_waitcnt lgkmcnt(0)1265; VI-NEXT: buffer_store_dword v0, off, s[0:3], 01266; VI-NEXT: s_endpgm1267 %bfe_u32 = call i32 @llvm.amdgcn.ubfe.i32(i32 127, i32 6, i32 8)1268 store i32 %bfe_u32, ptr addrspace(1) %out, align 41269 ret void1270}1271 1272define amdgpu_kernel void @bfe_u32_constant_fold_test_9(ptr addrspace(1) %out) #0 {1273; SI-LABEL: bfe_u32_constant_fold_test_9:1274; SI: ; %bb.0:1275; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x91276; SI-NEXT: s_mov_b32 s3, 0xf0001277; SI-NEXT: s_mov_b32 s2, -11278; SI-NEXT: v_mov_b32_e32 v0, 11279; SI-NEXT: s_waitcnt lgkmcnt(0)1280; SI-NEXT: buffer_store_dword v0, off, s[0:3], 01281; SI-NEXT: s_endpgm1282;1283; VI-LABEL: bfe_u32_constant_fold_test_9:1284; VI: ; %bb.0:1285; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x241286; VI-NEXT: s_mov_b32 s3, 0xf0001287; VI-NEXT: s_mov_b32 s2, -11288; VI-NEXT: v_mov_b32_e32 v0, 11289; VI-NEXT: s_waitcnt lgkmcnt(0)1290; VI-NEXT: buffer_store_dword v0, off, s[0:3], 01291; VI-NEXT: s_endpgm1292 %bfe_u32 = call i32 @llvm.amdgcn.ubfe.i32(i32 65536, i32 16, i32 8)1293 store i32 %bfe_u32, ptr addrspace(1) %out, align 41294 ret void1295}1296 1297define amdgpu_kernel void @bfe_u32_constant_fold_test_10(ptr addrspace(1) %out) #0 {1298; SI-LABEL: bfe_u32_constant_fold_test_10:1299; SI: ; %bb.0:1300; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x91301; SI-NEXT: s_mov_b32 s3, 0xf0001302; SI-NEXT: s_mov_b32 s2, -11303; SI-NEXT: v_mov_b32_e32 v0, 01304; SI-NEXT: s_waitcnt lgkmcnt(0)1305; SI-NEXT: buffer_store_dword v0, off, s[0:3], 01306; SI-NEXT: s_endpgm1307;1308; VI-LABEL: bfe_u32_constant_fold_test_10:1309; VI: ; %bb.0:1310; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x241311; VI-NEXT: s_mov_b32 s3, 0xf0001312; VI-NEXT: s_mov_b32 s2, -11313; VI-NEXT: v_mov_b32_e32 v0, 01314; VI-NEXT: s_waitcnt lgkmcnt(0)1315; VI-NEXT: buffer_store_dword v0, off, s[0:3], 01316; VI-NEXT: s_endpgm1317 %bfe_u32 = call i32 @llvm.amdgcn.ubfe.i32(i32 65535, i32 16, i32 16)1318 store i32 %bfe_u32, ptr addrspace(1) %out, align 41319 ret void1320}1321 1322define amdgpu_kernel void @bfe_u32_constant_fold_test_11(ptr addrspace(1) %out) #0 {1323; SI-LABEL: bfe_u32_constant_fold_test_11:1324; SI: ; %bb.0:1325; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x91326; SI-NEXT: s_mov_b32 s3, 0xf0001327; SI-NEXT: s_mov_b32 s2, -11328; SI-NEXT: v_mov_b32_e32 v0, 101329; SI-NEXT: s_waitcnt lgkmcnt(0)1330; SI-NEXT: buffer_store_dword v0, off, s[0:3], 01331; SI-NEXT: s_endpgm1332;1333; VI-LABEL: bfe_u32_constant_fold_test_11:1334; VI: ; %bb.0:1335; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x241336; VI-NEXT: s_mov_b32 s3, 0xf0001337; VI-NEXT: s_mov_b32 s2, -11338; VI-NEXT: v_mov_b32_e32 v0, 101339; VI-NEXT: s_waitcnt lgkmcnt(0)1340; VI-NEXT: buffer_store_dword v0, off, s[0:3], 01341; VI-NEXT: s_endpgm1342 %bfe_u32 = call i32 @llvm.amdgcn.ubfe.i32(i32 160, i32 4, i32 4)1343 store i32 %bfe_u32, ptr addrspace(1) %out, align 41344 ret void1345}1346 1347define amdgpu_kernel void @bfe_u32_constant_fold_test_12(ptr addrspace(1) %out) #0 {1348; SI-LABEL: bfe_u32_constant_fold_test_12:1349; SI: ; %bb.0:1350; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x91351; SI-NEXT: s_mov_b32 s3, 0xf0001352; SI-NEXT: s_mov_b32 s2, -11353; SI-NEXT: v_mov_b32_e32 v0, 01354; SI-NEXT: s_waitcnt lgkmcnt(0)1355; SI-NEXT: buffer_store_dword v0, off, s[0:3], 01356; SI-NEXT: s_endpgm1357;1358; VI-LABEL: bfe_u32_constant_fold_test_12:1359; VI: ; %bb.0:1360; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x241361; VI-NEXT: s_mov_b32 s3, 0xf0001362; VI-NEXT: s_mov_b32 s2, -11363; VI-NEXT: v_mov_b32_e32 v0, 01364; VI-NEXT: s_waitcnt lgkmcnt(0)1365; VI-NEXT: buffer_store_dword v0, off, s[0:3], 01366; VI-NEXT: s_endpgm1367 %bfe_u32 = call i32 @llvm.amdgcn.ubfe.i32(i32 160, i32 31, i32 1)1368 store i32 %bfe_u32, ptr addrspace(1) %out, align 41369 ret void1370}1371 1372define amdgpu_kernel void @bfe_u32_constant_fold_test_13(ptr addrspace(1) %out) #0 {1373; SI-LABEL: bfe_u32_constant_fold_test_13:1374; SI: ; %bb.0:1375; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x91376; SI-NEXT: s_mov_b32 s3, 0xf0001377; SI-NEXT: s_mov_b32 s2, -11378; SI-NEXT: v_mov_b32_e32 v0, 11379; SI-NEXT: s_waitcnt lgkmcnt(0)1380; SI-NEXT: buffer_store_dword v0, off, s[0:3], 01381; SI-NEXT: s_endpgm1382;1383; VI-LABEL: bfe_u32_constant_fold_test_13:1384; VI: ; %bb.0:1385; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x241386; VI-NEXT: s_mov_b32 s3, 0xf0001387; VI-NEXT: s_mov_b32 s2, -11388; VI-NEXT: v_mov_b32_e32 v0, 11389; VI-NEXT: s_waitcnt lgkmcnt(0)1390; VI-NEXT: buffer_store_dword v0, off, s[0:3], 01391; VI-NEXT: s_endpgm1392 %bfe_u32 = call i32 @llvm.amdgcn.ubfe.i32(i32 131070, i32 16, i32 16)1393 store i32 %bfe_u32, ptr addrspace(1) %out, align 41394 ret void1395}1396 1397define amdgpu_kernel void @bfe_u32_constant_fold_test_14(ptr addrspace(1) %out) #0 {1398; SI-LABEL: bfe_u32_constant_fold_test_14:1399; SI: ; %bb.0:1400; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x91401; SI-NEXT: s_mov_b32 s3, 0xf0001402; SI-NEXT: s_mov_b32 s2, -11403; SI-NEXT: v_mov_b32_e32 v0, 401404; SI-NEXT: s_waitcnt lgkmcnt(0)1405; SI-NEXT: buffer_store_dword v0, off, s[0:3], 01406; SI-NEXT: s_endpgm1407;1408; VI-LABEL: bfe_u32_constant_fold_test_14:1409; VI: ; %bb.0:1410; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x241411; VI-NEXT: s_mov_b32 s3, 0xf0001412; VI-NEXT: s_mov_b32 s2, -11413; VI-NEXT: v_mov_b32_e32 v0, 401414; VI-NEXT: s_waitcnt lgkmcnt(0)1415; VI-NEXT: buffer_store_dword v0, off, s[0:3], 01416; VI-NEXT: s_endpgm1417 %bfe_u32 = call i32 @llvm.amdgcn.ubfe.i32(i32 160, i32 2, i32 30)1418 store i32 %bfe_u32, ptr addrspace(1) %out, align 41419 ret void1420}1421 1422define amdgpu_kernel void @bfe_u32_constant_fold_test_15(ptr addrspace(1) %out) #0 {1423; SI-LABEL: bfe_u32_constant_fold_test_15:1424; SI: ; %bb.0:1425; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x91426; SI-NEXT: s_mov_b32 s3, 0xf0001427; SI-NEXT: s_mov_b32 s2, -11428; SI-NEXT: v_mov_b32_e32 v0, 101429; SI-NEXT: s_waitcnt lgkmcnt(0)1430; SI-NEXT: buffer_store_dword v0, off, s[0:3], 01431; SI-NEXT: s_endpgm1432;1433; VI-LABEL: bfe_u32_constant_fold_test_15:1434; VI: ; %bb.0:1435; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x241436; VI-NEXT: s_mov_b32 s3, 0xf0001437; VI-NEXT: s_mov_b32 s2, -11438; VI-NEXT: v_mov_b32_e32 v0, 101439; VI-NEXT: s_waitcnt lgkmcnt(0)1440; VI-NEXT: buffer_store_dword v0, off, s[0:3], 01441; VI-NEXT: s_endpgm1442 %bfe_u32 = call i32 @llvm.amdgcn.ubfe.i32(i32 160, i32 4, i32 28)1443 store i32 %bfe_u32, ptr addrspace(1) %out, align 41444 ret void1445}1446 1447define amdgpu_kernel void @bfe_u32_constant_fold_test_16(ptr addrspace(1) %out) #0 {1448; SI-LABEL: bfe_u32_constant_fold_test_16:1449; SI: ; %bb.0:1450; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x91451; SI-NEXT: s_mov_b32 s3, 0xf0001452; SI-NEXT: s_mov_b32 s2, -11453; SI-NEXT: v_mov_b32_e32 v0, 0x7f1454; SI-NEXT: s_waitcnt lgkmcnt(0)1455; SI-NEXT: buffer_store_dword v0, off, s[0:3], 01456; SI-NEXT: s_endpgm1457;1458; VI-LABEL: bfe_u32_constant_fold_test_16:1459; VI: ; %bb.0:1460; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x241461; VI-NEXT: s_mov_b32 s3, 0xf0001462; VI-NEXT: s_mov_b32 s2, -11463; VI-NEXT: v_mov_b32_e32 v0, 0x7f1464; VI-NEXT: s_waitcnt lgkmcnt(0)1465; VI-NEXT: buffer_store_dword v0, off, s[0:3], 01466; VI-NEXT: s_endpgm1467 %bfe_u32 = call i32 @llvm.amdgcn.ubfe.i32(i32 4294967295, i32 1, i32 7)1468 store i32 %bfe_u32, ptr addrspace(1) %out, align 41469 ret void1470}1471 1472define amdgpu_kernel void @bfe_u32_constant_fold_test_17(ptr addrspace(1) %out) #0 {1473; SI-LABEL: bfe_u32_constant_fold_test_17:1474; SI: ; %bb.0:1475; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x91476; SI-NEXT: s_mov_b32 s3, 0xf0001477; SI-NEXT: s_mov_b32 s2, -11478; SI-NEXT: v_mov_b32_e32 v0, 0x7f1479; SI-NEXT: s_waitcnt lgkmcnt(0)1480; SI-NEXT: buffer_store_dword v0, off, s[0:3], 01481; SI-NEXT: s_endpgm1482;1483; VI-LABEL: bfe_u32_constant_fold_test_17:1484; VI: ; %bb.0:1485; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x241486; VI-NEXT: s_mov_b32 s3, 0xf0001487; VI-NEXT: s_mov_b32 s2, -11488; VI-NEXT: v_mov_b32_e32 v0, 0x7f1489; VI-NEXT: s_waitcnt lgkmcnt(0)1490; VI-NEXT: buffer_store_dword v0, off, s[0:3], 01491; VI-NEXT: s_endpgm1492 %bfe_u32 = call i32 @llvm.amdgcn.ubfe.i32(i32 255, i32 1, i32 31)1493 store i32 %bfe_u32, ptr addrspace(1) %out, align 41494 ret void1495}1496 1497define amdgpu_kernel void @bfe_u32_constant_fold_test_18(ptr addrspace(1) %out) #0 {1498; SI-LABEL: bfe_u32_constant_fold_test_18:1499; SI: ; %bb.0:1500; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x91501; SI-NEXT: s_mov_b32 s3, 0xf0001502; SI-NEXT: s_mov_b32 s2, -11503; SI-NEXT: v_mov_b32_e32 v0, 01504; SI-NEXT: s_waitcnt lgkmcnt(0)1505; SI-NEXT: buffer_store_dword v0, off, s[0:3], 01506; SI-NEXT: s_endpgm1507;1508; VI-LABEL: bfe_u32_constant_fold_test_18:1509; VI: ; %bb.0:1510; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x241511; VI-NEXT: s_mov_b32 s3, 0xf0001512; VI-NEXT: s_mov_b32 s2, -11513; VI-NEXT: v_mov_b32_e32 v0, 01514; VI-NEXT: s_waitcnt lgkmcnt(0)1515; VI-NEXT: buffer_store_dword v0, off, s[0:3], 01516; VI-NEXT: s_endpgm1517 %bfe_u32 = call i32 @llvm.amdgcn.ubfe.i32(i32 255, i32 31, i32 1)1518 store i32 %bfe_u32, ptr addrspace(1) %out, align 41519 ret void1520}1521 1522; Make sure that SimplifyDemandedBits doesn't cause the and to be1523; reduced to the bits demanded by the bfe.1524 1525; XXX: The operand to v_bfe_u32 could also just directly be the load register.1526define amdgpu_kernel void @simplify_bfe_u32_multi_use_arg(ptr addrspace(1) %out0,1527; SI-LABEL: simplify_bfe_u32_multi_use_arg:1528; SI: ; %bb.0:1529; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0xd1530; SI-NEXT: s_mov_b32 s7, 0xf0001531; SI-NEXT: s_mov_b32 s6, -11532; SI-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x91533; SI-NEXT: s_mov_b32 s2, s61534; SI-NEXT: s_mov_b32 s3, s71535; SI-NEXT: s_waitcnt lgkmcnt(0)1536; SI-NEXT: buffer_load_dword v0, off, s[0:3], 01537; SI-NEXT: s_mov_b32 s4, s81538; SI-NEXT: s_mov_b32 s5, s91539; SI-NEXT: s_mov_b32 s0, s101540; SI-NEXT: s_mov_b32 s1, s111541; SI-NEXT: s_waitcnt vmcnt(0)1542; SI-NEXT: v_and_b32_e32 v0, 63, v01543; SI-NEXT: v_bfe_u32 v1, v0, 2, 21544; SI-NEXT: buffer_store_dword v1, off, s[4:7], 01545; SI-NEXT: buffer_store_dword v0, off, s[0:3], 01546; SI-NEXT: s_endpgm1547;1548; VI-LABEL: simplify_bfe_u32_multi_use_arg:1549; VI: ; %bb.0:1550; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x341551; VI-NEXT: s_mov_b32 s7, 0xf0001552; VI-NEXT: s_mov_b32 s6, -11553; VI-NEXT: s_mov_b32 s2, s61554; VI-NEXT: s_mov_b32 s3, s71555; VI-NEXT: s_waitcnt lgkmcnt(0)1556; VI-NEXT: buffer_load_dword v0, off, s[0:3], 01557; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241558; VI-NEXT: s_mov_b32 s10, s61559; VI-NEXT: s_mov_b32 s11, s71560; VI-NEXT: s_waitcnt lgkmcnt(0)1561; VI-NEXT: s_mov_b32 s4, s01562; VI-NEXT: s_mov_b32 s5, s11563; VI-NEXT: s_mov_b32 s8, s21564; VI-NEXT: s_mov_b32 s9, s31565; VI-NEXT: s_waitcnt vmcnt(0)1566; VI-NEXT: v_and_b32_e32 v0, 63, v01567; VI-NEXT: v_bfe_u32 v1, v0, 2, 21568; VI-NEXT: buffer_store_dword v1, off, s[4:7], 01569; VI-NEXT: buffer_store_dword v0, off, s[8:11], 01570; VI-NEXT: s_endpgm1571 ptr addrspace(1) %out1,1572 ptr addrspace(1) %in) #0 {1573 %src = load i32, ptr addrspace(1) %in, align 41574 %and = and i32 %src, 631575 %bfe_u32 = call i32 @llvm.amdgcn.ubfe.i32(i32 %and, i32 2, i32 2)1576 store i32 %bfe_u32, ptr addrspace(1) %out0, align 41577 store i32 %and, ptr addrspace(1) %out1, align 41578 ret void1579}1580 1581define amdgpu_kernel void @lshr_and(ptr addrspace(1) %out, i32 %a) #0 {1582; SI-LABEL: lshr_and:1583; SI: ; %bb.0:1584; SI-NEXT: s_load_dword s2, s[4:5], 0xb1585; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x91586; SI-NEXT: s_mov_b32 s3, 0xf0001587; SI-NEXT: s_waitcnt lgkmcnt(0)1588; SI-NEXT: s_bfe_u32 s4, s2, 0x300061589; SI-NEXT: s_mov_b32 s2, -11590; SI-NEXT: v_mov_b32_e32 v0, s41591; SI-NEXT: buffer_store_dword v0, off, s[0:3], 01592; SI-NEXT: s_endpgm1593;1594; VI-LABEL: lshr_and:1595; VI: ; %bb.0:1596; VI-NEXT: s_load_dword s6, s[4:5], 0x2c1597; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x241598; VI-NEXT: s_mov_b32 s3, 0xf0001599; VI-NEXT: s_mov_b32 s2, -11600; VI-NEXT: s_waitcnt lgkmcnt(0)1601; VI-NEXT: s_bfe_u32 s4, s6, 0x300061602; VI-NEXT: v_mov_b32_e32 v0, s41603; VI-NEXT: buffer_store_dword v0, off, s[0:3], 01604; VI-NEXT: s_endpgm1605 %b = lshr i32 %a, 61606 %c = and i32 %b, 71607 store i32 %c, ptr addrspace(1) %out, align 81608 ret void1609}1610 1611define amdgpu_kernel void @v_lshr_and(ptr addrspace(1) %out, i32 %a, i32 %b) #0 {1612; SI-LABEL: v_lshr_and:1613; SI: ; %bb.0:1614; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91615; SI-NEXT: s_waitcnt lgkmcnt(0)1616; SI-NEXT: s_mov_b64 s[4:5], s[2:3]1617; SI-NEXT: s_mov_b32 s3, 0xf0001618; SI-NEXT: s_lshr_b32 s2, s4, s51619; SI-NEXT: s_and_b32 s4, s2, 71620; SI-NEXT: s_mov_b32 s2, -11621; SI-NEXT: v_mov_b32_e32 v0, s41622; SI-NEXT: buffer_store_dword v0, off, s[0:3], 01623; SI-NEXT: s_endpgm1624;1625; VI-LABEL: v_lshr_and:1626; VI: ; %bb.0:1627; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241628; VI-NEXT: s_waitcnt lgkmcnt(0)1629; VI-NEXT: s_mov_b64 s[4:5], s[2:3]1630; VI-NEXT: s_lshr_b32 s4, s4, s51631; VI-NEXT: s_and_b32 s4, s4, 71632; VI-NEXT: s_mov_b32 s3, 0xf0001633; VI-NEXT: s_mov_b32 s2, -11634; VI-NEXT: v_mov_b32_e32 v0, s41635; VI-NEXT: buffer_store_dword v0, off, s[0:3], 01636; VI-NEXT: s_endpgm1637 %c = lshr i32 %a, %b1638 %d = and i32 %c, 71639 store i32 %d, ptr addrspace(1) %out, align 81640 ret void1641}1642 1643define amdgpu_kernel void @and_lshr(ptr addrspace(1) %out, i32 %a) #0 {1644; SI-LABEL: and_lshr:1645; SI: ; %bb.0:1646; SI-NEXT: s_load_dword s2, s[4:5], 0xb1647; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x91648; SI-NEXT: s_mov_b32 s3, 0xf0001649; SI-NEXT: s_waitcnt lgkmcnt(0)1650; SI-NEXT: s_bfe_u32 s4, s2, 0x300061651; SI-NEXT: s_mov_b32 s2, -11652; SI-NEXT: v_mov_b32_e32 v0, s41653; SI-NEXT: buffer_store_dword v0, off, s[0:3], 01654; SI-NEXT: s_endpgm1655;1656; VI-LABEL: and_lshr:1657; VI: ; %bb.0:1658; VI-NEXT: s_load_dword s6, s[4:5], 0x2c1659; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x241660; VI-NEXT: s_mov_b32 s3, 0xf0001661; VI-NEXT: s_mov_b32 s2, -11662; VI-NEXT: s_waitcnt lgkmcnt(0)1663; VI-NEXT: s_bfe_u32 s4, s6, 0x300061664; VI-NEXT: v_mov_b32_e32 v0, s41665; VI-NEXT: buffer_store_dword v0, off, s[0:3], 01666; VI-NEXT: s_endpgm1667 %b = and i32 %a, 4481668 %c = lshr i32 %b, 61669 store i32 %c, ptr addrspace(1) %out, align 81670 ret void1671}1672 1673define amdgpu_kernel void @and_lshr2(ptr addrspace(1) %out, i32 %a) #0 {1674; SI-LABEL: and_lshr2:1675; SI: ; %bb.0:1676; SI-NEXT: s_load_dword s2, s[4:5], 0xb1677; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x91678; SI-NEXT: s_mov_b32 s3, 0xf0001679; SI-NEXT: s_waitcnt lgkmcnt(0)1680; SI-NEXT: s_bfe_u32 s4, s2, 0x300061681; SI-NEXT: s_mov_b32 s2, -11682; SI-NEXT: v_mov_b32_e32 v0, s41683; SI-NEXT: buffer_store_dword v0, off, s[0:3], 01684; SI-NEXT: s_endpgm1685;1686; VI-LABEL: and_lshr2:1687; VI: ; %bb.0:1688; VI-NEXT: s_load_dword s6, s[4:5], 0x2c1689; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x241690; VI-NEXT: s_mov_b32 s3, 0xf0001691; VI-NEXT: s_mov_b32 s2, -11692; VI-NEXT: s_waitcnt lgkmcnt(0)1693; VI-NEXT: s_bfe_u32 s4, s6, 0x300061694; VI-NEXT: v_mov_b32_e32 v0, s41695; VI-NEXT: buffer_store_dword v0, off, s[0:3], 01696; VI-NEXT: s_endpgm1697 %b = and i32 %a, 5111698 %c = lshr i32 %b, 61699 store i32 %c, ptr addrspace(1) %out, align 81700 ret void1701}1702 1703define amdgpu_kernel void @shl_lshr(ptr addrspace(1) %out, i32 %a) #0 {1704; SI-LABEL: shl_lshr:1705; SI: ; %bb.0:1706; SI-NEXT: s_load_dword s2, s[4:5], 0xb1707; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x91708; SI-NEXT: s_mov_b32 s3, 0xf0001709; SI-NEXT: s_waitcnt lgkmcnt(0)1710; SI-NEXT: s_bfe_u32 s4, s2, 0x1500021711; SI-NEXT: s_mov_b32 s2, -11712; SI-NEXT: v_mov_b32_e32 v0, s41713; SI-NEXT: buffer_store_dword v0, off, s[0:3], 01714; SI-NEXT: s_endpgm1715;1716; VI-LABEL: shl_lshr:1717; VI: ; %bb.0:1718; VI-NEXT: s_load_dword s6, s[4:5], 0x2c1719; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x241720; VI-NEXT: s_mov_b32 s3, 0xf0001721; VI-NEXT: s_mov_b32 s2, -11722; VI-NEXT: s_waitcnt lgkmcnt(0)1723; VI-NEXT: s_bfe_u32 s4, s6, 0x1500021724; VI-NEXT: v_mov_b32_e32 v0, s41725; VI-NEXT: buffer_store_dword v0, off, s[0:3], 01726; VI-NEXT: s_endpgm1727 %b = shl i32 %a, 91728 %c = lshr i32 %b, 111729 store i32 %c, ptr addrspace(1) %out, align 81730 ret void1731}1732 1733declare i32 @llvm.amdgcn.ubfe.i32(i32, i32, i32) #11734 1735attributes #0 = { nounwind }1736attributes #1 = { nounwind readnone }1737