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1; RUN: llc -mtriple=amdgcn -mcpu=gfx906 < %s | FileCheck %s --check-prefixes=GCN,GFX92; RUN: llc -mtriple=amdgcn -mcpu=gfx942 < %s | FileCheck %s --check-prefixes=GCN,GFX93; RUN: llc -mtriple=amdgcn -mcpu=gfx1011 < %s | FileCheck %s --check-prefixes=GCN,GFX104; RUN: llc -mtriple=amdgcn -mcpu=gfx1012 < %s | FileCheck %s --check-prefixes=GCN,GFX105; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck %s --check-prefixes=GCN,GFX106 7declare i32 @llvm.amdgcn.udot4(i32 %a, i32 %b, i32 %c, i1 %clamp)8 9; GCN-LABEL: {{^}}test_llvm_amdgcn_udot4_clamp10; GFX9: v_dot4_u32_u8 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} clamp{{$}}11; GFX10: v_dot4_u32_u8 v{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}} clamp{{$}}12define amdgpu_kernel void @test_llvm_amdgcn_udot4_clamp(13 ptr addrspace(1) %r,14 ptr addrspace(1) %a,15 ptr addrspace(1) %b,16 ptr addrspace(1) %c) {17entry:18 %a.val = load <4 x i8>, ptr addrspace(1) %a19 %b.val = load <4 x i8>, ptr addrspace(1) %b20 %a.val.cast = bitcast <4 x i8> %a.val to i3221 %b.val.cast = bitcast <4 x i8> %b.val to i3222 %c.val = load i32, ptr addrspace(1) %c23 %r.val = call i32 @llvm.amdgcn.udot4(i32 %a.val.cast, i32 %b.val.cast, i32 %c.val, i1 1)24 store i32 %r.val, ptr addrspace(1) %r25 ret void26}27 28; GCN-LABEL: {{^}}test_llvm_amdgcn_udot4_no_clamp29; GFX9: v_dot4_u32_u8 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}{{$}}30; GFX10: v_dot4_u32_u8 v{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}{{$}}31define amdgpu_kernel void @test_llvm_amdgcn_udot4_no_clamp(32 ptr addrspace(1) %r,33 ptr addrspace(1) %a,34 ptr addrspace(1) %b,35 ptr addrspace(1) %c) {36entry:37 %a.val = load <4 x i8>, ptr addrspace(1) %a38 %b.val = load <4 x i8>, ptr addrspace(1) %b39 %a.val.cast = bitcast <4 x i8> %a.val to i3240 %b.val.cast = bitcast <4 x i8> %b.val to i3241 %c.val = load i32, ptr addrspace(1) %c42 %r.val = call i32 @llvm.amdgcn.udot4(i32 %a.val.cast, i32 %b.val.cast, i32 %c.val, i1 0)43 store i32 %r.val, ptr addrspace(1) %r44 ret void45}46