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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 22; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -global-isel=1 < %s | FileCheck -check-prefixes=GFX11 %s3; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -global-isel=0 < %s | FileCheck -check-prefixes=GFX11 %s4 5declare i32 @llvm.amdgcn.s.wqm.i32(i32)6declare i64 @llvm.amdgcn.s.wqm.i64(i64)7 8define i32 @test_s_wqm_constant_i32() {9; GFX11-LABEL: test_s_wqm_constant_i32:10; GFX11: ; %bb.0:11; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)12; GFX11-NEXT: v_mov_b32_e32 v0, 0xff00ff0f13; GFX11-NEXT: s_setpc_b64 s[30:31]14 %br = call i32 @llvm.amdgcn.s.wqm.i32(i32 u0x85003A02)15 ret i32 %br16}17 18define i32 @test_s_wqm_constant_zero_i32() {19; GFX11-LABEL: test_s_wqm_constant_zero_i32:20; GFX11: ; %bb.0:21; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)22; GFX11-NEXT: v_mov_b32_e32 v0, 023; GFX11-NEXT: s_setpc_b64 s[30:31]24 %br = call i32 @llvm.amdgcn.s.wqm.i32(i32 0)25 ret i32 %br26}27 28define i32 @test_s_wqm_constant_neg_one_i32() {29; GFX11-LABEL: test_s_wqm_constant_neg_one_i32:30; GFX11: ; %bb.0:31; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)32; GFX11-NEXT: v_mov_b32_e32 v0, -133; GFX11-NEXT: s_setpc_b64 s[30:31]34 %br = call i32 @llvm.amdgcn.s.wqm.i32(i32 -1)35 ret i32 %br36}37 38define i32 @test_s_wqm_constant_undef_i32() {39; GFX11-LABEL: test_s_wqm_constant_undef_i32:40; GFX11: ; %bb.0:41; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)42; GFX11-NEXT: s_wqm_b32 s0, s043; GFX11-NEXT: v_mov_b32_e32 v0, s044; GFX11-NEXT: s_setpc_b64 s[30:31]45 %br = call i32 @llvm.amdgcn.s.wqm.i32(i32 poison)46 ret i32 %br47}48 49define i32 @test_s_wqm_constant_poison_i32() {50; GFX11-LABEL: test_s_wqm_constant_poison_i32:51; GFX11: ; %bb.0:52; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)53; GFX11-NEXT: s_wqm_b32 s0, s054; GFX11-NEXT: v_mov_b32_e32 v0, s055; GFX11-NEXT: s_setpc_b64 s[30:31]56 %br = call i32 @llvm.amdgcn.s.wqm.i32(i32 poison)57 ret i32 %br58}59 60 61define amdgpu_cs void @test_s_wqm_sgpr_i32(i32 inreg %mask, ptr addrspace(1) %out) {62; GFX11-LABEL: test_s_wqm_sgpr_i32:63; GFX11: ; %bb.0: ; %entry64; GFX11-NEXT: s_wqm_b32 s0, s065; GFX11-NEXT: v_mov_b32_e32 v2, s066; GFX11-NEXT: global_store_b32 v[0:1], v2, off67; GFX11-NEXT: s_endpgm68entry:69 %br = call i32 @llvm.amdgcn.s.wqm.i32(i32 %mask)70 store i32 %br, ptr addrspace(1) %out71 ret void72}73 74define i32 @test_s_wqm_vgpr_i32(i32 %mask) {75; GFX11-LABEL: test_s_wqm_vgpr_i32:76; GFX11: ; %bb.0: ; %entry77; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)78; GFX11-NEXT: v_readfirstlane_b32 s0, v079; GFX11-NEXT: s_wqm_b32 s0, s080; GFX11-NEXT: v_mov_b32_e32 v0, s081; GFX11-NEXT: s_setpc_b64 s[30:31]82entry:83 %br = call i32 @llvm.amdgcn.s.wqm.i32(i32 %mask)84 ret i32 %br85}86 87define i64 @test_s_wqm_constant_i64() {88; GFX11-LABEL: test_s_wqm_constant_i64:89; GFX11: ; %bb.0:90; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)91; GFX11-NEXT: v_mov_b32_e32 v0, 0xff00ffff92; GFX11-NEXT: v_mov_b32_e32 v1, 0xffff0fff93; GFX11-NEXT: s_setpc_b64 s[30:31]94 %br = call i64 @llvm.amdgcn.s.wqm.i64(i64 u0x12480FDBAC00753E)95 ret i64 %br96}97 98define i64 @test_s_wqm_constant_zero_i64() {99; GFX11-LABEL: test_s_wqm_constant_zero_i64:100; GFX11: ; %bb.0:101; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)102; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0103; GFX11-NEXT: s_setpc_b64 s[30:31]104 %br = call i64 @llvm.amdgcn.s.wqm.i64(i64 0)105 ret i64 %br106}107 108define i64 @test_s_wqm_constant_neg_one_i64() {109; GFX11-LABEL: test_s_wqm_constant_neg_one_i64:110; GFX11: ; %bb.0:111; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)112; GFX11-NEXT: v_dual_mov_b32 v0, -1 :: v_dual_mov_b32 v1, -1113; GFX11-NEXT: s_setpc_b64 s[30:31]114 %br = call i64 @llvm.amdgcn.s.wqm.i64(i64 -1)115 ret i64 %br116}117 118define i64 @test_s_wqm_constant_undef_i64() {119; GFX11-LABEL: test_s_wqm_constant_undef_i64:120; GFX11: ; %bb.0:121; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)122; GFX11-NEXT: s_wqm_b64 s[0:1], s[0:1]123; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1124; GFX11-NEXT: s_setpc_b64 s[30:31]125 %br = call i64 @llvm.amdgcn.s.wqm.i64(i64 undef)126 ret i64 %br127}128 129define i64 @test_s_wqm_constant_poison_i64() {130; GFX11-LABEL: test_s_wqm_constant_poison_i64:131; GFX11: ; %bb.0:132; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)133; GFX11-NEXT: s_wqm_b64 s[0:1], s[0:1]134; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1135; GFX11-NEXT: s_setpc_b64 s[30:31]136 %br = call i64 @llvm.amdgcn.s.wqm.i64(i64 poison)137 ret i64 %br138}139 140define amdgpu_cs void @test_s_wqm_sgpr_i64(i64 inreg %mask, ptr addrspace(1) %out) {141; GFX11-LABEL: test_s_wqm_sgpr_i64:142; GFX11: ; %bb.0: ; %entry143; GFX11-NEXT: s_wqm_b64 s[0:1], s[0:1]144; GFX11-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0145; GFX11-NEXT: global_store_b64 v[0:1], v[2:3], off146; GFX11-NEXT: s_endpgm147entry:148 %br = call i64 @llvm.amdgcn.s.wqm.i64(i64 %mask)149 store i64 %br, ptr addrspace(1) %out150 ret void151}152 153define i64 @test_s_wqm_vgpr_i64(i64 %mask) {154; GFX11-LABEL: test_s_wqm_vgpr_i64:155; GFX11: ; %bb.0: ; %entry156; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)157; GFX11-NEXT: v_readfirstlane_b32 s0, v0158; GFX11-NEXT: v_readfirstlane_b32 s1, v1159; GFX11-NEXT: s_wqm_b64 s[0:1], s[0:1]160; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1161; GFX11-NEXT: s_setpc_b64 s[30:31]162entry:163 %br = call i64 @llvm.amdgcn.s.wqm.i64(i64 %mask)164 ret i64 %br165}166