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1; RUN: llc < %s -mtriple=amdgcn | FileCheck %s -check-prefix=SI -check-prefix=FUNC2; RUN: llc < %s -mtriple=amdgcn -mcpu=tonga | FileCheck %s -check-prefix=SI -check-prefix=FUNC3; RUN: llc < %s -mtriple=r600 -mcpu=redwood | FileCheck %s -check-prefix=EG -check-prefix=FUNC4 5;FUNC-LABEL: test6;EG: MULADD_IEEE *7;EG: FRACT *8;EG: ADD *9;EG: COS * T{{[0-9]+\.[XYZW], PV\.[XYZW]}}10;EG-NOT: COS11;SI: v_cos_f3212;SI-NOT: v_cos_f3213 14define amdgpu_kernel void @test(ptr addrspace(1) %out, float %x) #1 {15 %cos = call float @llvm.cos.f32(float %x)16 store float %cos, ptr addrspace(1) %out17 ret void18}19 20;FUNC-LABEL: testv21;EG: COS * T{{[0-9]+\.[XYZW], PV\.[XYZW]}}22;EG: COS * T{{[0-9]+\.[XYZW], PV\.[XYZW]}}23;EG: COS * T{{[0-9]+\.[XYZW], PV\.[XYZW]}}24;EG: COS * T{{[0-9]+\.[XYZW], PV\.[XYZW]}}25;EG-NOT: COS26;SI: v_cos_f3227;SI: v_cos_f3228;SI: v_cos_f3229;SI: v_cos_f3230;SI-NOT: v_cos_f3231 32define amdgpu_kernel void @testv(ptr addrspace(1) %out, <4 x float> inreg %vx) #1 {33 %cos = call <4 x float> @llvm.cos.v4f32(<4 x float> %vx)34 store <4 x float> %cos, ptr addrspace(1) %out35 ret void36}37 38declare float @llvm.cos.f32(float) readnone39declare <4 x float> @llvm.cos.v4f32(<4 x float>) readnone40