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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 22; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=GCN,GCN-SDAG,VI,VI-SDAG %s3; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=GCN,GCN-GISEL,VI,VI-GISEL %s4; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GCN-SDAG,GFX900,GFX900-SDAG %s5; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GCN-GISEL,GFX900,GFX900-GISEL %s6; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefixes=SI,SI-SDAG %s7; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefixes=SI,SI-GISEL %s8 9; RUN: llc -mtriple=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 %s10; RUN: llc -mtriple=r600 -mcpu=cayman < %s | FileCheck -check-prefix=CM %s11 12define amdgpu_kernel void @s_exp_f32(ptr addrspace(1) %out, float %in) {13; VI-SDAG-LABEL: s_exp_f32:14; VI-SDAG: ; %bb.0:15; VI-SDAG-NEXT: s_load_dword s2, s[4:5], 0x2c16; VI-SDAG-NEXT: v_mov_b32_e32 v0, 0x3fb8a00017; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)18; VI-SDAG-NEXT: s_and_b32 s0, s2, 0xfffff00019; VI-SDAG-NEXT: v_mov_b32_e32 v1, s020; VI-SDAG-NEXT: v_sub_f32_e32 v1, s2, v121; VI-SDAG-NEXT: v_mul_f32_e32 v3, 0x39a3b295, v122; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8a000, v123; VI-SDAG-NEXT: v_mul_f32_e32 v0, s0, v024; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v325; VI-SDAG-NEXT: v_mov_b32_e32 v3, 0x39a3b29526; VI-SDAG-NEXT: v_rndne_f32_e32 v2, v027; VI-SDAG-NEXT: v_mul_f32_e32 v3, s0, v328; VI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v229; VI-SDAG-NEXT: v_add_f32_e32 v1, v3, v130; VI-SDAG-NEXT: v_add_f32_e32 v0, v0, v131; VI-SDAG-NEXT: v_exp_f32_e32 v0, v032; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v1, v233; VI-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2434; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f80000035; VI-SDAG-NEXT: v_ldexp_f32 v0, v0, v136; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0xc2ce8ed037; VI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s2, v138; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x42b1721839; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc40; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s2, v141; VI-SDAG-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc42; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)43; VI-SDAG-NEXT: v_mov_b32_e32 v0, s044; VI-SDAG-NEXT: v_mov_b32_e32 v1, s145; VI-SDAG-NEXT: flat_store_dword v[0:1], v246; VI-SDAG-NEXT: s_endpgm47;48; VI-GISEL-LABEL: s_exp_f32:49; VI-GISEL: ; %bb.0:50; VI-GISEL-NEXT: s_load_dword s2, s[4:5], 0x2c51; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x3fb8a00052; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x39a3b29553; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)54; VI-GISEL-NEXT: s_and_b32 s0, s2, 0xfffff00055; VI-GISEL-NEXT: v_mov_b32_e32 v2, s056; VI-GISEL-NEXT: v_sub_f32_e32 v2, s2, v257; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x39a3b295, v258; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v259; VI-GISEL-NEXT: v_mul_f32_e32 v0, s0, v060; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v361; VI-GISEL-NEXT: v_mul_f32_e32 v1, s0, v162; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v263; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v064; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v265; VI-GISEL-NEXT: v_add_f32_e32 v0, v0, v166; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v1, v267; VI-GISEL-NEXT: v_exp_f32_e32 v0, v068; VI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2469; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f80000070; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v171; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2ce8ed072; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v173; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42b1721874; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc75; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s2, v176; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc77; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)78; VI-GISEL-NEXT: v_mov_b32_e32 v0, s079; VI-GISEL-NEXT: v_mov_b32_e32 v1, s180; VI-GISEL-NEXT: flat_store_dword v[0:1], v281; VI-GISEL-NEXT: s_endpgm82;83; GFX900-SDAG-LABEL: s_exp_f32:84; GFX900-SDAG: ; %bb.0:85; GFX900-SDAG-NEXT: s_load_dword s2, s[4:5], 0x2c86; GFX900-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2487; GFX900-SDAG-NEXT: v_mov_b32_e32 v0, 0x3fb8aa3b88; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x32a5705f89; GFX900-SDAG-NEXT: s_waitcnt lgkmcnt(0)90; GFX900-SDAG-NEXT: v_mul_f32_e32 v2, s2, v091; GFX900-SDAG-NEXT: v_rndne_f32_e32 v3, v292; GFX900-SDAG-NEXT: v_fma_f32 v0, s2, v0, -v293; GFX900-SDAG-NEXT: v_sub_f32_e32 v2, v2, v394; GFX900-SDAG-NEXT: v_fma_f32 v0, s2, v1, v095; GFX900-SDAG-NEXT: v_add_f32_e32 v0, v2, v096; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v1, v397; GFX900-SDAG-NEXT: v_exp_f32_e32 v0, v098; GFX900-SDAG-NEXT: v_mov_b32_e32 v3, 0x7f80000099; GFX900-SDAG-NEXT: v_mov_b32_e32 v2, 0100; GFX900-SDAG-NEXT: v_ldexp_f32 v0, v0, v1101; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0xc2ce8ed0102; GFX900-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s2, v1103; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x42b17218104; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc105; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s2, v1106; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc107; GFX900-SDAG-NEXT: global_store_dword v2, v0, s[0:1]108; GFX900-SDAG-NEXT: s_endpgm109;110; GFX900-GISEL-LABEL: s_exp_f32:111; GFX900-GISEL: ; %bb.0:112; GFX900-GISEL-NEXT: s_load_dword s2, s[4:5], 0x2c113; GFX900-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24114; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, 0x3fb8aa3b115; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x32a5705f116; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0)117; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, s2, v0118; GFX900-GISEL-NEXT: v_fma_f32 v0, s2, v0, -v2119; GFX900-GISEL-NEXT: v_rndne_f32_e32 v3, v2120; GFX900-GISEL-NEXT: v_fma_f32 v0, s2, v1, v0121; GFX900-GISEL-NEXT: v_sub_f32_e32 v1, v2, v3122; GFX900-GISEL-NEXT: v_add_f32_e32 v0, v1, v0123; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v1, v3124; GFX900-GISEL-NEXT: v_exp_f32_e32 v0, v0125; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed0126; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v2127; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000128; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1129; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x42b17218130; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc131; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s2, v1132; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc133; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0134; GFX900-GISEL-NEXT: global_store_dword v1, v0, s[0:1]135; GFX900-GISEL-NEXT: s_endpgm136;137; SI-SDAG-LABEL: s_exp_f32:138; SI-SDAG: ; %bb.0:139; SI-SDAG-NEXT: s_load_dword s6, s[4:5], 0xb140; SI-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9141; SI-SDAG-NEXT: v_mov_b32_e32 v0, 0x3fb8aa3b142; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x32a5705f143; SI-SDAG-NEXT: s_mov_b32 s3, 0xf000144; SI-SDAG-NEXT: s_waitcnt lgkmcnt(0)145; SI-SDAG-NEXT: v_mul_f32_e32 v2, s6, v0146; SI-SDAG-NEXT: v_rndne_f32_e32 v3, v2147; SI-SDAG-NEXT: v_fma_f32 v0, s6, v0, -v2148; SI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v3149; SI-SDAG-NEXT: v_fma_f32 v0, s6, v1, v0150; SI-SDAG-NEXT: v_add_f32_e32 v0, v2, v0151; SI-SDAG-NEXT: v_exp_f32_e32 v0, v0152; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v1, v3153; SI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000154; SI-SDAG-NEXT: s_mov_b32 s2, -1155; SI-SDAG-NEXT: v_ldexp_f32_e32 v0, v0, v1156; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0xc2ce8ed0157; SI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s6, v1158; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x42b17218159; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc160; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s6, v1161; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc162; SI-SDAG-NEXT: buffer_store_dword v0, off, s[0:3], 0163; SI-SDAG-NEXT: s_endpgm164;165; SI-GISEL-LABEL: s_exp_f32:166; SI-GISEL: ; %bb.0:167; SI-GISEL-NEXT: s_load_dword s2, s[4:5], 0xb168; SI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9169; SI-GISEL-NEXT: v_mov_b32_e32 v0, 0x3fb8aa3b170; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x32a5705f171; SI-GISEL-NEXT: s_mov_b32 s3, 0xf000172; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)173; SI-GISEL-NEXT: v_mul_f32_e32 v2, s2, v0174; SI-GISEL-NEXT: v_fma_f32 v0, s2, v0, -v2175; SI-GISEL-NEXT: v_rndne_f32_e32 v3, v2176; SI-GISEL-NEXT: v_fma_f32 v0, s2, v1, v0177; SI-GISEL-NEXT: v_sub_f32_e32 v1, v2, v3178; SI-GISEL-NEXT: v_add_f32_e32 v0, v1, v0179; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v1, v3180; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0181; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed0182; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v2183; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000184; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1185; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42b17218186; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc187; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s2, v1188; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc189; SI-GISEL-NEXT: s_mov_b32 s2, -1190; SI-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0191; SI-GISEL-NEXT: s_endpgm192;193; R600-LABEL: s_exp_f32:194; R600: ; %bb.0:195; R600-NEXT: ALU 59, @4, KC0[CB0:0-32], KC1[]196; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1197; R600-NEXT: CF_END198; R600-NEXT: PAD199; R600-NEXT: ALU clause starting at 4:200; R600-NEXT: AND_INT * T0.W, KC0[2].Z, literal.x,201; R600-NEXT: -4096(nan), 0(0.000000e+00)202; R600-NEXT: ADD T1.W, KC0[2].Z, -PV.W,203; R600-NEXT: MUL_IEEE * T2.W, PV.W, literal.x,204; R600-NEXT: 1069064192(1.442383e+00), 0(0.000000e+00)205; R600-NEXT: RNDNE T3.W, PS,206; R600-NEXT: MUL_IEEE * T4.W, PV.W, literal.x,207; R600-NEXT: 967029397(3.122284e-04), 0(0.000000e+00)208; R600-NEXT: MULADD_IEEE T1.W, T1.W, literal.x, PS,209; R600-NEXT: TRUNC * T4.W, PV.W,210; R600-NEXT: 1069064192(1.442383e+00), 0(0.000000e+00)211; R600-NEXT: FLT_TO_INT T0.Z, PS,212; R600-NEXT: MULADD_IEEE T0.W, T0.W, literal.x, PV.W,213; R600-NEXT: ADD * T1.W, T2.W, -T3.W,214; R600-NEXT: 967029397(3.122284e-04), 0(0.000000e+00)215; R600-NEXT: ADD T1.Z, PS, PV.W,216; R600-NEXT: MAX_INT T0.W, PV.Z, literal.x,217; R600-NEXT: MIN_INT * T1.W, PV.Z, literal.y,218; R600-NEXT: -330(nan), 381(5.338947e-43)219; R600-NEXT: ADD_INT T0.X, PS, literal.x,220; R600-NEXT: ADD_INT T0.Y, PV.W, literal.y,221; R600-NEXT: ADD_INT T2.Z, T0.Z, literal.z,222; R600-NEXT: SETGT_UINT T0.W, T0.Z, literal.w,223; R600-NEXT: EXP_IEEE * T1.X, PV.Z,224; R600-NEXT: -254(nan), 204(2.858649e-43)225; R600-NEXT: 102(1.429324e-43), -229(nan)226; R600-NEXT: ADD_INT T2.X, T0.Z, literal.x,227; R600-NEXT: SETGT_UINT T1.Y, T0.Z, literal.y,228; R600-NEXT: CNDE_INT T1.Z, PV.W, PV.Y, PV.Z,229; R600-NEXT: SETGT_INT T1.W, T0.Z, literal.x,230; R600-NEXT: MUL_IEEE * T2.W, PS, literal.z,231; R600-NEXT: -127(nan), 254(3.559298e-43)232; R600-NEXT: 209715200(1.972152e-31), 0(0.000000e+00)233; R600-NEXT: MUL_IEEE T3.X, PS, literal.x,234; R600-NEXT: MUL_IEEE T0.Y, T1.X, literal.y,235; R600-NEXT: CNDE_INT T1.Z, PV.W, PV.Z, T0.Z,236; R600-NEXT: CNDE_INT T3.W, PV.Y, PV.X, T0.X,237; R600-NEXT: SETGT_INT * T4.W, T0.Z, literal.z,238; R600-NEXT: 209715200(1.972152e-31), 2130706432(1.701412e+38)239; R600-NEXT: 127(1.779649e-43), 0(0.000000e+00)240; R600-NEXT: CNDE_INT T0.Z, PS, PV.Z, PV.W,241; R600-NEXT: MUL_IEEE T3.W, PV.Y, literal.x,242; R600-NEXT: CNDE_INT * T0.W, T0.W, PV.X, T2.W,243; R600-NEXT: 2130706432(1.701412e+38), 0(0.000000e+00)244; R600-NEXT: CNDE_INT T1.Z, T1.W, PS, T1.X,245; R600-NEXT: CNDE_INT T0.W, T1.Y, T0.Y, PV.W,246; R600-NEXT: LSHL * T1.W, PV.Z, literal.x,247; R600-NEXT: 23(3.222986e-44), 0(0.000000e+00)248; R600-NEXT: ADD_INT T1.W, PS, literal.x,249; R600-NEXT: CNDE_INT * T0.W, T4.W, PV.Z, PV.W,250; R600-NEXT: 1065353216(1.000000e+00), 0(0.000000e+00)251; R600-NEXT: MUL_IEEE T0.W, PS, PV.W,252; R600-NEXT: SETGT * T1.W, literal.x, KC0[2].Z,253; R600-NEXT: -1026650416(-1.032789e+02), 0(0.000000e+00)254; R600-NEXT: CNDE T0.W, PS, PV.W, 0.0,255; R600-NEXT: SETGT * T1.W, KC0[2].Z, literal.x,256; R600-NEXT: 1118925336(8.872284e+01), 0(0.000000e+00)257; R600-NEXT: CNDE T0.X, PS, PV.W, literal.x,258; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,259; R600-NEXT: 2139095040(INF), 2(2.802597e-45)260;261; CM-LABEL: s_exp_f32:262; CM: ; %bb.0:263; CM-NEXT: ALU 62, @4, KC0[CB0:0-32], KC1[]264; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0.X, T1.X265; CM-NEXT: CF_END266; CM-NEXT: PAD267; CM-NEXT: ALU clause starting at 4:268; CM-NEXT: AND_INT * T0.W, KC0[2].Z, literal.x,269; CM-NEXT: -4096(nan), 0(0.000000e+00)270; CM-NEXT: ADD * T1.W, KC0[2].Z, -PV.W,271; CM-NEXT: MUL_IEEE T0.Z, PV.W, literal.x,272; CM-NEXT: MUL_IEEE * T2.W, T0.W, literal.y,273; CM-NEXT: 967029397(3.122284e-04), 1069064192(1.442383e+00)274; CM-NEXT: RNDNE T1.Z, PV.W,275; CM-NEXT: MULADD_IEEE * T1.W, T1.W, literal.x, PV.Z,276; CM-NEXT: 1069064192(1.442383e+00), 0(0.000000e+00)277; CM-NEXT: MULADD_IEEE T0.Z, T0.W, literal.x, PV.W,278; CM-NEXT: ADD * T0.W, T2.W, -PV.Z, BS:VEC_120/SCL_212279; CM-NEXT: 967029397(3.122284e-04), 0(0.000000e+00)280; CM-NEXT: TRUNC T1.Z, T1.Z,281; CM-NEXT: ADD * T0.W, PV.W, PV.Z,282; CM-NEXT: EXP_IEEE T0.X, T0.W,283; CM-NEXT: EXP_IEEE T0.Y (MASKED), T0.W,284; CM-NEXT: EXP_IEEE T0.Z (MASKED), T0.W,285; CM-NEXT: EXP_IEEE * T0.W (MASKED), T0.W,286; CM-NEXT: FLT_TO_INT T0.Z, T1.Z,287; CM-NEXT: MUL_IEEE * T0.W, PV.X, literal.x,288; CM-NEXT: 209715200(1.972152e-31), 0(0.000000e+00)289; CM-NEXT: MUL_IEEE T0.Y, PV.W, literal.x,290; CM-NEXT: MAX_INT T1.Z, PV.Z, literal.y,291; CM-NEXT: MIN_INT * T1.W, PV.Z, literal.z,292; CM-NEXT: 209715200(1.972152e-31), -330(nan)293; CM-NEXT: 381(5.338947e-43), 0(0.000000e+00)294; CM-NEXT: ADD_INT T1.X, PV.W, literal.x,295; CM-NEXT: ADD_INT T1.Y, PV.Z, literal.y,296; CM-NEXT: ADD_INT T1.Z, T0.Z, literal.z,297; CM-NEXT: SETGT_UINT * T1.W, T0.Z, literal.w,298; CM-NEXT: -254(nan), 204(2.858649e-43)299; CM-NEXT: 102(1.429324e-43), -229(nan)300; CM-NEXT: ADD_INT T2.X, T0.Z, literal.x,301; CM-NEXT: SETGT_UINT T2.Y, T0.Z, literal.y,302; CM-NEXT: CNDE_INT T1.Z, PV.W, PV.Y, PV.Z,303; CM-NEXT: SETGT_INT * T2.W, T0.Z, literal.x,304; CM-NEXT: -127(nan), 254(3.559298e-43)305; CM-NEXT: MUL_IEEE T3.X, T0.X, literal.x,306; CM-NEXT: CNDE_INT T1.Y, PV.W, PV.Z, T0.Z,307; CM-NEXT: CNDE_INT T1.Z, PV.Y, PV.X, T1.X,308; CM-NEXT: SETGT_INT * T3.W, T0.Z, literal.y,309; CM-NEXT: 2130706432(1.701412e+38), 127(1.779649e-43)310; CM-NEXT: CNDE_INT T1.Y, PV.W, PV.Y, PV.Z,311; CM-NEXT: MUL_IEEE T0.Z, PV.X, literal.x,312; CM-NEXT: CNDE_INT * T0.W, T1.W, T0.Y, T0.W,313; CM-NEXT: 2130706432(1.701412e+38), 0(0.000000e+00)314; CM-NEXT: CNDE_INT T0.Y, T2.W, PV.W, T0.X,315; CM-NEXT: CNDE_INT T0.Z, T2.Y, T3.X, PV.Z,316; CM-NEXT: LSHL * T0.W, PV.Y, literal.x,317; CM-NEXT: 23(3.222986e-44), 0(0.000000e+00)318; CM-NEXT: ADD_INT T1.Z, PV.W, literal.x,319; CM-NEXT: CNDE_INT * T0.W, T3.W, PV.Y, PV.Z,320; CM-NEXT: 1065353216(1.000000e+00), 0(0.000000e+00)321; CM-NEXT: MUL_IEEE T0.Z, PV.W, PV.Z,322; CM-NEXT: SETGT * T0.W, literal.x, KC0[2].Z,323; CM-NEXT: -1026650416(-1.032789e+02), 0(0.000000e+00)324; CM-NEXT: CNDE T0.Z, PV.W, PV.Z, 0.0,325; CM-NEXT: SETGT * T0.W, KC0[2].Z, literal.x,326; CM-NEXT: 1118925336(8.872284e+01), 0(0.000000e+00)327; CM-NEXT: CNDE * T0.X, PV.W, PV.Z, literal.x,328; CM-NEXT: 2139095040(INF), 0(0.000000e+00)329; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,330; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)331 %result = call float @llvm.exp.f32(float %in)332 store float %result, ptr addrspace(1) %out333 ret void334}335 336; FIXME: We should be able to merge these packets together on Cayman so we337; have a maximum of 4 instructions.338define amdgpu_kernel void @s_exp_v2f32(ptr addrspace(1) %out, <2 x float> %in) {339; VI-SDAG-LABEL: s_exp_v2f32:340; VI-SDAG: ; %bb.0:341; VI-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24342; VI-SDAG-NEXT: v_mov_b32_e32 v0, 0x3fb8a000343; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)344; VI-SDAG-NEXT: s_and_b32 s4, s3, 0xfffff000345; VI-SDAG-NEXT: v_mov_b32_e32 v2, s4346; VI-SDAG-NEXT: v_sub_f32_e32 v2, s3, v2347; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x39a3b295, v2348; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v2349; VI-SDAG-NEXT: v_add_f32_e32 v2, v2, v4350; VI-SDAG-NEXT: v_mov_b32_e32 v4, 0x39a3b295351; VI-SDAG-NEXT: v_mul_f32_e32 v1, s4, v0352; VI-SDAG-NEXT: v_mul_f32_e32 v5, s4, v4353; VI-SDAG-NEXT: s_and_b32 s4, s2, 0xfffff000354; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v1355; VI-SDAG-NEXT: v_mov_b32_e32 v6, s4356; VI-SDAG-NEXT: v_sub_f32_e32 v1, v1, v3357; VI-SDAG-NEXT: v_add_f32_e32 v2, v5, v2358; VI-SDAG-NEXT: v_sub_f32_e32 v6, s2, v6359; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v2360; VI-SDAG-NEXT: v_mul_f32_e32 v0, s4, v0361; VI-SDAG-NEXT: v_mul_f32_e32 v7, 0x39a3b295, v6362; VI-SDAG-NEXT: v_mul_f32_e32 v6, 0x3fb8a000, v6363; VI-SDAG-NEXT: v_exp_f32_e32 v1, v1364; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v3365; VI-SDAG-NEXT: v_rndne_f32_e32 v5, v0366; VI-SDAG-NEXT: v_add_f32_e32 v6, v6, v7367; VI-SDAG-NEXT: v_mul_f32_e32 v4, s4, v4368; VI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v5369; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v6370; VI-SDAG-NEXT: v_add_f32_e32 v0, v0, v4371; VI-SDAG-NEXT: v_exp_f32_e32 v0, v0372; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v4, v5373; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v2374; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed0375; VI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s3, v2376; VI-SDAG-NEXT: v_mov_b32_e32 v3, 0x42b17218377; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc378; VI-SDAG-NEXT: v_mov_b32_e32 v5, 0x7f800000379; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s3, v3380; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc381; VI-SDAG-NEXT: v_ldexp_f32 v0, v0, v4382; VI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s2, v2383; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc384; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s2, v3385; VI-SDAG-NEXT: v_mov_b32_e32 v3, s1386; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc387; VI-SDAG-NEXT: v_mov_b32_e32 v2, s0388; VI-SDAG-NEXT: flat_store_dwordx2 v[2:3], v[0:1]389; VI-SDAG-NEXT: s_endpgm390;391; VI-GISEL-LABEL: s_exp_v2f32:392; VI-GISEL: ; %bb.0:393; VI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24394; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x3fb8a000395; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x39a3b295396; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)397; VI-GISEL-NEXT: s_and_b32 s4, s2, 0xfffff000398; VI-GISEL-NEXT: v_mov_b32_e32 v2, s4399; VI-GISEL-NEXT: v_sub_f32_e32 v2, s2, v2400; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x39a3b295, v2401; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v2402; VI-GISEL-NEXT: v_mul_f32_e32 v3, s4, v0403; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v4404; VI-GISEL-NEXT: v_mul_f32_e32 v4, s4, v1405; VI-GISEL-NEXT: s_and_b32 s4, s3, 0xfffff000406; VI-GISEL-NEXT: v_mov_b32_e32 v5, s4407; VI-GISEL-NEXT: v_add_f32_e32 v2, v4, v2408; VI-GISEL-NEXT: v_rndne_f32_e32 v4, v3409; VI-GISEL-NEXT: v_sub_f32_e32 v5, s3, v5410; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v4411; VI-GISEL-NEXT: v_mul_f32_e32 v6, 0x39a3b295, v5412; VI-GISEL-NEXT: v_mul_f32_e32 v5, 0x3fb8a000, v5413; VI-GISEL-NEXT: v_add_f32_e32 v2, v3, v2414; VI-GISEL-NEXT: v_mul_f32_e32 v0, s4, v0415; VI-GISEL-NEXT: v_add_f32_e32 v5, v5, v6416; VI-GISEL-NEXT: v_mul_f32_e32 v1, s4, v1417; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v3, v4418; VI-GISEL-NEXT: v_exp_f32_e32 v2, v2419; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v5420; VI-GISEL-NEXT: v_rndne_f32_e32 v5, v0421; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v5422; VI-GISEL-NEXT: v_add_f32_e32 v0, v0, v1423; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v1, v5424; VI-GISEL-NEXT: v_exp_f32_e32 v5, v0425; VI-GISEL-NEXT: v_ldexp_f32 v2, v2, v3426; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0xc2ce8ed0427; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v3428; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0x42b17218429; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc430; VI-GISEL-NEXT: v_mov_b32_e32 v6, 0x7f800000431; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s2, v4432; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v2, v6, vcc433; VI-GISEL-NEXT: v_ldexp_f32 v1, v5, v1434; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s3, v3435; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc436; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s3, v4437; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1438; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc439; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0440; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]441; VI-GISEL-NEXT: s_endpgm442;443; GFX900-SDAG-LABEL: s_exp_v2f32:444; GFX900-SDAG: ; %bb.0:445; GFX900-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24446; GFX900-SDAG-NEXT: v_mov_b32_e32 v0, 0x3fb8aa3b447; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x32a5705f448; GFX900-SDAG-NEXT: v_mov_b32_e32 v5, 0xc2ce8ed0449; GFX900-SDAG-NEXT: s_waitcnt lgkmcnt(0)450; GFX900-SDAG-NEXT: v_mul_f32_e32 v2, s3, v0451; GFX900-SDAG-NEXT: v_rndne_f32_e32 v3, v2452; GFX900-SDAG-NEXT: v_fma_f32 v4, s3, v0, -v2453; GFX900-SDAG-NEXT: v_sub_f32_e32 v2, v2, v3454; GFX900-SDAG-NEXT: v_fma_f32 v4, s3, v1, v4455; GFX900-SDAG-NEXT: v_mul_f32_e32 v6, s2, v0456; GFX900-SDAG-NEXT: v_add_f32_e32 v2, v2, v4457; GFX900-SDAG-NEXT: v_rndne_f32_e32 v7, v6458; GFX900-SDAG-NEXT: v_fma_f32 v0, s2, v0, -v6459; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v3, v3460; GFX900-SDAG-NEXT: v_exp_f32_e32 v2, v2461; GFX900-SDAG-NEXT: v_sub_f32_e32 v8, v6, v7462; GFX900-SDAG-NEXT: v_fma_f32 v0, s2, v1, v0463; GFX900-SDAG-NEXT: v_add_f32_e32 v0, v8, v0464; GFX900-SDAG-NEXT: v_exp_f32_e32 v0, v0465; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v6, v7466; GFX900-SDAG-NEXT: v_ldexp_f32 v2, v2, v3467; GFX900-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s3, v5468; GFX900-SDAG-NEXT: v_mov_b32_e32 v3, 0x42b17218469; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc470; GFX900-SDAG-NEXT: v_mov_b32_e32 v7, 0x7f800000471; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s3, v3472; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, v7, v2, vcc473; GFX900-SDAG-NEXT: v_ldexp_f32 v0, v0, v6474; GFX900-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s2, v5475; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc476; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s2, v3477; GFX900-SDAG-NEXT: v_mov_b32_e32 v4, 0478; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc479; GFX900-SDAG-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1]480; GFX900-SDAG-NEXT: s_endpgm481;482; GFX900-GISEL-LABEL: s_exp_v2f32:483; GFX900-GISEL: ; %bb.0:484; GFX900-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24485; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, 0x3fb8aa3b486; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x32a5705f487; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, 0x7f800000488; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0)489; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, s2, v0490; GFX900-GISEL-NEXT: v_fma_f32 v3, s2, v0, -v2491; GFX900-GISEL-NEXT: v_rndne_f32_e32 v4, v2492; GFX900-GISEL-NEXT: v_mul_f32_e32 v5, s3, v0493; GFX900-GISEL-NEXT: v_fma_f32 v3, s2, v1, v3494; GFX900-GISEL-NEXT: v_sub_f32_e32 v2, v2, v4495; GFX900-GISEL-NEXT: v_fma_f32 v0, s3, v0, -v5496; GFX900-GISEL-NEXT: v_add_f32_e32 v2, v2, v3497; GFX900-GISEL-NEXT: v_fma_f32 v0, s3, v1, v0498; GFX900-GISEL-NEXT: v_rndne_f32_e32 v1, v5499; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v3, v4500; GFX900-GISEL-NEXT: v_exp_f32_e32 v2, v2501; GFX900-GISEL-NEXT: v_sub_f32_e32 v5, v5, v1502; GFX900-GISEL-NEXT: v_add_f32_e32 v0, v5, v0503; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v1, v1504; GFX900-GISEL-NEXT: v_exp_f32_e32 v5, v0505; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0xc2ce8ed0506; GFX900-GISEL-NEXT: v_ldexp_f32 v2, v2, v3507; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v4508; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x42b17218509; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc510; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s2, v3511; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, v2, v6, vcc512; GFX900-GISEL-NEXT: v_ldexp_f32 v1, v5, v1513; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s3, v4514; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc515; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s3, v3516; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc517; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0518; GFX900-GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]519; GFX900-GISEL-NEXT: s_endpgm520;521; SI-SDAG-LABEL: s_exp_v2f32:522; SI-SDAG: ; %bb.0:523; SI-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9524; SI-SDAG-NEXT: v_mov_b32_e32 v0, 0x3fb8aa3b525; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x32a5705f526; SI-SDAG-NEXT: s_waitcnt lgkmcnt(0)527; SI-SDAG-NEXT: s_mov_b64 s[4:5], s[2:3]528; SI-SDAG-NEXT: v_mul_f32_e32 v2, s5, v0529; SI-SDAG-NEXT: v_rndne_f32_e32 v3, v2530; SI-SDAG-NEXT: v_fma_f32 v4, s5, v0, -v2531; SI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v3532; SI-SDAG-NEXT: v_fma_f32 v4, s5, v1, v4533; SI-SDAG-NEXT: v_add_f32_e32 v2, v2, v4534; SI-SDAG-NEXT: v_mul_f32_e32 v5, s4, v0535; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v3, v3536; SI-SDAG-NEXT: v_exp_f32_e32 v2, v2537; SI-SDAG-NEXT: v_rndne_f32_e32 v6, v5538; SI-SDAG-NEXT: v_fma_f32 v0, s4, v0, -v5539; SI-SDAG-NEXT: v_sub_f32_e32 v7, v5, v6540; SI-SDAG-NEXT: v_fma_f32 v0, s4, v1, v0541; SI-SDAG-NEXT: v_add_f32_e32 v0, v7, v0542; SI-SDAG-NEXT: v_exp_f32_e32 v0, v0543; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v5, v6544; SI-SDAG-NEXT: v_ldexp_f32_e32 v2, v2, v3545; SI-SDAG-NEXT: v_mov_b32_e32 v3, 0xc2ce8ed0546; SI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s5, v3547; SI-SDAG-NEXT: v_mov_b32_e32 v4, 0x42b17218548; SI-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc549; SI-SDAG-NEXT: v_mov_b32_e32 v6, 0x7f800000550; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s5, v4551; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, v6, v2, vcc552; SI-SDAG-NEXT: v_ldexp_f32_e32 v0, v0, v5553; SI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v3554; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc555; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v4556; SI-SDAG-NEXT: s_mov_b32 s3, 0xf000557; SI-SDAG-NEXT: s_mov_b32 s2, -1558; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc559; SI-SDAG-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0560; SI-SDAG-NEXT: s_endpgm561;562; SI-GISEL-LABEL: s_exp_v2f32:563; SI-GISEL: ; %bb.0:564; SI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9565; SI-GISEL-NEXT: v_mov_b32_e32 v0, 0x3fb8aa3b566; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x32a5705f567; SI-GISEL-NEXT: v_mov_b32_e32 v6, 0x7f800000568; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)569; SI-GISEL-NEXT: v_mul_f32_e32 v2, s2, v0570; SI-GISEL-NEXT: v_fma_f32 v3, s2, v0, -v2571; SI-GISEL-NEXT: v_rndne_f32_e32 v4, v2572; SI-GISEL-NEXT: v_mul_f32_e32 v5, s3, v0573; SI-GISEL-NEXT: v_fma_f32 v3, s2, v1, v3574; SI-GISEL-NEXT: v_sub_f32_e32 v2, v2, v4575; SI-GISEL-NEXT: v_fma_f32 v0, s3, v0, -v5576; SI-GISEL-NEXT: v_add_f32_e32 v2, v2, v3577; SI-GISEL-NEXT: v_fma_f32 v0, s3, v1, v0578; SI-GISEL-NEXT: v_rndne_f32_e32 v1, v5579; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v3, v4580; SI-GISEL-NEXT: v_exp_f32_e32 v2, v2581; SI-GISEL-NEXT: v_sub_f32_e32 v5, v5, v1582; SI-GISEL-NEXT: v_add_f32_e32 v0, v5, v0583; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v1, v1584; SI-GISEL-NEXT: v_exp_f32_e32 v5, v0585; SI-GISEL-NEXT: v_mov_b32_e32 v4, 0xc2ce8ed0586; SI-GISEL-NEXT: v_ldexp_f32_e32 v2, v2, v3587; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v4588; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x42b17218589; SI-GISEL-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc590; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s2, v3591; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v2, v6, vcc592; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, v5, v1593; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s3, v4594; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc595; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s3, v3596; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc597; SI-GISEL-NEXT: s_mov_b32 s2, -1598; SI-GISEL-NEXT: s_mov_b32 s3, 0xf000599; SI-GISEL-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0600; SI-GISEL-NEXT: s_endpgm601;602; R600-LABEL: s_exp_v2f32:603; R600: ; %bb.0:604; R600-NEXT: ALU 96, @4, KC0[CB0:0-32], KC1[]605; R600-NEXT: ALU 12, @101, KC0[CB0:0-32], KC1[]606; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.XY, T0.X, 1607; R600-NEXT: CF_END608; R600-NEXT: ALU clause starting at 4:609; R600-NEXT: AND_INT * T0.W, KC0[3].X, literal.x,610; R600-NEXT: -4096(nan), 0(0.000000e+00)611; R600-NEXT: ADD * T1.W, KC0[3].X, -PV.W,612; R600-NEXT: MUL_IEEE T2.W, PV.W, literal.x,613; R600-NEXT: MUL_IEEE * T3.W, T0.W, literal.y,614; R600-NEXT: 967029397(3.122284e-04), 1069064192(1.442383e+00)615; R600-NEXT: RNDNE T0.Z, PS,616; R600-NEXT: MULADD_IEEE T1.W, T1.W, literal.x, PV.W,617; R600-NEXT: AND_INT * T2.W, KC0[2].W, literal.y,618; R600-NEXT: 1069064192(1.442383e+00), -4096(nan)619; R600-NEXT: ADD T1.Z, KC0[2].W, -PS,620; R600-NEXT: MULADD_IEEE T0.W, T0.W, literal.x, PV.W,621; R600-NEXT: ADD * T1.W, T3.W, -PV.Z,622; R600-NEXT: 967029397(3.122284e-04), 0(0.000000e+00)623; R600-NEXT: ADD T2.Z, PS, PV.W,624; R600-NEXT: MUL_IEEE T0.W, PV.Z, literal.x,625; R600-NEXT: MUL_IEEE * T1.W, T2.W, literal.y,626; R600-NEXT: 967029397(3.122284e-04), 1069064192(1.442383e+00)627; R600-NEXT: RNDNE T0.Y, PS,628; R600-NEXT: MULADD_IEEE T1.Z, T1.Z, literal.x, PV.W,629; R600-NEXT: TRUNC T0.W, T0.Z, BS:VEC_120/SCL_212630; R600-NEXT: EXP_IEEE * T0.X, PV.Z,631; R600-NEXT: 1069064192(1.442383e+00), 0(0.000000e+00)632; R600-NEXT: FLT_TO_INT T1.Y, PV.W,633; R600-NEXT: MUL_IEEE T0.Z, PS, literal.x,634; R600-NEXT: MULADD_IEEE T0.W, T2.W, literal.y, PV.Z,635; R600-NEXT: ADD * T1.W, T1.W, -PV.Y,636; R600-NEXT: 209715200(1.972152e-31), 967029397(3.122284e-04)637; R600-NEXT: ADD T1.Z, PS, PV.W,638; R600-NEXT: MUL_IEEE T0.W, PV.Z, literal.x,639; R600-NEXT: SETGT_UINT * T1.W, PV.Y, literal.y,640; R600-NEXT: 209715200(1.972152e-31), -229(nan)641; R600-NEXT: CNDE_INT T0.Z, PS, PV.W, T0.Z,642; R600-NEXT: SETGT_INT T0.W, T1.Y, literal.x,643; R600-NEXT: EXP_IEEE * T1.X, PV.Z,644; R600-NEXT: -127(nan), 0(0.000000e+00)645; R600-NEXT: CNDE_INT T0.Z, PV.W, PV.Z, T0.X,646; R600-NEXT: MAX_INT T2.W, T1.Y, literal.x,647; R600-NEXT: MUL_IEEE * T3.W, PS, literal.y,648; R600-NEXT: -330(nan), 209715200(1.972152e-31)649; R600-NEXT: MUL_IEEE T2.X, PS, literal.x,650; R600-NEXT: ADD_INT T2.Y, PV.W, literal.y,651; R600-NEXT: ADD_INT T1.Z, T1.Y, literal.z,652; R600-NEXT: MIN_INT T2.W, T1.Y, literal.w,653; R600-NEXT: TRUNC * T4.W, T0.Y,654; R600-NEXT: 209715200(1.972152e-31), 204(2.858649e-43)655; R600-NEXT: 102(1.429324e-43), 381(5.338947e-43)656; R600-NEXT: FLT_TO_INT T3.X, PS,657; R600-NEXT: ADD_INT T0.Y, PV.W, literal.x,658; R600-NEXT: ADD_INT T2.Z, T1.Y, literal.y,659; R600-NEXT: SETGT_UINT T2.W, T1.Y, literal.z,660; R600-NEXT: CNDE_INT * T1.W, T1.W, PV.Y, PV.Z,661; R600-NEXT: -254(nan), -127(nan)662; R600-NEXT: 254(3.559298e-43), 0(0.000000e+00)663; R600-NEXT: MUL_IEEE T4.X, T1.X, literal.x,664; R600-NEXT: MUL_IEEE T2.Y, T0.X, literal.x, BS:VEC_120/SCL_212665; R600-NEXT: CNDE_INT T1.Z, T0.W, PS, T1.Y,666; R600-NEXT: CNDE_INT T0.W, PV.W, PV.Z, PV.Y,667; R600-NEXT: MAX_INT * T1.W, PV.X, literal.y,668; R600-NEXT: 2130706432(1.701412e+38), -330(nan)669; R600-NEXT: SETGT_INT T0.X, T1.Y, literal.x,670; R600-NEXT: ADD_INT T0.Y, PS, literal.y,671; R600-NEXT: ADD_INT T2.Z, T3.X, literal.z,672; R600-NEXT: SETGT_UINT * T1.W, T3.X, literal.w,673; R600-NEXT: 127(1.779649e-43), 204(2.858649e-43)674; R600-NEXT: 102(1.429324e-43), -229(nan)675; R600-NEXT: MIN_INT * T4.W, T3.X, literal.x,676; R600-NEXT: 381(5.338947e-43), 0(0.000000e+00)677; R600-NEXT: ADD_INT T5.X, PV.W, literal.x,678; R600-NEXT: ADD_INT T1.Y, T3.X, literal.y,679; R600-NEXT: SETGT_UINT T3.Z, T3.X, literal.z,680; R600-NEXT: CNDE_INT T4.W, T1.W, T0.Y, T2.Z,681; R600-NEXT: SETGT_INT * T5.W, T3.X, literal.y,682; R600-NEXT: -254(nan), -127(nan)683; R600-NEXT: 254(3.559298e-43), 0(0.000000e+00)684; R600-NEXT: CNDE_INT T6.X, PS, PV.W, T3.X,685; R600-NEXT: CNDE_INT T0.Y, PV.Z, PV.Y, PV.X,686; R600-NEXT: SETGT_INT T2.Z, T3.X, literal.x,687; R600-NEXT: CNDE_INT T0.W, T0.X, T1.Z, T0.W, BS:VEC_120/SCL_212688; R600-NEXT: MUL_IEEE * T4.W, T2.Y, literal.y,689; R600-NEXT: 127(1.779649e-43), 2130706432(1.701412e+38)690; R600-NEXT: CNDE_INT T3.X, T2.W, T2.Y, PS, BS:VEC_120/SCL_212691; R600-NEXT: LSHL T1.Y, PV.W, literal.x,692; R600-NEXT: CNDE_INT T1.Z, PV.Z, PV.X, PV.Y,693; R600-NEXT: MUL_IEEE T0.W, T4.X, literal.y,694; R600-NEXT: CNDE_INT * T1.W, T1.W, T2.X, T3.W,695; R600-NEXT: 23(3.222986e-44), 2130706432(1.701412e+38)696; R600-NEXT: CNDE_INT T1.X, T5.W, PS, T1.X, BS:VEC_021/SCL_122697; R600-NEXT: CNDE_INT T0.Y, T3.Z, T4.X, PV.W, BS:VEC_201698; R600-NEXT: LSHL T1.Z, PV.Z, literal.x,699; R600-NEXT: ADD_INT T0.W, PV.Y, literal.y,700; R600-NEXT: CNDE_INT * T1.W, T0.X, T0.Z, PV.X,701; R600-NEXT: 23(3.222986e-44), 1065353216(1.000000e+00)702; R600-NEXT: MUL_IEEE T1.Y, PS, PV.W,703; R600-NEXT: SETGT T0.Z, literal.x, KC0[3].X,704; R600-NEXT: ADD_INT * T0.W, PV.Z, literal.y,705; R600-NEXT: -1026650416(-1.032789e+02), 1065353216(1.000000e+00)706; R600-NEXT: ALU clause starting at 101:707; R600-NEXT: CNDE_INT * T1.W, T2.Z, T1.X, T0.Y,708; R600-NEXT: MUL_IEEE T0.Y, PV.W, T0.W,709; R600-NEXT: SETGT T1.Z, literal.x, KC0[2].W,710; R600-NEXT: CNDE T0.W, T0.Z, T1.Y, 0.0,711; R600-NEXT: SETGT * T1.W, KC0[3].X, literal.y,712; R600-NEXT: -1026650416(-1.032789e+02), 1118925336(8.872284e+01)713; R600-NEXT: CNDE T1.Y, PS, PV.W, literal.x,714; R600-NEXT: CNDE T0.W, PV.Z, PV.Y, 0.0,715; R600-NEXT: SETGT * T1.W, KC0[2].W, literal.y,716; R600-NEXT: 2139095040(INF), 1118925336(8.872284e+01)717; R600-NEXT: CNDE T1.X, PS, PV.W, literal.x,718; R600-NEXT: LSHR * T0.X, KC0[2].Y, literal.y,719; R600-NEXT: 2139095040(INF), 2(2.802597e-45)720;721; CM-LABEL: s_exp_v2f32:722; CM: ; %bb.0:723; CM-NEXT: ALU 98, @4, KC0[CB0:0-32], KC1[]724; CM-NEXT: ALU 18, @103, KC0[CB0:0-32], KC1[]725; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0, T1.X726; CM-NEXT: CF_END727; CM-NEXT: ALU clause starting at 4:728; CM-NEXT: AND_INT * T0.W, KC0[2].W, literal.x,729; CM-NEXT: -4096(nan), 0(0.000000e+00)730; CM-NEXT: ADD * T1.W, KC0[2].W, -PV.W,731; CM-NEXT: MUL_IEEE T0.Y, PV.W, literal.x,732; CM-NEXT: MUL_IEEE T0.Z, T0.W, literal.y,733; CM-NEXT: AND_INT * T2.W, KC0[3].X, literal.z,734; CM-NEXT: 967029397(3.122284e-04), 1069064192(1.442383e+00)735; CM-NEXT: -4096(nan), 0(0.000000e+00)736; CM-NEXT: ADD T1.Y, KC0[3].X, -PV.W,737; CM-NEXT: RNDNE T1.Z, PV.Z,738; CM-NEXT: MULADD_IEEE * T1.W, T1.W, literal.x, PV.Y,739; CM-NEXT: 1069064192(1.442383e+00), 0(0.000000e+00)740; CM-NEXT: MULADD_IEEE T0.X, T0.W, literal.x, PV.W,741; CM-NEXT: ADD T0.Y, T0.Z, -PV.Z,742; CM-NEXT: MUL_IEEE T0.Z, PV.Y, literal.x,743; CM-NEXT: MUL_IEEE * T0.W, T2.W, literal.y, BS:VEC_120/SCL_212744; CM-NEXT: 967029397(3.122284e-04), 1069064192(1.442383e+00)745; CM-NEXT: TRUNC T1.X, T1.Z,746; CM-NEXT: RNDNE T2.Y, PV.W,747; CM-NEXT: MULADD_IEEE T0.Z, T1.Y, literal.x, PV.Z,748; CM-NEXT: ADD * T1.W, PV.Y, PV.X,749; CM-NEXT: 1069064192(1.442383e+00), 0(0.000000e+00)750; CM-NEXT: EXP_IEEE T0.X, T1.W,751; CM-NEXT: EXP_IEEE T0.Y (MASKED), T1.W,752; CM-NEXT: EXP_IEEE T0.Z (MASKED), T1.W,753; CM-NEXT: EXP_IEEE * T0.W (MASKED), T1.W,754; CM-NEXT: MULADD_IEEE T2.X, T2.W, literal.x, T0.Z,755; CM-NEXT: ADD T0.Y, T0.W, -T2.Y, BS:VEC_120/SCL_212756; CM-NEXT: FLT_TO_INT T0.Z, T1.X,757; CM-NEXT: MUL_IEEE * T0.W, PV.X, literal.y,758; CM-NEXT: 967029397(3.122284e-04), 209715200(1.972152e-31)759; CM-NEXT: MUL_IEEE T1.X, PV.W, literal.x,760; CM-NEXT: SETGT_UINT T1.Y, PV.Z, literal.y,761; CM-NEXT: TRUNC T1.Z, T2.Y,762; CM-NEXT: ADD * T1.W, PV.Y, PV.X,763; CM-NEXT: 209715200(1.972152e-31), -229(nan)764; CM-NEXT: EXP_IEEE T0.X (MASKED), T1.W,765; CM-NEXT: EXP_IEEE T0.Y, T1.W,766; CM-NEXT: EXP_IEEE T0.Z (MASKED), T1.W,767; CM-NEXT: EXP_IEEE * T0.W (MASKED), T1.W,768; CM-NEXT: FLT_TO_INT T2.X, T1.Z,769; CM-NEXT: MUL_IEEE T2.Y, PV.Y, literal.x,770; CM-NEXT: CNDE_INT T1.Z, T1.Y, T1.X, T0.W,771; CM-NEXT: SETGT_INT * T0.W, T0.Z, literal.y, BS:VEC_120/SCL_212772; CM-NEXT: 209715200(1.972152e-31), -127(nan)773; CM-NEXT: CNDE_INT T1.X, PV.W, PV.Z, T0.X,774; CM-NEXT: MUL_IEEE T3.Y, PV.Y, literal.x,775; CM-NEXT: SETGT_UINT T1.Z, PV.X, literal.y,776; CM-NEXT: MAX_INT * T1.W, T0.Z, literal.z,777; CM-NEXT: 209715200(1.972152e-31), -229(nan)778; CM-NEXT: -330(nan), 0(0.000000e+00)779; CM-NEXT: ADD_INT T3.X, PV.W, literal.x,780; CM-NEXT: ADD_INT T4.Y, T0.Z, literal.y,781; CM-NEXT: CNDE_INT T2.Z, PV.Z, PV.Y, T2.Y,782; CM-NEXT: SETGT_INT * T1.W, T2.X, literal.z,783; CM-NEXT: 204(2.858649e-43), 102(1.429324e-43)784; CM-NEXT: -127(nan), 0(0.000000e+00)785; CM-NEXT: CNDE_INT T4.X, PV.W, PV.Z, T0.Y,786; CM-NEXT: MUL_IEEE T2.Y, T0.X, literal.x,787; CM-NEXT: MAX_INT T2.Z, T2.X, literal.y, BS:VEC_120/SCL_212788; CM-NEXT: CNDE_INT * T2.W, T1.Y, PV.X, PV.Y,789; CM-NEXT: 2130706432(1.701412e+38), -330(nan)790; CM-NEXT: CNDE_INT T0.X, T0.W, PV.W, T0.Z,791; CM-NEXT: ADD_INT T1.Y, PV.Z, literal.x,792; CM-NEXT: ADD_INT T2.Z, T2.X, literal.y,793; CM-NEXT: MIN_INT * T0.W, T2.X, literal.z,794; CM-NEXT: 204(2.858649e-43), 102(1.429324e-43)795; CM-NEXT: 381(5.338947e-43), 0(0.000000e+00)796; CM-NEXT: ADD_INT T3.X, PV.W, literal.x,797; CM-NEXT: ADD_INT T3.Y, T2.X, literal.y,798; CM-NEXT: SETGT_UINT T3.Z, T2.X, literal.z,799; CM-NEXT: CNDE_INT * T0.W, T1.Z, PV.Y, PV.Z,800; CM-NEXT: -254(nan), -127(nan)801; CM-NEXT: 254(3.559298e-43), 0(0.000000e+00)802; CM-NEXT: MUL_IEEE T5.X, T0.Y, literal.x,803; CM-NEXT: CNDE_INT T0.Y, T1.W, PV.W, T2.X,804; CM-NEXT: CNDE_INT T1.Z, PV.Z, PV.Y, PV.X,805; CM-NEXT: MIN_INT * T0.W, T0.Z, literal.y,806; CM-NEXT: 2130706432(1.701412e+38), 381(5.338947e-43)807; CM-NEXT: SETGT_INT T2.X, T2.X, literal.x,808; CM-NEXT: ADD_INT T1.Y, PV.W, literal.y,809; CM-NEXT: ADD_INT T2.Z, T0.Z, literal.z,810; CM-NEXT: SETGT_UINT * T0.W, T0.Z, literal.w,811; CM-NEXT: 127(1.779649e-43), -254(nan)812; CM-NEXT: -127(nan), 254(3.559298e-43)813; CM-NEXT: CNDE_INT T3.X, PV.W, PV.Z, PV.Y,814; CM-NEXT: SETGT_INT T1.Y, T0.Z, literal.x,815; CM-NEXT: CNDE_INT T0.Z, PV.X, T0.Y, T1.Z,816; CM-NEXT: MUL_IEEE * T1.W, T5.X, literal.y,817; CM-NEXT: 127(1.779649e-43), 2130706432(1.701412e+38)818; CM-NEXT: CNDE_INT T5.X, T3.Z, T5.X, PV.W,819; CM-NEXT: LSHL T0.Y, PV.Z, literal.x,820; CM-NEXT: CNDE_INT T0.Z, PV.Y, T0.X, PV.X, BS:VEC_021/SCL_122821; CM-NEXT: MUL_IEEE * T1.W, T2.Y, literal.y,822; CM-NEXT: 23(3.222986e-44), 2130706432(1.701412e+38)823; CM-NEXT: CNDE_INT T0.X, T0.W, T2.Y, PV.W,824; CM-NEXT: LSHL T2.Y, PV.Z, literal.x,825; CM-NEXT: ADD_INT * T0.Z, PV.Y, literal.y,826; CM-NEXT: 23(3.222986e-44), 1065353216(1.000000e+00)827; CM-NEXT: ALU clause starting at 103:828; CM-NEXT: CNDE_INT * T0.W, T2.X, T4.X, T5.X,829; CM-NEXT: MUL_IEEE T2.X, PV.W, T0.Z,830; CM-NEXT: SETGT T0.Y, literal.x, KC0[3].X,831; CM-NEXT: ADD_INT T0.Z, T2.Y, literal.y,832; CM-NEXT: CNDE_INT * T0.W, T1.Y, T1.X, T0.X, BS:VEC_120/SCL_212833; CM-NEXT: -1026650416(-1.032789e+02), 1065353216(1.000000e+00)834; CM-NEXT: MUL_IEEE T0.X, PV.W, PV.Z,835; CM-NEXT: SETGT T1.Y, literal.x, KC0[2].W,836; CM-NEXT: CNDE T0.Z, PV.Y, PV.X, 0.0,837; CM-NEXT: SETGT * T0.W, KC0[3].X, literal.y,838; CM-NEXT: -1026650416(-1.032789e+02), 1118925336(8.872284e+01)839; CM-NEXT: CNDE T0.Y, PV.W, PV.Z, literal.x,840; CM-NEXT: CNDE T0.Z, PV.Y, PV.X, 0.0,841; CM-NEXT: SETGT * T0.W, KC0[2].W, literal.y,842; CM-NEXT: 2139095040(INF), 1118925336(8.872284e+01)843; CM-NEXT: CNDE * T0.X, PV.W, PV.Z, literal.x,844; CM-NEXT: 2139095040(INF), 0(0.000000e+00)845; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,846; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)847 %result = call <2 x float> @llvm.exp.v2f32(<2 x float> %in)848 store <2 x float> %result, ptr addrspace(1) %out849 ret void850}851 852define amdgpu_kernel void @s_exp_v3f32(ptr addrspace(1) %out, <3 x float> %in) {853; VI-SDAG-LABEL: s_exp_v3f32:854; VI-SDAG: ; %bb.0:855; VI-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34856; VI-SDAG-NEXT: v_mov_b32_e32 v0, 0x3fb8a000857; VI-SDAG-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x24858; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)859; VI-SDAG-NEXT: s_and_b32 s3, s2, 0xfffff000860; VI-SDAG-NEXT: v_mov_b32_e32 v2, s3861; VI-SDAG-NEXT: v_sub_f32_e32 v2, s2, v2862; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x39a3b295, v2863; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v2864; VI-SDAG-NEXT: v_mul_f32_e32 v1, s3, v0865; VI-SDAG-NEXT: v_add_f32_e32 v2, v2, v4866; VI-SDAG-NEXT: v_mov_b32_e32 v4, 0x39a3b295867; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v1868; VI-SDAG-NEXT: v_mul_f32_e32 v5, s3, v4869; VI-SDAG-NEXT: v_sub_f32_e32 v1, v1, v3870; VI-SDAG-NEXT: v_add_f32_e32 v2, v5, v2871; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v2872; VI-SDAG-NEXT: v_exp_f32_e32 v1, v1873; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v3874; VI-SDAG-NEXT: s_and_b32 s3, s1, 0xfffff000875; VI-SDAG-NEXT: v_mov_b32_e32 v7, s3876; VI-SDAG-NEXT: v_sub_f32_e32 v7, s1, v7877; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v2878; VI-SDAG-NEXT: v_mul_f32_e32 v2, s3, v0879; VI-SDAG-NEXT: v_mul_f32_e32 v8, 0x39a3b295, v7880; VI-SDAG-NEXT: v_mul_f32_e32 v7, 0x3fb8a000, v7881; VI-SDAG-NEXT: v_rndne_f32_e32 v6, v2882; VI-SDAG-NEXT: v_add_f32_e32 v7, v7, v8883; VI-SDAG-NEXT: v_mul_f32_e32 v8, s3, v4884; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v6885; VI-SDAG-NEXT: v_add_f32_e32 v7, v8, v7886; VI-SDAG-NEXT: v_add_f32_e32 v2, v2, v7887; VI-SDAG-NEXT: v_exp_f32_e32 v7, v2888; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v6, v6889; VI-SDAG-NEXT: v_mov_b32_e32 v3, 0xc2ce8ed0890; VI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s2, v3891; VI-SDAG-NEXT: v_mov_b32_e32 v5, 0x42b17218892; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc893; VI-SDAG-NEXT: v_mov_b32_e32 v8, 0x7f800000894; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s2, v5895; VI-SDAG-NEXT: s_and_b32 s2, s0, 0xfffff000896; VI-SDAG-NEXT: v_cndmask_b32_e32 v2, v8, v1, vcc897; VI-SDAG-NEXT: v_ldexp_f32 v1, v7, v6898; VI-SDAG-NEXT: v_mov_b32_e32 v7, s2899; VI-SDAG-NEXT: v_sub_f32_e32 v7, s0, v7900; VI-SDAG-NEXT: v_mul_f32_e32 v0, s2, v0901; VI-SDAG-NEXT: v_mul_f32_e32 v9, 0x39a3b295, v7902; VI-SDAG-NEXT: v_mul_f32_e32 v7, 0x3fb8a000, v7903; VI-SDAG-NEXT: v_rndne_f32_e32 v6, v0904; VI-SDAG-NEXT: v_add_f32_e32 v7, v7, v9905; VI-SDAG-NEXT: v_mul_f32_e32 v4, s2, v4906; VI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v6907; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v7908; VI-SDAG-NEXT: v_add_f32_e32 v0, v0, v4909; VI-SDAG-NEXT: v_exp_f32_e32 v0, v0910; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v4, v6911; VI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s1, v3912; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc913; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s1, v5914; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc915; VI-SDAG-NEXT: v_ldexp_f32 v0, v0, v4916; VI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s0, v3917; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc918; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s0, v5919; VI-SDAG-NEXT: v_mov_b32_e32 v3, s4920; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc921; VI-SDAG-NEXT: v_mov_b32_e32 v4, s5922; VI-SDAG-NEXT: flat_store_dwordx3 v[3:4], v[0:2]923; VI-SDAG-NEXT: s_endpgm924;925; VI-GISEL-LABEL: s_exp_v3f32:926; VI-GISEL: ; %bb.0:927; VI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34928; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3fb8a000929; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x39a3b295930; VI-GISEL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x24931; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)932; VI-GISEL-NEXT: s_and_b32 s3, s0, 0xfffff000933; VI-GISEL-NEXT: v_mov_b32_e32 v0, s3934; VI-GISEL-NEXT: v_sub_f32_e32 v0, s0, v0935; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x39a3b295, v0936; VI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8a000, v0937; VI-GISEL-NEXT: v_mul_f32_e32 v3, s3, v1938; VI-GISEL-NEXT: v_add_f32_e32 v0, v0, v4939; VI-GISEL-NEXT: v_mul_f32_e32 v4, s3, v2940; VI-GISEL-NEXT: s_and_b32 s3, s1, 0xfffff000941; VI-GISEL-NEXT: v_mov_b32_e32 v5, s3942; VI-GISEL-NEXT: v_add_f32_e32 v0, v4, v0943; VI-GISEL-NEXT: v_rndne_f32_e32 v4, v3944; VI-GISEL-NEXT: v_sub_f32_e32 v5, s1, v5945; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v4946; VI-GISEL-NEXT: v_mul_f32_e32 v7, 0x39a3b295, v5947; VI-GISEL-NEXT: v_mul_f32_e32 v5, 0x3fb8a000, v5948; VI-GISEL-NEXT: v_add_f32_e32 v0, v3, v0949; VI-GISEL-NEXT: v_mul_f32_e32 v6, s3, v1950; VI-GISEL-NEXT: v_add_f32_e32 v5, v5, v7951; VI-GISEL-NEXT: v_mul_f32_e32 v7, s3, v2952; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v3, v4953; VI-GISEL-NEXT: v_exp_f32_e32 v0, v0954; VI-GISEL-NEXT: v_add_f32_e32 v5, v7, v5955; VI-GISEL-NEXT: v_rndne_f32_e32 v7, v6956; VI-GISEL-NEXT: v_sub_f32_e32 v6, v6, v7957; VI-GISEL-NEXT: v_add_f32_e32 v5, v6, v5958; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v6, v7959; VI-GISEL-NEXT: v_exp_f32_e32 v5, v5960; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v3961; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0xc2ce8ed0962; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s0, v3963; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0x42b17218964; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc965; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s0, v4966; VI-GISEL-NEXT: s_and_b32 s0, s2, 0xfffff000967; VI-GISEL-NEXT: v_ldexp_f32 v5, v5, v6968; VI-GISEL-NEXT: v_mov_b32_e32 v6, s0969; VI-GISEL-NEXT: v_sub_f32_e32 v6, s2, v6970; VI-GISEL-NEXT: v_mul_f32_e32 v8, 0x39a3b295, v6971; VI-GISEL-NEXT: v_mul_f32_e32 v6, 0x3fb8a000, v6972; VI-GISEL-NEXT: v_mul_f32_e32 v1, s0, v1973; VI-GISEL-NEXT: v_add_f32_e32 v6, v6, v8974; VI-GISEL-NEXT: v_mul_f32_e32 v2, s0, v2975; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v6976; VI-GISEL-NEXT: v_rndne_f32_e32 v6, v1977; VI-GISEL-NEXT: v_sub_f32_e32 v1, v1, v6978; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2979; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v6980; VI-GISEL-NEXT: v_exp_f32_e32 v6, v1981; VI-GISEL-NEXT: v_mov_b32_e32 v7, 0x7f800000982; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc983; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s1, v3984; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v5, 0, vcc985; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s1, v4986; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc987; VI-GISEL-NEXT: v_ldexp_f32 v2, v6, v2988; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v3989; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc990; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s2, v4991; VI-GISEL-NEXT: v_mov_b32_e32 v3, s4992; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc993; VI-GISEL-NEXT: v_mov_b32_e32 v4, s5994; VI-GISEL-NEXT: flat_store_dwordx3 v[3:4], v[0:2]995; VI-GISEL-NEXT: s_endpgm996;997; GFX900-SDAG-LABEL: s_exp_v3f32:998; GFX900-SDAG: ; %bb.0:999; GFX900-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x341000; GFX900-SDAG-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x241001; GFX900-SDAG-NEXT: v_mov_b32_e32 v0, 0x3fb8aa3b1002; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x32a5705f1003; GFX900-SDAG-NEXT: v_mov_b32_e32 v5, 0x42b172181004; GFX900-SDAG-NEXT: s_waitcnt lgkmcnt(0)1005; GFX900-SDAG-NEXT: v_mul_f32_e32 v6, s1, v01006; GFX900-SDAG-NEXT: v_rndne_f32_e32 v7, v61007; GFX900-SDAG-NEXT: v_sub_f32_e32 v8, v6, v71008; GFX900-SDAG-NEXT: v_fma_f32 v6, s1, v0, -v61009; GFX900-SDAG-NEXT: v_fma_f32 v6, s1, v1, v61010; GFX900-SDAG-NEXT: v_mul_f32_e32 v2, s2, v01011; GFX900-SDAG-NEXT: v_add_f32_e32 v6, v8, v61012; GFX900-SDAG-NEXT: v_rndne_f32_e32 v3, v21013; GFX900-SDAG-NEXT: v_fma_f32 v4, s2, v0, -v21014; GFX900-SDAG-NEXT: v_exp_f32_e32 v6, v61015; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v7, v71016; GFX900-SDAG-NEXT: v_sub_f32_e32 v2, v2, v31017; GFX900-SDAG-NEXT: v_fma_f32 v4, s2, v1, v41018; GFX900-SDAG-NEXT: v_add_f32_e32 v2, v2, v41019; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v3, v31020; GFX900-SDAG-NEXT: v_exp_f32_e32 v2, v21021; GFX900-SDAG-NEXT: v_ldexp_f32 v6, v6, v71022; GFX900-SDAG-NEXT: v_mul_f32_e32 v7, s0, v01023; GFX900-SDAG-NEXT: v_rndne_f32_e32 v9, v71024; GFX900-SDAG-NEXT: v_fma_f32 v0, s0, v0, -v71025; GFX900-SDAG-NEXT: v_sub_f32_e32 v10, v7, v91026; GFX900-SDAG-NEXT: v_fma_f32 v0, s0, v1, v01027; GFX900-SDAG-NEXT: v_ldexp_f32 v2, v2, v31028; GFX900-SDAG-NEXT: v_mov_b32_e32 v3, 0xc2ce8ed01029; GFX900-SDAG-NEXT: v_add_f32_e32 v0, v10, v01030; GFX900-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s2, v31031; GFX900-SDAG-NEXT: v_exp_f32_e32 v0, v01032; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v7, v91033; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc1034; GFX900-SDAG-NEXT: v_mov_b32_e32 v8, 0x7f8000001035; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s2, v51036; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v2, v8, v2, vcc1037; GFX900-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s1, v31038; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v6, vcc1039; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s1, v51040; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc1041; GFX900-SDAG-NEXT: v_ldexp_f32 v0, v0, v71042; GFX900-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s0, v31043; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc1044; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s0, v51045; GFX900-SDAG-NEXT: v_mov_b32_e32 v4, 01046; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc1047; GFX900-SDAG-NEXT: global_store_dwordx3 v4, v[0:2], s[6:7]1048; GFX900-SDAG-NEXT: s_endpgm1049;1050; GFX900-GISEL-LABEL: s_exp_v3f32:1051; GFX900-GISEL: ; %bb.0:1052; GFX900-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x341053; GFX900-GISEL-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x241054; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3fb8aa3b1055; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x32a5705f1056; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0)1057; GFX900-GISEL-NEXT: v_mul_f32_e32 v5, s1, v11058; GFX900-GISEL-NEXT: v_fma_f32 v6, s1, v1, -v51059; GFX900-GISEL-NEXT: v_rndne_f32_e32 v7, v51060; GFX900-GISEL-NEXT: v_fma_f32 v6, s1, v2, v61061; GFX900-GISEL-NEXT: v_sub_f32_e32 v5, v5, v71062; GFX900-GISEL-NEXT: v_add_f32_e32 v5, v5, v61063; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v6, v71064; GFX900-GISEL-NEXT: v_exp_f32_e32 v5, v51065; GFX900-GISEL-NEXT: v_mul_f32_e32 v0, s0, v11066; GFX900-GISEL-NEXT: v_fma_f32 v3, s0, v1, -v01067; GFX900-GISEL-NEXT: v_rndne_f32_e32 v4, v01068; GFX900-GISEL-NEXT: v_fma_f32 v3, s0, v2, v31069; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v41070; GFX900-GISEL-NEXT: v_add_f32_e32 v0, v0, v31071; GFX900-GISEL-NEXT: v_ldexp_f32 v5, v5, v61072; GFX900-GISEL-NEXT: v_mul_f32_e32 v6, s2, v11073; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v3, v41074; GFX900-GISEL-NEXT: v_exp_f32_e32 v0, v01075; GFX900-GISEL-NEXT: v_fma_f32 v1, s2, v1, -v61076; GFX900-GISEL-NEXT: v_fma_f32 v1, s2, v2, v11077; GFX900-GISEL-NEXT: v_rndne_f32_e32 v2, v61078; GFX900-GISEL-NEXT: v_sub_f32_e32 v6, v6, v21079; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0xc2ce8ed01080; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v6, v11081; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v31082; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s0, v41083; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x42b172181084; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v21085; GFX900-GISEL-NEXT: v_exp_f32_e32 v6, v11086; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc1087; GFX900-GISEL-NEXT: v_mov_b32_e32 v7, 0x7f8000001088; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s0, v31089; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc1090; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s1, v41091; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, v5, 0, vcc1092; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s1, v31093; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc1094; GFX900-GISEL-NEXT: v_ldexp_f32 v2, v6, v21095; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v41096; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc1097; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s2, v31098; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc1099; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 01100; GFX900-GISEL-NEXT: global_store_dwordx3 v3, v[0:2], s[6:7]1101; GFX900-GISEL-NEXT: s_endpgm1102;1103; SI-SDAG-LABEL: s_exp_v3f32:1104; SI-SDAG: ; %bb.0:1105; SI-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xd1106; SI-SDAG-NEXT: v_mov_b32_e32 v0, 0x3fb8aa3b1107; SI-SDAG-NEXT: v_mov_b32_e32 v2, 0x32a5705f1108; SI-SDAG-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x91109; SI-SDAG-NEXT: s_mov_b32 s7, 0xf0001110; SI-SDAG-NEXT: s_waitcnt lgkmcnt(0)1111; SI-SDAG-NEXT: v_mul_f32_e32 v5, s0, v01112; SI-SDAG-NEXT: v_rndne_f32_e32 v6, v51113; SI-SDAG-NEXT: v_sub_f32_e32 v7, v5, v61114; SI-SDAG-NEXT: v_fma_f32 v5, s0, v0, -v51115; SI-SDAG-NEXT: v_fma_f32 v5, s0, v2, v51116; SI-SDAG-NEXT: v_mul_f32_e32 v1, s1, v01117; SI-SDAG-NEXT: v_add_f32_e32 v5, v7, v51118; SI-SDAG-NEXT: v_rndne_f32_e32 v3, v11119; SI-SDAG-NEXT: v_fma_f32 v4, s1, v0, -v11120; SI-SDAG-NEXT: v_exp_f32_e32 v5, v51121; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v6, v61122; SI-SDAG-NEXT: v_sub_f32_e32 v1, v1, v31123; SI-SDAG-NEXT: v_fma_f32 v4, s1, v2, v41124; SI-SDAG-NEXT: v_add_f32_e32 v1, v1, v41125; SI-SDAG-NEXT: v_exp_f32_e32 v1, v11126; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v3, v31127; SI-SDAG-NEXT: v_ldexp_f32_e32 v5, v5, v61128; SI-SDAG-NEXT: v_mul_f32_e32 v6, s2, v01129; SI-SDAG-NEXT: v_rndne_f32_e32 v8, v61130; SI-SDAG-NEXT: v_fma_f32 v0, s2, v0, -v61131; SI-SDAG-NEXT: v_sub_f32_e32 v9, v6, v81132; SI-SDAG-NEXT: v_fma_f32 v0, s2, v2, v01133; SI-SDAG-NEXT: v_ldexp_f32_e32 v1, v1, v31134; SI-SDAG-NEXT: v_mov_b32_e32 v3, 0xc2ce8ed01135; SI-SDAG-NEXT: v_add_f32_e32 v0, v9, v01136; SI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s1, v31137; SI-SDAG-NEXT: v_mov_b32_e32 v4, 0x42b172181138; SI-SDAG-NEXT: v_exp_f32_e32 v2, v01139; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v6, v81140; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc1141; SI-SDAG-NEXT: v_mov_b32_e32 v7, 0x7f8000001142; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s1, v41143; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, v7, v1, vcc1144; SI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s0, v31145; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v5, vcc1146; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s0, v41147; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc1148; SI-SDAG-NEXT: v_ldexp_f32_e32 v2, v2, v61149; SI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s2, v31150; SI-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc1151; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s2, v41152; SI-SDAG-NEXT: s_mov_b32 s6, -11153; SI-SDAG-NEXT: v_cndmask_b32_e32 v2, v7, v2, vcc1154; SI-SDAG-NEXT: buffer_store_dword v2, off, s[4:7], 0 offset:81155; SI-SDAG-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 01156; SI-SDAG-NEXT: s_endpgm1157;1158; SI-GISEL-LABEL: s_exp_v3f32:1159; SI-GISEL: ; %bb.0:1160; SI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xd1161; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3fb8aa3b1162; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x32a5705f1163; SI-GISEL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x91164; SI-GISEL-NEXT: s_mov_b32 s6, -11165; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)1166; SI-GISEL-NEXT: v_mul_f32_e32 v5, s1, v11167; SI-GISEL-NEXT: v_fma_f32 v6, s1, v1, -v51168; SI-GISEL-NEXT: v_rndne_f32_e32 v7, v51169; SI-GISEL-NEXT: v_fma_f32 v6, s1, v2, v61170; SI-GISEL-NEXT: v_sub_f32_e32 v5, v5, v71171; SI-GISEL-NEXT: v_add_f32_e32 v5, v5, v61172; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v6, v71173; SI-GISEL-NEXT: v_exp_f32_e32 v5, v51174; SI-GISEL-NEXT: v_mul_f32_e32 v0, s0, v11175; SI-GISEL-NEXT: v_fma_f32 v3, s0, v1, -v01176; SI-GISEL-NEXT: v_rndne_f32_e32 v4, v01177; SI-GISEL-NEXT: v_fma_f32 v3, s0, v2, v31178; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v41179; SI-GISEL-NEXT: v_add_f32_e32 v0, v0, v31180; SI-GISEL-NEXT: v_ldexp_f32_e32 v5, v5, v61181; SI-GISEL-NEXT: v_mul_f32_e32 v6, s2, v11182; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v3, v41183; SI-GISEL-NEXT: v_exp_f32_e32 v0, v01184; SI-GISEL-NEXT: v_fma_f32 v1, s2, v1, -v61185; SI-GISEL-NEXT: v_fma_f32 v1, s2, v2, v11186; SI-GISEL-NEXT: v_rndne_f32_e32 v2, v61187; SI-GISEL-NEXT: v_sub_f32_e32 v6, v6, v21188; SI-GISEL-NEXT: v_mov_b32_e32 v4, 0xc2ce8ed01189; SI-GISEL-NEXT: v_add_f32_e32 v1, v6, v11190; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v31191; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s0, v41192; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x42b172181193; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v21194; SI-GISEL-NEXT: v_exp_f32_e32 v6, v11195; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc1196; SI-GISEL-NEXT: v_mov_b32_e32 v7, 0x7f8000001197; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s0, v31198; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc1199; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s1, v41200; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, v5, 0, vcc1201; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s1, v31202; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc1203; SI-GISEL-NEXT: v_ldexp_f32_e32 v2, v6, v21204; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v41205; SI-GISEL-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc1206; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s2, v31207; SI-GISEL-NEXT: s_mov_b32 s7, 0xf0001208; SI-GISEL-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc1209; SI-GISEL-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 01210; SI-GISEL-NEXT: buffer_store_dword v2, off, s[4:7], 0 offset:81211; SI-GISEL-NEXT: s_endpgm1212;1213; R600-LABEL: s_exp_v3f32:1214; R600: ; %bb.0:1215; R600-NEXT: ALU 99, @6, KC0[CB0:0-32], KC1[]1216; R600-NEXT: ALU 69, @106, KC0[CB0:0-32], KC1[]1217; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T2.X, T3.X, 01218; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 11219; R600-NEXT: CF_END1220; R600-NEXT: PAD1221; R600-NEXT: ALU clause starting at 6:1222; R600-NEXT: AND_INT * T0.W, KC0[3].Y, literal.x,1223; R600-NEXT: -4096(nan), 0(0.000000e+00)1224; R600-NEXT: MUL_IEEE T1.W, PV.W, literal.x,1225; R600-NEXT: ADD * T2.W, KC0[3].Y, -PV.W,1226; R600-NEXT: 1069064192(1.442383e+00), 0(0.000000e+00)1227; R600-NEXT: RNDNE * T3.W, PV.W,1228; R600-NEXT: TRUNC T4.W, PV.W,1229; R600-NEXT: MUL_IEEE * T5.W, T2.W, literal.x,1230; R600-NEXT: 967029397(3.122284e-04), 0(0.000000e+00)1231; R600-NEXT: MULADD_IEEE T2.W, T2.W, literal.x, PS,1232; R600-NEXT: FLT_TO_INT * T4.W, PV.W,1233; R600-NEXT: 1069064192(1.442383e+00), 0(0.000000e+00)1234; R600-NEXT: MAX_INT T0.Z, PS, literal.x,1235; R600-NEXT: MULADD_IEEE T0.W, T0.W, literal.y, PV.W,1236; R600-NEXT: ADD * T1.W, T1.W, -T3.W,1237; R600-NEXT: -330(nan), 967029397(3.122284e-04)1238; R600-NEXT: ADD T0.Y, PS, PV.W,1239; R600-NEXT: ADD_INT T0.Z, PV.Z, literal.x,1240; R600-NEXT: ADD_INT T0.W, T4.W, literal.y,1241; R600-NEXT: SETGT_UINT * T1.W, T4.W, literal.z,1242; R600-NEXT: 204(2.858649e-43), 102(1.429324e-43)1243; R600-NEXT: -229(nan), 0(0.000000e+00)1244; R600-NEXT: CNDE_INT T0.Z, PS, PV.Z, PV.W,1245; R600-NEXT: SETGT_INT T0.W, T4.W, literal.x,1246; R600-NEXT: EXP_IEEE * T0.X, PV.Y,1247; R600-NEXT: -127(nan), 0(0.000000e+00)1248; R600-NEXT: MUL_IEEE T1.X, PS, literal.x,1249; R600-NEXT: CNDE_INT T0.Y, PV.W, PV.Z, T4.W,1250; R600-NEXT: MIN_INT T0.Z, T4.W, literal.y,1251; R600-NEXT: AND_INT T2.W, KC0[3].W, literal.z,1252; R600-NEXT: MUL_IEEE * T3.W, PS, literal.w,1253; R600-NEXT: 2130706432(1.701412e+38), 381(5.338947e-43)1254; R600-NEXT: -4096(nan), 209715200(1.972152e-31)1255; R600-NEXT: MUL_IEEE T2.X, PS, literal.x,1256; R600-NEXT: ADD T1.Y, KC0[3].W, -PV.W,1257; R600-NEXT: ADD_INT T0.Z, PV.Z, literal.y,1258; R600-NEXT: ADD_INT T5.W, T4.W, literal.z,1259; R600-NEXT: SETGT_UINT * T6.W, T4.W, literal.w,1260; R600-NEXT: 209715200(1.972152e-31), -254(nan)1261; R600-NEXT: -127(nan), 254(3.559298e-43)1262; R600-NEXT: CNDE_INT T3.X, PS, PV.W, PV.Z,1263; R600-NEXT: SETGT_INT T2.Y, T4.W, literal.x,1264; R600-NEXT: MUL_IEEE T0.Z, PV.Y, literal.y,1265; R600-NEXT: MUL_IEEE * T4.W, T2.W, literal.z, BS:VEC_120/SCL_2121266; R600-NEXT: 127(1.779649e-43), 967029397(3.122284e-04)1267; R600-NEXT: 1069064192(1.442383e+00), 0(0.000000e+00)1268; R600-NEXT: CNDE_INT * T1.W, T1.W, T2.X, T3.W,1269; R600-NEXT: CNDE_INT T0.X, T0.W, PV.W, T0.X, BS:VEC_021/SCL_1221270; R600-NEXT: RNDNE T3.Y, T4.W, BS:VEC_120/SCL_2121271; R600-NEXT: MULADD_IEEE T0.Z, T1.Y, literal.x, T0.Z,1272; R600-NEXT: CNDE_INT T0.W, T2.Y, T0.Y, T3.X, BS:VEC_120/SCL_2121273; R600-NEXT: MUL_IEEE * T1.W, T1.X, literal.y,1274; R600-NEXT: 1069064192(1.442383e+00), 2130706432(1.701412e+38)1275; R600-NEXT: CNDE_INT T1.X, T6.W, T1.X, PS,1276; R600-NEXT: LSHL T0.Y, PV.W, literal.x,1277; R600-NEXT: AND_INT T1.Z, KC0[3].Z, literal.y,1278; R600-NEXT: MULADD_IEEE T0.W, T2.W, literal.z, PV.Z, BS:VEC_120/SCL_2121279; R600-NEXT: ADD * T1.W, T4.W, -PV.Y,1280; R600-NEXT: 23(3.222986e-44), -4096(nan)1281; R600-NEXT: 967029397(3.122284e-04), 0(0.000000e+00)1282; R600-NEXT: ADD T1.Y, PS, PV.W,1283; R600-NEXT: MUL_IEEE T0.Z, PV.Z, literal.x,1284; R600-NEXT: ADD_INT T0.W, PV.Y, literal.y,1285; R600-NEXT: CNDE_INT * T1.W, T2.Y, T0.X, PV.X,1286; R600-NEXT: 1069064192(1.442383e+00), 1065353216(1.000000e+00)1287; R600-NEXT: MUL_IEEE T0.X, PS, PV.W,1288; R600-NEXT: ADD T0.Y, KC0[3].Z, -T1.Z,1289; R600-NEXT: RNDNE T2.Z, PV.Z,1290; R600-NEXT: TRUNC T0.W, T3.Y,1291; R600-NEXT: EXP_IEEE * T1.X, PV.Y,1292; R600-NEXT: SETGT T2.X, literal.x, KC0[3].Y,1293; R600-NEXT: FLT_TO_INT T1.Y, PV.W,1294; R600-NEXT: TRUNC T3.Z, PV.Z,1295; R600-NEXT: MUL_IEEE T0.W, PV.Y, literal.y,1296; R600-NEXT: MUL_IEEE * T1.W, PS, literal.z,1297; R600-NEXT: -1026650416(-1.032789e+02), 967029397(3.122284e-04)1298; R600-NEXT: 209715200(1.972152e-31), 0(0.000000e+00)1299; R600-NEXT: MUL_IEEE T3.X, PS, literal.x,1300; R600-NEXT: MUL_IEEE T2.Y, T1.X, literal.y,1301; R600-NEXT: MULADD_IEEE T4.Z, T0.Y, literal.z, PV.W,1302; R600-NEXT: FLT_TO_INT T0.W, PV.Z,1303; R600-NEXT: MIN_INT * T2.W, PV.Y, literal.w,1304; R600-NEXT: 209715200(1.972152e-31), 2130706432(1.701412e+38)1305; R600-NEXT: 1069064192(1.442383e+00), 381(5.338947e-43)1306; R600-NEXT: ADD_INT T4.X, PS, literal.x,1307; R600-NEXT: MAX_INT T0.Y, PV.W, literal.y,1308; R600-NEXT: MULADD_IEEE T1.Z, T1.Z, literal.z, PV.Z,1309; R600-NEXT: ADD T2.W, T0.Z, -T2.Z, BS:VEC_120/SCL_2121310; R600-NEXT: MIN_INT * T3.W, PV.W, literal.w,1311; R600-NEXT: -254(nan), -330(nan)1312; R600-NEXT: 967029397(3.122284e-04), 381(5.338947e-43)1313; R600-NEXT: ADD_INT T5.X, PS, literal.x,1314; R600-NEXT: ADD T3.Y, PV.W, PV.Z,1315; R600-NEXT: ADD_INT T0.Z, PV.Y, literal.y,1316; R600-NEXT: ADD_INT T2.W, T0.W, literal.z,1317; R600-NEXT: SETGT_UINT * T3.W, T0.W, literal.w,1318; R600-NEXT: -254(nan), 204(2.858649e-43)1319; R600-NEXT: 102(1.429324e-43), -229(nan)1320; R600-NEXT: ADD_INT * T6.X, T0.W, literal.x,1321; R600-NEXT: -127(nan), 0(0.000000e+00)1322; R600-NEXT: ALU clause starting at 106:1323; R600-NEXT: SETGT_UINT T0.Y, T0.W, literal.x,1324; R600-NEXT: CNDE_INT T0.Z, T3.W, T0.Z, T2.W, BS:VEC_102/SCL_2211325; R600-NEXT: SETGT_INT T2.W, T0.W, literal.y,1326; R600-NEXT: EXP_IEEE * T1.Z, T3.Y,1327; R600-NEXT: 254(3.559298e-43), -127(nan)1328; R600-NEXT: ADD_INT T7.X, T1.Y, literal.x,1329; R600-NEXT: MUL_IEEE T3.Y, PS, literal.y,1330; R600-NEXT: CNDE_INT T0.Z, PV.W, PV.Z, T0.W,1331; R600-NEXT: CNDE_INT T4.W, PV.Y, T6.X, T5.X,1332; R600-NEXT: SETGT_INT * T0.W, T0.W, literal.z,1333; R600-NEXT: -127(nan), 209715200(1.972152e-31)1334; R600-NEXT: 127(1.779649e-43), 0(0.000000e+00)1335; R600-NEXT: SETGT_UINT T5.X, T1.Y, literal.x,1336; R600-NEXT: CNDE_INT T4.Y, PS, PV.Z, PV.W,1337; R600-NEXT: MAX_INT T0.Z, T1.Y, literal.y,1338; R600-NEXT: MUL_IEEE T4.W, PV.Y, literal.z,1339; R600-NEXT: MUL_IEEE * T5.W, T1.Z, literal.w,1340; R600-NEXT: 254(3.559298e-43), -330(nan)1341; R600-NEXT: 209715200(1.972152e-31), 2130706432(1.701412e+38)1342; R600-NEXT: MUL_IEEE T6.X, PS, literal.x,1343; R600-NEXT: CNDE_INT T3.Y, T3.W, PV.W, T3.Y, BS:VEC_021/SCL_1221344; R600-NEXT: ADD_INT T0.Z, PV.Z, literal.y,1345; R600-NEXT: ADD_INT T3.W, T1.Y, literal.z,1346; R600-NEXT: SETGT_UINT * T4.W, T1.Y, literal.w,1347; R600-NEXT: 2130706432(1.701412e+38), 204(2.858649e-43)1348; R600-NEXT: 102(1.429324e-43), -229(nan)1349; R600-NEXT: CNDE_INT T8.X, PS, PV.Z, PV.W,1350; R600-NEXT: SETGT_INT T5.Y, T1.Y, literal.x,1351; R600-NEXT: CNDE_INT T0.Z, T2.W, PV.Y, T1.Z,1352; R600-NEXT: CNDE_INT T2.W, T0.Y, T5.W, PV.X, BS:VEC_120/SCL_2121353; R600-NEXT: LSHL * T3.W, T4.Y, literal.y,1354; R600-NEXT: -127(nan), 23(3.222986e-44)1355; R600-NEXT: ADD_INT T6.X, PS, literal.x,1356; R600-NEXT: CNDE_INT T0.Y, T0.W, PV.Z, PV.W,1357; R600-NEXT: CNDE_INT T0.Z, PV.Y, PV.X, T1.Y,1358; R600-NEXT: CNDE_INT T0.W, T5.X, T7.X, T4.X,1359; R600-NEXT: SETGT_INT * T2.W, T1.Y, literal.y,1360; R600-NEXT: 1065353216(1.000000e+00), 127(1.779649e-43)1361; R600-NEXT: CNDE_INT T4.X, PS, PV.Z, PV.W,1362; R600-NEXT: MUL_IEEE T0.Y, PV.Y, PV.X,1363; R600-NEXT: SETGT T0.Z, literal.x, KC0[3].Z,1364; R600-NEXT: MUL_IEEE T0.W, T2.Y, literal.y,1365; R600-NEXT: CNDE_INT * T1.W, T4.W, T3.X, T1.W,1366; R600-NEXT: -1026650416(-1.032789e+02), 2130706432(1.701412e+38)1367; R600-NEXT: CNDE_INT T1.X, T5.Y, PS, T1.X,1368; R600-NEXT: CNDE_INT T1.Y, T5.X, T2.Y, PV.W,1369; R600-NEXT: CNDE T0.Z, PV.Z, PV.Y, 0.0,1370; R600-NEXT: SETGT T0.W, KC0[3].Z, literal.x,1371; R600-NEXT: LSHL * T1.W, PV.X, literal.y,1372; R600-NEXT: 1118925336(8.872284e+01), 23(3.222986e-44)1373; R600-NEXT: ADD_INT T3.X, PS, literal.x,1374; R600-NEXT: CNDE T0.Y, PV.W, PV.Z, literal.y,1375; R600-NEXT: CNDE_INT T0.Z, T2.W, PV.X, PV.Y,1376; R600-NEXT: CNDE T0.W, T2.X, T0.X, 0.0,1377; R600-NEXT: SETGT * T1.W, KC0[3].Y, literal.z,1378; R600-NEXT: 1065353216(1.000000e+00), 2139095040(INF)1379; R600-NEXT: 1118925336(8.872284e+01), 0(0.000000e+00)1380; R600-NEXT: CNDE T0.X, PS, PV.W, literal.x,1381; R600-NEXT: MUL_IEEE T0.W, PV.Z, PV.X,1382; R600-NEXT: SETGT * T1.W, literal.y, KC0[3].W,1383; R600-NEXT: 2139095040(INF), -1026650416(-1.032789e+02)1384; R600-NEXT: LSHR T1.X, KC0[2].Y, literal.x,1385; R600-NEXT: CNDE T0.W, PS, PV.W, 0.0,1386; R600-NEXT: SETGT * T1.W, KC0[3].W, literal.y,1387; R600-NEXT: 2(2.802597e-45), 1118925336(8.872284e+01)1388; R600-NEXT: CNDE T2.X, PS, PV.W, literal.x,1389; R600-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,1390; R600-NEXT: 2139095040(INF), 8(1.121039e-44)1391; R600-NEXT: LSHR * T3.X, PV.W, literal.x,1392; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)1393;1394; CM-LABEL: s_exp_v3f32:1395; CM: ; %bb.0:1396; CM-NEXT: ALU 101, @6, KC0[CB0:0-32], KC1[]1397; CM-NEXT: ALU 77, @108, KC0[CB0:0-32], KC1[]1398; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0, T1.X1399; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T2.X, T3.X1400; CM-NEXT: CF_END1401; CM-NEXT: PAD1402; CM-NEXT: ALU clause starting at 6:1403; CM-NEXT: AND_INT * T0.W, KC0[3].Y, literal.x,1404; CM-NEXT: -4096(nan), 0(0.000000e+00)1405; CM-NEXT: ADD * T1.W, KC0[3].Y, -PV.W,1406; CM-NEXT: MUL_IEEE T0.Z, PV.W, literal.x,1407; CM-NEXT: MUL_IEEE * T2.W, T0.W, literal.y,1408; CM-NEXT: 967029397(3.122284e-04), 1069064192(1.442383e+00)1409; CM-NEXT: RNDNE T1.Z, PV.W,1410; CM-NEXT: MULADD_IEEE * T1.W, T1.W, literal.x, PV.Z,1411; CM-NEXT: 1069064192(1.442383e+00), 0(0.000000e+00)1412; CM-NEXT: MULADD_IEEE T0.Z, T0.W, literal.x, PV.W,1413; CM-NEXT: ADD * T0.W, T2.W, -PV.Z, BS:VEC_120/SCL_2121414; CM-NEXT: 967029397(3.122284e-04), 0(0.000000e+00)1415; CM-NEXT: TRUNC T1.Z, T1.Z,1416; CM-NEXT: ADD * T0.W, PV.W, PV.Z,1417; CM-NEXT: EXP_IEEE T0.X, T0.W,1418; CM-NEXT: EXP_IEEE T0.Y (MASKED), T0.W,1419; CM-NEXT: EXP_IEEE T0.Z (MASKED), T0.W,1420; CM-NEXT: EXP_IEEE * T0.W (MASKED), T0.W,1421; CM-NEXT: FLT_TO_INT T0.Z, T1.Z,1422; CM-NEXT: MUL_IEEE * T0.W, PV.X, literal.x,1423; CM-NEXT: 209715200(1.972152e-31), 0(0.000000e+00)1424; CM-NEXT: MUL_IEEE T0.Y, PV.W, literal.x,1425; CM-NEXT: MAX_INT T1.Z, PV.Z, literal.y,1426; CM-NEXT: MIN_INT * T1.W, PV.Z, literal.z,1427; CM-NEXT: 209715200(1.972152e-31), -330(nan)1428; CM-NEXT: 381(5.338947e-43), 0(0.000000e+00)1429; CM-NEXT: ADD_INT T1.X, PV.W, literal.x,1430; CM-NEXT: ADD_INT T1.Y, PV.Z, literal.y,1431; CM-NEXT: ADD_INT T1.Z, T0.Z, literal.z,1432; CM-NEXT: SETGT_UINT * T1.W, T0.Z, literal.w,1433; CM-NEXT: -254(nan), 204(2.858649e-43)1434; CM-NEXT: 102(1.429324e-43), -229(nan)1435; CM-NEXT: ADD_INT T2.X, T0.Z, literal.x,1436; CM-NEXT: SETGT_UINT T2.Y, T0.Z, literal.y,1437; CM-NEXT: CNDE_INT T1.Z, PV.W, PV.Y, PV.Z,1438; CM-NEXT: SETGT_INT * T2.W, T0.Z, literal.x,1439; CM-NEXT: -127(nan), 254(3.559298e-43)1440; CM-NEXT: MUL_IEEE T3.X, T0.X, literal.x,1441; CM-NEXT: CNDE_INT T1.Y, PV.W, PV.Z, T0.Z,1442; CM-NEXT: CNDE_INT T1.Z, PV.Y, PV.X, T1.X,1443; CM-NEXT: SETGT_INT * T3.W, T0.Z, literal.y,1444; CM-NEXT: 2130706432(1.701412e+38), 127(1.779649e-43)1445; CM-NEXT: CNDE_INT T1.Y, PV.W, PV.Y, PV.Z,1446; CM-NEXT: MUL_IEEE T0.Z, PV.X, literal.x,1447; CM-NEXT: CNDE_INT * T0.W, T1.W, T0.Y, T0.W,1448; CM-NEXT: 2130706432(1.701412e+38), 0(0.000000e+00)1449; CM-NEXT: CNDE_INT T0.X, T2.W, PV.W, T0.X,1450; CM-NEXT: CNDE_INT T0.Y, T2.Y, T3.X, PV.Z,1451; CM-NEXT: LSHL T0.Z, PV.Y, literal.x,1452; CM-NEXT: AND_INT * T0.W, KC0[3].Z, literal.y,1453; CM-NEXT: 23(3.222986e-44), -4096(nan)1454; CM-NEXT: ADD T1.Y, KC0[3].Z, -PV.W,1455; CM-NEXT: ADD_INT T0.Z, PV.Z, literal.x,1456; CM-NEXT: CNDE_INT * T1.W, T3.W, PV.X, PV.Y,1457; CM-NEXT: 1065353216(1.000000e+00), 0(0.000000e+00)1458; CM-NEXT: MUL_IEEE T0.X, PV.W, PV.Z,1459; CM-NEXT: MUL_IEEE T0.Y, PV.Y, literal.x,1460; CM-NEXT: MUL_IEEE T0.Z, T0.W, literal.y,1461; CM-NEXT: AND_INT * T1.W, KC0[3].W, literal.z,1462; CM-NEXT: 967029397(3.122284e-04), 1069064192(1.442383e+00)1463; CM-NEXT: -4096(nan), 0(0.000000e+00)1464; CM-NEXT: SETGT T1.X, literal.x, KC0[3].Y,1465; CM-NEXT: ADD T2.Y, KC0[3].W, -PV.W,1466; CM-NEXT: RNDNE T1.Z, PV.Z,1467; CM-NEXT: MULADD_IEEE * T2.W, T1.Y, literal.y, PV.Y,1468; CM-NEXT: -1026650416(-1.032789e+02), 1069064192(1.442383e+00)1469; CM-NEXT: MULADD_IEEE T2.X, T0.W, literal.x, PV.W,1470; CM-NEXT: ADD T0.Y, T0.Z, -PV.Z,1471; CM-NEXT: MUL_IEEE T0.Z, PV.Y, literal.x,1472; CM-NEXT: MUL_IEEE * T0.W, T1.W, literal.y, BS:VEC_120/SCL_2121473; CM-NEXT: 967029397(3.122284e-04), 1069064192(1.442383e+00)1474; CM-NEXT: TRUNC T3.X, T1.Z,1475; CM-NEXT: RNDNE T1.Y, PV.W,1476; CM-NEXT: MULADD_IEEE T0.Z, T2.Y, literal.x, PV.Z,1477; CM-NEXT: ADD * T2.W, PV.Y, PV.X,1478; CM-NEXT: 1069064192(1.442383e+00), 0(0.000000e+00)1479; CM-NEXT: EXP_IEEE T0.X (MASKED), T2.W,1480; CM-NEXT: EXP_IEEE T0.Y, T2.W,1481; CM-NEXT: EXP_IEEE T0.Z (MASKED), T2.W,1482; CM-NEXT: EXP_IEEE * T0.W (MASKED), T2.W,1483; CM-NEXT: MULADD_IEEE T2.X, T1.W, literal.x, T0.Z,1484; CM-NEXT: ADD T2.Y, T0.W, -T1.Y, BS:VEC_120/SCL_2121485; CM-NEXT: FLT_TO_INT T0.Z, T3.X,1486; CM-NEXT: MUL_IEEE * T0.W, PV.Y, literal.y,1487; CM-NEXT: 967029397(3.122284e-04), 209715200(1.972152e-31)1488; CM-NEXT: MUL_IEEE T3.X, PV.W, literal.x,1489; CM-NEXT: SETGT_UINT T3.Y, PV.Z, literal.y,1490; CM-NEXT: TRUNC T1.Z, T1.Y,1491; CM-NEXT: ADD * T1.W, PV.Y, PV.X,1492; CM-NEXT: 209715200(1.972152e-31), -229(nan)1493; CM-NEXT: EXP_IEEE T1.X (MASKED), T1.W,1494; CM-NEXT: EXP_IEEE T1.Y, T1.W,1495; CM-NEXT: EXP_IEEE T1.Z (MASKED), T1.W,1496; CM-NEXT: EXP_IEEE * T1.W (MASKED), T1.W,1497; CM-NEXT: FLT_TO_INT T2.X, T1.Z,1498; CM-NEXT: MUL_IEEE T2.Y, PV.Y, literal.x,1499; CM-NEXT: CNDE_INT T1.Z, T3.Y, T3.X, T0.W,1500; CM-NEXT: SETGT_INT * T0.W, T0.Z, literal.y, BS:VEC_120/SCL_2121501; CM-NEXT: 209715200(1.972152e-31), -127(nan)1502; CM-NEXT: CNDE_INT T3.X, PV.W, PV.Z, T0.Y,1503; CM-NEXT: MUL_IEEE * T4.Y, PV.Y, literal.x,1504; CM-NEXT: 209715200(1.972152e-31), 0(0.000000e+00)1505; CM-NEXT: ALU clause starting at 108:1506; CM-NEXT: SETGT_UINT T1.Z, T2.X, literal.x,1507; CM-NEXT: MAX_INT * T1.W, T0.Z, literal.y,1508; CM-NEXT: -229(nan), -330(nan)1509; CM-NEXT: ADD_INT T4.X, PV.W, literal.x,1510; CM-NEXT: ADD_INT T5.Y, T0.Z, literal.y,1511; CM-NEXT: CNDE_INT T2.Z, PV.Z, T4.Y, T2.Y,1512; CM-NEXT: SETGT_INT * T1.W, T2.X, literal.z,1513; CM-NEXT: 204(2.858649e-43), 102(1.429324e-43)1514; CM-NEXT: -127(nan), 0(0.000000e+00)1515; CM-NEXT: CNDE_INT T5.X, PV.W, PV.Z, T1.Y,1516; CM-NEXT: MUL_IEEE T0.Y, T0.Y, literal.x,1517; CM-NEXT: MAX_INT T2.Z, T2.X, literal.y,1518; CM-NEXT: CNDE_INT * T2.W, T3.Y, PV.X, PV.Y, BS:VEC_120/SCL_2121519; CM-NEXT: 2130706432(1.701412e+38), -330(nan)1520; CM-NEXT: CNDE_INT T4.X, T0.W, PV.W, T0.Z,1521; CM-NEXT: ADD_INT T2.Y, PV.Z, literal.x,1522; CM-NEXT: ADD_INT T2.Z, T2.X, literal.y,1523; CM-NEXT: MIN_INT * T0.W, T2.X, literal.z,1524; CM-NEXT: 204(2.858649e-43), 102(1.429324e-43)1525; CM-NEXT: 381(5.338947e-43), 0(0.000000e+00)1526; CM-NEXT: ADD_INT T6.X, PV.W, literal.x,1527; CM-NEXT: ADD_INT T3.Y, T2.X, literal.y,1528; CM-NEXT: SETGT_UINT T3.Z, T2.X, literal.z,1529; CM-NEXT: CNDE_INT * T0.W, T1.Z, PV.Y, PV.Z,1530; CM-NEXT: -254(nan), -127(nan)1531; CM-NEXT: 254(3.559298e-43), 0(0.000000e+00)1532; CM-NEXT: MUL_IEEE T7.X, T1.Y, literal.x,1533; CM-NEXT: CNDE_INT T1.Y, T1.W, PV.W, T2.X,1534; CM-NEXT: CNDE_INT T1.Z, PV.Z, PV.Y, PV.X,1535; CM-NEXT: MIN_INT * T0.W, T0.Z, literal.y,1536; CM-NEXT: 2130706432(1.701412e+38), 381(5.338947e-43)1537; CM-NEXT: SETGT_INT T2.X, T2.X, literal.x,1538; CM-NEXT: ADD_INT T2.Y, PV.W, literal.y,1539; CM-NEXT: ADD_INT T2.Z, T0.Z, literal.z,1540; CM-NEXT: SETGT_UINT * T0.W, T0.Z, literal.w,1541; CM-NEXT: 127(1.779649e-43), -254(nan)1542; CM-NEXT: -127(nan), 254(3.559298e-43)1543; CM-NEXT: CNDE_INT T6.X, PV.W, PV.Z, PV.Y,1544; CM-NEXT: SETGT_INT T2.Y, T0.Z, literal.x,1545; CM-NEXT: CNDE_INT T0.Z, PV.X, T1.Y, T1.Z,1546; CM-NEXT: MUL_IEEE * T1.W, T7.X, literal.y,1547; CM-NEXT: 127(1.779649e-43), 2130706432(1.701412e+38)1548; CM-NEXT: CNDE_INT T7.X, T3.Z, T7.X, PV.W,1549; CM-NEXT: LSHL T1.Y, PV.Z, literal.x,1550; CM-NEXT: CNDE_INT T0.Z, PV.Y, T4.X, PV.X, BS:VEC_021/SCL_1221551; CM-NEXT: MUL_IEEE * T1.W, T0.Y, literal.y,1552; CM-NEXT: 23(3.222986e-44), 2130706432(1.701412e+38)1553; CM-NEXT: CNDE_INT T4.X, T0.W, T0.Y, PV.W,1554; CM-NEXT: LSHL T0.Y, PV.Z, literal.x,1555; CM-NEXT: ADD_INT T0.Z, PV.Y, literal.y,1556; CM-NEXT: CNDE_INT * T0.W, T2.X, T5.X, PV.X,1557; CM-NEXT: 23(3.222986e-44), 1065353216(1.000000e+00)1558; CM-NEXT: MUL_IEEE T2.X, PV.W, PV.Z,1559; CM-NEXT: SETGT T1.Y, literal.x, KC0[3].W,1560; CM-NEXT: ADD_INT T0.Z, PV.Y, literal.y,1561; CM-NEXT: CNDE_INT * T0.W, T2.Y, T3.X, PV.X,1562; CM-NEXT: -1026650416(-1.032789e+02), 1065353216(1.000000e+00)1563; CM-NEXT: MUL_IEEE T3.X, PV.W, PV.Z,1564; CM-NEXT: SETGT T0.Y, literal.x, KC0[3].Z,1565; CM-NEXT: CNDE T0.Z, PV.Y, PV.X, 0.0,1566; CM-NEXT: SETGT * T0.W, KC0[3].W, literal.y,1567; CM-NEXT: -1026650416(-1.032789e+02), 1118925336(8.872284e+01)1568; CM-NEXT: CNDE T2.X, PV.W, PV.Z, literal.x,1569; CM-NEXT: CNDE T0.Y, PV.Y, PV.X, 0.0,1570; CM-NEXT: SETGT T0.Z, KC0[3].Z, literal.y,1571; CM-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.z,1572; CM-NEXT: 2139095040(INF), 1118925336(8.872284e+01)1573; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00)1574; CM-NEXT: LSHR T3.X, PV.W, literal.x,1575; CM-NEXT: CNDE T0.Y, PV.Z, PV.Y, literal.y,1576; CM-NEXT: CNDE T0.Z, T1.X, T0.X, 0.0,1577; CM-NEXT: SETGT * T0.W, KC0[3].Y, literal.z,1578; CM-NEXT: 2(2.802597e-45), 2139095040(INF)1579; CM-NEXT: 1118925336(8.872284e+01), 0(0.000000e+00)1580; CM-NEXT: CNDE * T0.X, PV.W, PV.Z, literal.x,1581; CM-NEXT: 2139095040(INF), 0(0.000000e+00)1582; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,1583; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)1584 %result = call <3 x float> @llvm.exp.v3f32(<3 x float> %in)1585 store <3 x float> %result, ptr addrspace(1) %out1586 ret void1587}1588 1589; FIXME: We should be able to merge these packets together on Cayman so we1590; have a maximum of 4 instructions.1591define amdgpu_kernel void @s_exp_v4f32(ptr addrspace(1) %out, <4 x float> %in) {1592; VI-SDAG-LABEL: s_exp_v4f32:1593; VI-SDAG: ; %bb.0:1594; VI-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x341595; VI-SDAG-NEXT: v_mov_b32_e32 v0, 0x3fb8a0001596; VI-SDAG-NEXT: v_mov_b32_e32 v6, 0x42b172181597; VI-SDAG-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x241598; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)1599; VI-SDAG-NEXT: s_and_b32 s6, s3, 0xfffff0001600; VI-SDAG-NEXT: v_mov_b32_e32 v2, s61601; VI-SDAG-NEXT: v_sub_f32_e32 v2, s3, v21602; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x39a3b295, v21603; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v21604; VI-SDAG-NEXT: v_mul_f32_e32 v1, s6, v01605; VI-SDAG-NEXT: v_add_f32_e32 v2, v2, v41606; VI-SDAG-NEXT: v_mov_b32_e32 v4, 0x39a3b2951607; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v11608; VI-SDAG-NEXT: v_mul_f32_e32 v5, s6, v41609; VI-SDAG-NEXT: v_sub_f32_e32 v1, v1, v31610; VI-SDAG-NEXT: v_add_f32_e32 v2, v5, v21611; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v21612; VI-SDAG-NEXT: v_exp_f32_e32 v1, v11613; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v31614; VI-SDAG-NEXT: s_and_b32 s6, s2, 0xfffff0001615; VI-SDAG-NEXT: v_mov_b32_e32 v7, s61616; VI-SDAG-NEXT: v_sub_f32_e32 v7, s2, v71617; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v21618; VI-SDAG-NEXT: v_mul_f32_e32 v2, s6, v01619; VI-SDAG-NEXT: v_mul_f32_e32 v8, 0x39a3b295, v71620; VI-SDAG-NEXT: v_mul_f32_e32 v7, 0x3fb8a000, v71621; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v21622; VI-SDAG-NEXT: v_add_f32_e32 v7, v7, v81623; VI-SDAG-NEXT: v_mul_f32_e32 v8, s6, v41624; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v31625; VI-SDAG-NEXT: v_add_f32_e32 v7, v8, v71626; VI-SDAG-NEXT: v_mov_b32_e32 v5, 0xc2ce8ed01627; VI-SDAG-NEXT: v_add_f32_e32 v2, v2, v71628; VI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s3, v51629; VI-SDAG-NEXT: v_exp_f32_e32 v2, v21630; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v7, v31631; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc1632; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s3, v61633; VI-SDAG-NEXT: s_and_b32 s3, s1, 0xfffff0001634; VI-SDAG-NEXT: v_mov_b32_e32 v9, s31635; VI-SDAG-NEXT: v_mov_b32_e32 v8, 0x7f8000001636; VI-SDAG-NEXT: v_sub_f32_e32 v9, s1, v91637; VI-SDAG-NEXT: v_cndmask_b32_e32 v3, v8, v1, vcc1638; VI-SDAG-NEXT: v_ldexp_f32 v1, v2, v71639; VI-SDAG-NEXT: v_mul_f32_e32 v2, s3, v01640; VI-SDAG-NEXT: v_mul_f32_e32 v10, 0x39a3b295, v91641; VI-SDAG-NEXT: v_mul_f32_e32 v9, 0x3fb8a000, v91642; VI-SDAG-NEXT: v_rndne_f32_e32 v7, v21643; VI-SDAG-NEXT: v_add_f32_e32 v9, v9, v101644; VI-SDAG-NEXT: v_mul_f32_e32 v10, s3, v41645; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v71646; VI-SDAG-NEXT: v_add_f32_e32 v9, v10, v91647; VI-SDAG-NEXT: v_add_f32_e32 v2, v2, v91648; VI-SDAG-NEXT: v_exp_f32_e32 v9, v21649; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v7, v71650; VI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s2, v51651; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc1652; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s2, v61653; VI-SDAG-NEXT: s_and_b32 s2, s0, 0xfffff0001654; VI-SDAG-NEXT: v_cndmask_b32_e32 v2, v8, v1, vcc1655; VI-SDAG-NEXT: v_ldexp_f32 v1, v9, v71656; VI-SDAG-NEXT: v_mov_b32_e32 v9, s21657; VI-SDAG-NEXT: v_sub_f32_e32 v9, s0, v91658; VI-SDAG-NEXT: v_mul_f32_e32 v0, s2, v01659; VI-SDAG-NEXT: v_mul_f32_e32 v10, 0x39a3b295, v91660; VI-SDAG-NEXT: v_mul_f32_e32 v9, 0x3fb8a000, v91661; VI-SDAG-NEXT: v_rndne_f32_e32 v7, v01662; VI-SDAG-NEXT: v_add_f32_e32 v9, v9, v101663; VI-SDAG-NEXT: v_mul_f32_e32 v4, s2, v41664; VI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v71665; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v91666; VI-SDAG-NEXT: v_add_f32_e32 v0, v0, v41667; VI-SDAG-NEXT: v_exp_f32_e32 v0, v01668; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v4, v71669; VI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s1, v51670; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc1671; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s1, v61672; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc1673; VI-SDAG-NEXT: v_ldexp_f32 v0, v0, v41674; VI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s0, v51675; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc1676; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s0, v61677; VI-SDAG-NEXT: v_mov_b32_e32 v4, s41678; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc1679; VI-SDAG-NEXT: v_mov_b32_e32 v5, s51680; VI-SDAG-NEXT: flat_store_dwordx4 v[4:5], v[0:3]1681; VI-SDAG-NEXT: s_endpgm1682;1683; VI-GISEL-LABEL: s_exp_v4f32:1684; VI-GISEL: ; %bb.0:1685; VI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x341686; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x3fb8a0001687; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x39a3b2951688; VI-GISEL-NEXT: v_mov_b32_e32 v5, 0x42b172181689; VI-GISEL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x241690; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)1691; VI-GISEL-NEXT: s_and_b32 s6, s0, 0xfffff0001692; VI-GISEL-NEXT: v_mov_b32_e32 v0, s61693; VI-GISEL-NEXT: v_sub_f32_e32 v0, s0, v01694; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x39a3b295, v01695; VI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8a000, v01696; VI-GISEL-NEXT: v_mul_f32_e32 v1, s6, v21697; VI-GISEL-NEXT: v_add_f32_e32 v0, v0, v41698; VI-GISEL-NEXT: v_mul_f32_e32 v4, s6, v31699; VI-GISEL-NEXT: v_add_f32_e32 v0, v4, v01700; VI-GISEL-NEXT: v_rndne_f32_e32 v4, v11701; VI-GISEL-NEXT: v_sub_f32_e32 v1, v1, v41702; VI-GISEL-NEXT: v_add_f32_e32 v0, v1, v01703; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v1, v41704; VI-GISEL-NEXT: v_exp_f32_e32 v0, v01705; VI-GISEL-NEXT: s_and_b32 s6, s1, 0xfffff0001706; VI-GISEL-NEXT: v_mul_f32_e32 v6, s6, v21707; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0xc2ce8ed01708; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v11709; VI-GISEL-NEXT: v_mov_b32_e32 v1, s61710; VI-GISEL-NEXT: v_sub_f32_e32 v1, s1, v11711; VI-GISEL-NEXT: v_mul_f32_e32 v7, 0x39a3b295, v11712; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3fb8a000, v11713; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v71714; VI-GISEL-NEXT: v_mul_f32_e32 v7, s6, v31715; VI-GISEL-NEXT: v_add_f32_e32 v1, v7, v11716; VI-GISEL-NEXT: v_rndne_f32_e32 v7, v61717; VI-GISEL-NEXT: v_sub_f32_e32 v6, v6, v71718; VI-GISEL-NEXT: v_add_f32_e32 v1, v6, v11719; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v6, v71720; VI-GISEL-NEXT: v_exp_f32_e32 v1, v11721; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s0, v41722; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc1723; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s0, v51724; VI-GISEL-NEXT: s_and_b32 s0, s2, 0xfffff0001725; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v61726; VI-GISEL-NEXT: v_mov_b32_e32 v6, s01727; VI-GISEL-NEXT: v_sub_f32_e32 v6, s2, v61728; VI-GISEL-NEXT: v_mul_f32_e32 v9, 0x39a3b295, v61729; VI-GISEL-NEXT: v_mul_f32_e32 v6, 0x3fb8a000, v61730; VI-GISEL-NEXT: v_mul_f32_e32 v8, s0, v21731; VI-GISEL-NEXT: v_add_f32_e32 v6, v6, v91732; VI-GISEL-NEXT: v_mul_f32_e32 v9, s0, v31733; VI-GISEL-NEXT: v_add_f32_e32 v6, v9, v61734; VI-GISEL-NEXT: v_rndne_f32_e32 v9, v81735; VI-GISEL-NEXT: v_sub_f32_e32 v8, v8, v91736; VI-GISEL-NEXT: v_add_f32_e32 v6, v8, v61737; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v8, v91738; VI-GISEL-NEXT: v_exp_f32_e32 v6, v61739; VI-GISEL-NEXT: s_and_b32 s0, s3, 0xfffff0001740; VI-GISEL-NEXT: v_mul_f32_e32 v2, s0, v21741; VI-GISEL-NEXT: v_mul_f32_e32 v3, s0, v31742; VI-GISEL-NEXT: v_ldexp_f32 v6, v6, v81743; VI-GISEL-NEXT: v_mov_b32_e32 v8, s01744; VI-GISEL-NEXT: v_sub_f32_e32 v8, s3, v81745; VI-GISEL-NEXT: v_mul_f32_e32 v9, 0x39a3b295, v81746; VI-GISEL-NEXT: v_mul_f32_e32 v8, 0x3fb8a000, v81747; VI-GISEL-NEXT: v_add_f32_e32 v8, v8, v91748; VI-GISEL-NEXT: v_add_f32_e32 v3, v3, v81749; VI-GISEL-NEXT: v_rndne_f32_e32 v8, v21750; VI-GISEL-NEXT: v_sub_f32_e32 v2, v2, v81751; VI-GISEL-NEXT: v_mov_b32_e32 v7, 0x7f8000001752; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v31753; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc1754; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s1, v41755; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v3, v81756; VI-GISEL-NEXT: v_exp_f32_e32 v8, v21757; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc1758; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s1, v51759; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc1760; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v41761; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, v6, 0, vcc1762; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s2, v51763; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc1764; VI-GISEL-NEXT: v_ldexp_f32 v3, v8, v31765; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s3, v41766; VI-GISEL-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc1767; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s3, v51768; VI-GISEL-NEXT: v_mov_b32_e32 v4, s41769; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc1770; VI-GISEL-NEXT: v_mov_b32_e32 v5, s51771; VI-GISEL-NEXT: flat_store_dwordx4 v[4:5], v[0:3]1772; VI-GISEL-NEXT: s_endpgm1773;1774; GFX900-SDAG-LABEL: s_exp_v4f32:1775; GFX900-SDAG: ; %bb.0:1776; GFX900-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x341777; GFX900-SDAG-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x241778; GFX900-SDAG-NEXT: v_mov_b32_e32 v0, 0x3fb8aa3b1779; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x32a5705f1780; GFX900-SDAG-NEXT: v_mov_b32_e32 v5, 0xc2ce8ed01781; GFX900-SDAG-NEXT: s_waitcnt lgkmcnt(0)1782; GFX900-SDAG-NEXT: v_mul_f32_e32 v2, s3, v01783; GFX900-SDAG-NEXT: v_rndne_f32_e32 v3, v21784; GFX900-SDAG-NEXT: v_fma_f32 v4, s3, v0, -v21785; GFX900-SDAG-NEXT: v_sub_f32_e32 v2, v2, v31786; GFX900-SDAG-NEXT: v_fma_f32 v4, s3, v1, v41787; GFX900-SDAG-NEXT: v_add_f32_e32 v2, v2, v41788; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v3, v31789; GFX900-SDAG-NEXT: v_exp_f32_e32 v2, v21790; GFX900-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s3, v51791; GFX900-SDAG-NEXT: v_mov_b32_e32 v6, 0x42b172181792; GFX900-SDAG-NEXT: v_mov_b32_e32 v9, 0x7f8000001793; GFX900-SDAG-NEXT: v_ldexp_f32 v2, v2, v31794; GFX900-SDAG-NEXT: v_mul_f32_e32 v3, s2, v01795; GFX900-SDAG-NEXT: v_rndne_f32_e32 v7, v31796; GFX900-SDAG-NEXT: v_sub_f32_e32 v8, v3, v71797; GFX900-SDAG-NEXT: v_fma_f32 v3, s2, v0, -v31798; GFX900-SDAG-NEXT: v_fma_f32 v3, s2, v1, v31799; GFX900-SDAG-NEXT: v_add_f32_e32 v3, v8, v31800; GFX900-SDAG-NEXT: v_exp_f32_e32 v8, v31801; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v7, v71802; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc1803; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s3, v61804; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v3, v9, v2, vcc1805; GFX900-SDAG-NEXT: v_ldexp_f32 v2, v8, v71806; GFX900-SDAG-NEXT: v_mul_f32_e32 v7, s1, v01807; GFX900-SDAG-NEXT: v_rndne_f32_e32 v8, v71808; GFX900-SDAG-NEXT: v_sub_f32_e32 v10, v7, v81809; GFX900-SDAG-NEXT: v_fma_f32 v7, s1, v0, -v71810; GFX900-SDAG-NEXT: v_fma_f32 v7, s1, v1, v71811; GFX900-SDAG-NEXT: v_add_f32_e32 v7, v10, v71812; GFX900-SDAG-NEXT: v_exp_f32_e32 v7, v71813; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v8, v81814; GFX900-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s2, v51815; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc1816; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s2, v61817; GFX900-SDAG-NEXT: v_ldexp_f32 v7, v7, v81818; GFX900-SDAG-NEXT: v_mul_f32_e32 v8, s0, v01819; GFX900-SDAG-NEXT: v_rndne_f32_e32 v10, v81820; GFX900-SDAG-NEXT: v_fma_f32 v0, s0, v0, -v81821; GFX900-SDAG-NEXT: v_sub_f32_e32 v11, v8, v101822; GFX900-SDAG-NEXT: v_fma_f32 v0, s0, v1, v01823; GFX900-SDAG-NEXT: v_add_f32_e32 v0, v11, v01824; GFX900-SDAG-NEXT: v_exp_f32_e32 v0, v01825; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v8, v101826; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v2, v9, v2, vcc1827; GFX900-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s1, v51828; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v7, vcc1829; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s1, v61830; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc1831; GFX900-SDAG-NEXT: v_ldexp_f32 v0, v0, v81832; GFX900-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s0, v51833; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc1834; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s0, v61835; GFX900-SDAG-NEXT: v_mov_b32_e32 v4, 01836; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v9, v0, vcc1837; GFX900-SDAG-NEXT: global_store_dwordx4 v4, v[0:3], s[6:7]1838; GFX900-SDAG-NEXT: s_endpgm1839;1840; GFX900-GISEL-LABEL: s_exp_v4f32:1841; GFX900-GISEL: ; %bb.0:1842; GFX900-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x341843; GFX900-GISEL-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x241844; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x3fb8aa3b1845; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x32a5705f1846; GFX900-GISEL-NEXT: v_mov_b32_e32 v5, 0x42b172181847; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0)1848; GFX900-GISEL-NEXT: v_mul_f32_e32 v0, s0, v21849; GFX900-GISEL-NEXT: v_fma_f32 v1, s0, v2, -v01850; GFX900-GISEL-NEXT: v_rndne_f32_e32 v4, v01851; GFX900-GISEL-NEXT: v_fma_f32 v1, s0, v3, v11852; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v41853; GFX900-GISEL-NEXT: v_add_f32_e32 v0, v0, v11854; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v1, v41855; GFX900-GISEL-NEXT: v_exp_f32_e32 v0, v01856; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0xc2ce8ed01857; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s0, v41858; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v11859; GFX900-GISEL-NEXT: v_mul_f32_e32 v1, s1, v21860; GFX900-GISEL-NEXT: v_fma_f32 v6, s1, v2, -v11861; GFX900-GISEL-NEXT: v_rndne_f32_e32 v7, v11862; GFX900-GISEL-NEXT: v_fma_f32 v6, s1, v3, v61863; GFX900-GISEL-NEXT: v_sub_f32_e32 v1, v1, v71864; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v1, v61865; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v6, v71866; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, v11867; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc1868; GFX900-GISEL-NEXT: v_mov_b32_e32 v7, 0x7f8000001869; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s0, v51870; GFX900-GISEL-NEXT: v_ldexp_f32 v1, v1, v61871; GFX900-GISEL-NEXT: v_mul_f32_e32 v6, s2, v21872; GFX900-GISEL-NEXT: v_fma_f32 v8, s2, v2, -v61873; GFX900-GISEL-NEXT: v_rndne_f32_e32 v9, v61874; GFX900-GISEL-NEXT: v_fma_f32 v8, s2, v3, v81875; GFX900-GISEL-NEXT: v_sub_f32_e32 v6, v6, v91876; GFX900-GISEL-NEXT: v_add_f32_e32 v6, v6, v81877; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v8, v91878; GFX900-GISEL-NEXT: v_exp_f32_e32 v6, v61879; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc1880; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s1, v41881; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc1882; GFX900-GISEL-NEXT: v_ldexp_f32 v6, v6, v81883; GFX900-GISEL-NEXT: v_mul_f32_e32 v8, s3, v21884; GFX900-GISEL-NEXT: v_fma_f32 v2, s3, v2, -v81885; GFX900-GISEL-NEXT: v_fma_f32 v2, s3, v3, v21886; GFX900-GISEL-NEXT: v_rndne_f32_e32 v3, v81887; GFX900-GISEL-NEXT: v_sub_f32_e32 v8, v8, v31888; GFX900-GISEL-NEXT: v_add_f32_e32 v2, v8, v21889; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v3, v31890; GFX900-GISEL-NEXT: v_exp_f32_e32 v8, v21891; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s1, v51892; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc1893; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v41894; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v2, v6, 0, vcc1895; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s2, v51896; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc1897; GFX900-GISEL-NEXT: v_ldexp_f32 v3, v8, v31898; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s3, v41899; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc1900; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s3, v51901; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc1902; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 01903; GFX900-GISEL-NEXT: global_store_dwordx4 v4, v[0:3], s[6:7]1904; GFX900-GISEL-NEXT: s_endpgm1905;1906; SI-SDAG-LABEL: s_exp_v4f32:1907; SI-SDAG: ; %bb.0:1908; SI-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xd1909; SI-SDAG-NEXT: v_mov_b32_e32 v0, 0x3fb8aa3b1910; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x32a5705f1911; SI-SDAG-NEXT: v_mov_b32_e32 v5, 0x42b172181912; SI-SDAG-NEXT: v_mov_b32_e32 v8, 0x7f8000001913; SI-SDAG-NEXT: s_waitcnt lgkmcnt(0)1914; SI-SDAG-NEXT: v_mul_f32_e32 v2, s3, v01915; SI-SDAG-NEXT: v_rndne_f32_e32 v3, v21916; SI-SDAG-NEXT: v_fma_f32 v4, s3, v0, -v21917; SI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v31918; SI-SDAG-NEXT: v_fma_f32 v4, s3, v1, v41919; SI-SDAG-NEXT: v_add_f32_e32 v2, v2, v41920; SI-SDAG-NEXT: v_exp_f32_e32 v2, v21921; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v3, v31922; SI-SDAG-NEXT: v_mov_b32_e32 v4, 0xc2ce8ed01923; SI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s3, v41924; SI-SDAG-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x91925; SI-SDAG-NEXT: v_ldexp_f32_e32 v2, v2, v31926; SI-SDAG-NEXT: v_mul_f32_e32 v3, s2, v01927; SI-SDAG-NEXT: v_rndne_f32_e32 v6, v31928; SI-SDAG-NEXT: v_sub_f32_e32 v7, v3, v61929; SI-SDAG-NEXT: v_fma_f32 v3, s2, v0, -v31930; SI-SDAG-NEXT: v_fma_f32 v3, s2, v1, v31931; SI-SDAG-NEXT: v_add_f32_e32 v3, v7, v31932; SI-SDAG-NEXT: v_exp_f32_e32 v7, v31933; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v6, v61934; SI-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc1935; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s3, v51936; SI-SDAG-NEXT: v_cndmask_b32_e32 v3, v8, v2, vcc1937; SI-SDAG-NEXT: v_ldexp_f32_e32 v2, v7, v61938; SI-SDAG-NEXT: v_mul_f32_e32 v6, s1, v01939; SI-SDAG-NEXT: v_rndne_f32_e32 v7, v61940; SI-SDAG-NEXT: v_sub_f32_e32 v9, v6, v71941; SI-SDAG-NEXT: v_fma_f32 v6, s1, v0, -v61942; SI-SDAG-NEXT: v_fma_f32 v6, s1, v1, v61943; SI-SDAG-NEXT: v_add_f32_e32 v6, v9, v61944; SI-SDAG-NEXT: v_exp_f32_e32 v6, v61945; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v7, v71946; SI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s2, v41947; SI-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc1948; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s2, v51949; SI-SDAG-NEXT: v_ldexp_f32_e32 v6, v6, v71950; SI-SDAG-NEXT: v_mul_f32_e32 v7, s0, v01951; SI-SDAG-NEXT: v_rndne_f32_e32 v9, v71952; SI-SDAG-NEXT: v_fma_f32 v0, s0, v0, -v71953; SI-SDAG-NEXT: v_sub_f32_e32 v10, v7, v91954; SI-SDAG-NEXT: v_fma_f32 v0, s0, v1, v01955; SI-SDAG-NEXT: v_add_f32_e32 v0, v10, v01956; SI-SDAG-NEXT: v_exp_f32_e32 v0, v01957; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v7, v91958; SI-SDAG-NEXT: v_cndmask_b32_e32 v2, v8, v2, vcc1959; SI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s1, v41960; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v6, vcc1961; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s1, v51962; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc1963; SI-SDAG-NEXT: v_ldexp_f32_e32 v0, v0, v71964; SI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s0, v41965; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc1966; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s0, v51967; SI-SDAG-NEXT: s_mov_b32 s7, 0xf0001968; SI-SDAG-NEXT: s_mov_b32 s6, -11969; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc1970; SI-SDAG-NEXT: s_waitcnt lgkmcnt(0)1971; SI-SDAG-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 01972; SI-SDAG-NEXT: s_endpgm1973;1974; SI-GISEL-LABEL: s_exp_v4f32:1975; SI-GISEL: ; %bb.0:1976; SI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xd1977; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x3fb8aa3b1978; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x32a5705f1979; SI-GISEL-NEXT: v_mov_b32_e32 v5, 0x42b172181980; SI-GISEL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x91981; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)1982; SI-GISEL-NEXT: v_mul_f32_e32 v0, s0, v21983; SI-GISEL-NEXT: v_fma_f32 v1, s0, v2, -v01984; SI-GISEL-NEXT: v_rndne_f32_e32 v4, v01985; SI-GISEL-NEXT: v_fma_f32 v1, s0, v3, v11986; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v41987; SI-GISEL-NEXT: v_add_f32_e32 v0, v0, v11988; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v1, v41989; SI-GISEL-NEXT: v_exp_f32_e32 v0, v01990; SI-GISEL-NEXT: v_mov_b32_e32 v4, 0xc2ce8ed01991; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s0, v41992; SI-GISEL-NEXT: s_mov_b32 s6, -11993; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v11994; SI-GISEL-NEXT: v_mul_f32_e32 v1, s1, v21995; SI-GISEL-NEXT: v_fma_f32 v6, s1, v2, -v11996; SI-GISEL-NEXT: v_rndne_f32_e32 v7, v11997; SI-GISEL-NEXT: v_fma_f32 v6, s1, v3, v61998; SI-GISEL-NEXT: v_sub_f32_e32 v1, v1, v71999; SI-GISEL-NEXT: v_add_f32_e32 v1, v1, v62000; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v6, v72001; SI-GISEL-NEXT: v_exp_f32_e32 v1, v12002; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc2003; SI-GISEL-NEXT: v_mov_b32_e32 v7, 0x7f8000002004; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s0, v52005; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, v1, v62006; SI-GISEL-NEXT: v_mul_f32_e32 v6, s2, v22007; SI-GISEL-NEXT: v_fma_f32 v8, s2, v2, -v62008; SI-GISEL-NEXT: v_rndne_f32_e32 v9, v62009; SI-GISEL-NEXT: v_fma_f32 v8, s2, v3, v82010; SI-GISEL-NEXT: v_sub_f32_e32 v6, v6, v92011; SI-GISEL-NEXT: v_add_f32_e32 v6, v6, v82012; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v8, v92013; SI-GISEL-NEXT: v_exp_f32_e32 v6, v62014; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc2015; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s1, v42016; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc2017; SI-GISEL-NEXT: v_ldexp_f32_e32 v6, v6, v82018; SI-GISEL-NEXT: v_mul_f32_e32 v8, s3, v22019; SI-GISEL-NEXT: v_fma_f32 v2, s3, v2, -v82020; SI-GISEL-NEXT: v_fma_f32 v2, s3, v3, v22021; SI-GISEL-NEXT: v_rndne_f32_e32 v3, v82022; SI-GISEL-NEXT: v_sub_f32_e32 v8, v8, v32023; SI-GISEL-NEXT: v_add_f32_e32 v2, v8, v22024; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v3, v32025; SI-GISEL-NEXT: v_exp_f32_e32 v8, v22026; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s1, v52027; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc2028; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v42029; SI-GISEL-NEXT: v_cndmask_b32_e64 v2, v6, 0, vcc2030; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s2, v52031; SI-GISEL-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc2032; SI-GISEL-NEXT: v_ldexp_f32_e32 v3, v8, v32033; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s3, v42034; SI-GISEL-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc2035; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s3, v52036; SI-GISEL-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc2037; SI-GISEL-NEXT: s_mov_b32 s7, 0xf0002038; SI-GISEL-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 02039; SI-GISEL-NEXT: s_endpgm2040;2041; R600-LABEL: s_exp_v4f32:2042; R600: ; %bb.0:2043; R600-NEXT: ALU 98, @6, KC0[CB0:0-32], KC1[]2044; R600-NEXT: ALU 95, @105, KC0[CB0:0-32], KC1[]2045; R600-NEXT: ALU 24, @201, KC0[CB0:0-32], KC1[]2046; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.XYZW, T0.X, 12047; R600-NEXT: CF_END2048; R600-NEXT: PAD2049; R600-NEXT: ALU clause starting at 6:2050; R600-NEXT: AND_INT * T0.W, KC0[3].Z, literal.x,2051; R600-NEXT: -4096(nan), 0(0.000000e+00)2052; R600-NEXT: ADD * T1.W, KC0[3].Z, -PV.W,2053; R600-NEXT: MUL_IEEE T2.W, PV.W, literal.x,2054; R600-NEXT: MUL_IEEE * T3.W, T0.W, literal.y,2055; R600-NEXT: 967029397(3.122284e-04), 1069064192(1.442383e+00)2056; R600-NEXT: RNDNE T4.W, PS,2057; R600-NEXT: MULADD_IEEE * T1.W, T1.W, literal.x, PV.W, BS:VEC_021/SCL_1222058; R600-NEXT: 1069064192(1.442383e+00), 0(0.000000e+00)2059; R600-NEXT: MULADD_IEEE T0.W, T0.W, literal.x, PS,2060; R600-NEXT: ADD * T1.W, T3.W, -PV.W,2061; R600-NEXT: 967029397(3.122284e-04), 0(0.000000e+00)2062; R600-NEXT: ADD T0.W, PS, PV.W,2063; R600-NEXT: TRUNC * T1.W, T4.W,2064; R600-NEXT: FLT_TO_INT T1.W, PS,2065; R600-NEXT: EXP_IEEE * T0.X, PV.W,2066; R600-NEXT: MUL_IEEE T0.Z, PS, literal.x,2067; R600-NEXT: MAX_INT T0.W, PV.W, literal.y,2068; R600-NEXT: MIN_INT * T2.W, PV.W, literal.z,2069; R600-NEXT: 209715200(1.972152e-31), -330(nan)2070; R600-NEXT: 381(5.338947e-43), 0(0.000000e+00)2071; R600-NEXT: ADD_INT T1.X, PS, literal.x,2072; R600-NEXT: AND_INT T0.Y, KC0[4].X, literal.y,2073; R600-NEXT: ADD_INT T1.Z, PV.W, literal.z,2074; R600-NEXT: ADD_INT * T0.W, T1.W, literal.w,2075; R600-NEXT: -254(nan), -4096(nan)2076; R600-NEXT: 204(2.858649e-43), 102(1.429324e-43)2077; R600-NEXT: SETGT_UINT * T2.W, T1.W, literal.x,2078; R600-NEXT: -229(nan), 0(0.000000e+00)2079; R600-NEXT: ADD_INT T2.X, T1.W, literal.x,2080; R600-NEXT: SETGT_UINT T1.Y, T1.W, literal.y,2081; R600-NEXT: CNDE_INT T1.Z, PV.W, T1.Z, T0.W,2082; R600-NEXT: SETGT_INT T0.W, T1.W, literal.x,2083; R600-NEXT: ADD * T3.W, KC0[4].X, -T0.Y,2084; R600-NEXT: -127(nan), 254(3.559298e-43)2085; R600-NEXT: MUL_IEEE T3.X, PS, literal.x,2086; R600-NEXT: MUL_IEEE T2.Y, T0.Y, literal.y,2087; R600-NEXT: CNDE_INT T1.Z, PV.W, PV.Z, T1.W,2088; R600-NEXT: CNDE_INT T4.W, PV.Y, PV.X, T1.X,2089; R600-NEXT: SETGT_INT * T1.W, T1.W, literal.z,2090; R600-NEXT: 967029397(3.122284e-04), 1069064192(1.442383e+00)2091; R600-NEXT: 127(1.779649e-43), 0(0.000000e+00)2092; R600-NEXT: CNDE_INT T1.X, PS, PV.Z, PV.W,2093; R600-NEXT: RNDNE T3.Y, PV.Y,2094; R600-NEXT: MULADD_IEEE T1.Z, T3.W, literal.x, PV.X,2095; R600-NEXT: MUL_IEEE T3.W, T0.Z, literal.y,2096; R600-NEXT: MUL_IEEE * T4.W, T0.X, literal.z,2097; R600-NEXT: 1069064192(1.442383e+00), 209715200(1.972152e-31)2098; R600-NEXT: 2130706432(1.701412e+38), 0(0.000000e+00)2099; R600-NEXT: MUL_IEEE T2.X, PS, literal.x,2100; R600-NEXT: CNDE_INT T4.Y, T2.W, PV.W, T0.Z,2101; R600-NEXT: MULADD_IEEE T0.Z, T0.Y, literal.y, PV.Z,2102; R600-NEXT: ADD T2.W, T2.Y, -PV.Y, BS:VEC_120/SCL_2122103; R600-NEXT: AND_INT * T3.W, KC0[3].Y, literal.z,2104; R600-NEXT: 2130706432(1.701412e+38), 967029397(3.122284e-04)2105; R600-NEXT: -4096(nan), 0(0.000000e+00)2106; R600-NEXT: MUL_IEEE T3.X, PS, literal.x,2107; R600-NEXT: ADD T0.Y, PV.W, PV.Z,2108; R600-NEXT: CNDE_INT T0.Z, T0.W, PV.Y, T0.X, BS:VEC_021/SCL_1222109; R600-NEXT: CNDE_INT T0.W, T1.Y, T4.W, PV.X,2110; R600-NEXT: LSHL * T2.W, T1.X, literal.y,2111; R600-NEXT: 1069064192(1.442383e+00), 23(3.222986e-44)2112; R600-NEXT: AND_INT T0.X, KC0[3].W, literal.x,2113; R600-NEXT: TRUNC T1.Y, T3.Y,2114; R600-NEXT: ADD_INT T1.Z, PS, literal.y,2115; R600-NEXT: CNDE_INT T0.W, T1.W, PV.Z, PV.W,2116; R600-NEXT: EXP_IEEE * T0.Y, PV.Y,2117; R600-NEXT: -4096(nan), 1065353216(1.000000e+00)2118; R600-NEXT: MUL_IEEE T1.X, PV.W, PV.Z,2119; R600-NEXT: FLT_TO_INT T1.Y, PV.Y,2120; R600-NEXT: MUL_IEEE T0.Z, PS, literal.x,2121; R600-NEXT: ADD T0.W, KC0[3].W, -PV.X,2122; R600-NEXT: RNDNE * T1.W, T3.X,2123; R600-NEXT: 209715200(1.972152e-31), 0(0.000000e+00)2124; R600-NEXT: SETGT T2.X, literal.x, KC0[3].Z,2125; R600-NEXT: TRUNC T2.Y, PS,2126; R600-NEXT: MUL_IEEE T1.Z, PV.W, literal.y,2127; R600-NEXT: MUL_IEEE T2.W, PV.Z, literal.z,2128; R600-NEXT: MAX_INT * T4.W, PV.Y, literal.w,2129; R600-NEXT: -1026650416(-1.032789e+02), 967029397(3.122284e-04)2130; R600-NEXT: 209715200(1.972152e-31), -330(nan)2131; R600-NEXT: ADD T4.X, KC0[3].Y, -T3.W,2132; R600-NEXT: ADD_INT T3.Y, PS, literal.x,2133; R600-NEXT: ADD_INT T2.Z, T1.Y, literal.y,2134; R600-NEXT: SETGT_UINT T4.W, T1.Y, literal.z,2135; R600-NEXT: MIN_INT * T5.W, T1.Y, literal.w,2136; R600-NEXT: 204(2.858649e-43), 102(1.429324e-43)2137; R600-NEXT: -229(nan), 381(5.338947e-43)2138; R600-NEXT: ADD_INT T5.X, PS, literal.x,2139; R600-NEXT: ADD_INT T4.Y, T1.Y, literal.y,2140; R600-NEXT: SETGT_UINT T3.Z, T1.Y, literal.z,2141; R600-NEXT: CNDE_INT T5.W, PV.W, PV.Y, PV.Z,2142; R600-NEXT: SETGT_INT * T6.W, T1.Y, literal.y,2143; R600-NEXT: -254(nan), -127(nan)2144; R600-NEXT: 254(3.559298e-43), 0(0.000000e+00)2145; R600-NEXT: MUL_IEEE T6.X, T0.Y, literal.x,2146; R600-NEXT: CNDE_INT T3.Y, PS, PV.W, T1.Y,2147; R600-NEXT: CNDE_INT * T2.Z, PV.Z, PV.Y, PV.X,2148; R600-NEXT: 2130706432(1.701412e+38), 0(0.000000e+00)2149; R600-NEXT: ALU clause starting at 105:2150; R600-NEXT: SETGT_INT T5.W, T1.Y, literal.x,2151; R600-NEXT: MUL_IEEE * T7.W, T4.X, literal.y,2152; R600-NEXT: 127(1.779649e-43), 967029397(3.122284e-04)2153; R600-NEXT: MUL_IEEE T5.X, T0.X, literal.x,2154; R600-NEXT: MULADD_IEEE T1.Y, T4.X, literal.x, PS, BS:VEC_120/SCL_2122155; R600-NEXT: CNDE_INT T2.Z, PV.W, T3.Y, T2.Z,2156; R600-NEXT: MUL_IEEE T7.W, T6.X, literal.y, BS:VEC_2012157; R600-NEXT: CNDE_INT * T2.W, T4.W, T2.W, T0.Z,2158; R600-NEXT: 1069064192(1.442383e+00), 2130706432(1.701412e+38)2159; R600-NEXT: CNDE_INT T4.X, T6.W, PS, T0.Y,2160; R600-NEXT: CNDE_INT T0.Y, T3.Z, T6.X, PV.W,2161; R600-NEXT: LSHL T0.Z, PV.Z, literal.x,2162; R600-NEXT: MULADD_IEEE T2.W, T3.W, literal.y, PV.Y, BS:VEC_2012163; R600-NEXT: ADD * T1.W, T3.X, -T1.W,2164; R600-NEXT: 23(3.222986e-44), 967029397(3.122284e-04)2165; R600-NEXT: ADD T3.X, PS, PV.W,2166; R600-NEXT: ADD_INT T1.Y, PV.Z, literal.x,2167; R600-NEXT: CNDE_INT T0.Z, T5.W, PV.X, PV.Y,2168; R600-NEXT: RNDNE T1.W, T5.X,2169; R600-NEXT: MULADD_IEEE * T0.W, T0.W, literal.y, T1.Z, BS:VEC_021/SCL_1222170; R600-NEXT: 1065353216(1.000000e+00), 1069064192(1.442383e+00)2171; R600-NEXT: MULADD_IEEE T0.X, T0.X, literal.x, PS,2172; R600-NEXT: ADD T0.Y, T5.X, -PV.W, BS:VEC_120/SCL_2122173; R600-NEXT: MUL_IEEE T0.Z, PV.Z, PV.Y,2174; R600-NEXT: SETGT T0.W, literal.y, KC0[4].X,2175; R600-NEXT: EXP_IEEE * T1.Y, PV.X,2176; R600-NEXT: 967029397(3.122284e-04), -1026650416(-1.032789e+02)2177; R600-NEXT: CNDE T3.X, PV.W, PV.Z, 0.0,2178; R600-NEXT: ADD T0.Y, PV.Y, PV.X,2179; R600-NEXT: FLT_TO_INT T0.Z, T2.Y,2180; R600-NEXT: TRUNC T0.W, T1.W,2181; R600-NEXT: MUL_IEEE * T1.W, PS, literal.x,2182; R600-NEXT: 209715200(1.972152e-31), 0(0.000000e+00)2183; R600-NEXT: SETGT T0.X, KC0[4].X, literal.x,2184; R600-NEXT: MUL_IEEE T2.Y, PS, literal.y,2185; R600-NEXT: FLT_TO_INT T1.Z, PV.W,2186; R600-NEXT: MAX_INT T0.W, PV.Z, literal.z,2187; R600-NEXT: EXP_IEEE * T0.Y, PV.Y,2188; R600-NEXT: 1118925336(8.872284e+01), 209715200(1.972152e-31)2189; R600-NEXT: -330(nan), 0(0.000000e+00)2190; R600-NEXT: MUL_IEEE T4.X, T1.Y, literal.x,2191; R600-NEXT: MUL_IEEE T3.Y, PS, literal.y,2192; R600-NEXT: ADD_INT T2.Z, PV.W, literal.z,2193; R600-NEXT: ADD_INT * T0.W, T0.Z, literal.w,2194; R600-NEXT: 2130706432(1.701412e+38), 209715200(1.972152e-31)2195; R600-NEXT: 204(2.858649e-43), 102(1.429324e-43)2196; R600-NEXT: MAX_INT * T2.W, T1.Z, literal.x,2197; R600-NEXT: -330(nan), 0(0.000000e+00)2198; R600-NEXT: SETGT_UINT T5.X, T0.Z, literal.x,2199; R600-NEXT: ADD_INT T4.Y, PV.W, literal.y,2200; R600-NEXT: ADD_INT T3.Z, T1.Z, literal.z, BS:VEC_120/SCL_2122201; R600-NEXT: SETGT_UINT T2.W, T1.Z, literal.x, BS:VEC_120/SCL_2122202; R600-NEXT: MIN_INT * T3.W, T1.Z, literal.w,2203; R600-NEXT: -229(nan), 204(2.858649e-43)2204; R600-NEXT: 102(1.429324e-43), 381(5.338947e-43)2205; R600-NEXT: ADD_INT T6.X, PS, literal.x,2206; R600-NEXT: ADD_INT T5.Y, T1.Z, literal.y,2207; R600-NEXT: SETGT_UINT T4.Z, T1.Z, literal.z,2208; R600-NEXT: CNDE_INT T3.W, PV.W, PV.Y, PV.Z,2209; R600-NEXT: SETGT_INT * T4.W, T1.Z, literal.y,2210; R600-NEXT: -254(nan), -127(nan)2211; R600-NEXT: 254(3.559298e-43), 0(0.000000e+00)2212; R600-NEXT: CNDE_INT T7.X, PS, PV.W, T1.Z, BS:VEC_021/SCL_1222213; R600-NEXT: CNDE_INT T4.Y, PV.Z, PV.Y, PV.X,2214; R600-NEXT: SETGT_INT T1.Z, T1.Z, literal.x, BS:VEC_120/SCL_2122215; R600-NEXT: CNDE_INT T0.W, T5.X, T2.Z, T0.W, BS:VEC_102/SCL_2212216; R600-NEXT: SETGT_INT * T3.W, T0.Z, literal.y,2217; R600-NEXT: 127(1.779649e-43), -127(nan)2218; R600-NEXT: CNDE_INT T6.X, PS, PV.W, T0.Z,2219; R600-NEXT: CNDE_INT T4.Y, PV.Z, PV.X, PV.Y,2220; R600-NEXT: MIN_INT T2.Z, T0.Z, literal.x,2221; R600-NEXT: MUL_IEEE T0.W, T3.Y, literal.y,2222; R600-NEXT: MUL_IEEE * T5.W, T0.Y, literal.z,2223; R600-NEXT: 381(5.338947e-43), 209715200(1.972152e-31)2224; R600-NEXT: 2130706432(1.701412e+38), 0(0.000000e+00)2225; R600-NEXT: MUL_IEEE T7.X, PS, literal.x,2226; R600-NEXT: CNDE_INT T3.Y, T2.W, PV.W, T3.Y,2227; R600-NEXT: ADD_INT T2.Z, PV.Z, literal.y,2228; R600-NEXT: ADD_INT T0.W, T0.Z, literal.z,2229; R600-NEXT: SETGT_UINT * T2.W, T0.Z, literal.w,2230; R600-NEXT: 2130706432(1.701412e+38), -254(nan)2231; R600-NEXT: -127(nan), 254(3.559298e-43)2232; R600-NEXT: CNDE_INT T8.X, PS, PV.W, PV.Z,2233; R600-NEXT: SETGT_INT T5.Y, T0.Z, literal.x,2234; R600-NEXT: CNDE_INT T0.Z, T4.W, PV.Y, T0.Y, BS:VEC_021/SCL_1222235; R600-NEXT: CNDE_INT T0.W, T4.Z, T5.W, PV.X, BS:VEC_120/SCL_2122236; R600-NEXT: LSHL * T4.W, T4.Y, literal.y,2237; R600-NEXT: 127(1.779649e-43), 23(3.222986e-44)2238; R600-NEXT: ADD_INT T7.X, PS, literal.x,2239; R600-NEXT: CNDE_INT T0.Y, T1.Z, PV.Z, PV.W,2240; R600-NEXT: CNDE_INT T0.Z, PV.Y, T6.X, PV.X,2241; R600-NEXT: MUL_IEEE T0.W, T4.X, literal.y,2242; R600-NEXT: CNDE_INT * T1.W, T5.X, T2.Y, T1.W,2243; R600-NEXT: 1065353216(1.000000e+00), 2130706432(1.701412e+38)2244; R600-NEXT: CNDE_INT T5.X, T3.W, PS, T1.Y,2245; R600-NEXT: CNDE_INT * T1.Y, T2.W, T4.X, PV.W, BS:VEC_120/SCL_2122246; R600-NEXT: ALU clause starting at 201:2247; R600-NEXT: LSHL T0.Z, T0.Z, literal.x,2248; R600-NEXT: MUL_IEEE T0.W, T0.Y, T7.X,2249; R600-NEXT: SETGT * T1.W, literal.y, KC0[3].W,2250; R600-NEXT: 23(3.222986e-44), -1026650416(-1.032789e+02)2251; R600-NEXT: CNDE T4.X, PS, PV.W, 0.0,2252; R600-NEXT: SETGT T0.Y, KC0[3].W, literal.x,2253; R600-NEXT: ADD_INT T0.Z, PV.Z, literal.y,2254; R600-NEXT: CNDE_INT T0.W, T5.Y, T5.X, T1.Y, BS:VEC_102/SCL_2212255; R600-NEXT: CNDE * T1.W, T0.X, T3.X, literal.z,2256; R600-NEXT: 1118925336(8.872284e+01), 1065353216(1.000000e+00)2257; R600-NEXT: 2139095040(INF), 0(0.000000e+00)2258; R600-NEXT: MUL_IEEE T0.X, PV.W, PV.Z,2259; R600-NEXT: SETGT T2.Y, literal.x, KC0[3].Y,2260; R600-NEXT: CNDE T1.Z, PV.Y, PV.X, literal.y,2261; R600-NEXT: CNDE T0.W, T2.X, T1.X, 0.0,2262; R600-NEXT: SETGT * T2.W, KC0[3].Z, literal.z,2263; R600-NEXT: -1026650416(-1.032789e+02), 2139095040(INF)2264; R600-NEXT: 1118925336(8.872284e+01), 0(0.000000e+00)2265; R600-NEXT: CNDE T1.Y, PS, PV.W, literal.x,2266; R600-NEXT: CNDE T0.W, PV.Y, PV.X, 0.0,2267; R600-NEXT: SETGT * T2.W, KC0[3].Y, literal.y,2268; R600-NEXT: 2139095040(INF), 1118925336(8.872284e+01)2269; R600-NEXT: CNDE T1.X, PS, PV.W, literal.x,2270; R600-NEXT: LSHR * T0.X, KC0[2].Y, literal.y,2271; R600-NEXT: 2139095040(INF), 2(2.802597e-45)2272;2273; CM-LABEL: s_exp_v4f32:2274; CM: ; %bb.0:2275; CM-NEXT: ALU 97, @6, KC0[CB0:0-32], KC1[]2276; CM-NEXT: ALU 97, @104, KC0[CB0:0-32], KC1[]2277; CM-NEXT: ALU 35, @202, KC0[CB0:0-32], KC1[]2278; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0, T1.X2279; CM-NEXT: CF_END2280; CM-NEXT: PAD2281; CM-NEXT: ALU clause starting at 6:2282; CM-NEXT: AND_INT * T0.W, KC0[3].Y, literal.x,2283; CM-NEXT: -4096(nan), 0(0.000000e+00)2284; CM-NEXT: ADD * T1.W, KC0[3].Y, -PV.W,2285; CM-NEXT: MUL_IEEE T0.Y, PV.W, literal.x,2286; CM-NEXT: MUL_IEEE T0.Z, T0.W, literal.y,2287; CM-NEXT: AND_INT * T2.W, KC0[3].W, literal.z,2288; CM-NEXT: 967029397(3.122284e-04), 1069064192(1.442383e+00)2289; CM-NEXT: -4096(nan), 0(0.000000e+00)2290; CM-NEXT: ADD T1.Y, KC0[3].W, -PV.W,2291; CM-NEXT: RNDNE T1.Z, PV.Z,2292; CM-NEXT: MULADD_IEEE * T1.W, T1.W, literal.x, PV.Y,2293; CM-NEXT: 1069064192(1.442383e+00), 0(0.000000e+00)2294; CM-NEXT: MULADD_IEEE T0.X, T0.W, literal.x, PV.W,2295; CM-NEXT: ADD T0.Y, T0.Z, -PV.Z,2296; CM-NEXT: MUL_IEEE T0.Z, T2.W, literal.y, BS:VEC_120/SCL_2122297; CM-NEXT: MUL_IEEE * T0.W, PV.Y, literal.x,2298; CM-NEXT: 967029397(3.122284e-04), 1069064192(1.442383e+00)2299; CM-NEXT: TRUNC T1.X, T1.Z,2300; CM-NEXT: MULADD_IEEE T1.Y, T1.Y, literal.x, PV.W,2301; CM-NEXT: RNDNE T1.Z, PV.Z,2302; CM-NEXT: ADD * T0.W, PV.Y, PV.X,2303; CM-NEXT: 1069064192(1.442383e+00), 0(0.000000e+00)2304; CM-NEXT: EXP_IEEE T0.X, T0.W,2305; CM-NEXT: EXP_IEEE T0.Y (MASKED), T0.W,2306; CM-NEXT: EXP_IEEE T0.Z (MASKED), T0.W,2307; CM-NEXT: EXP_IEEE * T0.W (MASKED), T0.W,2308; CM-NEXT: TRUNC T2.X, T1.Z,2309; CM-NEXT: MULADD_IEEE T0.Y, T2.W, literal.x, T1.Y,2310; CM-NEXT: FLT_TO_INT T2.Z, T1.X,2311; CM-NEXT: MUL_IEEE * T0.W, PV.X, literal.y,2312; CM-NEXT: 967029397(3.122284e-04), 209715200(1.972152e-31)2313; CM-NEXT: ADD T1.X, T0.Z, -T1.Z,2314; CM-NEXT: MUL_IEEE T1.Y, PV.W, literal.x,2315; CM-NEXT: MAX_INT T0.Z, PV.Z, literal.y,2316; CM-NEXT: MIN_INT * T1.W, PV.Z, literal.z,2317; CM-NEXT: 209715200(1.972152e-31), -330(nan)2318; CM-NEXT: 381(5.338947e-43), 0(0.000000e+00)2319; CM-NEXT: ADD_INT T3.X, PV.W, literal.x,2320; CM-NEXT: ADD_INT T2.Y, PV.Z, literal.y,2321; CM-NEXT: ADD_INT T0.Z, T2.Z, literal.z,2322; CM-NEXT: SETGT_UINT * T1.W, T2.Z, literal.w,2323; CM-NEXT: -254(nan), 204(2.858649e-43)2324; CM-NEXT: 102(1.429324e-43), -229(nan)2325; CM-NEXT: ADD_INT T4.X, T2.Z, literal.x,2326; CM-NEXT: SETGT_UINT T3.Y, T2.Z, literal.y,2327; CM-NEXT: CNDE_INT T0.Z, PV.W, PV.Y, PV.Z,2328; CM-NEXT: SETGT_INT * T2.W, T2.Z, literal.x,2329; CM-NEXT: -127(nan), 254(3.559298e-43)2330; CM-NEXT: MUL_IEEE T5.X, T0.X, literal.x,2331; CM-NEXT: CNDE_INT T2.Y, PV.W, PV.Z, T2.Z,2332; CM-NEXT: CNDE_INT T0.Z, PV.Y, PV.X, T3.X,2333; CM-NEXT: SETGT_INT * T3.W, T2.Z, literal.y,2334; CM-NEXT: 2130706432(1.701412e+38), 127(1.779649e-43)2335; CM-NEXT: AND_INT T3.X, KC0[3].Z, literal.x,2336; CM-NEXT: CNDE_INT T2.Y, PV.W, PV.Y, PV.Z,2337; CM-NEXT: MUL_IEEE T0.Z, PV.X, literal.y,2338; CM-NEXT: CNDE_INT * T0.W, T1.W, T1.Y, T0.W,2339; CM-NEXT: -4096(nan), 2130706432(1.701412e+38)2340; CM-NEXT: CNDE_INT T0.X, T2.W, PV.W, T0.X,2341; CM-NEXT: CNDE_INT T1.Y, T3.Y, T5.X, PV.Z,2342; CM-NEXT: LSHL T0.Z, PV.Y, literal.x,2343; CM-NEXT: MUL_IEEE * T0.W, PV.X, literal.y,2344; CM-NEXT: 23(3.222986e-44), 1069064192(1.442383e+00)2345; CM-NEXT: RNDNE T4.X, PV.W,2346; CM-NEXT: ADD_INT T2.Y, PV.Z, literal.x,2347; CM-NEXT: CNDE_INT T0.Z, T3.W, PV.X, PV.Y,2348; CM-NEXT: ADD * T1.W, T1.X, T0.Y,2349; CM-NEXT: 1065353216(1.000000e+00), 0(0.000000e+00)2350; CM-NEXT: EXP_IEEE T0.X, T1.W,2351; CM-NEXT: EXP_IEEE T0.Y (MASKED), T1.W,2352; CM-NEXT: EXP_IEEE T0.Z (MASKED), T1.W,2353; CM-NEXT: EXP_IEEE * T0.W (MASKED), T1.W,2354; CM-NEXT: MUL_IEEE T1.X, T0.Z, T2.Y,2355; CM-NEXT: TRUNC T0.Y, T4.X,2356; CM-NEXT: FLT_TO_INT T0.Z, T2.X, BS:VEC_120/SCL_2122357; CM-NEXT: MUL_IEEE * T1.W, PV.X, literal.x,2358; CM-NEXT: 209715200(1.972152e-31), 0(0.000000e+00)2359; CM-NEXT: MUL_IEEE T2.X, PV.W, literal.x,2360; CM-NEXT: MUL_IEEE T1.Y, T0.X, literal.y,2361; CM-NEXT: MAX_INT T1.Z, PV.Z, literal.z,2362; CM-NEXT: MIN_INT * T2.W, PV.Z, literal.w,2363; CM-NEXT: 209715200(1.972152e-31), 2130706432(1.701412e+38)2364; CM-NEXT: -330(nan), 381(5.338947e-43)2365; CM-NEXT: ADD_INT T5.X, PV.W, literal.x,2366; CM-NEXT: ADD_INT T2.Y, PV.Z, literal.y,2367; CM-NEXT: ADD_INT T1.Z, T0.Z, literal.z,2368; CM-NEXT: SETGT_UINT * T2.W, T0.Z, literal.w,2369; CM-NEXT: -254(nan), 204(2.858649e-43)2370; CM-NEXT: 102(1.429324e-43), -229(nan)2371; CM-NEXT: ADD_INT T6.X, T0.Z, literal.x,2372; CM-NEXT: SETGT_UINT T3.Y, T0.Z, literal.y,2373; CM-NEXT: CNDE_INT T1.Z, PV.W, PV.Y, PV.Z,2374; CM-NEXT: SETGT_INT * T3.W, T0.Z, literal.x,2375; CM-NEXT: -127(nan), 254(3.559298e-43)2376; CM-NEXT: CNDE_INT T7.X, PV.W, PV.Z, T0.Z,2377; CM-NEXT: CNDE_INT T2.Y, PV.Y, PV.X, T5.X,2378; CM-NEXT: SETGT_INT * T0.Z, T0.Z, literal.x,2379; CM-NEXT: 127(1.779649e-43), 0(0.000000e+00)2380; CM-NEXT: ALU clause starting at 104:2381; CM-NEXT: ADD * T4.W, KC0[3].Z, -T3.X,2382; CM-NEXT: MUL_IEEE T5.X, PV.W, literal.x,2383; CM-NEXT: CNDE_INT T2.Y, T0.Z, T7.X, T2.Y,2384; CM-NEXT: MUL_IEEE T1.Z, T1.Y, literal.y,2385; CM-NEXT: CNDE_INT * T1.W, T2.W, T2.X, T1.W, BS:VEC_021/SCL_1222386; CM-NEXT: 967029397(3.122284e-04), 2130706432(1.701412e+38)2387; CM-NEXT: CNDE_INT T0.X, T3.W, PV.W, T0.X,2388; CM-NEXT: CNDE_INT T1.Y, T3.Y, T1.Y, PV.Z,2389; CM-NEXT: LSHL T1.Z, PV.Y, literal.x,2390; CM-NEXT: MULADD_IEEE * T1.W, T4.W, literal.y, PV.X, BS:VEC_120/SCL_2122391; CM-NEXT: 23(3.222986e-44), 1069064192(1.442383e+00)2392; CM-NEXT: MULADD_IEEE T2.X, T3.X, literal.x, PV.W,2393; CM-NEXT: ADD T2.Y, T0.W, -T4.X,2394; CM-NEXT: ADD_INT T1.Z, PV.Z, literal.y,2395; CM-NEXT: CNDE_INT * T0.W, T0.Z, PV.X, PV.Y,2396; CM-NEXT: 967029397(3.122284e-04), 1065353216(1.000000e+00)2397; CM-NEXT: AND_INT T0.X, KC0[4].X, literal.x,2398; CM-NEXT: MUL_IEEE T1.Y, PV.W, PV.Z,2399; CM-NEXT: SETGT T0.Z, literal.y, KC0[3].W,2400; CM-NEXT: ADD * T0.W, PV.Y, PV.X,2401; CM-NEXT: -4096(nan), -1026650416(-1.032789e+02)2402; CM-NEXT: EXP_IEEE T0.X (MASKED), T0.W,2403; CM-NEXT: EXP_IEEE T0.Y (MASKED), T0.W,2404; CM-NEXT: EXP_IEEE T0.Z (MASKED), T0.W,2405; CM-NEXT: EXP_IEEE * T0.W, T0.W,2406; CM-NEXT: CNDE T2.X, T0.Z, T1.Y, 0.0,2407; CM-NEXT: ADD T1.Y, KC0[4].X, -T0.X,2408; CM-NEXT: FLT_TO_INT T0.Z, T0.Y,2409; CM-NEXT: MUL_IEEE * T1.W, PV.W, literal.x,2410; CM-NEXT: 209715200(1.972152e-31), 0(0.000000e+00)2411; CM-NEXT: MUL_IEEE T3.X, PV.W, literal.x,2412; CM-NEXT: SETGT_UINT T0.Y, PV.Z, literal.y,2413; CM-NEXT: MUL_IEEE T1.Z, PV.Y, literal.z,2414; CM-NEXT: MUL_IEEE * T2.W, T0.X, literal.w,2415; CM-NEXT: 209715200(1.972152e-31), -229(nan)2416; CM-NEXT: 967029397(3.122284e-04), 1069064192(1.442383e+00)2417; CM-NEXT: RNDNE T4.X, PV.W,2418; CM-NEXT: MULADD_IEEE T1.Y, T1.Y, literal.x, PV.Z,2419; CM-NEXT: CNDE_INT T1.Z, PV.Y, PV.X, T1.W,2420; CM-NEXT: SETGT_INT * T1.W, T0.Z, literal.y,2421; CM-NEXT: 1069064192(1.442383e+00), -127(nan)2422; CM-NEXT: CNDE_INT T3.X, PV.W, PV.Z, T0.W,2423; CM-NEXT: MULADD_IEEE T1.Y, T0.X, literal.x, PV.Y,2424; CM-NEXT: ADD T1.Z, T2.W, -PV.X,2425; CM-NEXT: MAX_INT * T2.W, T0.Z, literal.y,2426; CM-NEXT: 967029397(3.122284e-04), -330(nan)2427; CM-NEXT: ADD_INT T0.X, PV.W, literal.x,2428; CM-NEXT: ADD_INT T2.Y, T0.Z, literal.y,2429; CM-NEXT: TRUNC T2.Z, T4.X,2430; CM-NEXT: ADD * T2.W, PV.Z, PV.Y,2431; CM-NEXT: 204(2.858649e-43), 102(1.429324e-43)2432; CM-NEXT: EXP_IEEE T1.X (MASKED), T2.W,2433; CM-NEXT: EXP_IEEE T1.Y, T2.W,2434; CM-NEXT: EXP_IEEE T1.Z (MASKED), T2.W,2435; CM-NEXT: EXP_IEEE * T1.W (MASKED), T2.W,2436; CM-NEXT: MUL_IEEE T4.X, T0.W, literal.x,2437; CM-NEXT: FLT_TO_INT T3.Y, T2.Z,2438; CM-NEXT: MUL_IEEE T1.Z, PV.Y, literal.y,2439; CM-NEXT: CNDE_INT * T0.W, T0.Y, T0.X, T2.Y,2440; CM-NEXT: 2130706432(1.701412e+38), 209715200(1.972152e-31)2441; CM-NEXT: CNDE_INT T0.X, T1.W, PV.W, T0.Z,2442; CM-NEXT: MUL_IEEE T0.Y, PV.Z, literal.x,2443; CM-NEXT: MAX_INT T2.Z, PV.Y, literal.y,2444; CM-NEXT: MIN_INT * T0.W, PV.Y, literal.z,2445; CM-NEXT: 209715200(1.972152e-31), -330(nan)2446; CM-NEXT: 381(5.338947e-43), 0(0.000000e+00)2447; CM-NEXT: ADD_INT T5.X, PV.W, literal.x,2448; CM-NEXT: ADD_INT T2.Y, PV.Z, literal.y,2449; CM-NEXT: ADD_INT T2.Z, T3.Y, literal.z,2450; CM-NEXT: SETGT_UINT * T0.W, T3.Y, literal.w,2451; CM-NEXT: -254(nan), 204(2.858649e-43)2452; CM-NEXT: 102(1.429324e-43), -229(nan)2453; CM-NEXT: ADD_INT T6.X, T3.Y, literal.x,2454; CM-NEXT: SETGT_UINT T4.Y, T3.Y, literal.y,2455; CM-NEXT: CNDE_INT T2.Z, PV.W, PV.Y, PV.Z,2456; CM-NEXT: SETGT_INT * T1.W, T3.Y, literal.x,2457; CM-NEXT: -127(nan), 254(3.559298e-43)2458; CM-NEXT: MUL_IEEE T7.X, T1.Y, literal.x,2459; CM-NEXT: CNDE_INT T2.Y, PV.W, PV.Z, T3.Y,2460; CM-NEXT: CNDE_INT T2.Z, PV.Y, PV.X, T5.X,2461; CM-NEXT: MIN_INT * T2.W, T0.Z, literal.y,2462; CM-NEXT: 2130706432(1.701412e+38), 381(5.338947e-43)2463; CM-NEXT: SETGT_INT T5.X, T3.Y, literal.x,2464; CM-NEXT: ADD_INT T3.Y, PV.W, literal.y,2465; CM-NEXT: ADD_INT T3.Z, T0.Z, literal.z,2466; CM-NEXT: SETGT_UINT * T2.W, T0.Z, literal.w,2467; CM-NEXT: 127(1.779649e-43), -254(nan)2468; CM-NEXT: -127(nan), 254(3.559298e-43)2469; CM-NEXT: CNDE_INT T6.X, PV.W, PV.Z, PV.Y,2470; CM-NEXT: CNDE_INT T2.Y, PV.X, T2.Y, T2.Z,2471; CM-NEXT: MUL_IEEE T2.Z, T7.X, literal.x,2472; CM-NEXT: CNDE_INT * T0.W, T0.W, T0.Y, T1.Z, BS:VEC_021/SCL_1222473; CM-NEXT: 2130706432(1.701412e+38), 0(0.000000e+00)2474; CM-NEXT: SETGT_INT T8.X, T0.Z, literal.x,2475; CM-NEXT: CNDE_INT T0.Y, T1.W, PV.W, T1.Y,2476; CM-NEXT: CNDE_INT T0.Z, T4.Y, T7.X, PV.Z,2477; CM-NEXT: LSHL * T0.W, PV.Y, literal.y,2478; CM-NEXT: 127(1.779649e-43), 23(3.222986e-44)2479; CM-NEXT: ALU clause starting at 202:2480; CM-NEXT: ADD_INT T7.X, T0.W, literal.x,2481; CM-NEXT: CNDE_INT * T0.Y, T5.X, T0.Y, T0.Z,2482; CM-NEXT: 1065353216(1.000000e+00), 0(0.000000e+00)2483; CM-NEXT: CNDE_INT * T0.Z, T8.X, T0.X, T6.X,2484; CM-NEXT: MUL_IEEE * T0.W, T4.X, literal.x,2485; CM-NEXT: 2130706432(1.701412e+38), 0(0.000000e+00)2486; CM-NEXT: CNDE_INT T0.X, T2.W, T4.X, PV.W,2487; CM-NEXT: LSHL T1.Y, T0.Z, literal.x,2488; CM-NEXT: MUL_IEEE T0.Z, T0.Y, T7.X, BS:VEC_021/SCL_1222489; CM-NEXT: SETGT * T0.W, literal.y, KC0[4].X,2490; CM-NEXT: 23(3.222986e-44), -1026650416(-1.032789e+02)2491; CM-NEXT: CNDE T4.X, PV.W, PV.Z, 0.0,2492; CM-NEXT: SETGT T0.Y, KC0[4].X, literal.x,2493; CM-NEXT: ADD_INT T0.Z, PV.Y, literal.y,2494; CM-NEXT: CNDE_INT * T0.W, T8.X, T3.X, PV.X,2495; CM-NEXT: 1118925336(8.872284e+01), 1065353216(1.000000e+00)2496; CM-NEXT: SETGT T0.X, KC0[3].W, literal.x,2497; CM-NEXT: MUL_IEEE T1.Y, PV.W, PV.Z,2498; CM-NEXT: SETGT T0.Z, literal.y, KC0[3].Z,2499; CM-NEXT: CNDE * T0.W, PV.Y, PV.X, literal.z,2500; CM-NEXT: 1118925336(8.872284e+01), -1026650416(-1.032789e+02)2501; CM-NEXT: 2139095040(INF), 0(0.000000e+00)2502; CM-NEXT: SETGT T3.X, literal.x, KC0[3].Y,2503; CM-NEXT: CNDE T0.Y, PV.Z, PV.Y, 0.0,2504; CM-NEXT: CNDE T0.Z, PV.X, T2.X, literal.y,2505; CM-NEXT: SETGT * T1.W, KC0[3].Z, literal.z,2506; CM-NEXT: -1026650416(-1.032789e+02), 2139095040(INF)2507; CM-NEXT: 1118925336(8.872284e+01), 0(0.000000e+00)2508; CM-NEXT: CNDE T0.Y, PV.W, PV.Y, literal.x,2509; CM-NEXT: CNDE T1.Z, PV.X, T1.X, 0.0,2510; CM-NEXT: SETGT * T1.W, KC0[3].Y, literal.y,2511; CM-NEXT: 2139095040(INF), 1118925336(8.872284e+01)2512; CM-NEXT: CNDE * T0.X, PV.W, PV.Z, literal.x,2513; CM-NEXT: 2139095040(INF), 0(0.000000e+00)2514; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,2515; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)2516 %result = call <4 x float> @llvm.exp.v4f32(<4 x float> %in)2517 store <4 x float> %result, ptr addrspace(1) %out2518 ret void2519}2520 2521define float @v_exp_f32(float %in) {2522; VI-SDAG-LABEL: v_exp_f32:2523; VI-SDAG: ; %bb.0:2524; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2525; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v02526; VI-SDAG-NEXT: v_sub_f32_e32 v4, v0, v12527; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v12528; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x39a3b295, v42529; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x3fb8a000, v42530; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v22531; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v52532; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v12533; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v32534; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v42535; VI-SDAG-NEXT: v_add_f32_e32 v1, v2, v12536; VI-SDAG-NEXT: v_exp_f32_e32 v1, v12537; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v32538; VI-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed02539; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v02540; VI-SDAG-NEXT: s_mov_b32 s4, 0x42b172182541; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v22542; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc2543; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f8000002544; VI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v02545; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc2546; VI-SDAG-NEXT: s_setpc_b64 s[30:31]2547;2548; VI-GISEL-LABEL: v_exp_f32:2549; VI-GISEL: ; %bb.0:2550; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2551; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v02552; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v12553; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x39a3b295, v22554; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v22555; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3fb8a000, v12556; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v42557; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v12558; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v22559; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v32560; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v22561; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v12562; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v22563; VI-GISEL-NEXT: v_exp_f32_e32 v1, v12564; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f8000002565; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v22566; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed02567; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v22568; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42b172182569; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc2570; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v22571; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc2572; VI-GISEL-NEXT: s_setpc_b64 s[30:31]2573;2574; GFX900-SDAG-LABEL: v_exp_f32:2575; GFX900-SDAG: ; %bb.0:2576; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2577; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v02578; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3fb8aa3b2579; GFX900-SDAG-NEXT: v_rndne_f32_e32 v2, v12580; GFX900-SDAG-NEXT: v_sub_f32_e32 v3, v1, v22581; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v12582; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x32a5705f2583; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, v12584; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v3, v12585; GFX900-SDAG-NEXT: v_exp_f32_e32 v1, v12586; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v22587; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed02588; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v02589; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x42b172182590; GFX900-SDAG-NEXT: v_ldexp_f32 v1, v1, v22591; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc2592; GFX900-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f8000002593; GFX900-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v02594; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc2595; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]2596;2597; GFX900-GISEL-LABEL: v_exp_f32:2598; GFX900-GISEL: ; %bb.0:2599; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2600; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3fb8aa3b2601; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, 0x3fb8aa3b, v02602; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v22603; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x32a5705f2604; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v3, v12605; GFX900-GISEL-NEXT: v_rndne_f32_e32 v3, v22606; GFX900-GISEL-NEXT: v_sub_f32_e32 v2, v2, v32607; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v2, v12608; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v32609; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, v12610; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f8000002611; GFX900-GISEL-NEXT: v_ldexp_f32 v1, v1, v22612; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed02613; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v22614; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x42b172182615; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc2616; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v22617; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc2618; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]2619;2620; SI-SDAG-LABEL: v_exp_f32:2621; SI-SDAG: ; %bb.0:2622; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2623; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v02624; SI-SDAG-NEXT: s_mov_b32 s4, 0x3fb8aa3b2625; SI-SDAG-NEXT: v_rndne_f32_e32 v2, v12626; SI-SDAG-NEXT: v_sub_f32_e32 v3, v1, v22627; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v12628; SI-SDAG-NEXT: s_mov_b32 s4, 0x32a5705f2629; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, v12630; SI-SDAG-NEXT: v_add_f32_e32 v1, v3, v12631; SI-SDAG-NEXT: v_exp_f32_e32 v1, v12632; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v22633; SI-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed02634; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v02635; SI-SDAG-NEXT: s_mov_b32 s4, 0x42b172182636; SI-SDAG-NEXT: v_ldexp_f32_e32 v1, v1, v22637; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc2638; SI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f8000002639; SI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v02640; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc2641; SI-SDAG-NEXT: s_setpc_b64 s[30:31]2642;2643; SI-GISEL-LABEL: v_exp_f32:2644; SI-GISEL: ; %bb.0:2645; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2646; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3fb8aa3b2647; SI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3fb8aa3b, v02648; SI-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v22649; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x32a5705f2650; SI-GISEL-NEXT: v_fma_f32 v1, v0, v3, v12651; SI-GISEL-NEXT: v_rndne_f32_e32 v3, v22652; SI-GISEL-NEXT: v_sub_f32_e32 v2, v2, v32653; SI-GISEL-NEXT: v_add_f32_e32 v1, v2, v12654; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v32655; SI-GISEL-NEXT: v_exp_f32_e32 v1, v12656; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f8000002657; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, v1, v22658; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed02659; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v22660; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42b172182661; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc2662; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v22663; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc2664; SI-GISEL-NEXT: s_setpc_b64 s[30:31]2665;2666; R600-LABEL: v_exp_f32:2667; R600: ; %bb.0:2668; R600-NEXT: CF_END2669; R600-NEXT: PAD2670;2671; CM-LABEL: v_exp_f32:2672; CM: ; %bb.0:2673; CM-NEXT: CF_END2674; CM-NEXT: PAD2675 %result = call float @llvm.exp.f32(float %in)2676 ret float %result2677}2678 2679define float @v_exp_fabs_f32(float %in) {2680; VI-SDAG-LABEL: v_exp_fabs_f32:2681; VI-SDAG: ; %bb.0:2682; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2683; VI-SDAG-NEXT: v_and_b32_e32 v1, 0x7fffffff, v02684; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v12685; VI-SDAG-NEXT: v_sub_f32_e64 v4, |v0|, v12686; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v12687; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x39a3b295, v42688; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x3fb8a000, v42689; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v22690; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v52691; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v12692; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v32693; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v42694; VI-SDAG-NEXT: v_add_f32_e32 v1, v2, v12695; VI-SDAG-NEXT: v_exp_f32_e32 v1, v12696; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v32697; VI-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed02698; VI-SDAG-NEXT: v_cmp_nlt_f32_e64 vcc, |v0|, s42699; VI-SDAG-NEXT: s_mov_b32 s4, 0x42b172182700; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v22701; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc2702; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f8000002703; VI-SDAG-NEXT: v_cmp_ngt_f32_e64 vcc, |v0|, s42704; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc2705; VI-SDAG-NEXT: s_setpc_b64 s[30:31]2706;2707; VI-GISEL-LABEL: v_exp_fabs_f32:2708; VI-GISEL: ; %bb.0:2709; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2710; VI-GISEL-NEXT: v_and_b32_e32 v1, 0x7fffffff, v02711; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v12712; VI-GISEL-NEXT: v_sub_f32_e64 v2, |v0|, v12713; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x39a3b295, v22714; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v22715; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3fb8a000, v12716; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v42717; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v12718; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v22719; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v32720; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v22721; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v12722; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v22723; VI-GISEL-NEXT: v_exp_f32_e32 v1, v12724; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f8000002725; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v22726; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed02727; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v22728; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42b172182729; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[4:5]2730; VI-GISEL-NEXT: v_cmp_gt_f32_e64 vcc, |v0|, v22731; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc2732; VI-GISEL-NEXT: s_setpc_b64 s[30:31]2733;2734; GFX900-SDAG-LABEL: v_exp_fabs_f32:2735; GFX900-SDAG: ; %bb.0:2736; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2737; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3fb8aa3b2738; GFX900-SDAG-NEXT: v_mul_f32_e64 v1, |v0|, s42739; GFX900-SDAG-NEXT: v_rndne_f32_e32 v2, v12740; GFX900-SDAG-NEXT: v_sub_f32_e32 v3, v1, v22741; GFX900-SDAG-NEXT: v_fma_f32 v1, |v0|, s4, -v12742; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x32a5705f2743; GFX900-SDAG-NEXT: v_fma_f32 v1, |v0|, s4, v12744; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v3, v12745; GFX900-SDAG-NEXT: v_exp_f32_e32 v1, v12746; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v22747; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed02748; GFX900-SDAG-NEXT: v_cmp_nlt_f32_e64 vcc, |v0|, s42749; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x42b172182750; GFX900-SDAG-NEXT: v_ldexp_f32 v1, v1, v22751; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc2752; GFX900-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f8000002753; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e64 vcc, |v0|, s42754; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc2755; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]2756;2757; GFX900-GISEL-LABEL: v_exp_fabs_f32:2758; GFX900-GISEL: ; %bb.0:2759; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2760; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3fb8aa3b2761; GFX900-GISEL-NEXT: v_mul_f32_e64 v2, |v0|, v12762; GFX900-GISEL-NEXT: v_fma_f32 v1, |v0|, v1, -v22763; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x32a5705f2764; GFX900-GISEL-NEXT: v_fma_f32 v1, |v0|, v3, v12765; GFX900-GISEL-NEXT: v_rndne_f32_e32 v3, v22766; GFX900-GISEL-NEXT: v_sub_f32_e32 v2, v2, v32767; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v2, v12768; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v32769; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, v12770; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f8000002771; GFX900-GISEL-NEXT: v_ldexp_f32 v1, v1, v22772; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed02773; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v22774; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x42b172182775; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[4:5]2776; GFX900-GISEL-NEXT: v_cmp_gt_f32_e64 vcc, |v0|, v22777; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc2778; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]2779;2780; SI-SDAG-LABEL: v_exp_fabs_f32:2781; SI-SDAG: ; %bb.0:2782; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2783; SI-SDAG-NEXT: s_mov_b32 s4, 0x3fb8aa3b2784; SI-SDAG-NEXT: v_mul_f32_e64 v1, |v0|, s42785; SI-SDAG-NEXT: v_rndne_f32_e32 v2, v12786; SI-SDAG-NEXT: v_sub_f32_e32 v3, v1, v22787; SI-SDAG-NEXT: v_fma_f32 v1, |v0|, s4, -v12788; SI-SDAG-NEXT: s_mov_b32 s4, 0x32a5705f2789; SI-SDAG-NEXT: v_fma_f32 v1, |v0|, s4, v12790; SI-SDAG-NEXT: v_add_f32_e32 v1, v3, v12791; SI-SDAG-NEXT: v_exp_f32_e32 v1, v12792; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v22793; SI-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed02794; SI-SDAG-NEXT: v_cmp_nlt_f32_e64 vcc, |v0|, s42795; SI-SDAG-NEXT: s_mov_b32 s4, 0x42b172182796; SI-SDAG-NEXT: v_ldexp_f32_e32 v1, v1, v22797; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc2798; SI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f8000002799; SI-SDAG-NEXT: v_cmp_ngt_f32_e64 vcc, |v0|, s42800; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc2801; SI-SDAG-NEXT: s_setpc_b64 s[30:31]2802;2803; SI-GISEL-LABEL: v_exp_fabs_f32:2804; SI-GISEL: ; %bb.0:2805; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2806; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3fb8aa3b2807; SI-GISEL-NEXT: v_mul_f32_e64 v2, |v0|, v12808; SI-GISEL-NEXT: v_fma_f32 v1, |v0|, v1, -v22809; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x32a5705f2810; SI-GISEL-NEXT: v_fma_f32 v1, |v0|, v3, v12811; SI-GISEL-NEXT: v_rndne_f32_e32 v3, v22812; SI-GISEL-NEXT: v_sub_f32_e32 v2, v2, v32813; SI-GISEL-NEXT: v_add_f32_e32 v1, v2, v12814; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v32815; SI-GISEL-NEXT: v_exp_f32_e32 v1, v12816; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f8000002817; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, v1, v22818; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed02819; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v22820; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42b172182821; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[4:5]2822; SI-GISEL-NEXT: v_cmp_gt_f32_e64 vcc, |v0|, v22823; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc2824; SI-GISEL-NEXT: s_setpc_b64 s[30:31]2825;2826; R600-LABEL: v_exp_fabs_f32:2827; R600: ; %bb.0:2828; R600-NEXT: CF_END2829; R600-NEXT: PAD2830;2831; CM-LABEL: v_exp_fabs_f32:2832; CM: ; %bb.0:2833; CM-NEXT: CF_END2834; CM-NEXT: PAD2835 %fabs = call float @llvm.fabs.f32(float %in)2836 %result = call float @llvm.exp.f32(float %fabs)2837 ret float %result2838}2839 2840define float @v_exp_fneg_fabs_f32(float %in) {2841; VI-SDAG-LABEL: v_exp_fneg_fabs_f32:2842; VI-SDAG: ; %bb.0:2843; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2844; VI-SDAG-NEXT: v_or_b32_e32 v1, 0x80000000, v02845; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v12846; VI-SDAG-NEXT: v_sub_f32_e64 v4, -|v0|, v12847; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v12848; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x39a3b295, v42849; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x3fb8a000, v42850; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v22851; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v52852; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v12853; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v32854; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v42855; VI-SDAG-NEXT: v_add_f32_e32 v1, v2, v12856; VI-SDAG-NEXT: v_exp_f32_e32 v1, v12857; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v32858; VI-SDAG-NEXT: s_mov_b32 s4, 0x42ce8ed02859; VI-SDAG-NEXT: v_cmp_ngt_f32_e64 vcc, |v0|, s42860; VI-SDAG-NEXT: s_mov_b32 s4, 0xc2b172182861; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v22862; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc2863; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f8000002864; VI-SDAG-NEXT: v_cmp_nlt_f32_e64 vcc, |v0|, s42865; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc2866; VI-SDAG-NEXT: s_setpc_b64 s[30:31]2867;2868; VI-GISEL-LABEL: v_exp_fneg_fabs_f32:2869; VI-GISEL: ; %bb.0:2870; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2871; VI-GISEL-NEXT: v_or_b32_e32 v1, 0x80000000, v02872; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v12873; VI-GISEL-NEXT: v_sub_f32_e64 v2, -|v0|, v12874; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x39a3b295, v22875; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v22876; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3fb8a000, v12877; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v42878; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v12879; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v22880; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v32881; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v22882; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v12883; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v22884; VI-GISEL-NEXT: v_exp_f32_e32 v1, v12885; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f8000002886; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v22887; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed02888; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], -|v0|, v22889; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42b172182890; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[4:5]2891; VI-GISEL-NEXT: v_cmp_gt_f32_e64 vcc, -|v0|, v22892; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc2893; VI-GISEL-NEXT: s_setpc_b64 s[30:31]2894;2895; GFX900-SDAG-LABEL: v_exp_fneg_fabs_f32:2896; GFX900-SDAG: ; %bb.0:2897; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2898; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xbfb8aa3b2899; GFX900-SDAG-NEXT: v_mul_f32_e64 v1, |v0|, s42900; GFX900-SDAG-NEXT: v_rndne_f32_e32 v2, v12901; GFX900-SDAG-NEXT: v_sub_f32_e32 v3, v1, v22902; GFX900-SDAG-NEXT: v_fma_f32 v1, |v0|, s4, -v12903; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xb2a5705f2904; GFX900-SDAG-NEXT: v_fma_f32 v1, |v0|, s4, v12905; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v3, v12906; GFX900-SDAG-NEXT: v_exp_f32_e32 v1, v12907; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v22908; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x42ce8ed02909; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e64 vcc, |v0|, s42910; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xc2b172182911; GFX900-SDAG-NEXT: v_ldexp_f32 v1, v1, v22912; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc2913; GFX900-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f8000002914; GFX900-SDAG-NEXT: v_cmp_nlt_f32_e64 vcc, |v0|, s42915; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc2916; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]2917;2918; GFX900-GISEL-LABEL: v_exp_fneg_fabs_f32:2919; GFX900-GISEL: ; %bb.0:2920; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2921; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3fb8aa3b2922; GFX900-GISEL-NEXT: v_mul_f32_e64 v2, -|v0|, v12923; GFX900-GISEL-NEXT: v_fma_f32 v1, -|v0|, v1, -v22924; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x32a5705f2925; GFX900-GISEL-NEXT: v_fma_f32 v1, -|v0|, v3, v12926; GFX900-GISEL-NEXT: v_rndne_f32_e32 v3, v22927; GFX900-GISEL-NEXT: v_sub_f32_e32 v2, v2, v32928; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v2, v12929; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v32930; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, v12931; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f8000002932; GFX900-GISEL-NEXT: v_ldexp_f32 v1, v1, v22933; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed02934; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], -|v0|, v22935; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x42b172182936; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[4:5]2937; GFX900-GISEL-NEXT: v_cmp_gt_f32_e64 vcc, -|v0|, v22938; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc2939; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]2940;2941; SI-SDAG-LABEL: v_exp_fneg_fabs_f32:2942; SI-SDAG: ; %bb.0:2943; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2944; SI-SDAG-NEXT: s_mov_b32 s4, 0xbfb8aa3b2945; SI-SDAG-NEXT: v_mul_f32_e64 v1, |v0|, s42946; SI-SDAG-NEXT: v_rndne_f32_e32 v2, v12947; SI-SDAG-NEXT: v_sub_f32_e32 v3, v1, v22948; SI-SDAG-NEXT: v_fma_f32 v1, |v0|, s4, -v12949; SI-SDAG-NEXT: s_mov_b32 s4, 0xb2a5705f2950; SI-SDAG-NEXT: v_fma_f32 v1, |v0|, s4, v12951; SI-SDAG-NEXT: v_add_f32_e32 v1, v3, v12952; SI-SDAG-NEXT: v_exp_f32_e32 v1, v12953; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v22954; SI-SDAG-NEXT: s_mov_b32 s4, 0x42ce8ed02955; SI-SDAG-NEXT: v_cmp_ngt_f32_e64 vcc, |v0|, s42956; SI-SDAG-NEXT: s_mov_b32 s4, 0xc2b172182957; SI-SDAG-NEXT: v_ldexp_f32_e32 v1, v1, v22958; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc2959; SI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f8000002960; SI-SDAG-NEXT: v_cmp_nlt_f32_e64 vcc, |v0|, s42961; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc2962; SI-SDAG-NEXT: s_setpc_b64 s[30:31]2963;2964; SI-GISEL-LABEL: v_exp_fneg_fabs_f32:2965; SI-GISEL: ; %bb.0:2966; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2967; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3fb8aa3b2968; SI-GISEL-NEXT: v_mul_f32_e64 v2, -|v0|, v12969; SI-GISEL-NEXT: v_fma_f32 v1, -|v0|, v1, -v22970; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x32a5705f2971; SI-GISEL-NEXT: v_fma_f32 v1, -|v0|, v3, v12972; SI-GISEL-NEXT: v_rndne_f32_e32 v3, v22973; SI-GISEL-NEXT: v_sub_f32_e32 v2, v2, v32974; SI-GISEL-NEXT: v_add_f32_e32 v1, v2, v12975; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v32976; SI-GISEL-NEXT: v_exp_f32_e32 v1, v12977; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f8000002978; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, v1, v22979; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed02980; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], -|v0|, v22981; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42b172182982; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[4:5]2983; SI-GISEL-NEXT: v_cmp_gt_f32_e64 vcc, -|v0|, v22984; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc2985; SI-GISEL-NEXT: s_setpc_b64 s[30:31]2986;2987; R600-LABEL: v_exp_fneg_fabs_f32:2988; R600: ; %bb.0:2989; R600-NEXT: CF_END2990; R600-NEXT: PAD2991;2992; CM-LABEL: v_exp_fneg_fabs_f32:2993; CM: ; %bb.0:2994; CM-NEXT: CF_END2995; CM-NEXT: PAD2996 %fabs = call float @llvm.fabs.f32(float %in)2997 %fneg.fabs = fneg float %fabs2998 %result = call float @llvm.exp.f32(float %fneg.fabs)2999 ret float %result3000}3001 3002define float @v_exp_fneg_f32(float %in) {3003; VI-SDAG-LABEL: v_exp_fneg_f32:3004; VI-SDAG: ; %bb.0:3005; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3006; VI-SDAG-NEXT: v_xor_b32_e32 v1, 0x80000000, v03007; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v13008; VI-SDAG-NEXT: v_sub_f32_e64 v4, -v0, v13009; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v13010; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x39a3b295, v43011; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x3fb8a000, v43012; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v23013; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v53014; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v13015; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v33016; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v43017; VI-SDAG-NEXT: v_add_f32_e32 v1, v2, v13018; VI-SDAG-NEXT: v_exp_f32_e32 v1, v13019; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v33020; VI-SDAG-NEXT: s_mov_b32 s4, 0x42ce8ed03021; VI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v03022; VI-SDAG-NEXT: s_mov_b32 s4, 0xc2b172183023; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v23024; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc3025; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f8000003026; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v03027; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc3028; VI-SDAG-NEXT: s_setpc_b64 s[30:31]3029;3030; VI-GISEL-LABEL: v_exp_fneg_f32:3031; VI-GISEL: ; %bb.0:3032; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3033; VI-GISEL-NEXT: v_xor_b32_e32 v1, 0x80000000, v03034; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v13035; VI-GISEL-NEXT: v_sub_f32_e64 v2, -v0, v13036; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x39a3b295, v23037; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v23038; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3fb8a000, v13039; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v43040; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v13041; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v23042; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v33043; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v23044; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v13045; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v23046; VI-GISEL-NEXT: v_exp_f32_e32 v1, v13047; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f8000003048; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v23049; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed03050; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], -v0, v23051; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42b172183052; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[4:5]3053; VI-GISEL-NEXT: v_cmp_gt_f32_e64 vcc, -v0, v23054; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc3055; VI-GISEL-NEXT: s_setpc_b64 s[30:31]3056;3057; GFX900-SDAG-LABEL: v_exp_fneg_f32:3058; GFX900-SDAG: ; %bb.0:3059; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3060; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0xbfb8aa3b, v03061; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xbfb8aa3b3062; GFX900-SDAG-NEXT: v_rndne_f32_e32 v2, v13063; GFX900-SDAG-NEXT: v_sub_f32_e32 v3, v1, v23064; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v13065; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xb2a5705f3066; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, v13067; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v3, v13068; GFX900-SDAG-NEXT: v_exp_f32_e32 v1, v13069; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v23070; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x42ce8ed03071; GFX900-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v03072; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xc2b172183073; GFX900-SDAG-NEXT: v_ldexp_f32 v1, v1, v23074; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc3075; GFX900-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f8000003076; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v03077; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc3078; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]3079;3080; GFX900-GISEL-LABEL: v_exp_fneg_f32:3081; GFX900-GISEL: ; %bb.0:3082; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3083; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3fb8aa3b3084; GFX900-GISEL-NEXT: v_mul_f32_e64 v2, -v0, v13085; GFX900-GISEL-NEXT: v_fma_f32 v1, -v0, v1, -v23086; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x32a5705f3087; GFX900-GISEL-NEXT: v_fma_f32 v1, -v0, v3, v13088; GFX900-GISEL-NEXT: v_rndne_f32_e32 v3, v23089; GFX900-GISEL-NEXT: v_sub_f32_e32 v2, v2, v33090; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v2, v13091; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v33092; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, v13093; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f8000003094; GFX900-GISEL-NEXT: v_ldexp_f32 v1, v1, v23095; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed03096; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], -v0, v23097; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x42b172183098; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[4:5]3099; GFX900-GISEL-NEXT: v_cmp_gt_f32_e64 vcc, -v0, v23100; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc3101; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]3102;3103; SI-SDAG-LABEL: v_exp_fneg_f32:3104; SI-SDAG: ; %bb.0:3105; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3106; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0xbfb8aa3b, v03107; SI-SDAG-NEXT: s_mov_b32 s4, 0xbfb8aa3b3108; SI-SDAG-NEXT: v_rndne_f32_e32 v2, v13109; SI-SDAG-NEXT: v_sub_f32_e32 v3, v1, v23110; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v13111; SI-SDAG-NEXT: s_mov_b32 s4, 0xb2a5705f3112; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, v13113; SI-SDAG-NEXT: v_add_f32_e32 v1, v3, v13114; SI-SDAG-NEXT: v_exp_f32_e32 v1, v13115; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v23116; SI-SDAG-NEXT: s_mov_b32 s4, 0x42ce8ed03117; SI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v03118; SI-SDAG-NEXT: s_mov_b32 s4, 0xc2b172183119; SI-SDAG-NEXT: v_ldexp_f32_e32 v1, v1, v23120; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc3121; SI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f8000003122; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v03123; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc3124; SI-SDAG-NEXT: s_setpc_b64 s[30:31]3125;3126; SI-GISEL-LABEL: v_exp_fneg_f32:3127; SI-GISEL: ; %bb.0:3128; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3129; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3fb8aa3b3130; SI-GISEL-NEXT: v_mul_f32_e64 v2, -v0, v13131; SI-GISEL-NEXT: v_fma_f32 v1, -v0, v1, -v23132; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x32a5705f3133; SI-GISEL-NEXT: v_fma_f32 v1, -v0, v3, v13134; SI-GISEL-NEXT: v_rndne_f32_e32 v3, v23135; SI-GISEL-NEXT: v_sub_f32_e32 v2, v2, v33136; SI-GISEL-NEXT: v_add_f32_e32 v1, v2, v13137; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v33138; SI-GISEL-NEXT: v_exp_f32_e32 v1, v13139; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f8000003140; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, v1, v23141; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed03142; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], -v0, v23143; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42b172183144; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[4:5]3145; SI-GISEL-NEXT: v_cmp_gt_f32_e64 vcc, -v0, v23146; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc3147; SI-GISEL-NEXT: s_setpc_b64 s[30:31]3148;3149; R600-LABEL: v_exp_fneg_f32:3150; R600: ; %bb.0:3151; R600-NEXT: CF_END3152; R600-NEXT: PAD3153;3154; CM-LABEL: v_exp_fneg_f32:3155; CM: ; %bb.0:3156; CM-NEXT: CF_END3157; CM-NEXT: PAD3158 %fneg = fneg float %in3159 %result = call float @llvm.exp.f32(float %fneg)3160 ret float %result3161}3162 3163define float @v_exp_f32_fast(float %in) {3164; GCN-SDAG-LABEL: v_exp_f32_fast:3165; GCN-SDAG: ; %bb.0:3166; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3167; GCN-SDAG-NEXT: s_mov_b32 s4, 0xc2aeac503168; GCN-SDAG-NEXT: v_add_f32_e32 v1, 0x42800000, v03169; GCN-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v03170; GCN-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc3171; GCN-SDAG-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v03172; GCN-SDAG-NEXT: v_exp_f32_e32 v0, v03173; GCN-SDAG-NEXT: v_mul_f32_e32 v1, 0x114b4ea4, v03174; GCN-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc3175; GCN-SDAG-NEXT: s_setpc_b64 s[30:31]3176;3177; GCN-GISEL-LABEL: v_exp_f32_fast:3178; GCN-GISEL: ; %bb.0:3179; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3180; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2aeac503181; GCN-GISEL-NEXT: v_add_f32_e32 v2, 0x42800000, v03182; GCN-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v13183; GCN-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc3184; GCN-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v03185; GCN-GISEL-NEXT: v_exp_f32_e32 v0, v03186; GCN-GISEL-NEXT: v_mul_f32_e32 v1, 0x114b4ea4, v03187; GCN-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc3188; GCN-GISEL-NEXT: s_setpc_b64 s[30:31]3189;3190; SI-SDAG-LABEL: v_exp_f32_fast:3191; SI-SDAG: ; %bb.0:3192; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3193; SI-SDAG-NEXT: s_mov_b32 s4, 0xc2aeac503194; SI-SDAG-NEXT: v_add_f32_e32 v1, 0x42800000, v03195; SI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v03196; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc3197; SI-SDAG-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v03198; SI-SDAG-NEXT: v_exp_f32_e32 v0, v03199; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x114b4ea4, v03200; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc3201; SI-SDAG-NEXT: s_setpc_b64 s[30:31]3202;3203; SI-GISEL-LABEL: v_exp_f32_fast:3204; SI-GISEL: ; %bb.0:3205; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3206; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2aeac503207; SI-GISEL-NEXT: v_add_f32_e32 v2, 0x42800000, v03208; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v13209; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc3210; SI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v03211; SI-GISEL-NEXT: v_exp_f32_e32 v0, v03212; SI-GISEL-NEXT: v_mul_f32_e32 v1, 0x114b4ea4, v03213; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc3214; SI-GISEL-NEXT: s_setpc_b64 s[30:31]3215;3216; R600-LABEL: v_exp_f32_fast:3217; R600: ; %bb.0:3218; R600-NEXT: CF_END3219; R600-NEXT: PAD3220;3221; CM-LABEL: v_exp_f32_fast:3222; CM: ; %bb.0:3223; CM-NEXT: CF_END3224; CM-NEXT: PAD3225 %result = call fast float @llvm.exp.f32(float %in)3226 ret float %result3227}3228 3229define float @v_exp_f32_ninf(float %in) {3230; VI-SDAG-LABEL: v_exp_f32_ninf:3231; VI-SDAG: ; %bb.0:3232; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3233; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v03234; VI-SDAG-NEXT: v_sub_f32_e32 v4, v0, v13235; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v13236; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x39a3b295, v43237; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x3fb8a000, v43238; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v23239; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v53240; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v13241; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v33242; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v43243; VI-SDAG-NEXT: v_add_f32_e32 v1, v2, v13244; VI-SDAG-NEXT: v_exp_f32_e32 v1, v13245; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v33246; VI-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed03247; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v03248; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v23249; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc3250; VI-SDAG-NEXT: s_setpc_b64 s[30:31]3251;3252; VI-GISEL-LABEL: v_exp_f32_ninf:3253; VI-GISEL: ; %bb.0:3254; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3255; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v03256; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v13257; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x39a3b295, v23258; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v23259; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3fb8a000, v13260; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v43261; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v13262; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v23263; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v33264; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v23265; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v13266; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v23267; VI-GISEL-NEXT: v_exp_f32_e32 v1, v13268; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v23269; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed03270; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v23271; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc3272; VI-GISEL-NEXT: s_setpc_b64 s[30:31]3273;3274; GFX900-SDAG-LABEL: v_exp_f32_ninf:3275; GFX900-SDAG: ; %bb.0:3276; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3277; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v03278; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3fb8aa3b3279; GFX900-SDAG-NEXT: v_rndne_f32_e32 v2, v13280; GFX900-SDAG-NEXT: v_sub_f32_e32 v3, v1, v23281; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v13282; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x32a5705f3283; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, v13284; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v3, v13285; GFX900-SDAG-NEXT: v_exp_f32_e32 v1, v13286; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v23287; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed03288; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v03289; GFX900-SDAG-NEXT: v_ldexp_f32 v1, v1, v23290; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc3291; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]3292;3293; GFX900-GISEL-LABEL: v_exp_f32_ninf:3294; GFX900-GISEL: ; %bb.0:3295; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3296; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3fb8aa3b3297; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, 0x3fb8aa3b, v03298; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v23299; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x32a5705f3300; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v3, v13301; GFX900-GISEL-NEXT: v_rndne_f32_e32 v3, v23302; GFX900-GISEL-NEXT: v_sub_f32_e32 v2, v2, v33303; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v2, v13304; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v33305; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, v13306; GFX900-GISEL-NEXT: v_ldexp_f32 v1, v1, v23307; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed03308; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v23309; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc3310; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]3311;3312; SI-SDAG-LABEL: v_exp_f32_ninf:3313; SI-SDAG: ; %bb.0:3314; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3315; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v03316; SI-SDAG-NEXT: s_mov_b32 s4, 0x3fb8aa3b3317; SI-SDAG-NEXT: v_rndne_f32_e32 v2, v13318; SI-SDAG-NEXT: v_sub_f32_e32 v3, v1, v23319; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v13320; SI-SDAG-NEXT: s_mov_b32 s4, 0x32a5705f3321; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, v13322; SI-SDAG-NEXT: v_add_f32_e32 v1, v3, v13323; SI-SDAG-NEXT: v_exp_f32_e32 v1, v13324; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v23325; SI-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed03326; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v03327; SI-SDAG-NEXT: v_ldexp_f32_e32 v1, v1, v23328; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc3329; SI-SDAG-NEXT: s_setpc_b64 s[30:31]3330;3331; SI-GISEL-LABEL: v_exp_f32_ninf:3332; SI-GISEL: ; %bb.0:3333; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3334; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3fb8aa3b3335; SI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3fb8aa3b, v03336; SI-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v23337; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x32a5705f3338; SI-GISEL-NEXT: v_fma_f32 v1, v0, v3, v13339; SI-GISEL-NEXT: v_rndne_f32_e32 v3, v23340; SI-GISEL-NEXT: v_sub_f32_e32 v2, v2, v33341; SI-GISEL-NEXT: v_add_f32_e32 v1, v2, v13342; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v33343; SI-GISEL-NEXT: v_exp_f32_e32 v1, v13344; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, v1, v23345; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed03346; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v23347; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc3348; SI-GISEL-NEXT: s_setpc_b64 s[30:31]3349;3350; R600-LABEL: v_exp_f32_ninf:3351; R600: ; %bb.0:3352; R600-NEXT: CF_END3353; R600-NEXT: PAD3354;3355; CM-LABEL: v_exp_f32_ninf:3356; CM: ; %bb.0:3357; CM-NEXT: CF_END3358; CM-NEXT: PAD3359 %result = call ninf float @llvm.exp.f32(float %in)3360 ret float %result3361}3362 3363define float @v_exp_f32_afn(float %in) {3364; GCN-SDAG-LABEL: v_exp_f32_afn:3365; GCN-SDAG: ; %bb.0:3366; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3367; GCN-SDAG-NEXT: s_mov_b32 s4, 0xc2aeac503368; GCN-SDAG-NEXT: v_add_f32_e32 v1, 0x42800000, v03369; GCN-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v03370; GCN-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc3371; GCN-SDAG-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v03372; GCN-SDAG-NEXT: v_exp_f32_e32 v0, v03373; GCN-SDAG-NEXT: v_mul_f32_e32 v1, 0x114b4ea4, v03374; GCN-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc3375; GCN-SDAG-NEXT: s_setpc_b64 s[30:31]3376;3377; GCN-GISEL-LABEL: v_exp_f32_afn:3378; GCN-GISEL: ; %bb.0:3379; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3380; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2aeac503381; GCN-GISEL-NEXT: v_add_f32_e32 v2, 0x42800000, v03382; GCN-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v13383; GCN-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc3384; GCN-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v03385; GCN-GISEL-NEXT: v_exp_f32_e32 v0, v03386; GCN-GISEL-NEXT: v_mul_f32_e32 v1, 0x114b4ea4, v03387; GCN-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc3388; GCN-GISEL-NEXT: s_setpc_b64 s[30:31]3389;3390; SI-SDAG-LABEL: v_exp_f32_afn:3391; SI-SDAG: ; %bb.0:3392; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3393; SI-SDAG-NEXT: s_mov_b32 s4, 0xc2aeac503394; SI-SDAG-NEXT: v_add_f32_e32 v1, 0x42800000, v03395; SI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v03396; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc3397; SI-SDAG-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v03398; SI-SDAG-NEXT: v_exp_f32_e32 v0, v03399; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x114b4ea4, v03400; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc3401; SI-SDAG-NEXT: s_setpc_b64 s[30:31]3402;3403; SI-GISEL-LABEL: v_exp_f32_afn:3404; SI-GISEL: ; %bb.0:3405; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3406; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2aeac503407; SI-GISEL-NEXT: v_add_f32_e32 v2, 0x42800000, v03408; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v13409; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc3410; SI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v03411; SI-GISEL-NEXT: v_exp_f32_e32 v0, v03412; SI-GISEL-NEXT: v_mul_f32_e32 v1, 0x114b4ea4, v03413; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc3414; SI-GISEL-NEXT: s_setpc_b64 s[30:31]3415;3416; R600-LABEL: v_exp_f32_afn:3417; R600: ; %bb.0:3418; R600-NEXT: CF_END3419; R600-NEXT: PAD3420;3421; CM-LABEL: v_exp_f32_afn:3422; CM: ; %bb.0:3423; CM-NEXT: CF_END3424; CM-NEXT: PAD3425 %result = call afn float @llvm.exp.f32(float %in)3426 ret float %result3427}3428 3429define float @v_exp_f32_afn_daz(float %in) #0 {3430; GCN-LABEL: v_exp_f32_afn_daz:3431; GCN: ; %bb.0:3432; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3433; GCN-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v03434; GCN-NEXT: v_exp_f32_e32 v0, v03435; GCN-NEXT: s_setpc_b64 s[30:31]3436;3437; SI-LABEL: v_exp_f32_afn_daz:3438; SI: ; %bb.0:3439; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3440; SI-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v03441; SI-NEXT: v_exp_f32_e32 v0, v03442; SI-NEXT: s_setpc_b64 s[30:31]3443;3444; R600-LABEL: v_exp_f32_afn_daz:3445; R600: ; %bb.0:3446; R600-NEXT: CF_END3447; R600-NEXT: PAD3448;3449; CM-LABEL: v_exp_f32_afn_daz:3450; CM: ; %bb.0:3451; CM-NEXT: CF_END3452; CM-NEXT: PAD3453 %result = call afn float @llvm.exp.f32(float %in)3454 ret float %result3455}3456 3457define float @v_exp_f32_afn_dynamic(float %in) #1 {3458; GCN-SDAG-LABEL: v_exp_f32_afn_dynamic:3459; GCN-SDAG: ; %bb.0:3460; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3461; GCN-SDAG-NEXT: s_mov_b32 s4, 0xc2aeac503462; GCN-SDAG-NEXT: v_add_f32_e32 v1, 0x42800000, v03463; GCN-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v03464; GCN-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc3465; GCN-SDAG-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v03466; GCN-SDAG-NEXT: v_exp_f32_e32 v0, v03467; GCN-SDAG-NEXT: v_mul_f32_e32 v1, 0x114b4ea4, v03468; GCN-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc3469; GCN-SDAG-NEXT: s_setpc_b64 s[30:31]3470;3471; GCN-GISEL-LABEL: v_exp_f32_afn_dynamic:3472; GCN-GISEL: ; %bb.0:3473; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3474; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2aeac503475; GCN-GISEL-NEXT: v_add_f32_e32 v2, 0x42800000, v03476; GCN-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v13477; GCN-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc3478; GCN-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v03479; GCN-GISEL-NEXT: v_exp_f32_e32 v0, v03480; GCN-GISEL-NEXT: v_mul_f32_e32 v1, 0x114b4ea4, v03481; GCN-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc3482; GCN-GISEL-NEXT: s_setpc_b64 s[30:31]3483;3484; SI-SDAG-LABEL: v_exp_f32_afn_dynamic:3485; SI-SDAG: ; %bb.0:3486; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3487; SI-SDAG-NEXT: s_mov_b32 s4, 0xc2aeac503488; SI-SDAG-NEXT: v_add_f32_e32 v1, 0x42800000, v03489; SI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v03490; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc3491; SI-SDAG-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v03492; SI-SDAG-NEXT: v_exp_f32_e32 v0, v03493; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x114b4ea4, v03494; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc3495; SI-SDAG-NEXT: s_setpc_b64 s[30:31]3496;3497; SI-GISEL-LABEL: v_exp_f32_afn_dynamic:3498; SI-GISEL: ; %bb.0:3499; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3500; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2aeac503501; SI-GISEL-NEXT: v_add_f32_e32 v2, 0x42800000, v03502; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v13503; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc3504; SI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v03505; SI-GISEL-NEXT: v_exp_f32_e32 v0, v03506; SI-GISEL-NEXT: v_mul_f32_e32 v1, 0x114b4ea4, v03507; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc3508; SI-GISEL-NEXT: s_setpc_b64 s[30:31]3509;3510; R600-LABEL: v_exp_f32_afn_dynamic:3511; R600: ; %bb.0:3512; R600-NEXT: CF_END3513; R600-NEXT: PAD3514;3515; CM-LABEL: v_exp_f32_afn_dynamic:3516; CM: ; %bb.0:3517; CM-NEXT: CF_END3518; CM-NEXT: PAD3519 %result = call afn float @llvm.exp.f32(float %in)3520 ret float %result3521}3522 3523define float @v_fabs_exp_f32_afn(float %in) {3524; GCN-SDAG-LABEL: v_fabs_exp_f32_afn:3525; GCN-SDAG: ; %bb.0:3526; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3527; GCN-SDAG-NEXT: s_mov_b32 s4, 0xc2aeac503528; GCN-SDAG-NEXT: s_mov_b32 s5, 0x428000003529; GCN-SDAG-NEXT: v_add_f32_e64 v1, |v0|, s53530; GCN-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s43531; GCN-SDAG-NEXT: v_cndmask_b32_e64 v0, |v0|, v1, vcc3532; GCN-SDAG-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v03533; GCN-SDAG-NEXT: v_exp_f32_e32 v0, v03534; GCN-SDAG-NEXT: v_mul_f32_e32 v1, 0x114b4ea4, v03535; GCN-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc3536; GCN-SDAG-NEXT: s_setpc_b64 s[30:31]3537;3538; GCN-GISEL-LABEL: v_fabs_exp_f32_afn:3539; GCN-GISEL: ; %bb.0:3540; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3541; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2aeac503542; GCN-GISEL-NEXT: v_mov_b32_e32 v2, 0x428000003543; GCN-GISEL-NEXT: v_add_f32_e64 v2, |v0|, v23544; GCN-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v13545; GCN-GISEL-NEXT: v_cndmask_b32_e64 v0, |v0|, v2, vcc3546; GCN-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v03547; GCN-GISEL-NEXT: v_exp_f32_e32 v0, v03548; GCN-GISEL-NEXT: v_mul_f32_e32 v1, 0x114b4ea4, v03549; GCN-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc3550; GCN-GISEL-NEXT: s_setpc_b64 s[30:31]3551;3552; SI-SDAG-LABEL: v_fabs_exp_f32_afn:3553; SI-SDAG: ; %bb.0:3554; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3555; SI-SDAG-NEXT: s_mov_b32 s4, 0xc2aeac503556; SI-SDAG-NEXT: s_mov_b32 s5, 0x428000003557; SI-SDAG-NEXT: v_add_f32_e64 v1, |v0|, s53558; SI-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s43559; SI-SDAG-NEXT: v_cndmask_b32_e64 v0, |v0|, v1, vcc3560; SI-SDAG-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v03561; SI-SDAG-NEXT: v_exp_f32_e32 v0, v03562; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x114b4ea4, v03563; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc3564; SI-SDAG-NEXT: s_setpc_b64 s[30:31]3565;3566; SI-GISEL-LABEL: v_fabs_exp_f32_afn:3567; SI-GISEL: ; %bb.0:3568; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3569; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2aeac503570; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x428000003571; SI-GISEL-NEXT: v_add_f32_e64 v2, |v0|, v23572; SI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v13573; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, |v0|, v2, vcc3574; SI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v03575; SI-GISEL-NEXT: v_exp_f32_e32 v0, v03576; SI-GISEL-NEXT: v_mul_f32_e32 v1, 0x114b4ea4, v03577; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc3578; SI-GISEL-NEXT: s_setpc_b64 s[30:31]3579;3580; R600-LABEL: v_fabs_exp_f32_afn:3581; R600: ; %bb.0:3582; R600-NEXT: CF_END3583; R600-NEXT: PAD3584;3585; CM-LABEL: v_fabs_exp_f32_afn:3586; CM: ; %bb.0:3587; CM-NEXT: CF_END3588; CM-NEXT: PAD3589 %fabs = call float @llvm.fabs.f32(float %in)3590 %result = call afn float @llvm.exp.f32(float %fabs)3591 ret float %result3592}3593 3594define float @v_exp_f32_daz(float %in) #0 {3595; VI-SDAG-LABEL: v_exp_f32_daz:3596; VI-SDAG: ; %bb.0:3597; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3598; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v03599; VI-SDAG-NEXT: v_sub_f32_e32 v4, v0, v13600; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v13601; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x39a3b295, v43602; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x3fb8a000, v43603; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v23604; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v53605; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v13606; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v33607; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v43608; VI-SDAG-NEXT: v_add_f32_e32 v1, v2, v13609; VI-SDAG-NEXT: v_exp_f32_e32 v1, v13610; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v33611; VI-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed03612; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v03613; VI-SDAG-NEXT: s_mov_b32 s4, 0x42b172183614; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v23615; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc3616; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f8000003617; VI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v03618; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc3619; VI-SDAG-NEXT: s_setpc_b64 s[30:31]3620;3621; VI-GISEL-LABEL: v_exp_f32_daz:3622; VI-GISEL: ; %bb.0:3623; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3624; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v03625; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v13626; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x39a3b295, v23627; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v23628; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3fb8a000, v13629; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v43630; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v13631; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v23632; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v33633; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v23634; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v13635; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v23636; VI-GISEL-NEXT: v_exp_f32_e32 v1, v13637; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f8000003638; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v23639; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed03640; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v23641; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42b172183642; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc3643; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v23644; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc3645; VI-GISEL-NEXT: s_setpc_b64 s[30:31]3646;3647; GFX900-SDAG-LABEL: v_exp_f32_daz:3648; GFX900-SDAG: ; %bb.0:3649; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3650; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v03651; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3fb8aa3b3652; GFX900-SDAG-NEXT: v_rndne_f32_e32 v2, v13653; GFX900-SDAG-NEXT: v_sub_f32_e32 v3, v1, v23654; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v13655; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x32a5705f3656; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, v13657; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v3, v13658; GFX900-SDAG-NEXT: v_exp_f32_e32 v1, v13659; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v23660; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed03661; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v03662; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x42b172183663; GFX900-SDAG-NEXT: v_ldexp_f32 v1, v1, v23664; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc3665; GFX900-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f8000003666; GFX900-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v03667; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc3668; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]3669;3670; GFX900-GISEL-LABEL: v_exp_f32_daz:3671; GFX900-GISEL: ; %bb.0:3672; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3673; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3fb8aa3b3674; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, 0x3fb8aa3b, v03675; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v23676; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x32a5705f3677; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v3, v13678; GFX900-GISEL-NEXT: v_rndne_f32_e32 v3, v23679; GFX900-GISEL-NEXT: v_sub_f32_e32 v2, v2, v33680; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v2, v13681; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v33682; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, v13683; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f8000003684; GFX900-GISEL-NEXT: v_ldexp_f32 v1, v1, v23685; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed03686; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v23687; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x42b172183688; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc3689; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v23690; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc3691; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]3692;3693; SI-SDAG-LABEL: v_exp_f32_daz:3694; SI-SDAG: ; %bb.0:3695; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3696; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v03697; SI-SDAG-NEXT: s_mov_b32 s4, 0x3fb8aa3b3698; SI-SDAG-NEXT: v_rndne_f32_e32 v2, v13699; SI-SDAG-NEXT: v_sub_f32_e32 v3, v1, v23700; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v13701; SI-SDAG-NEXT: s_mov_b32 s4, 0x32a5705f3702; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, v13703; SI-SDAG-NEXT: v_add_f32_e32 v1, v3, v13704; SI-SDAG-NEXT: v_exp_f32_e32 v1, v13705; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v23706; SI-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed03707; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v03708; SI-SDAG-NEXT: s_mov_b32 s4, 0x42b172183709; SI-SDAG-NEXT: v_ldexp_f32_e32 v1, v1, v23710; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc3711; SI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f8000003712; SI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v03713; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc3714; SI-SDAG-NEXT: s_setpc_b64 s[30:31]3715;3716; SI-GISEL-LABEL: v_exp_f32_daz:3717; SI-GISEL: ; %bb.0:3718; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3719; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3fb8aa3b3720; SI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3fb8aa3b, v03721; SI-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v23722; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x32a5705f3723; SI-GISEL-NEXT: v_fma_f32 v1, v0, v3, v13724; SI-GISEL-NEXT: v_rndne_f32_e32 v3, v23725; SI-GISEL-NEXT: v_sub_f32_e32 v2, v2, v33726; SI-GISEL-NEXT: v_add_f32_e32 v1, v2, v13727; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v33728; SI-GISEL-NEXT: v_exp_f32_e32 v1, v13729; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f8000003730; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, v1, v23731; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed03732; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v23733; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42b172183734; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc3735; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v23736; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc3737; SI-GISEL-NEXT: s_setpc_b64 s[30:31]3738;3739; R600-LABEL: v_exp_f32_daz:3740; R600: ; %bb.0:3741; R600-NEXT: CF_END3742; R600-NEXT: PAD3743;3744; CM-LABEL: v_exp_f32_daz:3745; CM: ; %bb.0:3746; CM-NEXT: CF_END3747; CM-NEXT: PAD3748 %result = call float @llvm.exp.f32(float %in)3749 ret float %result3750}3751 3752define float @v_exp_f32_nnan(float %in) {3753; VI-SDAG-LABEL: v_exp_f32_nnan:3754; VI-SDAG: ; %bb.0:3755; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3756; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v03757; VI-SDAG-NEXT: v_sub_f32_e32 v4, v0, v13758; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v13759; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x39a3b295, v43760; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x3fb8a000, v43761; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v23762; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v53763; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v13764; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v33765; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v43766; VI-SDAG-NEXT: v_add_f32_e32 v1, v2, v13767; VI-SDAG-NEXT: v_exp_f32_e32 v1, v13768; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v33769; VI-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed03770; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v03771; VI-SDAG-NEXT: s_mov_b32 s4, 0x42b172183772; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v23773; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc3774; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f8000003775; VI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v03776; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc3777; VI-SDAG-NEXT: s_setpc_b64 s[30:31]3778;3779; VI-GISEL-LABEL: v_exp_f32_nnan:3780; VI-GISEL: ; %bb.0:3781; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3782; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v03783; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v13784; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x39a3b295, v23785; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v23786; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3fb8a000, v13787; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v43788; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v13789; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v23790; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v33791; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v23792; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v13793; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v23794; VI-GISEL-NEXT: v_exp_f32_e32 v1, v13795; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f8000003796; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v23797; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed03798; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v23799; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42b172183800; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc3801; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v23802; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc3803; VI-GISEL-NEXT: s_setpc_b64 s[30:31]3804;3805; GFX900-SDAG-LABEL: v_exp_f32_nnan:3806; GFX900-SDAG: ; %bb.0:3807; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3808; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v03809; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3fb8aa3b3810; GFX900-SDAG-NEXT: v_rndne_f32_e32 v2, v13811; GFX900-SDAG-NEXT: v_sub_f32_e32 v3, v1, v23812; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v13813; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x32a5705f3814; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, v13815; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v3, v13816; GFX900-SDAG-NEXT: v_exp_f32_e32 v1, v13817; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v23818; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed03819; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v03820; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x42b172183821; GFX900-SDAG-NEXT: v_ldexp_f32 v1, v1, v23822; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc3823; GFX900-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f8000003824; GFX900-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v03825; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc3826; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]3827;3828; GFX900-GISEL-LABEL: v_exp_f32_nnan:3829; GFX900-GISEL: ; %bb.0:3830; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3831; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3fb8aa3b3832; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, 0x3fb8aa3b, v03833; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v23834; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x32a5705f3835; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v3, v13836; GFX900-GISEL-NEXT: v_rndne_f32_e32 v3, v23837; GFX900-GISEL-NEXT: v_sub_f32_e32 v2, v2, v33838; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v2, v13839; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v33840; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, v13841; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f8000003842; GFX900-GISEL-NEXT: v_ldexp_f32 v1, v1, v23843; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed03844; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v23845; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x42b172183846; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc3847; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v23848; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc3849; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]3850;3851; SI-SDAG-LABEL: v_exp_f32_nnan:3852; SI-SDAG: ; %bb.0:3853; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3854; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v03855; SI-SDAG-NEXT: s_mov_b32 s4, 0x3fb8aa3b3856; SI-SDAG-NEXT: v_rndne_f32_e32 v2, v13857; SI-SDAG-NEXT: v_sub_f32_e32 v3, v1, v23858; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v13859; SI-SDAG-NEXT: s_mov_b32 s4, 0x32a5705f3860; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, v13861; SI-SDAG-NEXT: v_add_f32_e32 v1, v3, v13862; SI-SDAG-NEXT: v_exp_f32_e32 v1, v13863; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v23864; SI-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed03865; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v03866; SI-SDAG-NEXT: s_mov_b32 s4, 0x42b172183867; SI-SDAG-NEXT: v_ldexp_f32_e32 v1, v1, v23868; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc3869; SI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f8000003870; SI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v03871; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc3872; SI-SDAG-NEXT: s_setpc_b64 s[30:31]3873;3874; SI-GISEL-LABEL: v_exp_f32_nnan:3875; SI-GISEL: ; %bb.0:3876; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3877; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3fb8aa3b3878; SI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3fb8aa3b, v03879; SI-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v23880; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x32a5705f3881; SI-GISEL-NEXT: v_fma_f32 v1, v0, v3, v13882; SI-GISEL-NEXT: v_rndne_f32_e32 v3, v23883; SI-GISEL-NEXT: v_sub_f32_e32 v2, v2, v33884; SI-GISEL-NEXT: v_add_f32_e32 v1, v2, v13885; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v33886; SI-GISEL-NEXT: v_exp_f32_e32 v1, v13887; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f8000003888; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, v1, v23889; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed03890; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v23891; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42b172183892; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc3893; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v23894; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc3895; SI-GISEL-NEXT: s_setpc_b64 s[30:31]3896;3897; R600-LABEL: v_exp_f32_nnan:3898; R600: ; %bb.0:3899; R600-NEXT: CF_END3900; R600-NEXT: PAD3901;3902; CM-LABEL: v_exp_f32_nnan:3903; CM: ; %bb.0:3904; CM-NEXT: CF_END3905; CM-NEXT: PAD3906 %result = call nnan float @llvm.exp.f32(float %in)3907 ret float %result3908}3909 3910define float @v_exp_f32_nnan_daz(float %in) #0 {3911; VI-SDAG-LABEL: v_exp_f32_nnan_daz:3912; VI-SDAG: ; %bb.0:3913; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3914; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v03915; VI-SDAG-NEXT: v_sub_f32_e32 v4, v0, v13916; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v13917; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x39a3b295, v43918; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x3fb8a000, v43919; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v23920; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v53921; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v13922; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v33923; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v43924; VI-SDAG-NEXT: v_add_f32_e32 v1, v2, v13925; VI-SDAG-NEXT: v_exp_f32_e32 v1, v13926; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v33927; VI-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed03928; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v03929; VI-SDAG-NEXT: s_mov_b32 s4, 0x42b172183930; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v23931; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc3932; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f8000003933; VI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v03934; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc3935; VI-SDAG-NEXT: s_setpc_b64 s[30:31]3936;3937; VI-GISEL-LABEL: v_exp_f32_nnan_daz:3938; VI-GISEL: ; %bb.0:3939; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3940; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v03941; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v13942; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x39a3b295, v23943; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v23944; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3fb8a000, v13945; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v43946; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v13947; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v23948; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v33949; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v23950; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v13951; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v23952; VI-GISEL-NEXT: v_exp_f32_e32 v1, v13953; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f8000003954; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v23955; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed03956; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v23957; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42b172183958; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc3959; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v23960; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc3961; VI-GISEL-NEXT: s_setpc_b64 s[30:31]3962;3963; GFX900-SDAG-LABEL: v_exp_f32_nnan_daz:3964; GFX900-SDAG: ; %bb.0:3965; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3966; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v03967; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3fb8aa3b3968; GFX900-SDAG-NEXT: v_rndne_f32_e32 v2, v13969; GFX900-SDAG-NEXT: v_sub_f32_e32 v3, v1, v23970; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v13971; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x32a5705f3972; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, v13973; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v3, v13974; GFX900-SDAG-NEXT: v_exp_f32_e32 v1, v13975; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v23976; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed03977; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v03978; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x42b172183979; GFX900-SDAG-NEXT: v_ldexp_f32 v1, v1, v23980; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc3981; GFX900-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f8000003982; GFX900-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v03983; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc3984; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]3985;3986; GFX900-GISEL-LABEL: v_exp_f32_nnan_daz:3987; GFX900-GISEL: ; %bb.0:3988; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3989; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3fb8aa3b3990; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, 0x3fb8aa3b, v03991; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v23992; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x32a5705f3993; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v3, v13994; GFX900-GISEL-NEXT: v_rndne_f32_e32 v3, v23995; GFX900-GISEL-NEXT: v_sub_f32_e32 v2, v2, v33996; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v2, v13997; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v33998; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, v13999; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f8000004000; GFX900-GISEL-NEXT: v_ldexp_f32 v1, v1, v24001; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed04002; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v24003; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x42b172184004; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc4005; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v24006; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc4007; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]4008;4009; SI-SDAG-LABEL: v_exp_f32_nnan_daz:4010; SI-SDAG: ; %bb.0:4011; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4012; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v04013; SI-SDAG-NEXT: s_mov_b32 s4, 0x3fb8aa3b4014; SI-SDAG-NEXT: v_rndne_f32_e32 v2, v14015; SI-SDAG-NEXT: v_sub_f32_e32 v3, v1, v24016; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v14017; SI-SDAG-NEXT: s_mov_b32 s4, 0x32a5705f4018; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, v14019; SI-SDAG-NEXT: v_add_f32_e32 v1, v3, v14020; SI-SDAG-NEXT: v_exp_f32_e32 v1, v14021; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v24022; SI-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed04023; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v04024; SI-SDAG-NEXT: s_mov_b32 s4, 0x42b172184025; SI-SDAG-NEXT: v_ldexp_f32_e32 v1, v1, v24026; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc4027; SI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f8000004028; SI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v04029; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc4030; SI-SDAG-NEXT: s_setpc_b64 s[30:31]4031;4032; SI-GISEL-LABEL: v_exp_f32_nnan_daz:4033; SI-GISEL: ; %bb.0:4034; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4035; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3fb8aa3b4036; SI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3fb8aa3b, v04037; SI-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v24038; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x32a5705f4039; SI-GISEL-NEXT: v_fma_f32 v1, v0, v3, v14040; SI-GISEL-NEXT: v_rndne_f32_e32 v3, v24041; SI-GISEL-NEXT: v_sub_f32_e32 v2, v2, v34042; SI-GISEL-NEXT: v_add_f32_e32 v1, v2, v14043; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v34044; SI-GISEL-NEXT: v_exp_f32_e32 v1, v14045; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f8000004046; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, v1, v24047; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed04048; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v24049; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42b172184050; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc4051; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v24052; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc4053; SI-GISEL-NEXT: s_setpc_b64 s[30:31]4054;4055; R600-LABEL: v_exp_f32_nnan_daz:4056; R600: ; %bb.0:4057; R600-NEXT: CF_END4058; R600-NEXT: PAD4059;4060; CM-LABEL: v_exp_f32_nnan_daz:4061; CM: ; %bb.0:4062; CM-NEXT: CF_END4063; CM-NEXT: PAD4064 %result = call nnan float @llvm.exp.f32(float %in)4065 ret float %result4066}4067 4068define float @v_exp_f32_nnan_dynamic(float %in) #1 {4069; VI-SDAG-LABEL: v_exp_f32_nnan_dynamic:4070; VI-SDAG: ; %bb.0:4071; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4072; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v04073; VI-SDAG-NEXT: v_sub_f32_e32 v4, v0, v14074; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v14075; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x39a3b295, v44076; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x3fb8a000, v44077; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v24078; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v54079; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v14080; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v34081; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v44082; VI-SDAG-NEXT: v_add_f32_e32 v1, v2, v14083; VI-SDAG-NEXT: v_exp_f32_e32 v1, v14084; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v34085; VI-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed04086; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v04087; VI-SDAG-NEXT: s_mov_b32 s4, 0x42b172184088; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v24089; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc4090; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f8000004091; VI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v04092; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc4093; VI-SDAG-NEXT: s_setpc_b64 s[30:31]4094;4095; VI-GISEL-LABEL: v_exp_f32_nnan_dynamic:4096; VI-GISEL: ; %bb.0:4097; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4098; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v04099; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v14100; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x39a3b295, v24101; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v24102; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3fb8a000, v14103; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v44104; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v14105; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v24106; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v34107; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v24108; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v14109; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v24110; VI-GISEL-NEXT: v_exp_f32_e32 v1, v14111; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f8000004112; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v24113; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed04114; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v24115; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42b172184116; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc4117; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v24118; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc4119; VI-GISEL-NEXT: s_setpc_b64 s[30:31]4120;4121; GFX900-SDAG-LABEL: v_exp_f32_nnan_dynamic:4122; GFX900-SDAG: ; %bb.0:4123; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4124; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v04125; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3fb8aa3b4126; GFX900-SDAG-NEXT: v_rndne_f32_e32 v2, v14127; GFX900-SDAG-NEXT: v_sub_f32_e32 v3, v1, v24128; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v14129; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x32a5705f4130; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, v14131; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v3, v14132; GFX900-SDAG-NEXT: v_exp_f32_e32 v1, v14133; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v24134; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed04135; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v04136; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x42b172184137; GFX900-SDAG-NEXT: v_ldexp_f32 v1, v1, v24138; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc4139; GFX900-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f8000004140; GFX900-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v04141; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc4142; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]4143;4144; GFX900-GISEL-LABEL: v_exp_f32_nnan_dynamic:4145; GFX900-GISEL: ; %bb.0:4146; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4147; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3fb8aa3b4148; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, 0x3fb8aa3b, v04149; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v24150; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x32a5705f4151; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v3, v14152; GFX900-GISEL-NEXT: v_rndne_f32_e32 v3, v24153; GFX900-GISEL-NEXT: v_sub_f32_e32 v2, v2, v34154; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v2, v14155; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v34156; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, v14157; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f8000004158; GFX900-GISEL-NEXT: v_ldexp_f32 v1, v1, v24159; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed04160; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v24161; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x42b172184162; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc4163; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v24164; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc4165; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]4166;4167; SI-SDAG-LABEL: v_exp_f32_nnan_dynamic:4168; SI-SDAG: ; %bb.0:4169; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4170; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v04171; SI-SDAG-NEXT: s_mov_b32 s4, 0x3fb8aa3b4172; SI-SDAG-NEXT: v_rndne_f32_e32 v2, v14173; SI-SDAG-NEXT: v_sub_f32_e32 v3, v1, v24174; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v14175; SI-SDAG-NEXT: s_mov_b32 s4, 0x32a5705f4176; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, v14177; SI-SDAG-NEXT: v_add_f32_e32 v1, v3, v14178; SI-SDAG-NEXT: v_exp_f32_e32 v1, v14179; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v24180; SI-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed04181; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v04182; SI-SDAG-NEXT: s_mov_b32 s4, 0x42b172184183; SI-SDAG-NEXT: v_ldexp_f32_e32 v1, v1, v24184; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc4185; SI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f8000004186; SI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v04187; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc4188; SI-SDAG-NEXT: s_setpc_b64 s[30:31]4189;4190; SI-GISEL-LABEL: v_exp_f32_nnan_dynamic:4191; SI-GISEL: ; %bb.0:4192; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4193; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3fb8aa3b4194; SI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3fb8aa3b, v04195; SI-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v24196; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x32a5705f4197; SI-GISEL-NEXT: v_fma_f32 v1, v0, v3, v14198; SI-GISEL-NEXT: v_rndne_f32_e32 v3, v24199; SI-GISEL-NEXT: v_sub_f32_e32 v2, v2, v34200; SI-GISEL-NEXT: v_add_f32_e32 v1, v2, v14201; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v34202; SI-GISEL-NEXT: v_exp_f32_e32 v1, v14203; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f8000004204; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, v1, v24205; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed04206; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v24207; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42b172184208; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc4209; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v24210; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc4211; SI-GISEL-NEXT: s_setpc_b64 s[30:31]4212;4213; R600-LABEL: v_exp_f32_nnan_dynamic:4214; R600: ; %bb.0:4215; R600-NEXT: CF_END4216; R600-NEXT: PAD4217;4218; CM-LABEL: v_exp_f32_nnan_dynamic:4219; CM: ; %bb.0:4220; CM-NEXT: CF_END4221; CM-NEXT: PAD4222 %result = call nnan float @llvm.exp.f32(float %in)4223 ret float %result4224}4225 4226define float @v_exp_f32_ninf_daz(float %in) #0 {4227; VI-SDAG-LABEL: v_exp_f32_ninf_daz:4228; VI-SDAG: ; %bb.0:4229; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4230; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v04231; VI-SDAG-NEXT: v_sub_f32_e32 v4, v0, v14232; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v14233; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x39a3b295, v44234; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x3fb8a000, v44235; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v24236; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v54237; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v14238; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v34239; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v44240; VI-SDAG-NEXT: v_add_f32_e32 v1, v2, v14241; VI-SDAG-NEXT: v_exp_f32_e32 v1, v14242; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v34243; VI-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed04244; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v04245; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v24246; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc4247; VI-SDAG-NEXT: s_setpc_b64 s[30:31]4248;4249; VI-GISEL-LABEL: v_exp_f32_ninf_daz:4250; VI-GISEL: ; %bb.0:4251; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4252; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v04253; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v14254; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x39a3b295, v24255; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v24256; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3fb8a000, v14257; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v44258; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v14259; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v24260; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v34261; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v24262; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v14263; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v24264; VI-GISEL-NEXT: v_exp_f32_e32 v1, v14265; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v24266; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed04267; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v24268; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc4269; VI-GISEL-NEXT: s_setpc_b64 s[30:31]4270;4271; GFX900-SDAG-LABEL: v_exp_f32_ninf_daz:4272; GFX900-SDAG: ; %bb.0:4273; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4274; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v04275; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3fb8aa3b4276; GFX900-SDAG-NEXT: v_rndne_f32_e32 v2, v14277; GFX900-SDAG-NEXT: v_sub_f32_e32 v3, v1, v24278; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v14279; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x32a5705f4280; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, v14281; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v3, v14282; GFX900-SDAG-NEXT: v_exp_f32_e32 v1, v14283; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v24284; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed04285; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v04286; GFX900-SDAG-NEXT: v_ldexp_f32 v1, v1, v24287; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc4288; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]4289;4290; GFX900-GISEL-LABEL: v_exp_f32_ninf_daz:4291; GFX900-GISEL: ; %bb.0:4292; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4293; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3fb8aa3b4294; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, 0x3fb8aa3b, v04295; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v24296; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x32a5705f4297; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v3, v14298; GFX900-GISEL-NEXT: v_rndne_f32_e32 v3, v24299; GFX900-GISEL-NEXT: v_sub_f32_e32 v2, v2, v34300; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v2, v14301; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v34302; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, v14303; GFX900-GISEL-NEXT: v_ldexp_f32 v1, v1, v24304; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed04305; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v24306; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc4307; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]4308;4309; SI-SDAG-LABEL: v_exp_f32_ninf_daz:4310; SI-SDAG: ; %bb.0:4311; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4312; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v04313; SI-SDAG-NEXT: s_mov_b32 s4, 0x3fb8aa3b4314; SI-SDAG-NEXT: v_rndne_f32_e32 v2, v14315; SI-SDAG-NEXT: v_sub_f32_e32 v3, v1, v24316; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v14317; SI-SDAG-NEXT: s_mov_b32 s4, 0x32a5705f4318; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, v14319; SI-SDAG-NEXT: v_add_f32_e32 v1, v3, v14320; SI-SDAG-NEXT: v_exp_f32_e32 v1, v14321; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v24322; SI-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed04323; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v04324; SI-SDAG-NEXT: v_ldexp_f32_e32 v1, v1, v24325; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc4326; SI-SDAG-NEXT: s_setpc_b64 s[30:31]4327;4328; SI-GISEL-LABEL: v_exp_f32_ninf_daz:4329; SI-GISEL: ; %bb.0:4330; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4331; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3fb8aa3b4332; SI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3fb8aa3b, v04333; SI-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v24334; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x32a5705f4335; SI-GISEL-NEXT: v_fma_f32 v1, v0, v3, v14336; SI-GISEL-NEXT: v_rndne_f32_e32 v3, v24337; SI-GISEL-NEXT: v_sub_f32_e32 v2, v2, v34338; SI-GISEL-NEXT: v_add_f32_e32 v1, v2, v14339; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v34340; SI-GISEL-NEXT: v_exp_f32_e32 v1, v14341; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, v1, v24342; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed04343; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v24344; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc4345; SI-GISEL-NEXT: s_setpc_b64 s[30:31]4346;4347; R600-LABEL: v_exp_f32_ninf_daz:4348; R600: ; %bb.0:4349; R600-NEXT: CF_END4350; R600-NEXT: PAD4351;4352; CM-LABEL: v_exp_f32_ninf_daz:4353; CM: ; %bb.0:4354; CM-NEXT: CF_END4355; CM-NEXT: PAD4356 %result = call ninf float @llvm.exp.f32(float %in)4357 ret float %result4358}4359 4360define float @v_exp_f32_ninf_dynamic(float %in) #1 {4361; VI-SDAG-LABEL: v_exp_f32_ninf_dynamic:4362; VI-SDAG: ; %bb.0:4363; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4364; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v04365; VI-SDAG-NEXT: v_sub_f32_e32 v4, v0, v14366; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v14367; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x39a3b295, v44368; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x3fb8a000, v44369; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v24370; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v54371; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v14372; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v34373; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v44374; VI-SDAG-NEXT: v_add_f32_e32 v1, v2, v14375; VI-SDAG-NEXT: v_exp_f32_e32 v1, v14376; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v34377; VI-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed04378; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v04379; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v24380; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc4381; VI-SDAG-NEXT: s_setpc_b64 s[30:31]4382;4383; VI-GISEL-LABEL: v_exp_f32_ninf_dynamic:4384; VI-GISEL: ; %bb.0:4385; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4386; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v04387; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v14388; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x39a3b295, v24389; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v24390; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3fb8a000, v14391; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v44392; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v14393; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v24394; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v34395; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v24396; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v14397; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v24398; VI-GISEL-NEXT: v_exp_f32_e32 v1, v14399; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v24400; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed04401; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v24402; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc4403; VI-GISEL-NEXT: s_setpc_b64 s[30:31]4404;4405; GFX900-SDAG-LABEL: v_exp_f32_ninf_dynamic:4406; GFX900-SDAG: ; %bb.0:4407; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4408; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v04409; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3fb8aa3b4410; GFX900-SDAG-NEXT: v_rndne_f32_e32 v2, v14411; GFX900-SDAG-NEXT: v_sub_f32_e32 v3, v1, v24412; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v14413; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x32a5705f4414; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, v14415; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v3, v14416; GFX900-SDAG-NEXT: v_exp_f32_e32 v1, v14417; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v24418; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed04419; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v04420; GFX900-SDAG-NEXT: v_ldexp_f32 v1, v1, v24421; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc4422; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]4423;4424; GFX900-GISEL-LABEL: v_exp_f32_ninf_dynamic:4425; GFX900-GISEL: ; %bb.0:4426; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4427; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3fb8aa3b4428; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, 0x3fb8aa3b, v04429; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v24430; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x32a5705f4431; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v3, v14432; GFX900-GISEL-NEXT: v_rndne_f32_e32 v3, v24433; GFX900-GISEL-NEXT: v_sub_f32_e32 v2, v2, v34434; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v2, v14435; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v34436; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, v14437; GFX900-GISEL-NEXT: v_ldexp_f32 v1, v1, v24438; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed04439; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v24440; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc4441; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]4442;4443; SI-SDAG-LABEL: v_exp_f32_ninf_dynamic:4444; SI-SDAG: ; %bb.0:4445; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4446; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v04447; SI-SDAG-NEXT: s_mov_b32 s4, 0x3fb8aa3b4448; SI-SDAG-NEXT: v_rndne_f32_e32 v2, v14449; SI-SDAG-NEXT: v_sub_f32_e32 v3, v1, v24450; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v14451; SI-SDAG-NEXT: s_mov_b32 s4, 0x32a5705f4452; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, v14453; SI-SDAG-NEXT: v_add_f32_e32 v1, v3, v14454; SI-SDAG-NEXT: v_exp_f32_e32 v1, v14455; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v24456; SI-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed04457; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v04458; SI-SDAG-NEXT: v_ldexp_f32_e32 v1, v1, v24459; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc4460; SI-SDAG-NEXT: s_setpc_b64 s[30:31]4461;4462; SI-GISEL-LABEL: v_exp_f32_ninf_dynamic:4463; SI-GISEL: ; %bb.0:4464; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4465; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3fb8aa3b4466; SI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3fb8aa3b, v04467; SI-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v24468; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x32a5705f4469; SI-GISEL-NEXT: v_fma_f32 v1, v0, v3, v14470; SI-GISEL-NEXT: v_rndne_f32_e32 v3, v24471; SI-GISEL-NEXT: v_sub_f32_e32 v2, v2, v34472; SI-GISEL-NEXT: v_add_f32_e32 v1, v2, v14473; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v34474; SI-GISEL-NEXT: v_exp_f32_e32 v1, v14475; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, v1, v24476; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed04477; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v24478; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc4479; SI-GISEL-NEXT: s_setpc_b64 s[30:31]4480;4481; R600-LABEL: v_exp_f32_ninf_dynamic:4482; R600: ; %bb.0:4483; R600-NEXT: CF_END4484; R600-NEXT: PAD4485;4486; CM-LABEL: v_exp_f32_ninf_dynamic:4487; CM: ; %bb.0:4488; CM-NEXT: CF_END4489; CM-NEXT: PAD4490 %result = call ninf float @llvm.exp.f32(float %in)4491 ret float %result4492}4493 4494define float @v_exp_f32_nnan_ninf(float %in) {4495; VI-SDAG-LABEL: v_exp_f32_nnan_ninf:4496; VI-SDAG: ; %bb.0:4497; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4498; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v04499; VI-SDAG-NEXT: v_sub_f32_e32 v4, v0, v14500; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v14501; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x39a3b295, v44502; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x3fb8a000, v44503; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v24504; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v54505; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v14506; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v34507; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v44508; VI-SDAG-NEXT: v_add_f32_e32 v1, v2, v14509; VI-SDAG-NEXT: v_exp_f32_e32 v1, v14510; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v34511; VI-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed04512; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v04513; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v24514; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc4515; VI-SDAG-NEXT: s_setpc_b64 s[30:31]4516;4517; VI-GISEL-LABEL: v_exp_f32_nnan_ninf:4518; VI-GISEL: ; %bb.0:4519; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4520; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v04521; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v14522; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x39a3b295, v24523; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v24524; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3fb8a000, v14525; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v44526; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v14527; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v24528; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v34529; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v24530; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v14531; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v24532; VI-GISEL-NEXT: v_exp_f32_e32 v1, v14533; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v24534; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed04535; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v24536; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc4537; VI-GISEL-NEXT: s_setpc_b64 s[30:31]4538;4539; GFX900-SDAG-LABEL: v_exp_f32_nnan_ninf:4540; GFX900-SDAG: ; %bb.0:4541; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4542; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v04543; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3fb8aa3b4544; GFX900-SDAG-NEXT: v_rndne_f32_e32 v2, v14545; GFX900-SDAG-NEXT: v_sub_f32_e32 v3, v1, v24546; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v14547; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x32a5705f4548; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, v14549; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v3, v14550; GFX900-SDAG-NEXT: v_exp_f32_e32 v1, v14551; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v24552; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed04553; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v04554; GFX900-SDAG-NEXT: v_ldexp_f32 v1, v1, v24555; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc4556; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]4557;4558; GFX900-GISEL-LABEL: v_exp_f32_nnan_ninf:4559; GFX900-GISEL: ; %bb.0:4560; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4561; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3fb8aa3b4562; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, 0x3fb8aa3b, v04563; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v24564; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x32a5705f4565; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v3, v14566; GFX900-GISEL-NEXT: v_rndne_f32_e32 v3, v24567; GFX900-GISEL-NEXT: v_sub_f32_e32 v2, v2, v34568; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v2, v14569; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v34570; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, v14571; GFX900-GISEL-NEXT: v_ldexp_f32 v1, v1, v24572; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed04573; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v24574; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc4575; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]4576;4577; SI-SDAG-LABEL: v_exp_f32_nnan_ninf:4578; SI-SDAG: ; %bb.0:4579; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4580; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v04581; SI-SDAG-NEXT: s_mov_b32 s4, 0x3fb8aa3b4582; SI-SDAG-NEXT: v_rndne_f32_e32 v2, v14583; SI-SDAG-NEXT: v_sub_f32_e32 v3, v1, v24584; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v14585; SI-SDAG-NEXT: s_mov_b32 s4, 0x32a5705f4586; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, v14587; SI-SDAG-NEXT: v_add_f32_e32 v1, v3, v14588; SI-SDAG-NEXT: v_exp_f32_e32 v1, v14589; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v24590; SI-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed04591; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v04592; SI-SDAG-NEXT: v_ldexp_f32_e32 v1, v1, v24593; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc4594; SI-SDAG-NEXT: s_setpc_b64 s[30:31]4595;4596; SI-GISEL-LABEL: v_exp_f32_nnan_ninf:4597; SI-GISEL: ; %bb.0:4598; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4599; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3fb8aa3b4600; SI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3fb8aa3b, v04601; SI-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v24602; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x32a5705f4603; SI-GISEL-NEXT: v_fma_f32 v1, v0, v3, v14604; SI-GISEL-NEXT: v_rndne_f32_e32 v3, v24605; SI-GISEL-NEXT: v_sub_f32_e32 v2, v2, v34606; SI-GISEL-NEXT: v_add_f32_e32 v1, v2, v14607; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v34608; SI-GISEL-NEXT: v_exp_f32_e32 v1, v14609; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, v1, v24610; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed04611; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v24612; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc4613; SI-GISEL-NEXT: s_setpc_b64 s[30:31]4614;4615; R600-LABEL: v_exp_f32_nnan_ninf:4616; R600: ; %bb.0:4617; R600-NEXT: CF_END4618; R600-NEXT: PAD4619;4620; CM-LABEL: v_exp_f32_nnan_ninf:4621; CM: ; %bb.0:4622; CM-NEXT: CF_END4623; CM-NEXT: PAD4624 %result = call nnan ninf float @llvm.exp.f32(float %in)4625 ret float %result4626}4627 4628define float @v_exp_f32_nnan_ninf_daz(float %in) #0 {4629; VI-SDAG-LABEL: v_exp_f32_nnan_ninf_daz:4630; VI-SDAG: ; %bb.0:4631; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4632; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v04633; VI-SDAG-NEXT: v_sub_f32_e32 v4, v0, v14634; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v14635; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x39a3b295, v44636; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x3fb8a000, v44637; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v24638; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v54639; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v14640; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v34641; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v44642; VI-SDAG-NEXT: v_add_f32_e32 v1, v2, v14643; VI-SDAG-NEXT: v_exp_f32_e32 v1, v14644; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v34645; VI-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed04646; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v04647; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v24648; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc4649; VI-SDAG-NEXT: s_setpc_b64 s[30:31]4650;4651; VI-GISEL-LABEL: v_exp_f32_nnan_ninf_daz:4652; VI-GISEL: ; %bb.0:4653; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4654; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v04655; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v14656; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x39a3b295, v24657; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v24658; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3fb8a000, v14659; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v44660; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v14661; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v24662; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v34663; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v24664; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v14665; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v24666; VI-GISEL-NEXT: v_exp_f32_e32 v1, v14667; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v24668; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed04669; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v24670; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc4671; VI-GISEL-NEXT: s_setpc_b64 s[30:31]4672;4673; GFX900-SDAG-LABEL: v_exp_f32_nnan_ninf_daz:4674; GFX900-SDAG: ; %bb.0:4675; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4676; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v04677; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3fb8aa3b4678; GFX900-SDAG-NEXT: v_rndne_f32_e32 v2, v14679; GFX900-SDAG-NEXT: v_sub_f32_e32 v3, v1, v24680; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v14681; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x32a5705f4682; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, v14683; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v3, v14684; GFX900-SDAG-NEXT: v_exp_f32_e32 v1, v14685; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v24686; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed04687; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v04688; GFX900-SDAG-NEXT: v_ldexp_f32 v1, v1, v24689; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc4690; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]4691;4692; GFX900-GISEL-LABEL: v_exp_f32_nnan_ninf_daz:4693; GFX900-GISEL: ; %bb.0:4694; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4695; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3fb8aa3b4696; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, 0x3fb8aa3b, v04697; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v24698; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x32a5705f4699; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v3, v14700; GFX900-GISEL-NEXT: v_rndne_f32_e32 v3, v24701; GFX900-GISEL-NEXT: v_sub_f32_e32 v2, v2, v34702; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v2, v14703; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v34704; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, v14705; GFX900-GISEL-NEXT: v_ldexp_f32 v1, v1, v24706; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed04707; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v24708; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc4709; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]4710;4711; SI-SDAG-LABEL: v_exp_f32_nnan_ninf_daz:4712; SI-SDAG: ; %bb.0:4713; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4714; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v04715; SI-SDAG-NEXT: s_mov_b32 s4, 0x3fb8aa3b4716; SI-SDAG-NEXT: v_rndne_f32_e32 v2, v14717; SI-SDAG-NEXT: v_sub_f32_e32 v3, v1, v24718; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v14719; SI-SDAG-NEXT: s_mov_b32 s4, 0x32a5705f4720; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, v14721; SI-SDAG-NEXT: v_add_f32_e32 v1, v3, v14722; SI-SDAG-NEXT: v_exp_f32_e32 v1, v14723; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v24724; SI-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed04725; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v04726; SI-SDAG-NEXT: v_ldexp_f32_e32 v1, v1, v24727; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc4728; SI-SDAG-NEXT: s_setpc_b64 s[30:31]4729;4730; SI-GISEL-LABEL: v_exp_f32_nnan_ninf_daz:4731; SI-GISEL: ; %bb.0:4732; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4733; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3fb8aa3b4734; SI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3fb8aa3b, v04735; SI-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v24736; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x32a5705f4737; SI-GISEL-NEXT: v_fma_f32 v1, v0, v3, v14738; SI-GISEL-NEXT: v_rndne_f32_e32 v3, v24739; SI-GISEL-NEXT: v_sub_f32_e32 v2, v2, v34740; SI-GISEL-NEXT: v_add_f32_e32 v1, v2, v14741; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v34742; SI-GISEL-NEXT: v_exp_f32_e32 v1, v14743; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, v1, v24744; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed04745; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v24746; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc4747; SI-GISEL-NEXT: s_setpc_b64 s[30:31]4748;4749; R600-LABEL: v_exp_f32_nnan_ninf_daz:4750; R600: ; %bb.0:4751; R600-NEXT: CF_END4752; R600-NEXT: PAD4753;4754; CM-LABEL: v_exp_f32_nnan_ninf_daz:4755; CM: ; %bb.0:4756; CM-NEXT: CF_END4757; CM-NEXT: PAD4758 %result = call nnan ninf float @llvm.exp.f32(float %in)4759 ret float %result4760}4761 4762define float @v_exp_f32_nnan_ninf_dynamic(float %in) #1 {4763; VI-SDAG-LABEL: v_exp_f32_nnan_ninf_dynamic:4764; VI-SDAG: ; %bb.0:4765; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4766; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v04767; VI-SDAG-NEXT: v_sub_f32_e32 v4, v0, v14768; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v14769; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x39a3b295, v44770; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x3fb8a000, v44771; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v24772; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v54773; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v14774; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v34775; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v44776; VI-SDAG-NEXT: v_add_f32_e32 v1, v2, v14777; VI-SDAG-NEXT: v_exp_f32_e32 v1, v14778; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v34779; VI-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed04780; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v04781; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v24782; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc4783; VI-SDAG-NEXT: s_setpc_b64 s[30:31]4784;4785; VI-GISEL-LABEL: v_exp_f32_nnan_ninf_dynamic:4786; VI-GISEL: ; %bb.0:4787; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4788; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v04789; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v14790; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x39a3b295, v24791; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v24792; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3fb8a000, v14793; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v44794; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v14795; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v24796; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v34797; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v24798; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v14799; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v24800; VI-GISEL-NEXT: v_exp_f32_e32 v1, v14801; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v24802; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed04803; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v24804; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc4805; VI-GISEL-NEXT: s_setpc_b64 s[30:31]4806;4807; GFX900-SDAG-LABEL: v_exp_f32_nnan_ninf_dynamic:4808; GFX900-SDAG: ; %bb.0:4809; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4810; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v04811; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3fb8aa3b4812; GFX900-SDAG-NEXT: v_rndne_f32_e32 v2, v14813; GFX900-SDAG-NEXT: v_sub_f32_e32 v3, v1, v24814; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v14815; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x32a5705f4816; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, v14817; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v3, v14818; GFX900-SDAG-NEXT: v_exp_f32_e32 v1, v14819; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v24820; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed04821; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v04822; GFX900-SDAG-NEXT: v_ldexp_f32 v1, v1, v24823; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc4824; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]4825;4826; GFX900-GISEL-LABEL: v_exp_f32_nnan_ninf_dynamic:4827; GFX900-GISEL: ; %bb.0:4828; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4829; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3fb8aa3b4830; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, 0x3fb8aa3b, v04831; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v24832; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x32a5705f4833; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v3, v14834; GFX900-GISEL-NEXT: v_rndne_f32_e32 v3, v24835; GFX900-GISEL-NEXT: v_sub_f32_e32 v2, v2, v34836; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v2, v14837; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v34838; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, v14839; GFX900-GISEL-NEXT: v_ldexp_f32 v1, v1, v24840; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed04841; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v24842; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc4843; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]4844;4845; SI-SDAG-LABEL: v_exp_f32_nnan_ninf_dynamic:4846; SI-SDAG: ; %bb.0:4847; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4848; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v04849; SI-SDAG-NEXT: s_mov_b32 s4, 0x3fb8aa3b4850; SI-SDAG-NEXT: v_rndne_f32_e32 v2, v14851; SI-SDAG-NEXT: v_sub_f32_e32 v3, v1, v24852; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v14853; SI-SDAG-NEXT: s_mov_b32 s4, 0x32a5705f4854; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, v14855; SI-SDAG-NEXT: v_add_f32_e32 v1, v3, v14856; SI-SDAG-NEXT: v_exp_f32_e32 v1, v14857; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v24858; SI-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed04859; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v04860; SI-SDAG-NEXT: v_ldexp_f32_e32 v1, v1, v24861; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc4862; SI-SDAG-NEXT: s_setpc_b64 s[30:31]4863;4864; SI-GISEL-LABEL: v_exp_f32_nnan_ninf_dynamic:4865; SI-GISEL: ; %bb.0:4866; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4867; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3fb8aa3b4868; SI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3fb8aa3b, v04869; SI-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v24870; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x32a5705f4871; SI-GISEL-NEXT: v_fma_f32 v1, v0, v3, v14872; SI-GISEL-NEXT: v_rndne_f32_e32 v3, v24873; SI-GISEL-NEXT: v_sub_f32_e32 v2, v2, v34874; SI-GISEL-NEXT: v_add_f32_e32 v1, v2, v14875; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v34876; SI-GISEL-NEXT: v_exp_f32_e32 v1, v14877; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, v1, v24878; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed04879; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v24880; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc4881; SI-GISEL-NEXT: s_setpc_b64 s[30:31]4882;4883; R600-LABEL: v_exp_f32_nnan_ninf_dynamic:4884; R600: ; %bb.0:4885; R600-NEXT: CF_END4886; R600-NEXT: PAD4887;4888; CM-LABEL: v_exp_f32_nnan_ninf_dynamic:4889; CM: ; %bb.0:4890; CM-NEXT: CF_END4891; CM-NEXT: PAD4892 %result = call nnan ninf float @llvm.exp.f32(float %in)4893 ret float %result4894}4895 4896define float @v_exp_f32_fast_daz(float %in) #0 {4897; GCN-LABEL: v_exp_f32_fast_daz:4898; GCN: ; %bb.0:4899; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4900; GCN-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v04901; GCN-NEXT: v_exp_f32_e32 v0, v04902; GCN-NEXT: s_setpc_b64 s[30:31]4903;4904; SI-LABEL: v_exp_f32_fast_daz:4905; SI: ; %bb.0:4906; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4907; SI-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v04908; SI-NEXT: v_exp_f32_e32 v0, v04909; SI-NEXT: s_setpc_b64 s[30:31]4910;4911; R600-LABEL: v_exp_f32_fast_daz:4912; R600: ; %bb.0:4913; R600-NEXT: CF_END4914; R600-NEXT: PAD4915;4916; CM-LABEL: v_exp_f32_fast_daz:4917; CM: ; %bb.0:4918; CM-NEXT: CF_END4919; CM-NEXT: PAD4920 %result = call fast float @llvm.exp.f32(float %in)4921 ret float %result4922}4923 4924define float @v_exp_f32_dynamic_mode(float %in) #1 {4925; VI-SDAG-LABEL: v_exp_f32_dynamic_mode:4926; VI-SDAG: ; %bb.0:4927; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4928; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v04929; VI-SDAG-NEXT: v_sub_f32_e32 v4, v0, v14930; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v14931; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x39a3b295, v44932; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x3fb8a000, v44933; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v24934; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v54935; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v14936; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v34937; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v44938; VI-SDAG-NEXT: v_add_f32_e32 v1, v2, v14939; VI-SDAG-NEXT: v_exp_f32_e32 v1, v14940; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v34941; VI-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed04942; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v04943; VI-SDAG-NEXT: s_mov_b32 s4, 0x42b172184944; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v24945; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc4946; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f8000004947; VI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v04948; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc4949; VI-SDAG-NEXT: s_setpc_b64 s[30:31]4950;4951; VI-GISEL-LABEL: v_exp_f32_dynamic_mode:4952; VI-GISEL: ; %bb.0:4953; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4954; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v04955; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v14956; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x39a3b295, v24957; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v24958; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3fb8a000, v14959; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v44960; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v14961; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v24962; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v34963; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v24964; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v14965; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v24966; VI-GISEL-NEXT: v_exp_f32_e32 v1, v14967; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f8000004968; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v24969; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed04970; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v24971; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42b172184972; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc4973; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v24974; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc4975; VI-GISEL-NEXT: s_setpc_b64 s[30:31]4976;4977; GFX900-SDAG-LABEL: v_exp_f32_dynamic_mode:4978; GFX900-SDAG: ; %bb.0:4979; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4980; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v04981; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3fb8aa3b4982; GFX900-SDAG-NEXT: v_rndne_f32_e32 v2, v14983; GFX900-SDAG-NEXT: v_sub_f32_e32 v3, v1, v24984; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v14985; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x32a5705f4986; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, v14987; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v3, v14988; GFX900-SDAG-NEXT: v_exp_f32_e32 v1, v14989; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v24990; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed04991; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v04992; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x42b172184993; GFX900-SDAG-NEXT: v_ldexp_f32 v1, v1, v24994; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc4995; GFX900-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f8000004996; GFX900-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v04997; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc4998; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]4999;5000; GFX900-GISEL-LABEL: v_exp_f32_dynamic_mode:5001; GFX900-GISEL: ; %bb.0:5002; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5003; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3fb8aa3b5004; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, 0x3fb8aa3b, v05005; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v25006; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x32a5705f5007; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v3, v15008; GFX900-GISEL-NEXT: v_rndne_f32_e32 v3, v25009; GFX900-GISEL-NEXT: v_sub_f32_e32 v2, v2, v35010; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v2, v15011; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v35012; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, v15013; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f8000005014; GFX900-GISEL-NEXT: v_ldexp_f32 v1, v1, v25015; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed05016; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v25017; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x42b172185018; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc5019; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v25020; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc5021; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]5022;5023; SI-SDAG-LABEL: v_exp_f32_dynamic_mode:5024; SI-SDAG: ; %bb.0:5025; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5026; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v05027; SI-SDAG-NEXT: s_mov_b32 s4, 0x3fb8aa3b5028; SI-SDAG-NEXT: v_rndne_f32_e32 v2, v15029; SI-SDAG-NEXT: v_sub_f32_e32 v3, v1, v25030; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v15031; SI-SDAG-NEXT: s_mov_b32 s4, 0x32a5705f5032; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, v15033; SI-SDAG-NEXT: v_add_f32_e32 v1, v3, v15034; SI-SDAG-NEXT: v_exp_f32_e32 v1, v15035; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v25036; SI-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed05037; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v05038; SI-SDAG-NEXT: s_mov_b32 s4, 0x42b172185039; SI-SDAG-NEXT: v_ldexp_f32_e32 v1, v1, v25040; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc5041; SI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f8000005042; SI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v05043; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc5044; SI-SDAG-NEXT: s_setpc_b64 s[30:31]5045;5046; SI-GISEL-LABEL: v_exp_f32_dynamic_mode:5047; SI-GISEL: ; %bb.0:5048; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5049; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3fb8aa3b5050; SI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3fb8aa3b, v05051; SI-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v25052; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x32a5705f5053; SI-GISEL-NEXT: v_fma_f32 v1, v0, v3, v15054; SI-GISEL-NEXT: v_rndne_f32_e32 v3, v25055; SI-GISEL-NEXT: v_sub_f32_e32 v2, v2, v35056; SI-GISEL-NEXT: v_add_f32_e32 v1, v2, v15057; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v35058; SI-GISEL-NEXT: v_exp_f32_e32 v1, v15059; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f8000005060; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, v1, v25061; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed05062; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v25063; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42b172185064; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc5065; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v25066; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc5067; SI-GISEL-NEXT: s_setpc_b64 s[30:31]5068;5069; R600-LABEL: v_exp_f32_dynamic_mode:5070; R600: ; %bb.0:5071; R600-NEXT: CF_END5072; R600-NEXT: PAD5073;5074; CM-LABEL: v_exp_f32_dynamic_mode:5075; CM: ; %bb.0:5076; CM-NEXT: CF_END5077; CM-NEXT: PAD5078 %result = call float @llvm.exp.f32(float %in)5079 ret float %result5080}5081 5082define float @v_exp_f32_undef() {5083; GCN-LABEL: v_exp_f32_undef:5084; GCN: ; %bb.0:5085; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5086; GCN-NEXT: s_setpc_b64 s[30:31]5087;5088; SI-LABEL: v_exp_f32_undef:5089; SI: ; %bb.0:5090; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5091; SI-NEXT: s_setpc_b64 s[30:31]5092;5093; R600-LABEL: v_exp_f32_undef:5094; R600: ; %bb.0:5095; R600-NEXT: CF_END5096; R600-NEXT: PAD5097;5098; CM-LABEL: v_exp_f32_undef:5099; CM: ; %bb.0:5100; CM-NEXT: CF_END5101; CM-NEXT: PAD5102 %result = call float @llvm.exp.f32(float poison)5103 ret float %result5104}5105 5106define float @v_exp_f32_0() {5107; GCN-LABEL: v_exp_f32_0:5108; GCN: ; %bb.0:5109; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5110; GCN-NEXT: v_mov_b32_e32 v0, 1.05111; GCN-NEXT: s_setpc_b64 s[30:31]5112;5113; SI-LABEL: v_exp_f32_0:5114; SI: ; %bb.0:5115; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5116; SI-NEXT: v_mov_b32_e32 v0, 1.05117; SI-NEXT: s_setpc_b64 s[30:31]5118;5119; R600-LABEL: v_exp_f32_0:5120; R600: ; %bb.0:5121; R600-NEXT: CF_END5122; R600-NEXT: PAD5123;5124; CM-LABEL: v_exp_f32_0:5125; CM: ; %bb.0:5126; CM-NEXT: CF_END5127; CM-NEXT: PAD5128 %result = call float @llvm.exp.f32(float 0.0)5129 ret float %result5130}5131 5132define float @v_exp_f32_from_fpext_f16(i16 %src.i) {5133; VI-SDAG-LABEL: v_exp_f32_from_fpext_f16:5134; VI-SDAG: ; %bb.0:5135; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5136; VI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v05137; VI-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed05138; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v05139; VI-SDAG-NEXT: v_sub_f32_e32 v3, v0, v15140; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v15141; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x39a3b295, v35142; VI-SDAG-NEXT: v_mul_f32_e32 v3, 0x3fb8a000, v35143; VI-SDAG-NEXT: v_rndne_f32_e32 v4, v25144; VI-SDAG-NEXT: v_add_f32_e32 v3, v3, v55145; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v15146; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v45147; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v35148; VI-SDAG-NEXT: v_add_f32_e32 v1, v2, v15149; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v45150; VI-SDAG-NEXT: v_exp_f32_e32 v1, v15151; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v05152; VI-SDAG-NEXT: s_mov_b32 s4, 0x42b172185153; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v25154; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc5155; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f8000005156; VI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v05157; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc5158; VI-SDAG-NEXT: s_setpc_b64 s[30:31]5159;5160; VI-GISEL-LABEL: v_exp_f32_from_fpext_f16:5161; VI-GISEL: ; %bb.0:5162; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5163; VI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v05164; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v05165; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v15166; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x39a3b295, v25167; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v25168; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3fb8a000, v15169; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v15170; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v45171; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v25172; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v35173; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v25174; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v15175; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v25176; VI-GISEL-NEXT: v_exp_f32_e32 v1, v15177; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f8000005178; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v25179; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed05180; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v25181; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42b172185182; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc5183; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v25184; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc5185; VI-GISEL-NEXT: s_setpc_b64 s[30:31]5186;5187; GFX900-SDAG-LABEL: v_exp_f32_from_fpext_f16:5188; GFX900-SDAG: ; %bb.0:5189; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5190; GFX900-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v05191; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3fb8aa3b5192; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x32a5705f5193; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v05194; GFX900-SDAG-NEXT: v_rndne_f32_e32 v2, v15195; GFX900-SDAG-NEXT: v_fma_f32 v3, v0, s4, -v15196; GFX900-SDAG-NEXT: v_sub_f32_e32 v1, v1, v25197; GFX900-SDAG-NEXT: v_fma_f32 v3, v0, s5, v35198; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v1, v35199; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v25200; GFX900-SDAG-NEXT: v_exp_f32_e32 v1, v15201; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed05202; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v05203; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x42b172185204; GFX900-SDAG-NEXT: v_ldexp_f32 v1, v1, v25205; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc5206; GFX900-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f8000005207; GFX900-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v05208; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc5209; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]5210;5211; GFX900-GISEL-LABEL: v_exp_f32_from_fpext_f16:5212; GFX900-GISEL: ; %bb.0:5213; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5214; GFX900-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v05215; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3fb8aa3b5216; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x32a5705f5217; GFX900-GISEL-NEXT: v_mul_f32_e32 v3, 0x3fb8aa3b, v05218; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v35219; GFX900-GISEL-NEXT: v_rndne_f32_e32 v4, v35220; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v2, v15221; GFX900-GISEL-NEXT: v_sub_f32_e32 v2, v3, v45222; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v2, v15223; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v45224; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, v15225; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0xc2ce8ed05226; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v35227; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f8000005228; GFX900-GISEL-NEXT: v_ldexp_f32 v1, v1, v25229; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x42b172185230; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc5231; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v25232; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc5233; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]5234;5235; SI-SDAG-LABEL: v_exp_f32_from_fpext_f16:5236; SI-SDAG: ; %bb.0:5237; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5238; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v05239; SI-SDAG-NEXT: s_mov_b32 s4, 0x3fb8aa3b5240; SI-SDAG-NEXT: s_mov_b32 s5, 0x32a5705f5241; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v05242; SI-SDAG-NEXT: v_rndne_f32_e32 v2, v15243; SI-SDAG-NEXT: v_fma_f32 v3, v0, s4, -v15244; SI-SDAG-NEXT: v_sub_f32_e32 v1, v1, v25245; SI-SDAG-NEXT: v_fma_f32 v3, v0, s5, v35246; SI-SDAG-NEXT: v_add_f32_e32 v1, v1, v35247; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v25248; SI-SDAG-NEXT: v_exp_f32_e32 v1, v15249; SI-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed05250; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v05251; SI-SDAG-NEXT: s_mov_b32 s4, 0x42b172185252; SI-SDAG-NEXT: v_ldexp_f32_e32 v1, v1, v25253; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc5254; SI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f8000005255; SI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v05256; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc5257; SI-SDAG-NEXT: s_setpc_b64 s[30:31]5258;5259; SI-GISEL-LABEL: v_exp_f32_from_fpext_f16:5260; SI-GISEL: ; %bb.0:5261; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5262; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v05263; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3fb8aa3b5264; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x32a5705f5265; SI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3fb8aa3b, v05266; SI-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v35267; SI-GISEL-NEXT: v_rndne_f32_e32 v4, v35268; SI-GISEL-NEXT: v_fma_f32 v1, v0, v2, v15269; SI-GISEL-NEXT: v_sub_f32_e32 v2, v3, v45270; SI-GISEL-NEXT: v_add_f32_e32 v1, v2, v15271; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v45272; SI-GISEL-NEXT: v_exp_f32_e32 v1, v15273; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0xc2ce8ed05274; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v35275; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f8000005276; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, v1, v25277; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42b172185278; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc5279; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v25280; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc5281; SI-GISEL-NEXT: s_setpc_b64 s[30:31]5282;5283; R600-LABEL: v_exp_f32_from_fpext_f16:5284; R600: ; %bb.0:5285; R600-NEXT: CF_END5286; R600-NEXT: PAD5287;5288; CM-LABEL: v_exp_f32_from_fpext_f16:5289; CM: ; %bb.0:5290; CM-NEXT: CF_END5291; CM-NEXT: PAD5292 %src = bitcast i16 %src.i to half5293 %fpext = fpext half %src to float5294 %result = call float @llvm.exp.f32(float %fpext)5295 ret float %result5296}5297 5298define float @v_exp_f32_from_fpext_math_f16(i16 %src0.i, i16 %src1.i) {5299; VI-SDAG-LABEL: v_exp_f32_from_fpext_math_f16:5300; VI-SDAG: ; %bb.0:5301; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5302; VI-SDAG-NEXT: v_add_f16_e32 v0, v0, v15303; VI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v05304; VI-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed05305; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v05306; VI-SDAG-NEXT: v_sub_f32_e32 v2, v0, v15307; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x39a3b295, v25308; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v25309; VI-SDAG-NEXT: v_mul_f32_e32 v3, 0x39a3b295, v15310; VI-SDAG-NEXT: v_add_f32_e32 v2, v2, v45311; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8a000, v15312; VI-SDAG-NEXT: v_add_f32_e32 v2, v3, v25313; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v15314; VI-SDAG-NEXT: v_sub_f32_e32 v1, v1, v35315; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v25316; VI-SDAG-NEXT: v_exp_f32_e32 v1, v15317; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v35318; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v05319; VI-SDAG-NEXT: s_mov_b32 s4, 0x42b172185320; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v25321; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc5322; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f8000005323; VI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v05324; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc5325; VI-SDAG-NEXT: s_setpc_b64 s[30:31]5326;5327; VI-GISEL-LABEL: v_exp_f32_from_fpext_math_f16:5328; VI-GISEL: ; %bb.0:5329; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5330; VI-GISEL-NEXT: v_add_f16_e32 v0, v0, v15331; VI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v05332; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v05333; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v15334; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x39a3b295, v25335; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v25336; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3fb8a000, v15337; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v45338; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v15339; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v25340; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v35341; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v25342; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v15343; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v25344; VI-GISEL-NEXT: v_exp_f32_e32 v1, v15345; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f8000005346; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v25347; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed05348; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v25349; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42b172185350; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc5351; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v25352; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc5353; VI-GISEL-NEXT: s_setpc_b64 s[30:31]5354;5355; GFX900-SDAG-LABEL: v_exp_f32_from_fpext_math_f16:5356; GFX900-SDAG: ; %bb.0:5357; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5358; GFX900-SDAG-NEXT: v_add_f16_e32 v0, v0, v15359; GFX900-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v05360; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3fb8aa3b5361; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x32a5705f5362; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v05363; GFX900-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v15364; GFX900-SDAG-NEXT: v_rndne_f32_e32 v3, v15365; GFX900-SDAG-NEXT: v_fma_f32 v2, v0, s5, v25366; GFX900-SDAG-NEXT: v_sub_f32_e32 v1, v1, v35367; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v1, v25368; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v35369; GFX900-SDAG-NEXT: v_exp_f32_e32 v1, v15370; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed05371; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v05372; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x42b172185373; GFX900-SDAG-NEXT: v_ldexp_f32 v1, v1, v25374; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc5375; GFX900-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f8000005376; GFX900-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v05377; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc5378; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]5379;5380; GFX900-GISEL-LABEL: v_exp_f32_from_fpext_math_f16:5381; GFX900-GISEL: ; %bb.0:5382; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5383; GFX900-GISEL-NEXT: v_add_f16_e32 v0, v0, v15384; GFX900-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v05385; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3fb8aa3b5386; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x32a5705f5387; GFX900-GISEL-NEXT: v_mul_f32_e32 v3, 0x3fb8aa3b, v05388; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v35389; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v2, v15390; GFX900-GISEL-NEXT: v_rndne_f32_e32 v2, v35391; GFX900-GISEL-NEXT: v_sub_f32_e32 v3, v3, v25392; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v3, v15393; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v25394; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, v15395; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f8000005396; GFX900-GISEL-NEXT: v_ldexp_f32 v1, v1, v25397; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed05398; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v25399; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x42b172185400; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc5401; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v25402; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc5403; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]5404;5405; SI-SDAG-LABEL: v_exp_f32_from_fpext_math_f16:5406; SI-SDAG: ; %bb.0:5407; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5408; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v05409; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v15410; SI-SDAG-NEXT: s_mov_b32 s4, 0x3fb8aa3b5411; SI-SDAG-NEXT: v_add_f32_e32 v0, v0, v15412; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v05413; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v15414; SI-SDAG-NEXT: s_mov_b32 s4, 0x32a5705f5415; SI-SDAG-NEXT: v_rndne_f32_e32 v3, v15416; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, v25417; SI-SDAG-NEXT: v_sub_f32_e32 v1, v1, v35418; SI-SDAG-NEXT: v_add_f32_e32 v1, v1, v25419; SI-SDAG-NEXT: v_exp_f32_e32 v1, v15420; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v35421; SI-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed05422; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v05423; SI-SDAG-NEXT: s_mov_b32 s4, 0x42b172185424; SI-SDAG-NEXT: v_ldexp_f32_e32 v1, v1, v25425; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc5426; SI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f8000005427; SI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v05428; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc5429; SI-SDAG-NEXT: s_setpc_b64 s[30:31]5430;5431; SI-GISEL-LABEL: v_exp_f32_from_fpext_math_f16:5432; SI-GISEL: ; %bb.0:5433; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5434; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v05435; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v15436; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x32a5705f5437; SI-GISEL-NEXT: v_mov_b32_e32 v5, 0x7f8000005438; SI-GISEL-NEXT: v_add_f32_e32 v0, v0, v15439; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v05440; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3fb8aa3b5441; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v05442; SI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3fb8aa3b, v05443; SI-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v35444; SI-GISEL-NEXT: v_rndne_f32_e32 v4, v35445; SI-GISEL-NEXT: v_fma_f32 v1, v0, v2, v15446; SI-GISEL-NEXT: v_sub_f32_e32 v2, v3, v45447; SI-GISEL-NEXT: v_add_f32_e32 v1, v2, v15448; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v3, v45449; SI-GISEL-NEXT: v_exp_f32_e32 v1, v15450; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed05451; SI-GISEL-NEXT: v_mov_b32_e32 v4, 0x42b172185452; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v25453; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, v1, v35454; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc5455; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v45456; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v5, vcc5457; SI-GISEL-NEXT: s_setpc_b64 s[30:31]5458;5459; R600-LABEL: v_exp_f32_from_fpext_math_f16:5460; R600: ; %bb.0:5461; R600-NEXT: CF_END5462; R600-NEXT: PAD5463;5464; CM-LABEL: v_exp_f32_from_fpext_math_f16:5465; CM: ; %bb.0:5466; CM-NEXT: CF_END5467; CM-NEXT: PAD5468 %src0 = bitcast i16 %src0.i to half5469 %src1 = bitcast i16 %src1.i to half5470 %fadd = fadd half %src0, %src15471 %fpext = fpext half %fadd to float5472 %result = call float @llvm.exp.f32(float %fpext)5473 ret float %result5474}5475 5476define float @v_exp_f32_from_fpext_bf16(bfloat %src) {5477; VI-LABEL: v_exp_f32_from_fpext_bf16:5478; VI: ; %bb.0:5479; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5480; VI-NEXT: v_lshlrev_b32_e32 v0, 16, v05481; VI-NEXT: v_sub_f32_e32 v3, v0, v05482; VI-NEXT: v_mul_f32_e32 v1, 0x3fb8a000, v05483; VI-NEXT: v_mul_f32_e32 v4, 0x39a3b295, v35484; VI-NEXT: v_mul_f32_e32 v3, 0x3fb8a000, v35485; VI-NEXT: v_rndne_f32_e32 v2, v15486; VI-NEXT: v_add_f32_e32 v3, v3, v45487; VI-NEXT: v_mul_f32_e32 v4, 0x39a3b295, v05488; VI-NEXT: v_sub_f32_e32 v1, v1, v25489; VI-NEXT: v_add_f32_e32 v3, v4, v35490; VI-NEXT: v_add_f32_e32 v1, v1, v35491; VI-NEXT: v_exp_f32_e32 v1, v15492; VI-NEXT: v_cvt_i32_f32_e32 v2, v25493; VI-NEXT: s_mov_b32 s4, 0xc2ce8ed05494; VI-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v05495; VI-NEXT: s_mov_b32 s4, 0x42b172185496; VI-NEXT: v_ldexp_f32 v1, v1, v25497; VI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc5498; VI-NEXT: v_mov_b32_e32 v2, 0x7f8000005499; VI-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v05500; VI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc5501; VI-NEXT: s_setpc_b64 s[30:31]5502;5503; GFX900-LABEL: v_exp_f32_from_fpext_bf16:5504; GFX900: ; %bb.0:5505; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5506; GFX900-NEXT: v_lshlrev_b32_e32 v0, 16, v05507; GFX900-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v05508; GFX900-NEXT: s_mov_b32 s4, 0x3fb8aa3b5509; GFX900-NEXT: v_rndne_f32_e32 v2, v15510; GFX900-NEXT: v_sub_f32_e32 v3, v1, v25511; GFX900-NEXT: v_fma_f32 v1, v0, s4, -v15512; GFX900-NEXT: s_mov_b32 s4, 0x32a5705f5513; GFX900-NEXT: v_fma_f32 v1, v0, s4, v15514; GFX900-NEXT: v_add_f32_e32 v1, v3, v15515; GFX900-NEXT: v_exp_f32_e32 v1, v15516; GFX900-NEXT: v_cvt_i32_f32_e32 v2, v25517; GFX900-NEXT: s_mov_b32 s4, 0xc2ce8ed05518; GFX900-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v05519; GFX900-NEXT: s_mov_b32 s4, 0x42b172185520; GFX900-NEXT: v_ldexp_f32 v1, v1, v25521; GFX900-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc5522; GFX900-NEXT: v_mov_b32_e32 v2, 0x7f8000005523; GFX900-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v05524; GFX900-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc5525; GFX900-NEXT: s_setpc_b64 s[30:31]5526;5527; SI-LABEL: v_exp_f32_from_fpext_bf16:5528; SI: ; %bb.0:5529; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5530; SI-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v05531; SI-NEXT: s_mov_b32 s4, 0x3fb8aa3b5532; SI-NEXT: v_rndne_f32_e32 v2, v15533; SI-NEXT: v_sub_f32_e32 v3, v1, v25534; SI-NEXT: v_fma_f32 v1, v0, s4, -v15535; SI-NEXT: s_mov_b32 s4, 0x32a5705f5536; SI-NEXT: v_fma_f32 v1, v0, s4, v15537; SI-NEXT: v_add_f32_e32 v1, v3, v15538; SI-NEXT: v_exp_f32_e32 v1, v15539; SI-NEXT: v_cvt_i32_f32_e32 v2, v25540; SI-NEXT: s_mov_b32 s4, 0xc2ce8ed05541; SI-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v05542; SI-NEXT: s_mov_b32 s4, 0x42b172185543; SI-NEXT: v_ldexp_f32_e32 v1, v1, v25544; SI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc5545; SI-NEXT: v_mov_b32_e32 v2, 0x7f8000005546; SI-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v05547; SI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc5548; SI-NEXT: s_setpc_b64 s[30:31]5549;5550; R600-LABEL: v_exp_f32_from_fpext_bf16:5551; R600: ; %bb.0:5552; R600-NEXT: CF_END5553; R600-NEXT: PAD5554;5555; CM-LABEL: v_exp_f32_from_fpext_bf16:5556; CM: ; %bb.0:5557; CM-NEXT: CF_END5558; CM-NEXT: PAD5559 %fpext = fpext bfloat %src to float5560 %result = call float @llvm.exp.f32(float %fpext)5561 ret float %result5562}5563 5564define float @v_exp_f32_from_fpext_math_f16_fast(i16 %src0.i, i16 %src1.i) {5565; GCN-LABEL: v_exp_f32_from_fpext_math_f16_fast:5566; GCN: ; %bb.0:5567; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5568; GCN-NEXT: v_add_f16_e32 v0, v0, v15569; GCN-NEXT: v_cvt_f32_f16_e32 v0, v05570; GCN-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v05571; GCN-NEXT: v_exp_f32_e32 v0, v05572; GCN-NEXT: s_setpc_b64 s[30:31]5573;5574; SI-SDAG-LABEL: v_exp_f32_from_fpext_math_f16_fast:5575; SI-SDAG: ; %bb.0:5576; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5577; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v05578; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v15579; SI-SDAG-NEXT: s_mov_b32 s4, 0xc2aeac505580; SI-SDAG-NEXT: v_add_f32_e32 v0, v0, v15581; SI-SDAG-NEXT: v_add_f32_e32 v1, 0x42800000, v05582; SI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v05583; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc5584; SI-SDAG-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v05585; SI-SDAG-NEXT: v_exp_f32_e32 v0, v05586; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x114b4ea4, v05587; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc5588; SI-SDAG-NEXT: s_setpc_b64 s[30:31]5589;5590; SI-GISEL-LABEL: v_exp_f32_from_fpext_math_f16_fast:5591; SI-GISEL: ; %bb.0:5592; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5593; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v05594; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v15595; SI-GISEL-NEXT: v_add_f32_e32 v0, v0, v15596; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v05597; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v05598; SI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v05599; SI-GISEL-NEXT: v_exp_f32_e32 v0, v05600; SI-GISEL-NEXT: s_setpc_b64 s[30:31]5601;5602; R600-LABEL: v_exp_f32_from_fpext_math_f16_fast:5603; R600: ; %bb.0:5604; R600-NEXT: CF_END5605; R600-NEXT: PAD5606;5607; CM-LABEL: v_exp_f32_from_fpext_math_f16_fast:5608; CM: ; %bb.0:5609; CM-NEXT: CF_END5610; CM-NEXT: PAD5611 %src0 = bitcast i16 %src0.i to half5612 %src1 = bitcast i16 %src1.i to half5613 %fadd = fadd half %src0, %src15614 %fpext = fpext half %fadd to float5615 %result = call fast float @llvm.exp.f32(float %fpext)5616 ret float %result5617}5618 5619define float @v_exp_f32_from_fpext_math_f16_daz(i16 %src0.i, i16 %src1.i) #0 {5620; VI-SDAG-LABEL: v_exp_f32_from_fpext_math_f16_daz:5621; VI-SDAG: ; %bb.0:5622; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5623; VI-SDAG-NEXT: v_add_f16_e32 v0, v0, v15624; VI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v05625; VI-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed05626; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v05627; VI-SDAG-NEXT: v_sub_f32_e32 v2, v0, v15628; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x39a3b295, v25629; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v25630; VI-SDAG-NEXT: v_mul_f32_e32 v3, 0x39a3b295, v15631; VI-SDAG-NEXT: v_add_f32_e32 v2, v2, v45632; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8a000, v15633; VI-SDAG-NEXT: v_add_f32_e32 v2, v3, v25634; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v15635; VI-SDAG-NEXT: v_sub_f32_e32 v1, v1, v35636; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v25637; VI-SDAG-NEXT: v_exp_f32_e32 v1, v15638; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v35639; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v05640; VI-SDAG-NEXT: s_mov_b32 s4, 0x42b172185641; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v25642; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc5643; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f8000005644; VI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v05645; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc5646; VI-SDAG-NEXT: s_setpc_b64 s[30:31]5647;5648; VI-GISEL-LABEL: v_exp_f32_from_fpext_math_f16_daz:5649; VI-GISEL: ; %bb.0:5650; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5651; VI-GISEL-NEXT: v_add_f16_e32 v0, v0, v15652; VI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v05653; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v05654; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v15655; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x39a3b295, v25656; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v25657; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3fb8a000, v15658; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v45659; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v15660; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v25661; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v35662; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v25663; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v15664; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v25665; VI-GISEL-NEXT: v_exp_f32_e32 v1, v15666; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f8000005667; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v25668; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed05669; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v25670; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42b172185671; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc5672; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v25673; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc5674; VI-GISEL-NEXT: s_setpc_b64 s[30:31]5675;5676; GFX900-SDAG-LABEL: v_exp_f32_from_fpext_math_f16_daz:5677; GFX900-SDAG: ; %bb.0:5678; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5679; GFX900-SDAG-NEXT: v_add_f16_e32 v0, v0, v15680; GFX900-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v05681; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3fb8aa3b5682; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x32a5705f5683; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v05684; GFX900-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v15685; GFX900-SDAG-NEXT: v_rndne_f32_e32 v3, v15686; GFX900-SDAG-NEXT: v_fma_f32 v2, v0, s5, v25687; GFX900-SDAG-NEXT: v_sub_f32_e32 v1, v1, v35688; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v1, v25689; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v35690; GFX900-SDAG-NEXT: v_exp_f32_e32 v1, v15691; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed05692; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v05693; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x42b172185694; GFX900-SDAG-NEXT: v_ldexp_f32 v1, v1, v25695; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc5696; GFX900-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f8000005697; GFX900-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v05698; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc5699; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]5700;5701; GFX900-GISEL-LABEL: v_exp_f32_from_fpext_math_f16_daz:5702; GFX900-GISEL: ; %bb.0:5703; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5704; GFX900-GISEL-NEXT: v_add_f16_e32 v0, v0, v15705; GFX900-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v05706; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3fb8aa3b5707; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x32a5705f5708; GFX900-GISEL-NEXT: v_mul_f32_e32 v3, 0x3fb8aa3b, v05709; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v35710; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v2, v15711; GFX900-GISEL-NEXT: v_rndne_f32_e32 v2, v35712; GFX900-GISEL-NEXT: v_sub_f32_e32 v3, v3, v25713; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v3, v15714; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v25715; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, v15716; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f8000005717; GFX900-GISEL-NEXT: v_ldexp_f32 v1, v1, v25718; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed05719; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v25720; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x42b172185721; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc5722; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v25723; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc5724; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]5725;5726; SI-SDAG-LABEL: v_exp_f32_from_fpext_math_f16_daz:5727; SI-SDAG: ; %bb.0:5728; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5729; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v05730; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v15731; SI-SDAG-NEXT: s_mov_b32 s4, 0x3fb8aa3b5732; SI-SDAG-NEXT: v_add_f32_e32 v0, v0, v15733; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v05734; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v15735; SI-SDAG-NEXT: s_mov_b32 s4, 0x32a5705f5736; SI-SDAG-NEXT: v_rndne_f32_e32 v3, v15737; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, v25738; SI-SDAG-NEXT: v_sub_f32_e32 v1, v1, v35739; SI-SDAG-NEXT: v_add_f32_e32 v1, v1, v25740; SI-SDAG-NEXT: v_exp_f32_e32 v1, v15741; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v35742; SI-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed05743; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v05744; SI-SDAG-NEXT: s_mov_b32 s4, 0x42b172185745; SI-SDAG-NEXT: v_ldexp_f32_e32 v1, v1, v25746; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc5747; SI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f8000005748; SI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v05749; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc5750; SI-SDAG-NEXT: s_setpc_b64 s[30:31]5751;5752; SI-GISEL-LABEL: v_exp_f32_from_fpext_math_f16_daz:5753; SI-GISEL: ; %bb.0:5754; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5755; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v05756; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v15757; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x32a5705f5758; SI-GISEL-NEXT: v_mov_b32_e32 v5, 0x7f8000005759; SI-GISEL-NEXT: v_add_f32_e32 v0, v0, v15760; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v05761; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3fb8aa3b5762; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v05763; SI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3fb8aa3b, v05764; SI-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v35765; SI-GISEL-NEXT: v_rndne_f32_e32 v4, v35766; SI-GISEL-NEXT: v_fma_f32 v1, v0, v2, v15767; SI-GISEL-NEXT: v_sub_f32_e32 v2, v3, v45768; SI-GISEL-NEXT: v_add_f32_e32 v1, v2, v15769; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v3, v45770; SI-GISEL-NEXT: v_exp_f32_e32 v1, v15771; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed05772; SI-GISEL-NEXT: v_mov_b32_e32 v4, 0x42b172185773; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v25774; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, v1, v35775; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc5776; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v45777; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v5, vcc5778; SI-GISEL-NEXT: s_setpc_b64 s[30:31]5779;5780; R600-LABEL: v_exp_f32_from_fpext_math_f16_daz:5781; R600: ; %bb.0:5782; R600-NEXT: CF_END5783; R600-NEXT: PAD5784;5785; CM-LABEL: v_exp_f32_from_fpext_math_f16_daz:5786; CM: ; %bb.0:5787; CM-NEXT: CF_END5788; CM-NEXT: PAD5789 %src0 = bitcast i16 %src0.i to half5790 %src1 = bitcast i16 %src1.i to half5791 %fadd = fadd half %src0, %src15792 %fpext = fpext half %fadd to float5793 %result = call float @llvm.exp.f32(float %fpext)5794 ret float %result5795}5796 5797; FIXME: Fold out fp16_to_fp (FP_TO_FP16) on no-f16 targets5798define half @v_exp_f16(half %in) {5799; GCN-LABEL: v_exp_f16:5800; GCN: ; %bb.0:5801; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5802; GCN-NEXT: v_cvt_f32_f16_e32 v0, v05803; GCN-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v05804; GCN-NEXT: v_exp_f32_e32 v0, v05805; GCN-NEXT: v_cvt_f16_f32_e32 v0, v05806; GCN-NEXT: s_setpc_b64 s[30:31]5807;5808; SI-SDAG-LABEL: v_exp_f16:5809; SI-SDAG: ; %bb.0:5810; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5811; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v05812; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v05813; SI-SDAG-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v05814; SI-SDAG-NEXT: v_exp_f32_e32 v0, v05815; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v05816; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v05817; SI-SDAG-NEXT: s_setpc_b64 s[30:31]5818;5819; SI-GISEL-LABEL: v_exp_f16:5820; SI-GISEL: ; %bb.0:5821; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5822; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v05823; SI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v05824; SI-GISEL-NEXT: v_exp_f32_e32 v0, v05825; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v05826; SI-GISEL-NEXT: s_setpc_b64 s[30:31]5827;5828; R600-LABEL: v_exp_f16:5829; R600: ; %bb.0:5830; R600-NEXT: CF_END5831; R600-NEXT: PAD5832;5833; CM-LABEL: v_exp_f16:5834; CM: ; %bb.0:5835; CM-NEXT: CF_END5836; CM-NEXT: PAD5837 %result = call half @llvm.exp.f16(half %in)5838 ret half %result5839}5840 5841define half @v_exp_fabs_f16(half %in) {5842; GCN-LABEL: v_exp_fabs_f16:5843; GCN: ; %bb.0:5844; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5845; GCN-NEXT: v_cvt_f32_f16_e64 v0, |v0|5846; GCN-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v05847; GCN-NEXT: v_exp_f32_e32 v0, v05848; GCN-NEXT: v_cvt_f16_f32_e32 v0, v05849; GCN-NEXT: s_setpc_b64 s[30:31]5850;5851; SI-SDAG-LABEL: v_exp_fabs_f16:5852; SI-SDAG: ; %bb.0:5853; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5854; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v05855; SI-SDAG-NEXT: v_cvt_f32_f16_e64 v0, |v0|5856; SI-SDAG-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v05857; SI-SDAG-NEXT: v_exp_f32_e32 v0, v05858; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v05859; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v05860; SI-SDAG-NEXT: s_setpc_b64 s[30:31]5861;5862; SI-GISEL-LABEL: v_exp_fabs_f16:5863; SI-GISEL: ; %bb.0:5864; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5865; SI-GISEL-NEXT: v_cvt_f32_f16_e64 v0, |v0|5866; SI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v05867; SI-GISEL-NEXT: v_exp_f32_e32 v0, v05868; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v05869; SI-GISEL-NEXT: s_setpc_b64 s[30:31]5870;5871; R600-LABEL: v_exp_fabs_f16:5872; R600: ; %bb.0:5873; R600-NEXT: CF_END5874; R600-NEXT: PAD5875;5876; CM-LABEL: v_exp_fabs_f16:5877; CM: ; %bb.0:5878; CM-NEXT: CF_END5879; CM-NEXT: PAD5880 %fabs = call half @llvm.fabs.f16(half %in)5881 %result = call half @llvm.exp.f16(half %fabs)5882 ret half %result5883}5884 5885define half @v_exp_fneg_fabs_f16(half %in) {5886; GCN-SDAG-LABEL: v_exp_fneg_fabs_f16:5887; GCN-SDAG: ; %bb.0:5888; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5889; GCN-SDAG-NEXT: v_cvt_f32_f16_e64 v0, |v0|5890; GCN-SDAG-NEXT: v_mul_f32_e32 v0, 0xbfb8aa3b, v05891; GCN-SDAG-NEXT: v_exp_f32_e32 v0, v05892; GCN-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v05893; GCN-SDAG-NEXT: s_setpc_b64 s[30:31]5894;5895; GCN-GISEL-LABEL: v_exp_fneg_fabs_f16:5896; GCN-GISEL: ; %bb.0:5897; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5898; GCN-GISEL-NEXT: v_cvt_f32_f16_e64 v0, -|v0|5899; GCN-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v05900; GCN-GISEL-NEXT: v_exp_f32_e32 v0, v05901; GCN-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v05902; GCN-GISEL-NEXT: s_setpc_b64 s[30:31]5903;5904; SI-SDAG-LABEL: v_exp_fneg_fabs_f16:5905; SI-SDAG: ; %bb.0:5906; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5907; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v05908; SI-SDAG-NEXT: v_cvt_f32_f16_e64 v0, |v0|5909; SI-SDAG-NEXT: v_mul_f32_e32 v0, 0xbfb8aa3b, v05910; SI-SDAG-NEXT: v_exp_f32_e32 v0, v05911; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v05912; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v05913; SI-SDAG-NEXT: s_setpc_b64 s[30:31]5914;5915; SI-GISEL-LABEL: v_exp_fneg_fabs_f16:5916; SI-GISEL: ; %bb.0:5917; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5918; SI-GISEL-NEXT: v_cvt_f32_f16_e64 v0, -|v0|5919; SI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v05920; SI-GISEL-NEXT: v_exp_f32_e32 v0, v05921; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v05922; SI-GISEL-NEXT: s_setpc_b64 s[30:31]5923;5924; R600-LABEL: v_exp_fneg_fabs_f16:5925; R600: ; %bb.0:5926; R600-NEXT: CF_END5927; R600-NEXT: PAD5928;5929; CM-LABEL: v_exp_fneg_fabs_f16:5930; CM: ; %bb.0:5931; CM-NEXT: CF_END5932; CM-NEXT: PAD5933 %fabs = call half @llvm.fabs.f16(half %in)5934 %fneg.fabs = fneg half %fabs5935 %result = call half @llvm.exp.f16(half %fneg.fabs)5936 ret half %result5937}5938 5939define half @v_exp_fneg_f16(half %in) {5940; GCN-SDAG-LABEL: v_exp_fneg_f16:5941; GCN-SDAG: ; %bb.0:5942; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5943; GCN-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v05944; GCN-SDAG-NEXT: v_mul_f32_e32 v0, 0xbfb8aa3b, v05945; GCN-SDAG-NEXT: v_exp_f32_e32 v0, v05946; GCN-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v05947; GCN-SDAG-NEXT: s_setpc_b64 s[30:31]5948;5949; GCN-GISEL-LABEL: v_exp_fneg_f16:5950; GCN-GISEL: ; %bb.0:5951; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5952; GCN-GISEL-NEXT: v_cvt_f32_f16_e64 v0, -v05953; GCN-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v05954; GCN-GISEL-NEXT: v_exp_f32_e32 v0, v05955; GCN-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v05956; GCN-GISEL-NEXT: s_setpc_b64 s[30:31]5957;5958; SI-SDAG-LABEL: v_exp_fneg_f16:5959; SI-SDAG: ; %bb.0:5960; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5961; SI-SDAG-NEXT: v_cvt_f16_f32_e64 v0, -v05962; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v05963; SI-SDAG-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v05964; SI-SDAG-NEXT: v_exp_f32_e32 v0, v05965; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v05966; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v05967; SI-SDAG-NEXT: s_setpc_b64 s[30:31]5968;5969; SI-GISEL-LABEL: v_exp_fneg_f16:5970; SI-GISEL: ; %bb.0:5971; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5972; SI-GISEL-NEXT: v_cvt_f32_f16_e64 v0, -v05973; SI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v05974; SI-GISEL-NEXT: v_exp_f32_e32 v0, v05975; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v05976; SI-GISEL-NEXT: s_setpc_b64 s[30:31]5977;5978; R600-LABEL: v_exp_fneg_f16:5979; R600: ; %bb.0:5980; R600-NEXT: CF_END5981; R600-NEXT: PAD5982;5983; CM-LABEL: v_exp_fneg_f16:5984; CM: ; %bb.0:5985; CM-NEXT: CF_END5986; CM-NEXT: PAD5987 %fneg = fneg half %in5988 %result = call half @llvm.exp.f16(half %fneg)5989 ret half %result5990}5991 5992define half @v_exp_f16_fast(half %in) {5993; GCN-LABEL: v_exp_f16_fast:5994; GCN: ; %bb.0:5995; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5996; GCN-NEXT: v_mul_f16_e32 v0, 0x3dc5, v05997; GCN-NEXT: v_exp_f16_e32 v0, v05998; GCN-NEXT: s_setpc_b64 s[30:31]5999;6000; SI-SDAG-LABEL: v_exp_f16_fast:6001; SI-SDAG: ; %bb.0:6002; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6003; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v06004; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v06005; SI-SDAG-NEXT: v_mul_f32_e32 v0, 0x3fb8a000, v06006; SI-SDAG-NEXT: v_exp_f32_e32 v0, v06007; SI-SDAG-NEXT: s_setpc_b64 s[30:31]6008;6009; SI-GISEL-LABEL: v_exp_f16_fast:6010; SI-GISEL: ; %bb.0:6011; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6012; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v06013; SI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8a000, v06014; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v06015; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v06016; SI-GISEL-NEXT: v_exp_f32_e32 v0, v06017; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v06018; SI-GISEL-NEXT: s_setpc_b64 s[30:31]6019;6020; R600-LABEL: v_exp_f16_fast:6021; R600: ; %bb.0:6022; R600-NEXT: CF_END6023; R600-NEXT: PAD6024;6025; CM-LABEL: v_exp_f16_fast:6026; CM: ; %bb.0:6027; CM-NEXT: CF_END6028; CM-NEXT: PAD6029 %result = call fast half @llvm.exp.f16(half %in)6030 ret half %result6031}6032 6033define <2 x half> @v_exp_v2f16(<2 x half> %in) {6034; VI-SDAG-LABEL: v_exp_v2f16:6035; VI-SDAG: ; %bb.0:6036; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6037; VI-SDAG-NEXT: v_cvt_f32_f16_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_16038; VI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v06039; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v16040; VI-SDAG-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v06041; VI-SDAG-NEXT: v_exp_f32_e32 v1, v16042; VI-SDAG-NEXT: v_exp_f32_e32 v0, v06043; VI-SDAG-NEXT: v_cvt_f16_f32_sdwa v1, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD6044; VI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v06045; VI-SDAG-NEXT: v_or_b32_e32 v0, v0, v16046; VI-SDAG-NEXT: s_setpc_b64 s[30:31]6047;6048; VI-GISEL-LABEL: v_exp_v2f16:6049; VI-GISEL: ; %bb.0:6050; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6051; VI-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v06052; VI-GISEL-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_16053; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v16054; VI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v06055; VI-GISEL-NEXT: v_exp_f32_e32 v1, v16056; VI-GISEL-NEXT: v_exp_f32_e32 v0, v06057; VI-GISEL-NEXT: v_cvt_f16_f32_e32 v1, v16058; VI-GISEL-NEXT: v_cvt_f16_f32_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD6059; VI-GISEL-NEXT: v_or_b32_e32 v0, v1, v06060; VI-GISEL-NEXT: s_setpc_b64 s[30:31]6061;6062; GFX900-LABEL: v_exp_v2f16:6063; GFX900: ; %bb.0:6064; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6065; GFX900-NEXT: v_cvt_f32_f16_e32 v1, v06066; GFX900-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_16067; GFX900-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v16068; GFX900-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v06069; GFX900-NEXT: v_exp_f32_e32 v1, v16070; GFX900-NEXT: v_exp_f32_e32 v0, v06071; GFX900-NEXT: v_cvt_f16_f32_e32 v1, v16072; GFX900-NEXT: v_cvt_f16_f32_e32 v0, v06073; GFX900-NEXT: v_pack_b32_f16 v0, v1, v06074; GFX900-NEXT: s_setpc_b64 s[30:31]6075;6076; SI-SDAG-LABEL: v_exp_v2f16:6077; SI-SDAG: ; %bb.0:6078; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6079; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v06080; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v1, v16081; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v06082; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v16083; SI-SDAG-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v06084; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v16085; SI-SDAG-NEXT: v_exp_f32_e32 v0, v06086; SI-SDAG-NEXT: v_exp_f32_e32 v1, v16087; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v06088; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v1, v16089; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v06090; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v16091; SI-SDAG-NEXT: s_setpc_b64 s[30:31]6092;6093; SI-GISEL-LABEL: v_exp_v2f16:6094; SI-GISEL: ; %bb.0:6095; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6096; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v06097; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v16098; SI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v06099; SI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v16100; SI-GISEL-NEXT: v_exp_f32_e32 v0, v06101; SI-GISEL-NEXT: v_exp_f32_e32 v1, v16102; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v06103; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v1, v16104; SI-GISEL-NEXT: s_setpc_b64 s[30:31]6105;6106; R600-LABEL: v_exp_v2f16:6107; R600: ; %bb.0:6108; R600-NEXT: CF_END6109; R600-NEXT: PAD6110;6111; CM-LABEL: v_exp_v2f16:6112; CM: ; %bb.0:6113; CM-NEXT: CF_END6114; CM-NEXT: PAD6115 %result = call <2 x half> @llvm.exp.v2f16(<2 x half> %in)6116 ret <2 x half> %result6117}6118 6119define <2 x half> @v_exp_fabs_v2f16(<2 x half> %in) {6120; VI-SDAG-LABEL: v_exp_fabs_v2f16:6121; VI-SDAG: ; %bb.0:6122; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6123; VI-SDAG-NEXT: v_cvt_f32_f16_sdwa v1, |v0| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_16124; VI-SDAG-NEXT: v_cvt_f32_f16_e64 v0, |v0|6125; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v16126; VI-SDAG-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v06127; VI-SDAG-NEXT: v_exp_f32_e32 v1, v16128; VI-SDAG-NEXT: v_exp_f32_e32 v0, v06129; VI-SDAG-NEXT: v_cvt_f16_f32_sdwa v1, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD6130; VI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v06131; VI-SDAG-NEXT: v_or_b32_e32 v0, v0, v16132; VI-SDAG-NEXT: s_setpc_b64 s[30:31]6133;6134; VI-GISEL-LABEL: v_exp_fabs_v2f16:6135; VI-GISEL: ; %bb.0:6136; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6137; VI-GISEL-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v06138; VI-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v06139; VI-GISEL-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_16140; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v16141; VI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v06142; VI-GISEL-NEXT: v_exp_f32_e32 v1, v16143; VI-GISEL-NEXT: v_exp_f32_e32 v0, v06144; VI-GISEL-NEXT: v_cvt_f16_f32_e32 v1, v16145; VI-GISEL-NEXT: v_cvt_f16_f32_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD6146; VI-GISEL-NEXT: v_or_b32_e32 v0, v1, v06147; VI-GISEL-NEXT: s_setpc_b64 s[30:31]6148;6149; GFX900-SDAG-LABEL: v_exp_fabs_v2f16:6150; GFX900-SDAG: ; %bb.0:6151; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6152; GFX900-SDAG-NEXT: v_cvt_f32_f16_e64 v1, |v0|6153; GFX900-SDAG-NEXT: v_cvt_f32_f16_sdwa v0, |v0| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_16154; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v16155; GFX900-SDAG-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v06156; GFX900-SDAG-NEXT: v_exp_f32_e32 v1, v16157; GFX900-SDAG-NEXT: v_exp_f32_e32 v0, v06158; GFX900-SDAG-NEXT: v_cvt_f16_f32_e32 v1, v16159; GFX900-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v06160; GFX900-SDAG-NEXT: v_pack_b32_f16 v0, v1, v06161; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]6162;6163; GFX900-GISEL-LABEL: v_exp_fabs_v2f16:6164; GFX900-GISEL: ; %bb.0:6165; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6166; GFX900-GISEL-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v06167; GFX900-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v06168; GFX900-GISEL-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_16169; GFX900-GISEL-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v16170; GFX900-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v06171; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, v16172; GFX900-GISEL-NEXT: v_exp_f32_e32 v0, v06173; GFX900-GISEL-NEXT: v_cvt_f16_f32_e32 v1, v16174; GFX900-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v06175; GFX900-GISEL-NEXT: v_pack_b32_f16 v0, v1, v06176; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]6177;6178; SI-SDAG-LABEL: v_exp_fabs_v2f16:6179; SI-SDAG: ; %bb.0:6180; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6181; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v06182; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v1, v16183; SI-SDAG-NEXT: v_cvt_f32_f16_e64 v0, |v0|6184; SI-SDAG-NEXT: v_cvt_f32_f16_e64 v1, |v1|6185; SI-SDAG-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v06186; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v16187; SI-SDAG-NEXT: v_exp_f32_e32 v0, v06188; SI-SDAG-NEXT: v_exp_f32_e32 v1, v16189; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v06190; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v1, v16191; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v06192; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v16193; SI-SDAG-NEXT: s_setpc_b64 s[30:31]6194;6195; SI-GISEL-LABEL: v_exp_fabs_v2f16:6196; SI-GISEL: ; %bb.0:6197; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6198; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v16199; SI-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v06200; SI-GISEL-NEXT: v_or_b32_e32 v0, v1, v06201; SI-GISEL-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v06202; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v06203; SI-GISEL-NEXT: v_lshrrev_b32_e32 v0, 16, v06204; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v06205; SI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v16206; SI-GISEL-NEXT: v_exp_f32_e32 v1, v16207; SI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v06208; SI-GISEL-NEXT: v_exp_f32_e32 v2, v06209; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v16210; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v1, v26211; SI-GISEL-NEXT: s_setpc_b64 s[30:31]6212;6213; R600-LABEL: v_exp_fabs_v2f16:6214; R600: ; %bb.0:6215; R600-NEXT: CF_END6216; R600-NEXT: PAD6217;6218; CM-LABEL: v_exp_fabs_v2f16:6219; CM: ; %bb.0:6220; CM-NEXT: CF_END6221; CM-NEXT: PAD6222 %fabs = call <2 x half> @llvm.fabs.v2f16(<2 x half> %in)6223 %result = call <2 x half> @llvm.exp.v2f16(<2 x half> %fabs)6224 ret <2 x half> %result6225}6226 6227define <2 x half> @v_exp_fneg_fabs_v2f16(<2 x half> %in) {6228; VI-SDAG-LABEL: v_exp_fneg_fabs_v2f16:6229; VI-SDAG: ; %bb.0:6230; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6231; VI-SDAG-NEXT: v_cvt_f32_f16_sdwa v1, -|v0| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_16232; VI-SDAG-NEXT: v_cvt_f32_f16_e64 v0, -|v0|6233; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v16234; VI-SDAG-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v06235; VI-SDAG-NEXT: v_exp_f32_e32 v1, v16236; VI-SDAG-NEXT: v_exp_f32_e32 v0, v06237; VI-SDAG-NEXT: v_cvt_f16_f32_sdwa v1, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD6238; VI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v06239; VI-SDAG-NEXT: v_or_b32_e32 v0, v0, v16240; VI-SDAG-NEXT: s_setpc_b64 s[30:31]6241;6242; VI-GISEL-LABEL: v_exp_fneg_fabs_v2f16:6243; VI-GISEL: ; %bb.0:6244; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6245; VI-GISEL-NEXT: v_or_b32_e32 v0, 0x80008000, v06246; VI-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v06247; VI-GISEL-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_16248; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v16249; VI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v06250; VI-GISEL-NEXT: v_exp_f32_e32 v1, v16251; VI-GISEL-NEXT: v_exp_f32_e32 v0, v06252; VI-GISEL-NEXT: v_cvt_f16_f32_e32 v1, v16253; VI-GISEL-NEXT: v_cvt_f16_f32_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD6254; VI-GISEL-NEXT: v_or_b32_e32 v0, v1, v06255; VI-GISEL-NEXT: s_setpc_b64 s[30:31]6256;6257; GFX900-SDAG-LABEL: v_exp_fneg_fabs_v2f16:6258; GFX900-SDAG: ; %bb.0:6259; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6260; GFX900-SDAG-NEXT: v_cvt_f32_f16_e64 v1, -|v0|6261; GFX900-SDAG-NEXT: v_cvt_f32_f16_sdwa v0, -|v0| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_16262; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v16263; GFX900-SDAG-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v06264; GFX900-SDAG-NEXT: v_exp_f32_e32 v1, v16265; GFX900-SDAG-NEXT: v_exp_f32_e32 v0, v06266; GFX900-SDAG-NEXT: v_cvt_f16_f32_e32 v1, v16267; GFX900-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v06268; GFX900-SDAG-NEXT: v_pack_b32_f16 v0, v1, v06269; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]6270;6271; GFX900-GISEL-LABEL: v_exp_fneg_fabs_v2f16:6272; GFX900-GISEL: ; %bb.0:6273; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6274; GFX900-GISEL-NEXT: v_or_b32_e32 v0, 0x80008000, v06275; GFX900-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v06276; GFX900-GISEL-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_16277; GFX900-GISEL-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v16278; GFX900-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v06279; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, v16280; GFX900-GISEL-NEXT: v_exp_f32_e32 v0, v06281; GFX900-GISEL-NEXT: v_cvt_f16_f32_e32 v1, v16282; GFX900-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v06283; GFX900-GISEL-NEXT: v_pack_b32_f16 v0, v1, v06284; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]6285;6286; SI-SDAG-LABEL: v_exp_fneg_fabs_v2f16:6287; SI-SDAG: ; %bb.0:6288; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6289; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v1, v16290; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v06291; SI-SDAG-NEXT: v_lshlrev_b32_e32 v1, 16, v16292; SI-SDAG-NEXT: v_or_b32_e32 v0, v0, v16293; SI-SDAG-NEXT: v_or_b32_e32 v0, 0x80008000, v06294; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v06295; SI-SDAG-NEXT: v_lshrrev_b32_e32 v0, 16, v06296; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v06297; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v16298; SI-SDAG-NEXT: v_exp_f32_e32 v1, v16299; SI-SDAG-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v06300; SI-SDAG-NEXT: v_exp_f32_e32 v0, v06301; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v1, v16302; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v2, v06303; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v16304; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v26305; SI-SDAG-NEXT: s_setpc_b64 s[30:31]6306;6307; SI-GISEL-LABEL: v_exp_fneg_fabs_v2f16:6308; SI-GISEL: ; %bb.0:6309; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6310; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v16311; SI-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v06312; SI-GISEL-NEXT: v_or_b32_e32 v0, v1, v06313; SI-GISEL-NEXT: v_or_b32_e32 v0, 0x80008000, v06314; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v06315; SI-GISEL-NEXT: v_lshrrev_b32_e32 v0, 16, v06316; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v06317; SI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v16318; SI-GISEL-NEXT: v_exp_f32_e32 v1, v16319; SI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v06320; SI-GISEL-NEXT: v_exp_f32_e32 v2, v06321; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v16322; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v1, v26323; SI-GISEL-NEXT: s_setpc_b64 s[30:31]6324;6325; R600-LABEL: v_exp_fneg_fabs_v2f16:6326; R600: ; %bb.0:6327; R600-NEXT: CF_END6328; R600-NEXT: PAD6329;6330; CM-LABEL: v_exp_fneg_fabs_v2f16:6331; CM: ; %bb.0:6332; CM-NEXT: CF_END6333; CM-NEXT: PAD6334 %fabs = call <2 x half> @llvm.fabs.v2f16(<2 x half> %in)6335 %fneg.fabs = fneg <2 x half> %fabs6336 %result = call <2 x half> @llvm.exp.v2f16(<2 x half> %fneg.fabs)6337 ret <2 x half> %result6338}6339 6340define <2 x half> @v_exp_fneg_v2f16(<2 x half> %in) {6341; VI-SDAG-LABEL: v_exp_fneg_v2f16:6342; VI-SDAG: ; %bb.0:6343; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6344; VI-SDAG-NEXT: v_cvt_f32_f16_sdwa v1, -v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_16345; VI-SDAG-NEXT: v_cvt_f32_f16_e64 v0, -v06346; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v16347; VI-SDAG-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v06348; VI-SDAG-NEXT: v_exp_f32_e32 v1, v16349; VI-SDAG-NEXT: v_exp_f32_e32 v0, v06350; VI-SDAG-NEXT: v_cvt_f16_f32_sdwa v1, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD6351; VI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v06352; VI-SDAG-NEXT: v_or_b32_e32 v0, v0, v16353; VI-SDAG-NEXT: s_setpc_b64 s[30:31]6354;6355; VI-GISEL-LABEL: v_exp_fneg_v2f16:6356; VI-GISEL: ; %bb.0:6357; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6358; VI-GISEL-NEXT: v_xor_b32_e32 v0, 0x80008000, v06359; VI-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v06360; VI-GISEL-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_16361; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v16362; VI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v06363; VI-GISEL-NEXT: v_exp_f32_e32 v1, v16364; VI-GISEL-NEXT: v_exp_f32_e32 v0, v06365; VI-GISEL-NEXT: v_cvt_f16_f32_e32 v1, v16366; VI-GISEL-NEXT: v_cvt_f16_f32_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD6367; VI-GISEL-NEXT: v_or_b32_e32 v0, v1, v06368; VI-GISEL-NEXT: s_setpc_b64 s[30:31]6369;6370; GFX900-SDAG-LABEL: v_exp_fneg_v2f16:6371; GFX900-SDAG: ; %bb.0:6372; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6373; GFX900-SDAG-NEXT: v_cvt_f32_f16_e64 v1, -v06374; GFX900-SDAG-NEXT: v_cvt_f32_f16_sdwa v0, -v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_16375; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v16376; GFX900-SDAG-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v06377; GFX900-SDAG-NEXT: v_exp_f32_e32 v1, v16378; GFX900-SDAG-NEXT: v_exp_f32_e32 v0, v06379; GFX900-SDAG-NEXT: v_cvt_f16_f32_e32 v1, v16380; GFX900-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v06381; GFX900-SDAG-NEXT: v_pack_b32_f16 v0, v1, v06382; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]6383;6384; GFX900-GISEL-LABEL: v_exp_fneg_v2f16:6385; GFX900-GISEL: ; %bb.0:6386; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6387; GFX900-GISEL-NEXT: v_xor_b32_e32 v0, 0x80008000, v06388; GFX900-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v06389; GFX900-GISEL-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_16390; GFX900-GISEL-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v16391; GFX900-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v06392; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, v16393; GFX900-GISEL-NEXT: v_exp_f32_e32 v0, v06394; GFX900-GISEL-NEXT: v_cvt_f16_f32_e32 v1, v16395; GFX900-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v06396; GFX900-GISEL-NEXT: v_pack_b32_f16 v0, v1, v06397; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]6398;6399; SI-SDAG-LABEL: v_exp_fneg_v2f16:6400; SI-SDAG: ; %bb.0:6401; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6402; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v1, v16403; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v06404; SI-SDAG-NEXT: v_lshlrev_b32_e32 v1, 16, v16405; SI-SDAG-NEXT: v_or_b32_e32 v0, v0, v16406; SI-SDAG-NEXT: v_xor_b32_e32 v0, 0x80008000, v06407; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v06408; SI-SDAG-NEXT: v_lshrrev_b32_e32 v0, 16, v06409; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v06410; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v16411; SI-SDAG-NEXT: v_exp_f32_e32 v1, v16412; SI-SDAG-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v06413; SI-SDAG-NEXT: v_exp_f32_e32 v0, v06414; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v1, v16415; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v2, v06416; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v16417; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v26418; SI-SDAG-NEXT: s_setpc_b64 s[30:31]6419;6420; SI-GISEL-LABEL: v_exp_fneg_v2f16:6421; SI-GISEL: ; %bb.0:6422; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6423; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v16424; SI-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v06425; SI-GISEL-NEXT: v_or_b32_e32 v0, v1, v06426; SI-GISEL-NEXT: v_xor_b32_e32 v0, 0x80008000, v06427; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v06428; SI-GISEL-NEXT: v_lshrrev_b32_e32 v0, 16, v06429; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v06430; SI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v16431; SI-GISEL-NEXT: v_exp_f32_e32 v1, v16432; SI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v06433; SI-GISEL-NEXT: v_exp_f32_e32 v2, v06434; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v16435; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v1, v26436; SI-GISEL-NEXT: s_setpc_b64 s[30:31]6437;6438; R600-LABEL: v_exp_fneg_v2f16:6439; R600: ; %bb.0:6440; R600-NEXT: CF_END6441; R600-NEXT: PAD6442;6443; CM-LABEL: v_exp_fneg_v2f16:6444; CM: ; %bb.0:6445; CM-NEXT: CF_END6446; CM-NEXT: PAD6447 %fneg = fneg <2 x half> %in6448 %result = call <2 x half> @llvm.exp.v2f16(<2 x half> %fneg)6449 ret <2 x half> %result6450}6451 6452define <2 x half> @v_exp_v2f16_fast(<2 x half> %in) {6453; VI-SDAG-LABEL: v_exp_v2f16_fast:6454; VI-SDAG: ; %bb.0:6455; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6456; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x3dc56457; VI-SDAG-NEXT: v_mul_f16_sdwa v1, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD6458; VI-SDAG-NEXT: v_mul_f16_e32 v0, 0x3dc5, v06459; VI-SDAG-NEXT: v_exp_f16_sdwa v1, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD6460; VI-SDAG-NEXT: v_exp_f16_e32 v0, v06461; VI-SDAG-NEXT: v_or_b32_e32 v0, v0, v16462; VI-SDAG-NEXT: s_setpc_b64 s[30:31]6463;6464; VI-GISEL-LABEL: v_exp_v2f16_fast:6465; VI-GISEL: ; %bb.0:6466; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6467; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3dc56468; VI-GISEL-NEXT: v_mul_f16_e32 v2, 0x3dc5, v06469; VI-GISEL-NEXT: v_mul_f16_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD6470; VI-GISEL-NEXT: v_exp_f16_e32 v2, v26471; VI-GISEL-NEXT: v_exp_f16_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD6472; VI-GISEL-NEXT: v_or_b32_e32 v0, v2, v06473; VI-GISEL-NEXT: s_setpc_b64 s[30:31]6474;6475; GFX900-SDAG-LABEL: v_exp_v2f16_fast:6476; GFX900-SDAG: ; %bb.0:6477; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6478; GFX900-SDAG-NEXT: s_movk_i32 s4, 0x3dc56479; GFX900-SDAG-NEXT: v_pk_mul_f16 v0, v0, s4 op_sel_hi:[1,0]6480; GFX900-SDAG-NEXT: v_exp_f16_e32 v1, v06481; GFX900-SDAG-NEXT: v_exp_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_16482; GFX900-SDAG-NEXT: v_pack_b32_f16 v0, v1, v06483; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]6484;6485; GFX900-GISEL-LABEL: v_exp_v2f16_fast:6486; GFX900-GISEL: ; %bb.0:6487; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6488; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3dc56489; GFX900-GISEL-NEXT: v_mul_f16_e32 v2, 0x3dc5, v06490; GFX900-GISEL-NEXT: v_mul_f16_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD6491; GFX900-GISEL-NEXT: v_exp_f16_e32 v2, v26492; GFX900-GISEL-NEXT: v_exp_f16_e32 v0, v06493; GFX900-GISEL-NEXT: v_lshl_or_b32 v0, v0, 16, v26494; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]6495;6496; SI-SDAG-LABEL: v_exp_v2f16_fast:6497; SI-SDAG: ; %bb.0:6498; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6499; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v06500; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v1, v16501; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v06502; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v16503; SI-SDAG-NEXT: v_mul_f32_e32 v0, 0x3fb8a000, v06504; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8a000, v16505; SI-SDAG-NEXT: v_exp_f32_e32 v0, v06506; SI-SDAG-NEXT: v_exp_f32_e32 v1, v16507; SI-SDAG-NEXT: s_setpc_b64 s[30:31]6508;6509; SI-GISEL-LABEL: v_exp_v2f16_fast:6510; SI-GISEL: ; %bb.0:6511; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6512; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v06513; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v16514; SI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8a000, v06515; SI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3fb8a000, v16516; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v06517; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v1, v16518; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v06519; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v16520; SI-GISEL-NEXT: v_exp_f32_e32 v0, v06521; SI-GISEL-NEXT: v_exp_f32_e32 v1, v16522; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v06523; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v1, v16524; SI-GISEL-NEXT: s_setpc_b64 s[30:31]6525;6526; R600-LABEL: v_exp_v2f16_fast:6527; R600: ; %bb.0:6528; R600-NEXT: CF_END6529; R600-NEXT: PAD6530;6531; CM-LABEL: v_exp_v2f16_fast:6532; CM: ; %bb.0:6533; CM-NEXT: CF_END6534; CM-NEXT: PAD6535 %result = call fast <2 x half> @llvm.exp.v2f16(<2 x half> %in)6536 ret <2 x half> %result6537}6538 6539define <3 x half> @v_exp_v3f16(<3 x half> %in) {6540; VI-LABEL: v_exp_v3f16:6541; VI: ; %bb.0:6542; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6543; VI-NEXT: v_cvt_f32_f16_e32 v2, v06544; VI-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_16545; VI-NEXT: v_cvt_f32_f16_e32 v1, v16546; VI-NEXT: v_mul_f32_e32 v2, 0x3fb8aa3b, v26547; VI-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v06548; VI-NEXT: v_exp_f32_e32 v2, v26549; VI-NEXT: v_exp_f32_e32 v0, v06550; VI-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v16551; VI-NEXT: v_exp_f32_e32 v1, v16552; VI-NEXT: v_cvt_f16_f32_e32 v2, v26553; VI-NEXT: v_cvt_f16_f32_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD6554; VI-NEXT: v_cvt_f16_f32_e32 v1, v16555; VI-NEXT: v_or_b32_e32 v0, v2, v06556; VI-NEXT: s_setpc_b64 s[30:31]6557;6558; GFX900-LABEL: v_exp_v3f16:6559; GFX900: ; %bb.0:6560; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6561; GFX900-NEXT: v_cvt_f32_f16_e32 v2, v06562; GFX900-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_16563; GFX900-NEXT: v_cvt_f32_f16_e32 v1, v16564; GFX900-NEXT: v_mul_f32_e32 v2, 0x3fb8aa3b, v26565; GFX900-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v06566; GFX900-NEXT: v_exp_f32_e32 v2, v26567; GFX900-NEXT: v_exp_f32_e32 v0, v06568; GFX900-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v16569; GFX900-NEXT: v_exp_f32_e32 v1, v16570; GFX900-NEXT: v_cvt_f16_f32_e32 v2, v26571; GFX900-NEXT: v_cvt_f16_f32_e32 v0, v06572; GFX900-NEXT: v_cvt_f16_f32_e32 v1, v16573; GFX900-NEXT: v_pack_b32_f16 v0, v2, v06574; GFX900-NEXT: s_setpc_b64 s[30:31]6575;6576; SI-SDAG-LABEL: v_exp_v3f16:6577; SI-SDAG: ; %bb.0:6578; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6579; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v06580; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v1, v16581; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v2, v26582; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v06583; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v16584; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v2, v26585; SI-SDAG-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v06586; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v16587; SI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3fb8aa3b, v26588; SI-SDAG-NEXT: v_exp_f32_e32 v0, v06589; SI-SDAG-NEXT: v_exp_f32_e32 v1, v16590; SI-SDAG-NEXT: v_exp_f32_e32 v2, v26591; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v06592; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v1, v16593; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v2, v26594; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v06595; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v16596; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v2, v26597; SI-SDAG-NEXT: s_setpc_b64 s[30:31]6598;6599; SI-GISEL-LABEL: v_exp_v3f16:6600; SI-GISEL: ; %bb.0:6601; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6602; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v06603; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v16604; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v2, v26605; SI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v06606; SI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v16607; SI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3fb8aa3b, v26608; SI-GISEL-NEXT: v_exp_f32_e32 v0, v06609; SI-GISEL-NEXT: v_exp_f32_e32 v1, v16610; SI-GISEL-NEXT: v_exp_f32_e32 v2, v26611; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v06612; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v1, v16613; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v2, v26614; SI-GISEL-NEXT: s_setpc_b64 s[30:31]6615;6616; R600-LABEL: v_exp_v3f16:6617; R600: ; %bb.0:6618; R600-NEXT: CF_END6619; R600-NEXT: PAD6620;6621; CM-LABEL: v_exp_v3f16:6622; CM: ; %bb.0:6623; CM-NEXT: CF_END6624; CM-NEXT: PAD6625 %result = call <3 x half> @llvm.exp.v3f16(<3 x half> %in)6626 ret <3 x half> %result6627}6628 6629define <3 x half> @v_exp_v3f16_afn(<3 x half> %in) {6630; VI-SDAG-LABEL: v_exp_v3f16_afn:6631; VI-SDAG: ; %bb.0:6632; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6633; VI-SDAG-NEXT: v_mov_b32_e32 v3, 0x3dc56634; VI-SDAG-NEXT: v_mul_f16_e32 v2, 0x3dc5, v06635; VI-SDAG-NEXT: v_mul_f16_sdwa v0, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD6636; VI-SDAG-NEXT: v_exp_f16_e32 v2, v26637; VI-SDAG-NEXT: v_exp_f16_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD6638; VI-SDAG-NEXT: v_mul_f16_e32 v1, 0x3dc5, v16639; VI-SDAG-NEXT: v_exp_f16_e32 v1, v16640; VI-SDAG-NEXT: v_or_b32_e32 v0, v2, v06641; VI-SDAG-NEXT: s_setpc_b64 s[30:31]6642;6643; VI-GISEL-LABEL: v_exp_v3f16_afn:6644; VI-GISEL: ; %bb.0:6645; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6646; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x3dc56647; VI-GISEL-NEXT: v_mul_f16_e32 v3, 0x3dc5, v06648; VI-GISEL-NEXT: v_mul_f16_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD6649; VI-GISEL-NEXT: v_exp_f16_e32 v3, v36650; VI-GISEL-NEXT: v_exp_f16_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD6651; VI-GISEL-NEXT: v_mul_f16_e32 v1, 0x3dc5, v16652; VI-GISEL-NEXT: v_exp_f16_e32 v1, v16653; VI-GISEL-NEXT: v_or_b32_e32 v0, v3, v06654; VI-GISEL-NEXT: s_setpc_b64 s[30:31]6655;6656; GFX900-SDAG-LABEL: v_exp_v3f16_afn:6657; GFX900-SDAG: ; %bb.0:6658; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6659; GFX900-SDAG-NEXT: s_movk_i32 s4, 0x3dc56660; GFX900-SDAG-NEXT: v_mul_f16_e32 v2, 0x3dc5, v06661; GFX900-SDAG-NEXT: v_mul_f16_sdwa v0, v0, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD6662; GFX900-SDAG-NEXT: v_exp_f16_e32 v2, v26663; GFX900-SDAG-NEXT: v_exp_f16_e32 v0, v06664; GFX900-SDAG-NEXT: v_mul_f16_e32 v1, 0x3dc5, v16665; GFX900-SDAG-NEXT: v_exp_f16_e32 v1, v16666; GFX900-SDAG-NEXT: v_pack_b32_f16 v0, v2, v06667; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]6668;6669; GFX900-GISEL-LABEL: v_exp_v3f16_afn:6670; GFX900-GISEL: ; %bb.0:6671; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6672; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x3dc56673; GFX900-GISEL-NEXT: v_mul_f16_e32 v3, 0x3dc5, v06674; GFX900-GISEL-NEXT: v_mul_f16_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD6675; GFX900-GISEL-NEXT: v_exp_f16_e32 v3, v36676; GFX900-GISEL-NEXT: v_exp_f16_e32 v0, v06677; GFX900-GISEL-NEXT: v_mul_f16_e32 v1, 0x3dc5, v16678; GFX900-GISEL-NEXT: v_exp_f16_e32 v1, v16679; GFX900-GISEL-NEXT: v_lshl_or_b32 v0, v0, 16, v36680; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]6681;6682; SI-SDAG-LABEL: v_exp_v3f16_afn:6683; SI-SDAG: ; %bb.0:6684; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6685; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v06686; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v1, v16687; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v2, v26688; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v06689; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v16690; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v2, v26691; SI-SDAG-NEXT: v_mul_f32_e32 v0, 0x3fb8a000, v06692; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8a000, v16693; SI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v26694; SI-SDAG-NEXT: v_exp_f32_e32 v0, v06695; SI-SDAG-NEXT: v_exp_f32_e32 v1, v16696; SI-SDAG-NEXT: v_exp_f32_e32 v2, v26697; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v06698; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v1, v16699; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v2, v26700; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v06701; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v16702; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v2, v26703; SI-SDAG-NEXT: s_setpc_b64 s[30:31]6704;6705; SI-GISEL-LABEL: v_exp_v3f16_afn:6706; SI-GISEL: ; %bb.0:6707; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6708; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v06709; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v16710; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v2, v26711; SI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8a000, v06712; SI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3fb8a000, v16713; SI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v26714; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v06715; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v1, v16716; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v2, v26717; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v06718; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v16719; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v2, v26720; SI-GISEL-NEXT: v_exp_f32_e32 v0, v06721; SI-GISEL-NEXT: v_exp_f32_e32 v1, v16722; SI-GISEL-NEXT: v_exp_f32_e32 v2, v26723; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v06724; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v1, v16725; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v2, v26726; SI-GISEL-NEXT: s_setpc_b64 s[30:31]6727;6728; R600-LABEL: v_exp_v3f16_afn:6729; R600: ; %bb.0:6730; R600-NEXT: CF_END6731; R600-NEXT: PAD6732;6733; CM-LABEL: v_exp_v3f16_afn:6734; CM: ; %bb.0:6735; CM-NEXT: CF_END6736; CM-NEXT: PAD6737 %result = call afn <3 x half> @llvm.exp.v3f16(<3 x half> %in)6738 ret <3 x half> %result6739}6740 6741define float @v_exp_f32_contract(float %in) {6742; VI-SDAG-LABEL: v_exp_f32_contract:6743; VI-SDAG: ; %bb.0:6744; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6745; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v06746; VI-SDAG-NEXT: v_sub_f32_e32 v4, v0, v16747; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v16748; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x39a3b295, v46749; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x3fb8a000, v46750; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v26751; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v56752; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v16753; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v36754; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v46755; VI-SDAG-NEXT: v_add_f32_e32 v1, v2, v16756; VI-SDAG-NEXT: v_exp_f32_e32 v1, v16757; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v36758; VI-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed06759; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v06760; VI-SDAG-NEXT: s_mov_b32 s4, 0x42b172186761; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v26762; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc6763; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f8000006764; VI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v06765; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc6766; VI-SDAG-NEXT: s_setpc_b64 s[30:31]6767;6768; VI-GISEL-LABEL: v_exp_f32_contract:6769; VI-GISEL: ; %bb.0:6770; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6771; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v06772; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v16773; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x39a3b295, v26774; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v26775; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3fb8a000, v16776; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v46777; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v16778; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v26779; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v36780; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v26781; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v16782; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v26783; VI-GISEL-NEXT: v_exp_f32_e32 v1, v16784; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f8000006785; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v26786; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed06787; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v26788; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42b172186789; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc6790; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v26791; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc6792; VI-GISEL-NEXT: s_setpc_b64 s[30:31]6793;6794; GFX900-SDAG-LABEL: v_exp_f32_contract:6795; GFX900-SDAG: ; %bb.0:6796; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6797; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v06798; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3fb8aa3b6799; GFX900-SDAG-NEXT: v_rndne_f32_e32 v2, v16800; GFX900-SDAG-NEXT: v_sub_f32_e32 v3, v1, v26801; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v16802; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x32a5705f6803; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, v16804; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v3, v16805; GFX900-SDAG-NEXT: v_exp_f32_e32 v1, v16806; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v26807; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed06808; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v06809; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x42b172186810; GFX900-SDAG-NEXT: v_ldexp_f32 v1, v1, v26811; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc6812; GFX900-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f8000006813; GFX900-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v06814; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc6815; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]6816;6817; GFX900-GISEL-LABEL: v_exp_f32_contract:6818; GFX900-GISEL: ; %bb.0:6819; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6820; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3fb8aa3b6821; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, 0x3fb8aa3b, v06822; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v26823; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x32a5705f6824; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v3, v16825; GFX900-GISEL-NEXT: v_rndne_f32_e32 v3, v26826; GFX900-GISEL-NEXT: v_sub_f32_e32 v2, v2, v36827; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v2, v16828; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v36829; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, v16830; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f8000006831; GFX900-GISEL-NEXT: v_ldexp_f32 v1, v1, v26832; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed06833; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v26834; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x42b172186835; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc6836; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v26837; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc6838; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]6839;6840; SI-SDAG-LABEL: v_exp_f32_contract:6841; SI-SDAG: ; %bb.0:6842; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6843; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v06844; SI-SDAG-NEXT: s_mov_b32 s4, 0x3fb8aa3b6845; SI-SDAG-NEXT: v_rndne_f32_e32 v2, v16846; SI-SDAG-NEXT: v_sub_f32_e32 v3, v1, v26847; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v16848; SI-SDAG-NEXT: s_mov_b32 s4, 0x32a5705f6849; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, v16850; SI-SDAG-NEXT: v_add_f32_e32 v1, v3, v16851; SI-SDAG-NEXT: v_exp_f32_e32 v1, v16852; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v26853; SI-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed06854; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v06855; SI-SDAG-NEXT: s_mov_b32 s4, 0x42b172186856; SI-SDAG-NEXT: v_ldexp_f32_e32 v1, v1, v26857; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc6858; SI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f8000006859; SI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v06860; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc6861; SI-SDAG-NEXT: s_setpc_b64 s[30:31]6862;6863; SI-GISEL-LABEL: v_exp_f32_contract:6864; SI-GISEL: ; %bb.0:6865; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6866; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3fb8aa3b6867; SI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3fb8aa3b, v06868; SI-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v26869; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x32a5705f6870; SI-GISEL-NEXT: v_fma_f32 v1, v0, v3, v16871; SI-GISEL-NEXT: v_rndne_f32_e32 v3, v26872; SI-GISEL-NEXT: v_sub_f32_e32 v2, v2, v36873; SI-GISEL-NEXT: v_add_f32_e32 v1, v2, v16874; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v36875; SI-GISEL-NEXT: v_exp_f32_e32 v1, v16876; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f8000006877; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, v1, v26878; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed06879; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v26880; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42b172186881; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc6882; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v26883; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc6884; SI-GISEL-NEXT: s_setpc_b64 s[30:31]6885;6886; R600-LABEL: v_exp_f32_contract:6887; R600: ; %bb.0:6888; R600-NEXT: CF_END6889; R600-NEXT: PAD6890;6891; CM-LABEL: v_exp_f32_contract:6892; CM: ; %bb.0:6893; CM-NEXT: CF_END6894; CM-NEXT: PAD6895 %result = call contract float @llvm.exp.f32(float %in)6896 ret float %result6897}6898 6899define float @v_exp_f32_contract_daz(float %in) #0 {6900; VI-SDAG-LABEL: v_exp_f32_contract_daz:6901; VI-SDAG: ; %bb.0:6902; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6903; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v06904; VI-SDAG-NEXT: v_sub_f32_e32 v4, v0, v16905; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v16906; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x39a3b295, v46907; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x3fb8a000, v46908; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v26909; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v56910; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v16911; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v36912; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v46913; VI-SDAG-NEXT: v_add_f32_e32 v1, v2, v16914; VI-SDAG-NEXT: v_exp_f32_e32 v1, v16915; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v36916; VI-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed06917; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v06918; VI-SDAG-NEXT: s_mov_b32 s4, 0x42b172186919; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v26920; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc6921; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f8000006922; VI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v06923; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc6924; VI-SDAG-NEXT: s_setpc_b64 s[30:31]6925;6926; VI-GISEL-LABEL: v_exp_f32_contract_daz:6927; VI-GISEL: ; %bb.0:6928; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6929; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v06930; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v16931; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x39a3b295, v26932; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v26933; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3fb8a000, v16934; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v46935; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v16936; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v26937; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v36938; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v26939; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v16940; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v26941; VI-GISEL-NEXT: v_exp_f32_e32 v1, v16942; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f8000006943; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v26944; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed06945; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v26946; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42b172186947; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc6948; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v26949; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc6950; VI-GISEL-NEXT: s_setpc_b64 s[30:31]6951;6952; GFX900-SDAG-LABEL: v_exp_f32_contract_daz:6953; GFX900-SDAG: ; %bb.0:6954; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6955; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v06956; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3fb8aa3b6957; GFX900-SDAG-NEXT: v_rndne_f32_e32 v2, v16958; GFX900-SDAG-NEXT: v_sub_f32_e32 v3, v1, v26959; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v16960; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x32a5705f6961; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, v16962; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v3, v16963; GFX900-SDAG-NEXT: v_exp_f32_e32 v1, v16964; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v26965; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed06966; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v06967; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x42b172186968; GFX900-SDAG-NEXT: v_ldexp_f32 v1, v1, v26969; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc6970; GFX900-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f8000006971; GFX900-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v06972; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc6973; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]6974;6975; GFX900-GISEL-LABEL: v_exp_f32_contract_daz:6976; GFX900-GISEL: ; %bb.0:6977; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6978; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3fb8aa3b6979; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, 0x3fb8aa3b, v06980; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v26981; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x32a5705f6982; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v3, v16983; GFX900-GISEL-NEXT: v_rndne_f32_e32 v3, v26984; GFX900-GISEL-NEXT: v_sub_f32_e32 v2, v2, v36985; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v2, v16986; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v36987; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, v16988; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f8000006989; GFX900-GISEL-NEXT: v_ldexp_f32 v1, v1, v26990; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed06991; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v26992; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x42b172186993; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc6994; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v26995; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc6996; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]6997;6998; SI-SDAG-LABEL: v_exp_f32_contract_daz:6999; SI-SDAG: ; %bb.0:7000; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7001; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v07002; SI-SDAG-NEXT: s_mov_b32 s4, 0x3fb8aa3b7003; SI-SDAG-NEXT: v_rndne_f32_e32 v2, v17004; SI-SDAG-NEXT: v_sub_f32_e32 v3, v1, v27005; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v17006; SI-SDAG-NEXT: s_mov_b32 s4, 0x32a5705f7007; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, v17008; SI-SDAG-NEXT: v_add_f32_e32 v1, v3, v17009; SI-SDAG-NEXT: v_exp_f32_e32 v1, v17010; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v27011; SI-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed07012; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v07013; SI-SDAG-NEXT: s_mov_b32 s4, 0x42b172187014; SI-SDAG-NEXT: v_ldexp_f32_e32 v1, v1, v27015; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc7016; SI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f8000007017; SI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v07018; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc7019; SI-SDAG-NEXT: s_setpc_b64 s[30:31]7020;7021; SI-GISEL-LABEL: v_exp_f32_contract_daz:7022; SI-GISEL: ; %bb.0:7023; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7024; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3fb8aa3b7025; SI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3fb8aa3b, v07026; SI-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v27027; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x32a5705f7028; SI-GISEL-NEXT: v_fma_f32 v1, v0, v3, v17029; SI-GISEL-NEXT: v_rndne_f32_e32 v3, v27030; SI-GISEL-NEXT: v_sub_f32_e32 v2, v2, v37031; SI-GISEL-NEXT: v_add_f32_e32 v1, v2, v17032; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v37033; SI-GISEL-NEXT: v_exp_f32_e32 v1, v17034; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f8000007035; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, v1, v27036; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed07037; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v27038; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42b172187039; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc7040; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v27041; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc7042; SI-GISEL-NEXT: s_setpc_b64 s[30:31]7043;7044; R600-LABEL: v_exp_f32_contract_daz:7045; R600: ; %bb.0:7046; R600-NEXT: CF_END7047; R600-NEXT: PAD7048;7049; CM-LABEL: v_exp_f32_contract_daz:7050; CM: ; %bb.0:7051; CM-NEXT: CF_END7052; CM-NEXT: PAD7053 %result = call contract float @llvm.exp.f32(float %in)7054 ret float %result7055}7056 7057define float @v_exp_f32_contract_nnan_ninf(float %in) {7058; VI-SDAG-LABEL: v_exp_f32_contract_nnan_ninf:7059; VI-SDAG: ; %bb.0:7060; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7061; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v07062; VI-SDAG-NEXT: v_sub_f32_e32 v4, v0, v17063; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v17064; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x39a3b295, v47065; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x3fb8a000, v47066; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v27067; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v57068; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v17069; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v37070; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v47071; VI-SDAG-NEXT: v_add_f32_e32 v1, v2, v17072; VI-SDAG-NEXT: v_exp_f32_e32 v1, v17073; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v37074; VI-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed07075; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v07076; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v27077; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc7078; VI-SDAG-NEXT: s_setpc_b64 s[30:31]7079;7080; VI-GISEL-LABEL: v_exp_f32_contract_nnan_ninf:7081; VI-GISEL: ; %bb.0:7082; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7083; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v07084; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v17085; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x39a3b295, v27086; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v27087; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3fb8a000, v17088; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v47089; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v17090; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v27091; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v37092; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v27093; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v17094; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v27095; VI-GISEL-NEXT: v_exp_f32_e32 v1, v17096; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v27097; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed07098; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v27099; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc7100; VI-GISEL-NEXT: s_setpc_b64 s[30:31]7101;7102; GFX900-SDAG-LABEL: v_exp_f32_contract_nnan_ninf:7103; GFX900-SDAG: ; %bb.0:7104; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7105; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v07106; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3fb8aa3b7107; GFX900-SDAG-NEXT: v_rndne_f32_e32 v2, v17108; GFX900-SDAG-NEXT: v_sub_f32_e32 v3, v1, v27109; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v17110; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x32a5705f7111; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, v17112; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v3, v17113; GFX900-SDAG-NEXT: v_exp_f32_e32 v1, v17114; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v27115; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed07116; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v07117; GFX900-SDAG-NEXT: v_ldexp_f32 v1, v1, v27118; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc7119; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]7120;7121; GFX900-GISEL-LABEL: v_exp_f32_contract_nnan_ninf:7122; GFX900-GISEL: ; %bb.0:7123; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7124; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3fb8aa3b7125; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, 0x3fb8aa3b, v07126; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v27127; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x32a5705f7128; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v3, v17129; GFX900-GISEL-NEXT: v_rndne_f32_e32 v3, v27130; GFX900-GISEL-NEXT: v_sub_f32_e32 v2, v2, v37131; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v2, v17132; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v37133; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, v17134; GFX900-GISEL-NEXT: v_ldexp_f32 v1, v1, v27135; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed07136; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v27137; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc7138; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]7139;7140; SI-SDAG-LABEL: v_exp_f32_contract_nnan_ninf:7141; SI-SDAG: ; %bb.0:7142; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7143; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v07144; SI-SDAG-NEXT: s_mov_b32 s4, 0x3fb8aa3b7145; SI-SDAG-NEXT: v_rndne_f32_e32 v2, v17146; SI-SDAG-NEXT: v_sub_f32_e32 v3, v1, v27147; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v17148; SI-SDAG-NEXT: s_mov_b32 s4, 0x32a5705f7149; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, v17150; SI-SDAG-NEXT: v_add_f32_e32 v1, v3, v17151; SI-SDAG-NEXT: v_exp_f32_e32 v1, v17152; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v27153; SI-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed07154; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v07155; SI-SDAG-NEXT: v_ldexp_f32_e32 v1, v1, v27156; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc7157; SI-SDAG-NEXT: s_setpc_b64 s[30:31]7158;7159; SI-GISEL-LABEL: v_exp_f32_contract_nnan_ninf:7160; SI-GISEL: ; %bb.0:7161; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7162; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3fb8aa3b7163; SI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3fb8aa3b, v07164; SI-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v27165; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x32a5705f7166; SI-GISEL-NEXT: v_fma_f32 v1, v0, v3, v17167; SI-GISEL-NEXT: v_rndne_f32_e32 v3, v27168; SI-GISEL-NEXT: v_sub_f32_e32 v2, v2, v37169; SI-GISEL-NEXT: v_add_f32_e32 v1, v2, v17170; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v37171; SI-GISEL-NEXT: v_exp_f32_e32 v1, v17172; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, v1, v27173; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed07174; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v27175; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc7176; SI-GISEL-NEXT: s_setpc_b64 s[30:31]7177;7178; R600-LABEL: v_exp_f32_contract_nnan_ninf:7179; R600: ; %bb.0:7180; R600-NEXT: CF_END7181; R600-NEXT: PAD7182;7183; CM-LABEL: v_exp_f32_contract_nnan_ninf:7184; CM: ; %bb.0:7185; CM-NEXT: CF_END7186; CM-NEXT: PAD7187 %result = call contract nnan ninf float @llvm.exp.f32(float %in)7188 ret float %result7189}7190 7191declare float @llvm.fabs.f32(float) #27192declare float @llvm.exp.f32(float) #27193declare <2 x float> @llvm.exp.v2f32(<2 x float>) #27194declare <3 x float> @llvm.exp.v3f32(<3 x float>) #27195declare <4 x float> @llvm.exp.v4f32(<4 x float>) #27196declare half @llvm.fabs.f16(half) #27197declare half @llvm.exp.f16(half) #27198declare <2 x half> @llvm.exp.v2f16(<2 x half>) #27199declare <3 x half> @llvm.exp.v3f16(<3 x half>) #27200declare <2 x half> @llvm.fabs.v2f16(<2 x half>) #27201 7202attributes #0 = { "denormal-fp-math-f32"="ieee,preserve-sign" }7203attributes #1 = { "denormal-fp-math-f32"="dynamic,dynamic" }7204attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }7205