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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 22; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=GCN,GCN-SDAG,VI,VI-SDAG %s3; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=GCN,GCN-GISEL,VI,VI-GISEL %s4; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GCN-SDAG,GFX900,GFX900-SDAG %s5; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GCN-GISEL,GFX900,GFX900-GISEL %s6; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefixes=SI,SI-SDAG %s7; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefixes=SI,SI-GISEL %s8 9; RUN: llc -mtriple=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 %s10; RUN: llc -mtriple=r600 -mcpu=cayman < %s | FileCheck -check-prefix=CM %s11 12; FIXME: Fallback enabled due to bfloat extensions13 14define amdgpu_kernel void @s_exp10_f32(ptr addrspace(1) %out, float %in) {15; VI-SDAG-LABEL: s_exp10_f32:16; VI-SDAG: ; %bb.0:17; VI-SDAG-NEXT: s_load_dword s2, s[4:5], 0x2c18; VI-SDAG-NEXT: v_mov_b32_e32 v0, 0x4054900019; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)20; VI-SDAG-NEXT: s_and_b32 s0, s2, 0xfffff00021; VI-SDAG-NEXT: v_mov_b32_e32 v1, s022; VI-SDAG-NEXT: v_sub_f32_e32 v1, s2, v123; VI-SDAG-NEXT: v_mul_f32_e32 v3, 0x3a2784bc, v124; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x40549000, v125; VI-SDAG-NEXT: v_mul_f32_e32 v0, s0, v026; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v327; VI-SDAG-NEXT: v_mov_b32_e32 v3, 0x3a2784bc28; VI-SDAG-NEXT: v_rndne_f32_e32 v2, v029; VI-SDAG-NEXT: v_mul_f32_e32 v3, s0, v330; VI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v231; VI-SDAG-NEXT: v_add_f32_e32 v1, v3, v132; VI-SDAG-NEXT: v_add_f32_e32 v0, v0, v133; VI-SDAG-NEXT: v_exp_f32_e32 v0, v034; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v1, v235; VI-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2436; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f80000037; VI-SDAG-NEXT: v_ldexp_f32 v0, v0, v138; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0xc23369f439; VI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s2, v140; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x421a209b41; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc42; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s2, v143; VI-SDAG-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc44; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)45; VI-SDAG-NEXT: v_mov_b32_e32 v0, s046; VI-SDAG-NEXT: v_mov_b32_e32 v1, s147; VI-SDAG-NEXT: flat_store_dword v[0:1], v248; VI-SDAG-NEXT: s_endpgm49;50; VI-GISEL-LABEL: s_exp10_f32:51; VI-GISEL: ; %bb.0:52; VI-GISEL-NEXT: s_load_dword s2, s[4:5], 0x2c53; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x4054900054; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3a2784bc55; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)56; VI-GISEL-NEXT: s_and_b32 s0, s2, 0xfffff00057; VI-GISEL-NEXT: v_mov_b32_e32 v2, s058; VI-GISEL-NEXT: v_sub_f32_e32 v2, s2, v259; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3a2784bc, v260; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549000, v261; VI-GISEL-NEXT: v_mul_f32_e32 v0, s0, v062; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v363; VI-GISEL-NEXT: v_mul_f32_e32 v1, s0, v164; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v265; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v066; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v267; VI-GISEL-NEXT: v_add_f32_e32 v0, v0, v168; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v1, v269; VI-GISEL-NEXT: v_exp_f32_e32 v0, v070; VI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2471; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f80000072; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v173; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc23369f474; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v175; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x421a209b76; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc77; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s2, v178; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc79; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)80; VI-GISEL-NEXT: v_mov_b32_e32 v0, s081; VI-GISEL-NEXT: v_mov_b32_e32 v1, s182; VI-GISEL-NEXT: flat_store_dword v[0:1], v283; VI-GISEL-NEXT: s_endpgm84;85; GFX900-SDAG-LABEL: s_exp10_f32:86; GFX900-SDAG: ; %bb.0:87; GFX900-SDAG-NEXT: s_load_dword s2, s[4:5], 0x2c88; GFX900-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2489; GFX900-SDAG-NEXT: v_mov_b32_e32 v0, 0x40549a7890; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x33979a3791; GFX900-SDAG-NEXT: s_waitcnt lgkmcnt(0)92; GFX900-SDAG-NEXT: v_mul_f32_e32 v2, s2, v093; GFX900-SDAG-NEXT: v_rndne_f32_e32 v3, v294; GFX900-SDAG-NEXT: v_fma_f32 v0, s2, v0, -v295; GFX900-SDAG-NEXT: v_sub_f32_e32 v2, v2, v396; GFX900-SDAG-NEXT: v_fma_f32 v0, s2, v1, v097; GFX900-SDAG-NEXT: v_add_f32_e32 v0, v2, v098; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v1, v399; GFX900-SDAG-NEXT: v_exp_f32_e32 v0, v0100; GFX900-SDAG-NEXT: v_mov_b32_e32 v3, 0x7f800000101; GFX900-SDAG-NEXT: v_mov_b32_e32 v2, 0102; GFX900-SDAG-NEXT: v_ldexp_f32 v0, v0, v1103; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0xc23369f4104; GFX900-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s2, v1105; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x421a209b106; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc107; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s2, v1108; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc109; GFX900-SDAG-NEXT: global_store_dword v2, v0, s[0:1]110; GFX900-SDAG-NEXT: s_endpgm111;112; GFX900-GISEL-LABEL: s_exp10_f32:113; GFX900-GISEL: ; %bb.0:114; GFX900-GISEL-NEXT: s_load_dword s2, s[4:5], 0x2c115; GFX900-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24116; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, 0x40549a78117; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x33979a37118; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0)119; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, s2, v0120; GFX900-GISEL-NEXT: v_fma_f32 v0, s2, v0, -v2121; GFX900-GISEL-NEXT: v_rndne_f32_e32 v3, v2122; GFX900-GISEL-NEXT: v_fma_f32 v0, s2, v1, v0123; GFX900-GISEL-NEXT: v_sub_f32_e32 v1, v2, v3124; GFX900-GISEL-NEXT: v_add_f32_e32 v0, v1, v0125; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v1, v3126; GFX900-GISEL-NEXT: v_exp_f32_e32 v0, v0127; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f4128; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v2129; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000130; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1131; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x421a209b132; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc133; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s2, v1134; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc135; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0136; GFX900-GISEL-NEXT: global_store_dword v1, v0, s[0:1]137; GFX900-GISEL-NEXT: s_endpgm138;139; SI-SDAG-LABEL: s_exp10_f32:140; SI-SDAG: ; %bb.0:141; SI-SDAG-NEXT: s_load_dword s6, s[4:5], 0xb142; SI-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9143; SI-SDAG-NEXT: v_mov_b32_e32 v0, 0x40549a78144; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x33979a37145; SI-SDAG-NEXT: s_mov_b32 s3, 0xf000146; SI-SDAG-NEXT: s_waitcnt lgkmcnt(0)147; SI-SDAG-NEXT: v_mul_f32_e32 v2, s6, v0148; SI-SDAG-NEXT: v_rndne_f32_e32 v3, v2149; SI-SDAG-NEXT: v_fma_f32 v0, s6, v0, -v2150; SI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v3151; SI-SDAG-NEXT: v_fma_f32 v0, s6, v1, v0152; SI-SDAG-NEXT: v_add_f32_e32 v0, v2, v0153; SI-SDAG-NEXT: v_exp_f32_e32 v0, v0154; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v1, v3155; SI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000156; SI-SDAG-NEXT: s_mov_b32 s2, -1157; SI-SDAG-NEXT: v_ldexp_f32_e32 v0, v0, v1158; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0xc23369f4159; SI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s6, v1160; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x421a209b161; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc162; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s6, v1163; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc164; SI-SDAG-NEXT: buffer_store_dword v0, off, s[0:3], 0165; SI-SDAG-NEXT: s_endpgm166;167; SI-GISEL-LABEL: s_exp10_f32:168; SI-GISEL: ; %bb.0:169; SI-GISEL-NEXT: s_load_dword s2, s[4:5], 0xb170; SI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9171; SI-GISEL-NEXT: v_mov_b32_e32 v0, 0x40549a78172; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x33979a37173; SI-GISEL-NEXT: s_mov_b32 s3, 0xf000174; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)175; SI-GISEL-NEXT: v_mul_f32_e32 v2, s2, v0176; SI-GISEL-NEXT: v_fma_f32 v0, s2, v0, -v2177; SI-GISEL-NEXT: v_rndne_f32_e32 v3, v2178; SI-GISEL-NEXT: v_fma_f32 v0, s2, v1, v0179; SI-GISEL-NEXT: v_sub_f32_e32 v1, v2, v3180; SI-GISEL-NEXT: v_add_f32_e32 v0, v1, v0181; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v1, v3182; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0183; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f4184; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v2185; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000186; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1187; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x421a209b188; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc189; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s2, v1190; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc191; SI-GISEL-NEXT: s_mov_b32 s2, -1192; SI-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0193; SI-GISEL-NEXT: s_endpgm194;195; R600-LABEL: s_exp10_f32:196; R600: ; %bb.0:197; R600-NEXT: ALU 59, @4, KC0[CB0:0-32], KC1[]198; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1199; R600-NEXT: CF_END200; R600-NEXT: PAD201; R600-NEXT: ALU clause starting at 4:202; R600-NEXT: AND_INT * T0.W, KC0[2].Z, literal.x,203; R600-NEXT: -4096(nan), 0(0.000000e+00)204; R600-NEXT: ADD T1.W, KC0[2].Z, -PV.W,205; R600-NEXT: MUL_IEEE * T2.W, PV.W, literal.x,206; R600-NEXT: 1079283712(3.321289e+00), 0(0.000000e+00)207; R600-NEXT: RNDNE T3.W, PS,208; R600-NEXT: MUL_IEEE * T4.W, PV.W, literal.x,209; R600-NEXT: 975668412(6.390323e-04), 0(0.000000e+00)210; R600-NEXT: MULADD_IEEE T1.W, T1.W, literal.x, PS,211; R600-NEXT: TRUNC * T4.W, PV.W,212; R600-NEXT: 1079283712(3.321289e+00), 0(0.000000e+00)213; R600-NEXT: FLT_TO_INT T0.Z, PS,214; R600-NEXT: MULADD_IEEE T0.W, T0.W, literal.x, PV.W,215; R600-NEXT: ADD * T1.W, T2.W, -T3.W,216; R600-NEXT: 975668412(6.390323e-04), 0(0.000000e+00)217; R600-NEXT: ADD T1.Z, PS, PV.W,218; R600-NEXT: MAX_INT T0.W, PV.Z, literal.x,219; R600-NEXT: MIN_INT * T1.W, PV.Z, literal.y,220; R600-NEXT: -330(nan), 381(5.338947e-43)221; R600-NEXT: ADD_INT T0.X, PS, literal.x,222; R600-NEXT: ADD_INT T0.Y, PV.W, literal.y,223; R600-NEXT: ADD_INT T2.Z, T0.Z, literal.z,224; R600-NEXT: SETGT_UINT T0.W, T0.Z, literal.w,225; R600-NEXT: EXP_IEEE * T1.X, PV.Z,226; R600-NEXT: -254(nan), 204(2.858649e-43)227; R600-NEXT: 102(1.429324e-43), -229(nan)228; R600-NEXT: ADD_INT T2.X, T0.Z, literal.x,229; R600-NEXT: SETGT_UINT T1.Y, T0.Z, literal.y,230; R600-NEXT: CNDE_INT T1.Z, PV.W, PV.Y, PV.Z,231; R600-NEXT: SETGT_INT T1.W, T0.Z, literal.x,232; R600-NEXT: MUL_IEEE * T2.W, PS, literal.z,233; R600-NEXT: -127(nan), 254(3.559298e-43)234; R600-NEXT: 209715200(1.972152e-31), 0(0.000000e+00)235; R600-NEXT: MUL_IEEE T3.X, PS, literal.x,236; R600-NEXT: MUL_IEEE T0.Y, T1.X, literal.y,237; R600-NEXT: CNDE_INT T1.Z, PV.W, PV.Z, T0.Z,238; R600-NEXT: CNDE_INT T3.W, PV.Y, PV.X, T0.X,239; R600-NEXT: SETGT_INT * T4.W, T0.Z, literal.z,240; R600-NEXT: 209715200(1.972152e-31), 2130706432(1.701412e+38)241; R600-NEXT: 127(1.779649e-43), 0(0.000000e+00)242; R600-NEXT: CNDE_INT T0.Z, PS, PV.Z, PV.W,243; R600-NEXT: MUL_IEEE T3.W, PV.Y, literal.x,244; R600-NEXT: CNDE_INT * T0.W, T0.W, PV.X, T2.W,245; R600-NEXT: 2130706432(1.701412e+38), 0(0.000000e+00)246; R600-NEXT: CNDE_INT T1.Z, T1.W, PS, T1.X,247; R600-NEXT: CNDE_INT T0.W, T1.Y, T0.Y, PV.W,248; R600-NEXT: LSHL * T1.W, PV.Z, literal.x,249; R600-NEXT: 23(3.222986e-44), 0(0.000000e+00)250; R600-NEXT: ADD_INT T1.W, PS, literal.x,251; R600-NEXT: CNDE_INT * T0.W, T4.W, PV.Z, PV.W,252; R600-NEXT: 1065353216(1.000000e+00), 0(0.000000e+00)253; R600-NEXT: MUL_IEEE T0.W, PS, PV.W,254; R600-NEXT: SETGT * T1.W, literal.x, KC0[2].Z,255; R600-NEXT: -1036817932(-4.485347e+01), 0(0.000000e+00)256; R600-NEXT: CNDE T0.W, PS, PV.W, 0.0,257; R600-NEXT: SETGT * T1.W, KC0[2].Z, literal.x,258; R600-NEXT: 1109008539(3.853184e+01), 0(0.000000e+00)259; R600-NEXT: CNDE T0.X, PS, PV.W, literal.x,260; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,261; R600-NEXT: 2139095040(INF), 2(2.802597e-45)262;263; CM-LABEL: s_exp10_f32:264; CM: ; %bb.0:265; CM-NEXT: ALU 62, @4, KC0[CB0:0-32], KC1[]266; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0.X, T1.X267; CM-NEXT: CF_END268; CM-NEXT: PAD269; CM-NEXT: ALU clause starting at 4:270; CM-NEXT: AND_INT * T0.W, KC0[2].Z, literal.x,271; CM-NEXT: -4096(nan), 0(0.000000e+00)272; CM-NEXT: ADD * T1.W, KC0[2].Z, -PV.W,273; CM-NEXT: MUL_IEEE T0.Z, PV.W, literal.x,274; CM-NEXT: MUL_IEEE * T2.W, T0.W, literal.y,275; CM-NEXT: 975668412(6.390323e-04), 1079283712(3.321289e+00)276; CM-NEXT: RNDNE T1.Z, PV.W,277; CM-NEXT: MULADD_IEEE * T1.W, T1.W, literal.x, PV.Z,278; CM-NEXT: 1079283712(3.321289e+00), 0(0.000000e+00)279; CM-NEXT: MULADD_IEEE T0.Z, T0.W, literal.x, PV.W,280; CM-NEXT: ADD * T0.W, T2.W, -PV.Z, BS:VEC_120/SCL_212281; CM-NEXT: 975668412(6.390323e-04), 0(0.000000e+00)282; CM-NEXT: TRUNC T1.Z, T1.Z,283; CM-NEXT: ADD * T0.W, PV.W, PV.Z,284; CM-NEXT: EXP_IEEE T0.X, T0.W,285; CM-NEXT: EXP_IEEE T0.Y (MASKED), T0.W,286; CM-NEXT: EXP_IEEE T0.Z (MASKED), T0.W,287; CM-NEXT: EXP_IEEE * T0.W (MASKED), T0.W,288; CM-NEXT: FLT_TO_INT T0.Z, T1.Z,289; CM-NEXT: MUL_IEEE * T0.W, PV.X, literal.x,290; CM-NEXT: 209715200(1.972152e-31), 0(0.000000e+00)291; CM-NEXT: MUL_IEEE T0.Y, PV.W, literal.x,292; CM-NEXT: MAX_INT T1.Z, PV.Z, literal.y,293; CM-NEXT: MIN_INT * T1.W, PV.Z, literal.z,294; CM-NEXT: 209715200(1.972152e-31), -330(nan)295; CM-NEXT: 381(5.338947e-43), 0(0.000000e+00)296; CM-NEXT: ADD_INT T1.X, PV.W, literal.x,297; CM-NEXT: ADD_INT T1.Y, PV.Z, literal.y,298; CM-NEXT: ADD_INT T1.Z, T0.Z, literal.z,299; CM-NEXT: SETGT_UINT * T1.W, T0.Z, literal.w,300; CM-NEXT: -254(nan), 204(2.858649e-43)301; CM-NEXT: 102(1.429324e-43), -229(nan)302; CM-NEXT: ADD_INT T2.X, T0.Z, literal.x,303; CM-NEXT: SETGT_UINT T2.Y, T0.Z, literal.y,304; CM-NEXT: CNDE_INT T1.Z, PV.W, PV.Y, PV.Z,305; CM-NEXT: SETGT_INT * T2.W, T0.Z, literal.x,306; CM-NEXT: -127(nan), 254(3.559298e-43)307; CM-NEXT: MUL_IEEE T3.X, T0.X, literal.x,308; CM-NEXT: CNDE_INT T1.Y, PV.W, PV.Z, T0.Z,309; CM-NEXT: CNDE_INT T1.Z, PV.Y, PV.X, T1.X,310; CM-NEXT: SETGT_INT * T3.W, T0.Z, literal.y,311; CM-NEXT: 2130706432(1.701412e+38), 127(1.779649e-43)312; CM-NEXT: CNDE_INT T1.Y, PV.W, PV.Y, PV.Z,313; CM-NEXT: MUL_IEEE T0.Z, PV.X, literal.x,314; CM-NEXT: CNDE_INT * T0.W, T1.W, T0.Y, T0.W,315; CM-NEXT: 2130706432(1.701412e+38), 0(0.000000e+00)316; CM-NEXT: CNDE_INT T0.Y, T2.W, PV.W, T0.X,317; CM-NEXT: CNDE_INT T0.Z, T2.Y, T3.X, PV.Z,318; CM-NEXT: LSHL * T0.W, PV.Y, literal.x,319; CM-NEXT: 23(3.222986e-44), 0(0.000000e+00)320; CM-NEXT: ADD_INT T1.Z, PV.W, literal.x,321; CM-NEXT: CNDE_INT * T0.W, T3.W, PV.Y, PV.Z,322; CM-NEXT: 1065353216(1.000000e+00), 0(0.000000e+00)323; CM-NEXT: MUL_IEEE T0.Z, PV.W, PV.Z,324; CM-NEXT: SETGT * T0.W, literal.x, KC0[2].Z,325; CM-NEXT: -1036817932(-4.485347e+01), 0(0.000000e+00)326; CM-NEXT: CNDE T0.Z, PV.W, PV.Z, 0.0,327; CM-NEXT: SETGT * T0.W, KC0[2].Z, literal.x,328; CM-NEXT: 1109008539(3.853184e+01), 0(0.000000e+00)329; CM-NEXT: CNDE * T0.X, PV.W, PV.Z, literal.x,330; CM-NEXT: 2139095040(INF), 0(0.000000e+00)331; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,332; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)333 %result = call float @llvm.exp10.f32(float %in)334 store float %result, ptr addrspace(1) %out335 ret void336}337 338; FIXME: We should be able to merge these packets together on Cayman so we339; have a maximum of 4 instructions.340define amdgpu_kernel void @s_exp10_v2f32(ptr addrspace(1) %out, <2 x float> %in) {341; VI-SDAG-LABEL: s_exp10_v2f32:342; VI-SDAG: ; %bb.0:343; VI-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24344; VI-SDAG-NEXT: v_mov_b32_e32 v0, 0x40549000345; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)346; VI-SDAG-NEXT: s_and_b32 s4, s3, 0xfffff000347; VI-SDAG-NEXT: v_mov_b32_e32 v2, s4348; VI-SDAG-NEXT: v_sub_f32_e32 v2, s3, v2349; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x3a2784bc, v2350; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x40549000, v2351; VI-SDAG-NEXT: v_add_f32_e32 v2, v2, v4352; VI-SDAG-NEXT: v_mov_b32_e32 v4, 0x3a2784bc353; VI-SDAG-NEXT: v_mul_f32_e32 v1, s4, v0354; VI-SDAG-NEXT: v_mul_f32_e32 v5, s4, v4355; VI-SDAG-NEXT: s_and_b32 s4, s2, 0xfffff000356; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v1357; VI-SDAG-NEXT: v_mov_b32_e32 v6, s4358; VI-SDAG-NEXT: v_sub_f32_e32 v1, v1, v3359; VI-SDAG-NEXT: v_add_f32_e32 v2, v5, v2360; VI-SDAG-NEXT: v_sub_f32_e32 v6, s2, v6361; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v2362; VI-SDAG-NEXT: v_mul_f32_e32 v0, s4, v0363; VI-SDAG-NEXT: v_mul_f32_e32 v7, 0x3a2784bc, v6364; VI-SDAG-NEXT: v_mul_f32_e32 v6, 0x40549000, v6365; VI-SDAG-NEXT: v_exp_f32_e32 v1, v1366; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v3367; VI-SDAG-NEXT: v_rndne_f32_e32 v5, v0368; VI-SDAG-NEXT: v_add_f32_e32 v6, v6, v7369; VI-SDAG-NEXT: v_mul_f32_e32 v4, s4, v4370; VI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v5371; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v6372; VI-SDAG-NEXT: v_add_f32_e32 v0, v0, v4373; VI-SDAG-NEXT: v_exp_f32_e32 v0, v0374; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v4, v5375; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v2376; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0xc23369f4377; VI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s3, v2378; VI-SDAG-NEXT: v_mov_b32_e32 v3, 0x421a209b379; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc380; VI-SDAG-NEXT: v_mov_b32_e32 v5, 0x7f800000381; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s3, v3382; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc383; VI-SDAG-NEXT: v_ldexp_f32 v0, v0, v4384; VI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s2, v2385; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc386; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s2, v3387; VI-SDAG-NEXT: v_mov_b32_e32 v3, s1388; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc389; VI-SDAG-NEXT: v_mov_b32_e32 v2, s0390; VI-SDAG-NEXT: flat_store_dwordx2 v[2:3], v[0:1]391; VI-SDAG-NEXT: s_endpgm392;393; VI-GISEL-LABEL: s_exp10_v2f32:394; VI-GISEL: ; %bb.0:395; VI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24396; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x40549000397; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3a2784bc398; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)399; VI-GISEL-NEXT: s_and_b32 s4, s2, 0xfffff000400; VI-GISEL-NEXT: v_mov_b32_e32 v2, s4401; VI-GISEL-NEXT: v_sub_f32_e32 v2, s2, v2402; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3a2784bc, v2403; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549000, v2404; VI-GISEL-NEXT: v_mul_f32_e32 v3, s4, v0405; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v4406; VI-GISEL-NEXT: v_mul_f32_e32 v4, s4, v1407; VI-GISEL-NEXT: s_and_b32 s4, s3, 0xfffff000408; VI-GISEL-NEXT: v_mov_b32_e32 v5, s4409; VI-GISEL-NEXT: v_add_f32_e32 v2, v4, v2410; VI-GISEL-NEXT: v_rndne_f32_e32 v4, v3411; VI-GISEL-NEXT: v_sub_f32_e32 v5, s3, v5412; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v4413; VI-GISEL-NEXT: v_mul_f32_e32 v6, 0x3a2784bc, v5414; VI-GISEL-NEXT: v_mul_f32_e32 v5, 0x40549000, v5415; VI-GISEL-NEXT: v_add_f32_e32 v2, v3, v2416; VI-GISEL-NEXT: v_mul_f32_e32 v0, s4, v0417; VI-GISEL-NEXT: v_add_f32_e32 v5, v5, v6418; VI-GISEL-NEXT: v_mul_f32_e32 v1, s4, v1419; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v3, v4420; VI-GISEL-NEXT: v_exp_f32_e32 v2, v2421; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v5422; VI-GISEL-NEXT: v_rndne_f32_e32 v5, v0423; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v5424; VI-GISEL-NEXT: v_add_f32_e32 v0, v0, v1425; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v1, v5426; VI-GISEL-NEXT: v_exp_f32_e32 v5, v0427; VI-GISEL-NEXT: v_ldexp_f32 v2, v2, v3428; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0xc23369f4429; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v3430; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0x421a209b431; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc432; VI-GISEL-NEXT: v_mov_b32_e32 v6, 0x7f800000433; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s2, v4434; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v2, v6, vcc435; VI-GISEL-NEXT: v_ldexp_f32 v1, v5, v1436; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s3, v3437; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc438; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s3, v4439; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1440; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc441; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0442; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]443; VI-GISEL-NEXT: s_endpgm444;445; GFX900-SDAG-LABEL: s_exp10_v2f32:446; GFX900-SDAG: ; %bb.0:447; GFX900-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24448; GFX900-SDAG-NEXT: v_mov_b32_e32 v0, 0x40549a78449; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x33979a37450; GFX900-SDAG-NEXT: v_mov_b32_e32 v5, 0xc23369f4451; GFX900-SDAG-NEXT: s_waitcnt lgkmcnt(0)452; GFX900-SDAG-NEXT: v_mul_f32_e32 v2, s3, v0453; GFX900-SDAG-NEXT: v_rndne_f32_e32 v3, v2454; GFX900-SDAG-NEXT: v_fma_f32 v4, s3, v0, -v2455; GFX900-SDAG-NEXT: v_sub_f32_e32 v2, v2, v3456; GFX900-SDAG-NEXT: v_fma_f32 v4, s3, v1, v4457; GFX900-SDAG-NEXT: v_mul_f32_e32 v6, s2, v0458; GFX900-SDAG-NEXT: v_add_f32_e32 v2, v2, v4459; GFX900-SDAG-NEXT: v_rndne_f32_e32 v7, v6460; GFX900-SDAG-NEXT: v_fma_f32 v0, s2, v0, -v6461; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v3, v3462; GFX900-SDAG-NEXT: v_exp_f32_e32 v2, v2463; GFX900-SDAG-NEXT: v_sub_f32_e32 v8, v6, v7464; GFX900-SDAG-NEXT: v_fma_f32 v0, s2, v1, v0465; GFX900-SDAG-NEXT: v_add_f32_e32 v0, v8, v0466; GFX900-SDAG-NEXT: v_exp_f32_e32 v0, v0467; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v6, v7468; GFX900-SDAG-NEXT: v_ldexp_f32 v2, v2, v3469; GFX900-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s3, v5470; GFX900-SDAG-NEXT: v_mov_b32_e32 v3, 0x421a209b471; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc472; GFX900-SDAG-NEXT: v_mov_b32_e32 v7, 0x7f800000473; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s3, v3474; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, v7, v2, vcc475; GFX900-SDAG-NEXT: v_ldexp_f32 v0, v0, v6476; GFX900-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s2, v5477; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc478; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s2, v3479; GFX900-SDAG-NEXT: v_mov_b32_e32 v4, 0480; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc481; GFX900-SDAG-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1]482; GFX900-SDAG-NEXT: s_endpgm483;484; GFX900-GISEL-LABEL: s_exp10_v2f32:485; GFX900-GISEL: ; %bb.0:486; GFX900-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24487; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, 0x40549a78488; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x33979a37489; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, 0x7f800000490; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0)491; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, s2, v0492; GFX900-GISEL-NEXT: v_fma_f32 v3, s2, v0, -v2493; GFX900-GISEL-NEXT: v_rndne_f32_e32 v4, v2494; GFX900-GISEL-NEXT: v_mul_f32_e32 v5, s3, v0495; GFX900-GISEL-NEXT: v_fma_f32 v3, s2, v1, v3496; GFX900-GISEL-NEXT: v_sub_f32_e32 v2, v2, v4497; GFX900-GISEL-NEXT: v_fma_f32 v0, s3, v0, -v5498; GFX900-GISEL-NEXT: v_add_f32_e32 v2, v2, v3499; GFX900-GISEL-NEXT: v_fma_f32 v0, s3, v1, v0500; GFX900-GISEL-NEXT: v_rndne_f32_e32 v1, v5501; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v3, v4502; GFX900-GISEL-NEXT: v_exp_f32_e32 v2, v2503; GFX900-GISEL-NEXT: v_sub_f32_e32 v5, v5, v1504; GFX900-GISEL-NEXT: v_add_f32_e32 v0, v5, v0505; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v1, v1506; GFX900-GISEL-NEXT: v_exp_f32_e32 v5, v0507; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0xc23369f4508; GFX900-GISEL-NEXT: v_ldexp_f32 v2, v2, v3509; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v4510; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x421a209b511; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc512; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s2, v3513; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, v2, v6, vcc514; GFX900-GISEL-NEXT: v_ldexp_f32 v1, v5, v1515; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s3, v4516; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc517; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s3, v3518; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc519; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0520; GFX900-GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]521; GFX900-GISEL-NEXT: s_endpgm522;523; SI-SDAG-LABEL: s_exp10_v2f32:524; SI-SDAG: ; %bb.0:525; SI-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9526; SI-SDAG-NEXT: v_mov_b32_e32 v0, 0x40549a78527; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x33979a37528; SI-SDAG-NEXT: s_waitcnt lgkmcnt(0)529; SI-SDAG-NEXT: s_mov_b64 s[4:5], s[2:3]530; SI-SDAG-NEXT: v_mul_f32_e32 v2, s5, v0531; SI-SDAG-NEXT: v_rndne_f32_e32 v3, v2532; SI-SDAG-NEXT: v_fma_f32 v4, s5, v0, -v2533; SI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v3534; SI-SDAG-NEXT: v_fma_f32 v4, s5, v1, v4535; SI-SDAG-NEXT: v_add_f32_e32 v2, v2, v4536; SI-SDAG-NEXT: v_mul_f32_e32 v5, s4, v0537; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v3, v3538; SI-SDAG-NEXT: v_exp_f32_e32 v2, v2539; SI-SDAG-NEXT: v_rndne_f32_e32 v6, v5540; SI-SDAG-NEXT: v_fma_f32 v0, s4, v0, -v5541; SI-SDAG-NEXT: v_sub_f32_e32 v7, v5, v6542; SI-SDAG-NEXT: v_fma_f32 v0, s4, v1, v0543; SI-SDAG-NEXT: v_add_f32_e32 v0, v7, v0544; SI-SDAG-NEXT: v_exp_f32_e32 v0, v0545; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v5, v6546; SI-SDAG-NEXT: v_ldexp_f32_e32 v2, v2, v3547; SI-SDAG-NEXT: v_mov_b32_e32 v3, 0xc23369f4548; SI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s5, v3549; SI-SDAG-NEXT: v_mov_b32_e32 v4, 0x421a209b550; SI-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc551; SI-SDAG-NEXT: v_mov_b32_e32 v6, 0x7f800000552; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s5, v4553; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, v6, v2, vcc554; SI-SDAG-NEXT: v_ldexp_f32_e32 v0, v0, v5555; SI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v3556; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc557; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v4558; SI-SDAG-NEXT: s_mov_b32 s3, 0xf000559; SI-SDAG-NEXT: s_mov_b32 s2, -1560; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc561; SI-SDAG-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0562; SI-SDAG-NEXT: s_endpgm563;564; SI-GISEL-LABEL: s_exp10_v2f32:565; SI-GISEL: ; %bb.0:566; SI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9567; SI-GISEL-NEXT: v_mov_b32_e32 v0, 0x40549a78568; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x33979a37569; SI-GISEL-NEXT: v_mov_b32_e32 v6, 0x7f800000570; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)571; SI-GISEL-NEXT: v_mul_f32_e32 v2, s2, v0572; SI-GISEL-NEXT: v_fma_f32 v3, s2, v0, -v2573; SI-GISEL-NEXT: v_rndne_f32_e32 v4, v2574; SI-GISEL-NEXT: v_mul_f32_e32 v5, s3, v0575; SI-GISEL-NEXT: v_fma_f32 v3, s2, v1, v3576; SI-GISEL-NEXT: v_sub_f32_e32 v2, v2, v4577; SI-GISEL-NEXT: v_fma_f32 v0, s3, v0, -v5578; SI-GISEL-NEXT: v_add_f32_e32 v2, v2, v3579; SI-GISEL-NEXT: v_fma_f32 v0, s3, v1, v0580; SI-GISEL-NEXT: v_rndne_f32_e32 v1, v5581; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v3, v4582; SI-GISEL-NEXT: v_exp_f32_e32 v2, v2583; SI-GISEL-NEXT: v_sub_f32_e32 v5, v5, v1584; SI-GISEL-NEXT: v_add_f32_e32 v0, v5, v0585; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v1, v1586; SI-GISEL-NEXT: v_exp_f32_e32 v5, v0587; SI-GISEL-NEXT: v_mov_b32_e32 v4, 0xc23369f4588; SI-GISEL-NEXT: v_ldexp_f32_e32 v2, v2, v3589; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v4590; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x421a209b591; SI-GISEL-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc592; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s2, v3593; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v2, v6, vcc594; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, v5, v1595; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s3, v4596; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc597; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s3, v3598; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc599; SI-GISEL-NEXT: s_mov_b32 s2, -1600; SI-GISEL-NEXT: s_mov_b32 s3, 0xf000601; SI-GISEL-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0602; SI-GISEL-NEXT: s_endpgm603;604; R600-LABEL: s_exp10_v2f32:605; R600: ; %bb.0:606; R600-NEXT: ALU 96, @4, KC0[CB0:0-32], KC1[]607; R600-NEXT: ALU 12, @101, KC0[CB0:0-32], KC1[]608; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.XY, T0.X, 1609; R600-NEXT: CF_END610; R600-NEXT: ALU clause starting at 4:611; R600-NEXT: AND_INT * T0.W, KC0[3].X, literal.x,612; R600-NEXT: -4096(nan), 0(0.000000e+00)613; R600-NEXT: ADD * T1.W, KC0[3].X, -PV.W,614; R600-NEXT: MUL_IEEE T2.W, PV.W, literal.x,615; R600-NEXT: MUL_IEEE * T3.W, T0.W, literal.y,616; R600-NEXT: 975668412(6.390323e-04), 1079283712(3.321289e+00)617; R600-NEXT: RNDNE T0.Z, PS,618; R600-NEXT: MULADD_IEEE T1.W, T1.W, literal.x, PV.W,619; R600-NEXT: AND_INT * T2.W, KC0[2].W, literal.y,620; R600-NEXT: 1079283712(3.321289e+00), -4096(nan)621; R600-NEXT: ADD T1.Z, KC0[2].W, -PS,622; R600-NEXT: MULADD_IEEE T0.W, T0.W, literal.x, PV.W,623; R600-NEXT: ADD * T1.W, T3.W, -PV.Z,624; R600-NEXT: 975668412(6.390323e-04), 0(0.000000e+00)625; R600-NEXT: ADD T2.Z, PS, PV.W,626; R600-NEXT: MUL_IEEE T0.W, PV.Z, literal.x,627; R600-NEXT: MUL_IEEE * T1.W, T2.W, literal.y,628; R600-NEXT: 975668412(6.390323e-04), 1079283712(3.321289e+00)629; R600-NEXT: RNDNE T0.Y, PS,630; R600-NEXT: MULADD_IEEE T1.Z, T1.Z, literal.x, PV.W,631; R600-NEXT: TRUNC T0.W, T0.Z, BS:VEC_120/SCL_212632; R600-NEXT: EXP_IEEE * T0.X, PV.Z,633; R600-NEXT: 1079283712(3.321289e+00), 0(0.000000e+00)634; R600-NEXT: FLT_TO_INT T1.Y, PV.W,635; R600-NEXT: MUL_IEEE T0.Z, PS, literal.x,636; R600-NEXT: MULADD_IEEE T0.W, T2.W, literal.y, PV.Z,637; R600-NEXT: ADD * T1.W, T1.W, -PV.Y,638; R600-NEXT: 209715200(1.972152e-31), 975668412(6.390323e-04)639; R600-NEXT: ADD T1.Z, PS, PV.W,640; R600-NEXT: MUL_IEEE T0.W, PV.Z, literal.x,641; R600-NEXT: SETGT_UINT * T1.W, PV.Y, literal.y,642; R600-NEXT: 209715200(1.972152e-31), -229(nan)643; R600-NEXT: CNDE_INT T0.Z, PS, PV.W, T0.Z,644; R600-NEXT: SETGT_INT T0.W, T1.Y, literal.x,645; R600-NEXT: EXP_IEEE * T1.X, PV.Z,646; R600-NEXT: -127(nan), 0(0.000000e+00)647; R600-NEXT: CNDE_INT T0.Z, PV.W, PV.Z, T0.X,648; R600-NEXT: MAX_INT T2.W, T1.Y, literal.x,649; R600-NEXT: MUL_IEEE * T3.W, PS, literal.y,650; R600-NEXT: -330(nan), 209715200(1.972152e-31)651; R600-NEXT: MUL_IEEE T2.X, PS, literal.x,652; R600-NEXT: ADD_INT T2.Y, PV.W, literal.y,653; R600-NEXT: ADD_INT T1.Z, T1.Y, literal.z,654; R600-NEXT: MIN_INT T2.W, T1.Y, literal.w,655; R600-NEXT: TRUNC * T4.W, T0.Y,656; R600-NEXT: 209715200(1.972152e-31), 204(2.858649e-43)657; R600-NEXT: 102(1.429324e-43), 381(5.338947e-43)658; R600-NEXT: FLT_TO_INT T3.X, PS,659; R600-NEXT: ADD_INT T0.Y, PV.W, literal.x,660; R600-NEXT: ADD_INT T2.Z, T1.Y, literal.y,661; R600-NEXT: SETGT_UINT T2.W, T1.Y, literal.z,662; R600-NEXT: CNDE_INT * T1.W, T1.W, PV.Y, PV.Z,663; R600-NEXT: -254(nan), -127(nan)664; R600-NEXT: 254(3.559298e-43), 0(0.000000e+00)665; R600-NEXT: MUL_IEEE T4.X, T1.X, literal.x,666; R600-NEXT: MUL_IEEE T2.Y, T0.X, literal.x, BS:VEC_120/SCL_212667; R600-NEXT: CNDE_INT T1.Z, T0.W, PS, T1.Y,668; R600-NEXT: CNDE_INT T0.W, PV.W, PV.Z, PV.Y,669; R600-NEXT: MAX_INT * T1.W, PV.X, literal.y,670; R600-NEXT: 2130706432(1.701412e+38), -330(nan)671; R600-NEXT: SETGT_INT T0.X, T1.Y, literal.x,672; R600-NEXT: ADD_INT T0.Y, PS, literal.y,673; R600-NEXT: ADD_INT T2.Z, T3.X, literal.z,674; R600-NEXT: SETGT_UINT * T1.W, T3.X, literal.w,675; R600-NEXT: 127(1.779649e-43), 204(2.858649e-43)676; R600-NEXT: 102(1.429324e-43), -229(nan)677; R600-NEXT: MIN_INT * T4.W, T3.X, literal.x,678; R600-NEXT: 381(5.338947e-43), 0(0.000000e+00)679; R600-NEXT: ADD_INT T5.X, PV.W, literal.x,680; R600-NEXT: ADD_INT T1.Y, T3.X, literal.y,681; R600-NEXT: SETGT_UINT T3.Z, T3.X, literal.z,682; R600-NEXT: CNDE_INT T4.W, T1.W, T0.Y, T2.Z,683; R600-NEXT: SETGT_INT * T5.W, T3.X, literal.y,684; R600-NEXT: -254(nan), -127(nan)685; R600-NEXT: 254(3.559298e-43), 0(0.000000e+00)686; R600-NEXT: CNDE_INT T6.X, PS, PV.W, T3.X,687; R600-NEXT: CNDE_INT T0.Y, PV.Z, PV.Y, PV.X,688; R600-NEXT: SETGT_INT T2.Z, T3.X, literal.x,689; R600-NEXT: CNDE_INT T0.W, T0.X, T1.Z, T0.W, BS:VEC_120/SCL_212690; R600-NEXT: MUL_IEEE * T4.W, T2.Y, literal.y,691; R600-NEXT: 127(1.779649e-43), 2130706432(1.701412e+38)692; R600-NEXT: CNDE_INT T3.X, T2.W, T2.Y, PS, BS:VEC_120/SCL_212693; R600-NEXT: LSHL T1.Y, PV.W, literal.x,694; R600-NEXT: CNDE_INT T1.Z, PV.Z, PV.X, PV.Y,695; R600-NEXT: MUL_IEEE T0.W, T4.X, literal.y,696; R600-NEXT: CNDE_INT * T1.W, T1.W, T2.X, T3.W,697; R600-NEXT: 23(3.222986e-44), 2130706432(1.701412e+38)698; R600-NEXT: CNDE_INT T1.X, T5.W, PS, T1.X, BS:VEC_021/SCL_122699; R600-NEXT: CNDE_INT T0.Y, T3.Z, T4.X, PV.W, BS:VEC_201700; R600-NEXT: LSHL T1.Z, PV.Z, literal.x,701; R600-NEXT: ADD_INT T0.W, PV.Y, literal.y,702; R600-NEXT: CNDE_INT * T1.W, T0.X, T0.Z, PV.X,703; R600-NEXT: 23(3.222986e-44), 1065353216(1.000000e+00)704; R600-NEXT: MUL_IEEE T1.Y, PS, PV.W,705; R600-NEXT: SETGT T0.Z, literal.x, KC0[3].X,706; R600-NEXT: ADD_INT * T0.W, PV.Z, literal.y,707; R600-NEXT: -1036817932(-4.485347e+01), 1065353216(1.000000e+00)708; R600-NEXT: ALU clause starting at 101:709; R600-NEXT: CNDE_INT * T1.W, T2.Z, T1.X, T0.Y,710; R600-NEXT: MUL_IEEE T0.Y, PV.W, T0.W,711; R600-NEXT: SETGT T1.Z, literal.x, KC0[2].W,712; R600-NEXT: CNDE T0.W, T0.Z, T1.Y, 0.0,713; R600-NEXT: SETGT * T1.W, KC0[3].X, literal.y,714; R600-NEXT: -1036817932(-4.485347e+01), 1109008539(3.853184e+01)715; R600-NEXT: CNDE T1.Y, PS, PV.W, literal.x,716; R600-NEXT: CNDE T0.W, PV.Z, PV.Y, 0.0,717; R600-NEXT: SETGT * T1.W, KC0[2].W, literal.y,718; R600-NEXT: 2139095040(INF), 1109008539(3.853184e+01)719; R600-NEXT: CNDE T1.X, PS, PV.W, literal.x,720; R600-NEXT: LSHR * T0.X, KC0[2].Y, literal.y,721; R600-NEXT: 2139095040(INF), 2(2.802597e-45)722;723; CM-LABEL: s_exp10_v2f32:724; CM: ; %bb.0:725; CM-NEXT: ALU 98, @4, KC0[CB0:0-32], KC1[]726; CM-NEXT: ALU 18, @103, KC0[CB0:0-32], KC1[]727; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0, T1.X728; CM-NEXT: CF_END729; CM-NEXT: ALU clause starting at 4:730; CM-NEXT: AND_INT * T0.W, KC0[2].W, literal.x,731; CM-NEXT: -4096(nan), 0(0.000000e+00)732; CM-NEXT: ADD * T1.W, KC0[2].W, -PV.W,733; CM-NEXT: MUL_IEEE T0.Y, PV.W, literal.x,734; CM-NEXT: MUL_IEEE T0.Z, T0.W, literal.y,735; CM-NEXT: AND_INT * T2.W, KC0[3].X, literal.z,736; CM-NEXT: 975668412(6.390323e-04), 1079283712(3.321289e+00)737; CM-NEXT: -4096(nan), 0(0.000000e+00)738; CM-NEXT: ADD T1.Y, KC0[3].X, -PV.W,739; CM-NEXT: RNDNE T1.Z, PV.Z,740; CM-NEXT: MULADD_IEEE * T1.W, T1.W, literal.x, PV.Y,741; CM-NEXT: 1079283712(3.321289e+00), 0(0.000000e+00)742; CM-NEXT: MULADD_IEEE T0.X, T0.W, literal.x, PV.W,743; CM-NEXT: ADD T0.Y, T0.Z, -PV.Z,744; CM-NEXT: MUL_IEEE T0.Z, PV.Y, literal.x,745; CM-NEXT: MUL_IEEE * T0.W, T2.W, literal.y, BS:VEC_120/SCL_212746; CM-NEXT: 975668412(6.390323e-04), 1079283712(3.321289e+00)747; CM-NEXT: TRUNC T1.X, T1.Z,748; CM-NEXT: RNDNE T2.Y, PV.W,749; CM-NEXT: MULADD_IEEE T0.Z, T1.Y, literal.x, PV.Z,750; CM-NEXT: ADD * T1.W, PV.Y, PV.X,751; CM-NEXT: 1079283712(3.321289e+00), 0(0.000000e+00)752; CM-NEXT: EXP_IEEE T0.X, T1.W,753; CM-NEXT: EXP_IEEE T0.Y (MASKED), T1.W,754; CM-NEXT: EXP_IEEE T0.Z (MASKED), T1.W,755; CM-NEXT: EXP_IEEE * T0.W (MASKED), T1.W,756; CM-NEXT: MULADD_IEEE T2.X, T2.W, literal.x, T0.Z,757; CM-NEXT: ADD T0.Y, T0.W, -T2.Y, BS:VEC_120/SCL_212758; CM-NEXT: FLT_TO_INT T0.Z, T1.X,759; CM-NEXT: MUL_IEEE * T0.W, PV.X, literal.y,760; CM-NEXT: 975668412(6.390323e-04), 209715200(1.972152e-31)761; CM-NEXT: MUL_IEEE T1.X, PV.W, literal.x,762; CM-NEXT: SETGT_UINT T1.Y, PV.Z, literal.y,763; CM-NEXT: TRUNC T1.Z, T2.Y,764; CM-NEXT: ADD * T1.W, PV.Y, PV.X,765; CM-NEXT: 209715200(1.972152e-31), -229(nan)766; CM-NEXT: EXP_IEEE T0.X (MASKED), T1.W,767; CM-NEXT: EXP_IEEE T0.Y, T1.W,768; CM-NEXT: EXP_IEEE T0.Z (MASKED), T1.W,769; CM-NEXT: EXP_IEEE * T0.W (MASKED), T1.W,770; CM-NEXT: FLT_TO_INT T2.X, T1.Z,771; CM-NEXT: MUL_IEEE T2.Y, PV.Y, literal.x,772; CM-NEXT: CNDE_INT T1.Z, T1.Y, T1.X, T0.W,773; CM-NEXT: SETGT_INT * T0.W, T0.Z, literal.y, BS:VEC_120/SCL_212774; CM-NEXT: 209715200(1.972152e-31), -127(nan)775; CM-NEXT: CNDE_INT T1.X, PV.W, PV.Z, T0.X,776; CM-NEXT: MUL_IEEE T3.Y, PV.Y, literal.x,777; CM-NEXT: SETGT_UINT T1.Z, PV.X, literal.y,778; CM-NEXT: MAX_INT * T1.W, T0.Z, literal.z,779; CM-NEXT: 209715200(1.972152e-31), -229(nan)780; CM-NEXT: -330(nan), 0(0.000000e+00)781; CM-NEXT: ADD_INT T3.X, PV.W, literal.x,782; CM-NEXT: ADD_INT T4.Y, T0.Z, literal.y,783; CM-NEXT: CNDE_INT T2.Z, PV.Z, PV.Y, T2.Y,784; CM-NEXT: SETGT_INT * T1.W, T2.X, literal.z,785; CM-NEXT: 204(2.858649e-43), 102(1.429324e-43)786; CM-NEXT: -127(nan), 0(0.000000e+00)787; CM-NEXT: CNDE_INT T4.X, PV.W, PV.Z, T0.Y,788; CM-NEXT: MUL_IEEE T2.Y, T0.X, literal.x,789; CM-NEXT: MAX_INT T2.Z, T2.X, literal.y, BS:VEC_120/SCL_212790; CM-NEXT: CNDE_INT * T2.W, T1.Y, PV.X, PV.Y,791; CM-NEXT: 2130706432(1.701412e+38), -330(nan)792; CM-NEXT: CNDE_INT T0.X, T0.W, PV.W, T0.Z,793; CM-NEXT: ADD_INT T1.Y, PV.Z, literal.x,794; CM-NEXT: ADD_INT T2.Z, T2.X, literal.y,795; CM-NEXT: MIN_INT * T0.W, T2.X, literal.z,796; CM-NEXT: 204(2.858649e-43), 102(1.429324e-43)797; CM-NEXT: 381(5.338947e-43), 0(0.000000e+00)798; CM-NEXT: ADD_INT T3.X, PV.W, literal.x,799; CM-NEXT: ADD_INT T3.Y, T2.X, literal.y,800; CM-NEXT: SETGT_UINT T3.Z, T2.X, literal.z,801; CM-NEXT: CNDE_INT * T0.W, T1.Z, PV.Y, PV.Z,802; CM-NEXT: -254(nan), -127(nan)803; CM-NEXT: 254(3.559298e-43), 0(0.000000e+00)804; CM-NEXT: MUL_IEEE T5.X, T0.Y, literal.x,805; CM-NEXT: CNDE_INT T0.Y, T1.W, PV.W, T2.X,806; CM-NEXT: CNDE_INT T1.Z, PV.Z, PV.Y, PV.X,807; CM-NEXT: MIN_INT * T0.W, T0.Z, literal.y,808; CM-NEXT: 2130706432(1.701412e+38), 381(5.338947e-43)809; CM-NEXT: SETGT_INT T2.X, T2.X, literal.x,810; CM-NEXT: ADD_INT T1.Y, PV.W, literal.y,811; CM-NEXT: ADD_INT T2.Z, T0.Z, literal.z,812; CM-NEXT: SETGT_UINT * T0.W, T0.Z, literal.w,813; CM-NEXT: 127(1.779649e-43), -254(nan)814; CM-NEXT: -127(nan), 254(3.559298e-43)815; CM-NEXT: CNDE_INT T3.X, PV.W, PV.Z, PV.Y,816; CM-NEXT: SETGT_INT T1.Y, T0.Z, literal.x,817; CM-NEXT: CNDE_INT T0.Z, PV.X, T0.Y, T1.Z,818; CM-NEXT: MUL_IEEE * T1.W, T5.X, literal.y,819; CM-NEXT: 127(1.779649e-43), 2130706432(1.701412e+38)820; CM-NEXT: CNDE_INT T5.X, T3.Z, T5.X, PV.W,821; CM-NEXT: LSHL T0.Y, PV.Z, literal.x,822; CM-NEXT: CNDE_INT T0.Z, PV.Y, T0.X, PV.X, BS:VEC_021/SCL_122823; CM-NEXT: MUL_IEEE * T1.W, T2.Y, literal.y,824; CM-NEXT: 23(3.222986e-44), 2130706432(1.701412e+38)825; CM-NEXT: CNDE_INT T0.X, T0.W, T2.Y, PV.W,826; CM-NEXT: LSHL T2.Y, PV.Z, literal.x,827; CM-NEXT: ADD_INT * T0.Z, PV.Y, literal.y,828; CM-NEXT: 23(3.222986e-44), 1065353216(1.000000e+00)829; CM-NEXT: ALU clause starting at 103:830; CM-NEXT: CNDE_INT * T0.W, T2.X, T4.X, T5.X,831; CM-NEXT: MUL_IEEE T2.X, PV.W, T0.Z,832; CM-NEXT: SETGT T0.Y, literal.x, KC0[3].X,833; CM-NEXT: ADD_INT T0.Z, T2.Y, literal.y,834; CM-NEXT: CNDE_INT * T0.W, T1.Y, T1.X, T0.X, BS:VEC_120/SCL_212835; CM-NEXT: -1036817932(-4.485347e+01), 1065353216(1.000000e+00)836; CM-NEXT: MUL_IEEE T0.X, PV.W, PV.Z,837; CM-NEXT: SETGT T1.Y, literal.x, KC0[2].W,838; CM-NEXT: CNDE T0.Z, PV.Y, PV.X, 0.0,839; CM-NEXT: SETGT * T0.W, KC0[3].X, literal.y,840; CM-NEXT: -1036817932(-4.485347e+01), 1109008539(3.853184e+01)841; CM-NEXT: CNDE T0.Y, PV.W, PV.Z, literal.x,842; CM-NEXT: CNDE T0.Z, PV.Y, PV.X, 0.0,843; CM-NEXT: SETGT * T0.W, KC0[2].W, literal.y,844; CM-NEXT: 2139095040(INF), 1109008539(3.853184e+01)845; CM-NEXT: CNDE * T0.X, PV.W, PV.Z, literal.x,846; CM-NEXT: 2139095040(INF), 0(0.000000e+00)847; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,848; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)849 %result = call <2 x float> @llvm.exp10.v2f32(<2 x float> %in)850 store <2 x float> %result, ptr addrspace(1) %out851 ret void852}853 854define amdgpu_kernel void @s_exp10_v3f32(ptr addrspace(1) %out, <3 x float> %in) {855; VI-SDAG-LABEL: s_exp10_v3f32:856; VI-SDAG: ; %bb.0:857; VI-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34858; VI-SDAG-NEXT: v_mov_b32_e32 v0, 0x40549000859; VI-SDAG-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x24860; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)861; VI-SDAG-NEXT: s_and_b32 s3, s2, 0xfffff000862; VI-SDAG-NEXT: v_mov_b32_e32 v2, s3863; VI-SDAG-NEXT: v_sub_f32_e32 v2, s2, v2864; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x3a2784bc, v2865; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x40549000, v2866; VI-SDAG-NEXT: v_mul_f32_e32 v1, s3, v0867; VI-SDAG-NEXT: v_add_f32_e32 v2, v2, v4868; VI-SDAG-NEXT: v_mov_b32_e32 v4, 0x3a2784bc869; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v1870; VI-SDAG-NEXT: v_mul_f32_e32 v5, s3, v4871; VI-SDAG-NEXT: v_sub_f32_e32 v1, v1, v3872; VI-SDAG-NEXT: v_add_f32_e32 v2, v5, v2873; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v2874; VI-SDAG-NEXT: v_exp_f32_e32 v1, v1875; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v3876; VI-SDAG-NEXT: s_and_b32 s3, s1, 0xfffff000877; VI-SDAG-NEXT: v_mov_b32_e32 v7, s3878; VI-SDAG-NEXT: v_sub_f32_e32 v7, s1, v7879; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v2880; VI-SDAG-NEXT: v_mul_f32_e32 v2, s3, v0881; VI-SDAG-NEXT: v_mul_f32_e32 v8, 0x3a2784bc, v7882; VI-SDAG-NEXT: v_mul_f32_e32 v7, 0x40549000, v7883; VI-SDAG-NEXT: v_rndne_f32_e32 v6, v2884; VI-SDAG-NEXT: v_add_f32_e32 v7, v7, v8885; VI-SDAG-NEXT: v_mul_f32_e32 v8, s3, v4886; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v6887; VI-SDAG-NEXT: v_add_f32_e32 v7, v8, v7888; VI-SDAG-NEXT: v_add_f32_e32 v2, v2, v7889; VI-SDAG-NEXT: v_exp_f32_e32 v7, v2890; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v6, v6891; VI-SDAG-NEXT: v_mov_b32_e32 v3, 0xc23369f4892; VI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s2, v3893; VI-SDAG-NEXT: v_mov_b32_e32 v5, 0x421a209b894; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc895; VI-SDAG-NEXT: v_mov_b32_e32 v8, 0x7f800000896; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s2, v5897; VI-SDAG-NEXT: s_and_b32 s2, s0, 0xfffff000898; VI-SDAG-NEXT: v_cndmask_b32_e32 v2, v8, v1, vcc899; VI-SDAG-NEXT: v_ldexp_f32 v1, v7, v6900; VI-SDAG-NEXT: v_mov_b32_e32 v7, s2901; VI-SDAG-NEXT: v_sub_f32_e32 v7, s0, v7902; VI-SDAG-NEXT: v_mul_f32_e32 v0, s2, v0903; VI-SDAG-NEXT: v_mul_f32_e32 v9, 0x3a2784bc, v7904; VI-SDAG-NEXT: v_mul_f32_e32 v7, 0x40549000, v7905; VI-SDAG-NEXT: v_rndne_f32_e32 v6, v0906; VI-SDAG-NEXT: v_add_f32_e32 v7, v7, v9907; VI-SDAG-NEXT: v_mul_f32_e32 v4, s2, v4908; VI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v6909; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v7910; VI-SDAG-NEXT: v_add_f32_e32 v0, v0, v4911; VI-SDAG-NEXT: v_exp_f32_e32 v0, v0912; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v4, v6913; VI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s1, v3914; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc915; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s1, v5916; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc917; VI-SDAG-NEXT: v_ldexp_f32 v0, v0, v4918; VI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s0, v3919; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc920; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s0, v5921; VI-SDAG-NEXT: v_mov_b32_e32 v3, s4922; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc923; VI-SDAG-NEXT: v_mov_b32_e32 v4, s5924; VI-SDAG-NEXT: flat_store_dwordx3 v[3:4], v[0:2]925; VI-SDAG-NEXT: s_endpgm926;927; VI-GISEL-LABEL: s_exp10_v3f32:928; VI-GISEL: ; %bb.0:929; VI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34930; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x40549000931; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x3a2784bc932; VI-GISEL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x24933; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)934; VI-GISEL-NEXT: s_and_b32 s3, s0, 0xfffff000935; VI-GISEL-NEXT: v_mov_b32_e32 v0, s3936; VI-GISEL-NEXT: v_sub_f32_e32 v0, s0, v0937; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3a2784bc, v0938; VI-GISEL-NEXT: v_mul_f32_e32 v0, 0x40549000, v0939; VI-GISEL-NEXT: v_mul_f32_e32 v3, s3, v1940; VI-GISEL-NEXT: v_add_f32_e32 v0, v0, v4941; VI-GISEL-NEXT: v_mul_f32_e32 v4, s3, v2942; VI-GISEL-NEXT: s_and_b32 s3, s1, 0xfffff000943; VI-GISEL-NEXT: v_mov_b32_e32 v5, s3944; VI-GISEL-NEXT: v_add_f32_e32 v0, v4, v0945; VI-GISEL-NEXT: v_rndne_f32_e32 v4, v3946; VI-GISEL-NEXT: v_sub_f32_e32 v5, s1, v5947; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v4948; VI-GISEL-NEXT: v_mul_f32_e32 v7, 0x3a2784bc, v5949; VI-GISEL-NEXT: v_mul_f32_e32 v5, 0x40549000, v5950; VI-GISEL-NEXT: v_add_f32_e32 v0, v3, v0951; VI-GISEL-NEXT: v_mul_f32_e32 v6, s3, v1952; VI-GISEL-NEXT: v_add_f32_e32 v5, v5, v7953; VI-GISEL-NEXT: v_mul_f32_e32 v7, s3, v2954; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v3, v4955; VI-GISEL-NEXT: v_exp_f32_e32 v0, v0956; VI-GISEL-NEXT: v_add_f32_e32 v5, v7, v5957; VI-GISEL-NEXT: v_rndne_f32_e32 v7, v6958; VI-GISEL-NEXT: v_sub_f32_e32 v6, v6, v7959; VI-GISEL-NEXT: v_add_f32_e32 v5, v6, v5960; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v6, v7961; VI-GISEL-NEXT: v_exp_f32_e32 v5, v5962; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v3963; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0xc23369f4964; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s0, v3965; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0x421a209b966; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc967; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s0, v4968; VI-GISEL-NEXT: s_and_b32 s0, s2, 0xfffff000969; VI-GISEL-NEXT: v_ldexp_f32 v5, v5, v6970; VI-GISEL-NEXT: v_mov_b32_e32 v6, s0971; VI-GISEL-NEXT: v_sub_f32_e32 v6, s2, v6972; VI-GISEL-NEXT: v_mul_f32_e32 v8, 0x3a2784bc, v6973; VI-GISEL-NEXT: v_mul_f32_e32 v6, 0x40549000, v6974; VI-GISEL-NEXT: v_mul_f32_e32 v1, s0, v1975; VI-GISEL-NEXT: v_add_f32_e32 v6, v6, v8976; VI-GISEL-NEXT: v_mul_f32_e32 v2, s0, v2977; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v6978; VI-GISEL-NEXT: v_rndne_f32_e32 v6, v1979; VI-GISEL-NEXT: v_sub_f32_e32 v1, v1, v6980; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2981; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v6982; VI-GISEL-NEXT: v_exp_f32_e32 v6, v1983; VI-GISEL-NEXT: v_mov_b32_e32 v7, 0x7f800000984; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc985; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s1, v3986; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v5, 0, vcc987; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s1, v4988; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc989; VI-GISEL-NEXT: v_ldexp_f32 v2, v6, v2990; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v3991; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc992; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s2, v4993; VI-GISEL-NEXT: v_mov_b32_e32 v3, s4994; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc995; VI-GISEL-NEXT: v_mov_b32_e32 v4, s5996; VI-GISEL-NEXT: flat_store_dwordx3 v[3:4], v[0:2]997; VI-GISEL-NEXT: s_endpgm998;999; GFX900-SDAG-LABEL: s_exp10_v3f32:1000; GFX900-SDAG: ; %bb.0:1001; GFX900-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x341002; GFX900-SDAG-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x241003; GFX900-SDAG-NEXT: v_mov_b32_e32 v0, 0x40549a781004; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x33979a371005; GFX900-SDAG-NEXT: v_mov_b32_e32 v5, 0x421a209b1006; GFX900-SDAG-NEXT: s_waitcnt lgkmcnt(0)1007; GFX900-SDAG-NEXT: v_mul_f32_e32 v6, s1, v01008; GFX900-SDAG-NEXT: v_rndne_f32_e32 v7, v61009; GFX900-SDAG-NEXT: v_sub_f32_e32 v8, v6, v71010; GFX900-SDAG-NEXT: v_fma_f32 v6, s1, v0, -v61011; GFX900-SDAG-NEXT: v_fma_f32 v6, s1, v1, v61012; GFX900-SDAG-NEXT: v_mul_f32_e32 v2, s2, v01013; GFX900-SDAG-NEXT: v_add_f32_e32 v6, v8, v61014; GFX900-SDAG-NEXT: v_rndne_f32_e32 v3, v21015; GFX900-SDAG-NEXT: v_fma_f32 v4, s2, v0, -v21016; GFX900-SDAG-NEXT: v_exp_f32_e32 v6, v61017; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v7, v71018; GFX900-SDAG-NEXT: v_sub_f32_e32 v2, v2, v31019; GFX900-SDAG-NEXT: v_fma_f32 v4, s2, v1, v41020; GFX900-SDAG-NEXT: v_add_f32_e32 v2, v2, v41021; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v3, v31022; GFX900-SDAG-NEXT: v_exp_f32_e32 v2, v21023; GFX900-SDAG-NEXT: v_ldexp_f32 v6, v6, v71024; GFX900-SDAG-NEXT: v_mul_f32_e32 v7, s0, v01025; GFX900-SDAG-NEXT: v_rndne_f32_e32 v9, v71026; GFX900-SDAG-NEXT: v_fma_f32 v0, s0, v0, -v71027; GFX900-SDAG-NEXT: v_sub_f32_e32 v10, v7, v91028; GFX900-SDAG-NEXT: v_fma_f32 v0, s0, v1, v01029; GFX900-SDAG-NEXT: v_ldexp_f32 v2, v2, v31030; GFX900-SDAG-NEXT: v_mov_b32_e32 v3, 0xc23369f41031; GFX900-SDAG-NEXT: v_add_f32_e32 v0, v10, v01032; GFX900-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s2, v31033; GFX900-SDAG-NEXT: v_exp_f32_e32 v0, v01034; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v7, v91035; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc1036; GFX900-SDAG-NEXT: v_mov_b32_e32 v8, 0x7f8000001037; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s2, v51038; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v2, v8, v2, vcc1039; GFX900-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s1, v31040; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v6, vcc1041; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s1, v51042; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc1043; GFX900-SDAG-NEXT: v_ldexp_f32 v0, v0, v71044; GFX900-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s0, v31045; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc1046; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s0, v51047; GFX900-SDAG-NEXT: v_mov_b32_e32 v4, 01048; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc1049; GFX900-SDAG-NEXT: global_store_dwordx3 v4, v[0:2], s[6:7]1050; GFX900-SDAG-NEXT: s_endpgm1051;1052; GFX900-GISEL-LABEL: s_exp10_v3f32:1053; GFX900-GISEL: ; %bb.0:1054; GFX900-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x341055; GFX900-GISEL-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x241056; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x40549a781057; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x33979a371058; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0)1059; GFX900-GISEL-NEXT: v_mul_f32_e32 v5, s1, v11060; GFX900-GISEL-NEXT: v_fma_f32 v6, s1, v1, -v51061; GFX900-GISEL-NEXT: v_rndne_f32_e32 v7, v51062; GFX900-GISEL-NEXT: v_fma_f32 v6, s1, v2, v61063; GFX900-GISEL-NEXT: v_sub_f32_e32 v5, v5, v71064; GFX900-GISEL-NEXT: v_add_f32_e32 v5, v5, v61065; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v6, v71066; GFX900-GISEL-NEXT: v_exp_f32_e32 v5, v51067; GFX900-GISEL-NEXT: v_mul_f32_e32 v0, s0, v11068; GFX900-GISEL-NEXT: v_fma_f32 v3, s0, v1, -v01069; GFX900-GISEL-NEXT: v_rndne_f32_e32 v4, v01070; GFX900-GISEL-NEXT: v_fma_f32 v3, s0, v2, v31071; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v41072; GFX900-GISEL-NEXT: v_add_f32_e32 v0, v0, v31073; GFX900-GISEL-NEXT: v_ldexp_f32 v5, v5, v61074; GFX900-GISEL-NEXT: v_mul_f32_e32 v6, s2, v11075; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v3, v41076; GFX900-GISEL-NEXT: v_exp_f32_e32 v0, v01077; GFX900-GISEL-NEXT: v_fma_f32 v1, s2, v1, -v61078; GFX900-GISEL-NEXT: v_fma_f32 v1, s2, v2, v11079; GFX900-GISEL-NEXT: v_rndne_f32_e32 v2, v61080; GFX900-GISEL-NEXT: v_sub_f32_e32 v6, v6, v21081; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0xc23369f41082; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v6, v11083; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v31084; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s0, v41085; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x421a209b1086; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v21087; GFX900-GISEL-NEXT: v_exp_f32_e32 v6, v11088; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc1089; GFX900-GISEL-NEXT: v_mov_b32_e32 v7, 0x7f8000001090; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s0, v31091; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc1092; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s1, v41093; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, v5, 0, vcc1094; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s1, v31095; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc1096; GFX900-GISEL-NEXT: v_ldexp_f32 v2, v6, v21097; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v41098; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc1099; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s2, v31100; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc1101; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 01102; GFX900-GISEL-NEXT: global_store_dwordx3 v3, v[0:2], s[6:7]1103; GFX900-GISEL-NEXT: s_endpgm1104;1105; SI-SDAG-LABEL: s_exp10_v3f32:1106; SI-SDAG: ; %bb.0:1107; SI-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xd1108; SI-SDAG-NEXT: v_mov_b32_e32 v0, 0x40549a781109; SI-SDAG-NEXT: v_mov_b32_e32 v2, 0x33979a371110; SI-SDAG-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x91111; SI-SDAG-NEXT: s_mov_b32 s7, 0xf0001112; SI-SDAG-NEXT: s_waitcnt lgkmcnt(0)1113; SI-SDAG-NEXT: v_mul_f32_e32 v5, s0, v01114; SI-SDAG-NEXT: v_rndne_f32_e32 v6, v51115; SI-SDAG-NEXT: v_sub_f32_e32 v7, v5, v61116; SI-SDAG-NEXT: v_fma_f32 v5, s0, v0, -v51117; SI-SDAG-NEXT: v_fma_f32 v5, s0, v2, v51118; SI-SDAG-NEXT: v_mul_f32_e32 v1, s1, v01119; SI-SDAG-NEXT: v_add_f32_e32 v5, v7, v51120; SI-SDAG-NEXT: v_rndne_f32_e32 v3, v11121; SI-SDAG-NEXT: v_fma_f32 v4, s1, v0, -v11122; SI-SDAG-NEXT: v_exp_f32_e32 v5, v51123; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v6, v61124; SI-SDAG-NEXT: v_sub_f32_e32 v1, v1, v31125; SI-SDAG-NEXT: v_fma_f32 v4, s1, v2, v41126; SI-SDAG-NEXT: v_add_f32_e32 v1, v1, v41127; SI-SDAG-NEXT: v_exp_f32_e32 v1, v11128; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v3, v31129; SI-SDAG-NEXT: v_ldexp_f32_e32 v5, v5, v61130; SI-SDAG-NEXT: v_mul_f32_e32 v6, s2, v01131; SI-SDAG-NEXT: v_rndne_f32_e32 v8, v61132; SI-SDAG-NEXT: v_fma_f32 v0, s2, v0, -v61133; SI-SDAG-NEXT: v_sub_f32_e32 v9, v6, v81134; SI-SDAG-NEXT: v_fma_f32 v0, s2, v2, v01135; SI-SDAG-NEXT: v_ldexp_f32_e32 v1, v1, v31136; SI-SDAG-NEXT: v_mov_b32_e32 v3, 0xc23369f41137; SI-SDAG-NEXT: v_add_f32_e32 v0, v9, v01138; SI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s1, v31139; SI-SDAG-NEXT: v_mov_b32_e32 v4, 0x421a209b1140; SI-SDAG-NEXT: v_exp_f32_e32 v2, v01141; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v6, v81142; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc1143; SI-SDAG-NEXT: v_mov_b32_e32 v7, 0x7f8000001144; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s1, v41145; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, v7, v1, vcc1146; SI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s0, v31147; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v5, vcc1148; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s0, v41149; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc1150; SI-SDAG-NEXT: v_ldexp_f32_e32 v2, v2, v61151; SI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s2, v31152; SI-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc1153; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s2, v41154; SI-SDAG-NEXT: s_mov_b32 s6, -11155; SI-SDAG-NEXT: v_cndmask_b32_e32 v2, v7, v2, vcc1156; SI-SDAG-NEXT: buffer_store_dword v2, off, s[4:7], 0 offset:81157; SI-SDAG-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 01158; SI-SDAG-NEXT: s_endpgm1159;1160; SI-GISEL-LABEL: s_exp10_v3f32:1161; SI-GISEL: ; %bb.0:1162; SI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xd1163; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x40549a781164; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x33979a371165; SI-GISEL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x91166; SI-GISEL-NEXT: s_mov_b32 s6, -11167; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)1168; SI-GISEL-NEXT: v_mul_f32_e32 v5, s1, v11169; SI-GISEL-NEXT: v_fma_f32 v6, s1, v1, -v51170; SI-GISEL-NEXT: v_rndne_f32_e32 v7, v51171; SI-GISEL-NEXT: v_fma_f32 v6, s1, v2, v61172; SI-GISEL-NEXT: v_sub_f32_e32 v5, v5, v71173; SI-GISEL-NEXT: v_add_f32_e32 v5, v5, v61174; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v6, v71175; SI-GISEL-NEXT: v_exp_f32_e32 v5, v51176; SI-GISEL-NEXT: v_mul_f32_e32 v0, s0, v11177; SI-GISEL-NEXT: v_fma_f32 v3, s0, v1, -v01178; SI-GISEL-NEXT: v_rndne_f32_e32 v4, v01179; SI-GISEL-NEXT: v_fma_f32 v3, s0, v2, v31180; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v41181; SI-GISEL-NEXT: v_add_f32_e32 v0, v0, v31182; SI-GISEL-NEXT: v_ldexp_f32_e32 v5, v5, v61183; SI-GISEL-NEXT: v_mul_f32_e32 v6, s2, v11184; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v3, v41185; SI-GISEL-NEXT: v_exp_f32_e32 v0, v01186; SI-GISEL-NEXT: v_fma_f32 v1, s2, v1, -v61187; SI-GISEL-NEXT: v_fma_f32 v1, s2, v2, v11188; SI-GISEL-NEXT: v_rndne_f32_e32 v2, v61189; SI-GISEL-NEXT: v_sub_f32_e32 v6, v6, v21190; SI-GISEL-NEXT: v_mov_b32_e32 v4, 0xc23369f41191; SI-GISEL-NEXT: v_add_f32_e32 v1, v6, v11192; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v31193; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s0, v41194; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x421a209b1195; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v21196; SI-GISEL-NEXT: v_exp_f32_e32 v6, v11197; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc1198; SI-GISEL-NEXT: v_mov_b32_e32 v7, 0x7f8000001199; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s0, v31200; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc1201; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s1, v41202; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, v5, 0, vcc1203; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s1, v31204; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc1205; SI-GISEL-NEXT: v_ldexp_f32_e32 v2, v6, v21206; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v41207; SI-GISEL-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc1208; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s2, v31209; SI-GISEL-NEXT: s_mov_b32 s7, 0xf0001210; SI-GISEL-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc1211; SI-GISEL-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 01212; SI-GISEL-NEXT: buffer_store_dword v2, off, s[4:7], 0 offset:81213; SI-GISEL-NEXT: s_endpgm1214;1215; R600-LABEL: s_exp10_v3f32:1216; R600: ; %bb.0:1217; R600-NEXT: ALU 99, @6, KC0[CB0:0-32], KC1[]1218; R600-NEXT: ALU 69, @106, KC0[CB0:0-32], KC1[]1219; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T2.X, T3.X, 01220; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 11221; R600-NEXT: CF_END1222; R600-NEXT: PAD1223; R600-NEXT: ALU clause starting at 6:1224; R600-NEXT: AND_INT * T0.W, KC0[3].Y, literal.x,1225; R600-NEXT: -4096(nan), 0(0.000000e+00)1226; R600-NEXT: MUL_IEEE T1.W, PV.W, literal.x,1227; R600-NEXT: ADD * T2.W, KC0[3].Y, -PV.W,1228; R600-NEXT: 1079283712(3.321289e+00), 0(0.000000e+00)1229; R600-NEXT: RNDNE * T3.W, PV.W,1230; R600-NEXT: TRUNC T4.W, PV.W,1231; R600-NEXT: MUL_IEEE * T5.W, T2.W, literal.x,1232; R600-NEXT: 975668412(6.390323e-04), 0(0.000000e+00)1233; R600-NEXT: MULADD_IEEE T2.W, T2.W, literal.x, PS,1234; R600-NEXT: FLT_TO_INT * T4.W, PV.W,1235; R600-NEXT: 1079283712(3.321289e+00), 0(0.000000e+00)1236; R600-NEXT: MAX_INT T0.Z, PS, literal.x,1237; R600-NEXT: MULADD_IEEE T0.W, T0.W, literal.y, PV.W,1238; R600-NEXT: ADD * T1.W, T1.W, -T3.W,1239; R600-NEXT: -330(nan), 975668412(6.390323e-04)1240; R600-NEXT: ADD T0.Y, PS, PV.W,1241; R600-NEXT: ADD_INT T0.Z, PV.Z, literal.x,1242; R600-NEXT: ADD_INT T0.W, T4.W, literal.y,1243; R600-NEXT: SETGT_UINT * T1.W, T4.W, literal.z,1244; R600-NEXT: 204(2.858649e-43), 102(1.429324e-43)1245; R600-NEXT: -229(nan), 0(0.000000e+00)1246; R600-NEXT: CNDE_INT T0.Z, PS, PV.Z, PV.W,1247; R600-NEXT: SETGT_INT T0.W, T4.W, literal.x,1248; R600-NEXT: EXP_IEEE * T0.X, PV.Y,1249; R600-NEXT: -127(nan), 0(0.000000e+00)1250; R600-NEXT: MUL_IEEE T1.X, PS, literal.x,1251; R600-NEXT: CNDE_INT T0.Y, PV.W, PV.Z, T4.W,1252; R600-NEXT: MIN_INT T0.Z, T4.W, literal.y,1253; R600-NEXT: AND_INT T2.W, KC0[3].W, literal.z,1254; R600-NEXT: MUL_IEEE * T3.W, PS, literal.w,1255; R600-NEXT: 2130706432(1.701412e+38), 381(5.338947e-43)1256; R600-NEXT: -4096(nan), 209715200(1.972152e-31)1257; R600-NEXT: MUL_IEEE T2.X, PS, literal.x,1258; R600-NEXT: ADD T1.Y, KC0[3].W, -PV.W,1259; R600-NEXT: ADD_INT T0.Z, PV.Z, literal.y,1260; R600-NEXT: ADD_INT T5.W, T4.W, literal.z,1261; R600-NEXT: SETGT_UINT * T6.W, T4.W, literal.w,1262; R600-NEXT: 209715200(1.972152e-31), -254(nan)1263; R600-NEXT: -127(nan), 254(3.559298e-43)1264; R600-NEXT: CNDE_INT T3.X, PS, PV.W, PV.Z,1265; R600-NEXT: SETGT_INT T2.Y, T4.W, literal.x,1266; R600-NEXT: MUL_IEEE T0.Z, PV.Y, literal.y,1267; R600-NEXT: MUL_IEEE * T4.W, T2.W, literal.z, BS:VEC_120/SCL_2121268; R600-NEXT: 127(1.779649e-43), 975668412(6.390323e-04)1269; R600-NEXT: 1079283712(3.321289e+00), 0(0.000000e+00)1270; R600-NEXT: CNDE_INT * T1.W, T1.W, T2.X, T3.W,1271; R600-NEXT: CNDE_INT T0.X, T0.W, PV.W, T0.X, BS:VEC_021/SCL_1221272; R600-NEXT: RNDNE T3.Y, T4.W, BS:VEC_120/SCL_2121273; R600-NEXT: MULADD_IEEE T0.Z, T1.Y, literal.x, T0.Z,1274; R600-NEXT: CNDE_INT T0.W, T2.Y, T0.Y, T3.X, BS:VEC_120/SCL_2121275; R600-NEXT: MUL_IEEE * T1.W, T1.X, literal.y,1276; R600-NEXT: 1079283712(3.321289e+00), 2130706432(1.701412e+38)1277; R600-NEXT: CNDE_INT T1.X, T6.W, T1.X, PS,1278; R600-NEXT: LSHL T0.Y, PV.W, literal.x,1279; R600-NEXT: AND_INT T1.Z, KC0[3].Z, literal.y,1280; R600-NEXT: MULADD_IEEE T0.W, T2.W, literal.z, PV.Z, BS:VEC_120/SCL_2121281; R600-NEXT: ADD * T1.W, T4.W, -PV.Y,1282; R600-NEXT: 23(3.222986e-44), -4096(nan)1283; R600-NEXT: 975668412(6.390323e-04), 0(0.000000e+00)1284; R600-NEXT: ADD T1.Y, PS, PV.W,1285; R600-NEXT: MUL_IEEE T0.Z, PV.Z, literal.x,1286; R600-NEXT: ADD_INT T0.W, PV.Y, literal.y,1287; R600-NEXT: CNDE_INT * T1.W, T2.Y, T0.X, PV.X,1288; R600-NEXT: 1079283712(3.321289e+00), 1065353216(1.000000e+00)1289; R600-NEXT: MUL_IEEE T0.X, PS, PV.W,1290; R600-NEXT: ADD T0.Y, KC0[3].Z, -T1.Z,1291; R600-NEXT: RNDNE T2.Z, PV.Z,1292; R600-NEXT: TRUNC T0.W, T3.Y,1293; R600-NEXT: EXP_IEEE * T1.X, PV.Y,1294; R600-NEXT: SETGT T2.X, literal.x, KC0[3].Y,1295; R600-NEXT: FLT_TO_INT T1.Y, PV.W,1296; R600-NEXT: TRUNC T3.Z, PV.Z,1297; R600-NEXT: MUL_IEEE T0.W, PV.Y, literal.y,1298; R600-NEXT: MUL_IEEE * T1.W, PS, literal.z,1299; R600-NEXT: -1036817932(-4.485347e+01), 975668412(6.390323e-04)1300; R600-NEXT: 209715200(1.972152e-31), 0(0.000000e+00)1301; R600-NEXT: MUL_IEEE T3.X, PS, literal.x,1302; R600-NEXT: MUL_IEEE T2.Y, T1.X, literal.y,1303; R600-NEXT: MULADD_IEEE T4.Z, T0.Y, literal.z, PV.W,1304; R600-NEXT: FLT_TO_INT T0.W, PV.Z,1305; R600-NEXT: MIN_INT * T2.W, PV.Y, literal.w,1306; R600-NEXT: 209715200(1.972152e-31), 2130706432(1.701412e+38)1307; R600-NEXT: 1079283712(3.321289e+00), 381(5.338947e-43)1308; R600-NEXT: ADD_INT T4.X, PS, literal.x,1309; R600-NEXT: MAX_INT T0.Y, PV.W, literal.y,1310; R600-NEXT: MULADD_IEEE T1.Z, T1.Z, literal.z, PV.Z,1311; R600-NEXT: ADD T2.W, T0.Z, -T2.Z, BS:VEC_120/SCL_2121312; R600-NEXT: MIN_INT * T3.W, PV.W, literal.w,1313; R600-NEXT: -254(nan), -330(nan)1314; R600-NEXT: 975668412(6.390323e-04), 381(5.338947e-43)1315; R600-NEXT: ADD_INT T5.X, PS, literal.x,1316; R600-NEXT: ADD T3.Y, PV.W, PV.Z,1317; R600-NEXT: ADD_INT T0.Z, PV.Y, literal.y,1318; R600-NEXT: ADD_INT T2.W, T0.W, literal.z,1319; R600-NEXT: SETGT_UINT * T3.W, T0.W, literal.w,1320; R600-NEXT: -254(nan), 204(2.858649e-43)1321; R600-NEXT: 102(1.429324e-43), -229(nan)1322; R600-NEXT: ADD_INT * T6.X, T0.W, literal.x,1323; R600-NEXT: -127(nan), 0(0.000000e+00)1324; R600-NEXT: ALU clause starting at 106:1325; R600-NEXT: SETGT_UINT T0.Y, T0.W, literal.x,1326; R600-NEXT: CNDE_INT T0.Z, T3.W, T0.Z, T2.W, BS:VEC_102/SCL_2211327; R600-NEXT: SETGT_INT T2.W, T0.W, literal.y,1328; R600-NEXT: EXP_IEEE * T1.Z, T3.Y,1329; R600-NEXT: 254(3.559298e-43), -127(nan)1330; R600-NEXT: ADD_INT T7.X, T1.Y, literal.x,1331; R600-NEXT: MUL_IEEE T3.Y, PS, literal.y,1332; R600-NEXT: CNDE_INT T0.Z, PV.W, PV.Z, T0.W,1333; R600-NEXT: CNDE_INT T4.W, PV.Y, T6.X, T5.X,1334; R600-NEXT: SETGT_INT * T0.W, T0.W, literal.z,1335; R600-NEXT: -127(nan), 209715200(1.972152e-31)1336; R600-NEXT: 127(1.779649e-43), 0(0.000000e+00)1337; R600-NEXT: SETGT_UINT T5.X, T1.Y, literal.x,1338; R600-NEXT: CNDE_INT T4.Y, PS, PV.Z, PV.W,1339; R600-NEXT: MAX_INT T0.Z, T1.Y, literal.y,1340; R600-NEXT: MUL_IEEE T4.W, PV.Y, literal.z,1341; R600-NEXT: MUL_IEEE * T5.W, T1.Z, literal.w,1342; R600-NEXT: 254(3.559298e-43), -330(nan)1343; R600-NEXT: 209715200(1.972152e-31), 2130706432(1.701412e+38)1344; R600-NEXT: MUL_IEEE T6.X, PS, literal.x,1345; R600-NEXT: CNDE_INT T3.Y, T3.W, PV.W, T3.Y, BS:VEC_021/SCL_1221346; R600-NEXT: ADD_INT T0.Z, PV.Z, literal.y,1347; R600-NEXT: ADD_INT T3.W, T1.Y, literal.z,1348; R600-NEXT: SETGT_UINT * T4.W, T1.Y, literal.w,1349; R600-NEXT: 2130706432(1.701412e+38), 204(2.858649e-43)1350; R600-NEXT: 102(1.429324e-43), -229(nan)1351; R600-NEXT: CNDE_INT T8.X, PS, PV.Z, PV.W,1352; R600-NEXT: SETGT_INT T5.Y, T1.Y, literal.x,1353; R600-NEXT: CNDE_INT T0.Z, T2.W, PV.Y, T1.Z,1354; R600-NEXT: CNDE_INT T2.W, T0.Y, T5.W, PV.X, BS:VEC_120/SCL_2121355; R600-NEXT: LSHL * T3.W, T4.Y, literal.y,1356; R600-NEXT: -127(nan), 23(3.222986e-44)1357; R600-NEXT: ADD_INT T6.X, PS, literal.x,1358; R600-NEXT: CNDE_INT T0.Y, T0.W, PV.Z, PV.W,1359; R600-NEXT: CNDE_INT T0.Z, PV.Y, PV.X, T1.Y,1360; R600-NEXT: CNDE_INT T0.W, T5.X, T7.X, T4.X,1361; R600-NEXT: SETGT_INT * T2.W, T1.Y, literal.y,1362; R600-NEXT: 1065353216(1.000000e+00), 127(1.779649e-43)1363; R600-NEXT: CNDE_INT T4.X, PS, PV.Z, PV.W,1364; R600-NEXT: MUL_IEEE T0.Y, PV.Y, PV.X,1365; R600-NEXT: SETGT T0.Z, literal.x, KC0[3].Z,1366; R600-NEXT: MUL_IEEE T0.W, T2.Y, literal.y,1367; R600-NEXT: CNDE_INT * T1.W, T4.W, T3.X, T1.W,1368; R600-NEXT: -1036817932(-4.485347e+01), 2130706432(1.701412e+38)1369; R600-NEXT: CNDE_INT T1.X, T5.Y, PS, T1.X,1370; R600-NEXT: CNDE_INT T1.Y, T5.X, T2.Y, PV.W,1371; R600-NEXT: CNDE T0.Z, PV.Z, PV.Y, 0.0,1372; R600-NEXT: SETGT T0.W, KC0[3].Z, literal.x,1373; R600-NEXT: LSHL * T1.W, PV.X, literal.y,1374; R600-NEXT: 1109008539(3.853184e+01), 23(3.222986e-44)1375; R600-NEXT: ADD_INT T3.X, PS, literal.x,1376; R600-NEXT: CNDE T0.Y, PV.W, PV.Z, literal.y,1377; R600-NEXT: CNDE_INT T0.Z, T2.W, PV.X, PV.Y,1378; R600-NEXT: CNDE T0.W, T2.X, T0.X, 0.0,1379; R600-NEXT: SETGT * T1.W, KC0[3].Y, literal.z,1380; R600-NEXT: 1065353216(1.000000e+00), 2139095040(INF)1381; R600-NEXT: 1109008539(3.853184e+01), 0(0.000000e+00)1382; R600-NEXT: CNDE T0.X, PS, PV.W, literal.x,1383; R600-NEXT: MUL_IEEE T0.W, PV.Z, PV.X,1384; R600-NEXT: SETGT * T1.W, literal.y, KC0[3].W,1385; R600-NEXT: 2139095040(INF), -1036817932(-4.485347e+01)1386; R600-NEXT: LSHR T1.X, KC0[2].Y, literal.x,1387; R600-NEXT: CNDE T0.W, PS, PV.W, 0.0,1388; R600-NEXT: SETGT * T1.W, KC0[3].W, literal.y,1389; R600-NEXT: 2(2.802597e-45), 1109008539(3.853184e+01)1390; R600-NEXT: CNDE T2.X, PS, PV.W, literal.x,1391; R600-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,1392; R600-NEXT: 2139095040(INF), 8(1.121039e-44)1393; R600-NEXT: LSHR * T3.X, PV.W, literal.x,1394; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)1395;1396; CM-LABEL: s_exp10_v3f32:1397; CM: ; %bb.0:1398; CM-NEXT: ALU 101, @6, KC0[CB0:0-32], KC1[]1399; CM-NEXT: ALU 77, @108, KC0[CB0:0-32], KC1[]1400; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0, T1.X1401; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T2.X, T3.X1402; CM-NEXT: CF_END1403; CM-NEXT: PAD1404; CM-NEXT: ALU clause starting at 6:1405; CM-NEXT: AND_INT * T0.W, KC0[3].Y, literal.x,1406; CM-NEXT: -4096(nan), 0(0.000000e+00)1407; CM-NEXT: ADD * T1.W, KC0[3].Y, -PV.W,1408; CM-NEXT: MUL_IEEE T0.Z, PV.W, literal.x,1409; CM-NEXT: MUL_IEEE * T2.W, T0.W, literal.y,1410; CM-NEXT: 975668412(6.390323e-04), 1079283712(3.321289e+00)1411; CM-NEXT: RNDNE T1.Z, PV.W,1412; CM-NEXT: MULADD_IEEE * T1.W, T1.W, literal.x, PV.Z,1413; CM-NEXT: 1079283712(3.321289e+00), 0(0.000000e+00)1414; CM-NEXT: MULADD_IEEE T0.Z, T0.W, literal.x, PV.W,1415; CM-NEXT: ADD * T0.W, T2.W, -PV.Z, BS:VEC_120/SCL_2121416; CM-NEXT: 975668412(6.390323e-04), 0(0.000000e+00)1417; CM-NEXT: TRUNC T1.Z, T1.Z,1418; CM-NEXT: ADD * T0.W, PV.W, PV.Z,1419; CM-NEXT: EXP_IEEE T0.X, T0.W,1420; CM-NEXT: EXP_IEEE T0.Y (MASKED), T0.W,1421; CM-NEXT: EXP_IEEE T0.Z (MASKED), T0.W,1422; CM-NEXT: EXP_IEEE * T0.W (MASKED), T0.W,1423; CM-NEXT: FLT_TO_INT T0.Z, T1.Z,1424; CM-NEXT: MUL_IEEE * T0.W, PV.X, literal.x,1425; CM-NEXT: 209715200(1.972152e-31), 0(0.000000e+00)1426; CM-NEXT: MUL_IEEE T0.Y, PV.W, literal.x,1427; CM-NEXT: MAX_INT T1.Z, PV.Z, literal.y,1428; CM-NEXT: MIN_INT * T1.W, PV.Z, literal.z,1429; CM-NEXT: 209715200(1.972152e-31), -330(nan)1430; CM-NEXT: 381(5.338947e-43), 0(0.000000e+00)1431; CM-NEXT: ADD_INT T1.X, PV.W, literal.x,1432; CM-NEXT: ADD_INT T1.Y, PV.Z, literal.y,1433; CM-NEXT: ADD_INT T1.Z, T0.Z, literal.z,1434; CM-NEXT: SETGT_UINT * T1.W, T0.Z, literal.w,1435; CM-NEXT: -254(nan), 204(2.858649e-43)1436; CM-NEXT: 102(1.429324e-43), -229(nan)1437; CM-NEXT: ADD_INT T2.X, T0.Z, literal.x,1438; CM-NEXT: SETGT_UINT T2.Y, T0.Z, literal.y,1439; CM-NEXT: CNDE_INT T1.Z, PV.W, PV.Y, PV.Z,1440; CM-NEXT: SETGT_INT * T2.W, T0.Z, literal.x,1441; CM-NEXT: -127(nan), 254(3.559298e-43)1442; CM-NEXT: MUL_IEEE T3.X, T0.X, literal.x,1443; CM-NEXT: CNDE_INT T1.Y, PV.W, PV.Z, T0.Z,1444; CM-NEXT: CNDE_INT T1.Z, PV.Y, PV.X, T1.X,1445; CM-NEXT: SETGT_INT * T3.W, T0.Z, literal.y,1446; CM-NEXT: 2130706432(1.701412e+38), 127(1.779649e-43)1447; CM-NEXT: CNDE_INT T1.Y, PV.W, PV.Y, PV.Z,1448; CM-NEXT: MUL_IEEE T0.Z, PV.X, literal.x,1449; CM-NEXT: CNDE_INT * T0.W, T1.W, T0.Y, T0.W,1450; CM-NEXT: 2130706432(1.701412e+38), 0(0.000000e+00)1451; CM-NEXT: CNDE_INT T0.X, T2.W, PV.W, T0.X,1452; CM-NEXT: CNDE_INT T0.Y, T2.Y, T3.X, PV.Z,1453; CM-NEXT: LSHL T0.Z, PV.Y, literal.x,1454; CM-NEXT: AND_INT * T0.W, KC0[3].Z, literal.y,1455; CM-NEXT: 23(3.222986e-44), -4096(nan)1456; CM-NEXT: ADD T1.Y, KC0[3].Z, -PV.W,1457; CM-NEXT: ADD_INT T0.Z, PV.Z, literal.x,1458; CM-NEXT: CNDE_INT * T1.W, T3.W, PV.X, PV.Y,1459; CM-NEXT: 1065353216(1.000000e+00), 0(0.000000e+00)1460; CM-NEXT: MUL_IEEE T0.X, PV.W, PV.Z,1461; CM-NEXT: MUL_IEEE T0.Y, PV.Y, literal.x,1462; CM-NEXT: MUL_IEEE T0.Z, T0.W, literal.y,1463; CM-NEXT: AND_INT * T1.W, KC0[3].W, literal.z,1464; CM-NEXT: 975668412(6.390323e-04), 1079283712(3.321289e+00)1465; CM-NEXT: -4096(nan), 0(0.000000e+00)1466; CM-NEXT: SETGT T1.X, literal.x, KC0[3].Y,1467; CM-NEXT: ADD T2.Y, KC0[3].W, -PV.W,1468; CM-NEXT: RNDNE T1.Z, PV.Z,1469; CM-NEXT: MULADD_IEEE * T2.W, T1.Y, literal.y, PV.Y,1470; CM-NEXT: -1036817932(-4.485347e+01), 1079283712(3.321289e+00)1471; CM-NEXT: MULADD_IEEE T2.X, T0.W, literal.x, PV.W,1472; CM-NEXT: ADD T0.Y, T0.Z, -PV.Z,1473; CM-NEXT: MUL_IEEE T0.Z, PV.Y, literal.x,1474; CM-NEXT: MUL_IEEE * T0.W, T1.W, literal.y, BS:VEC_120/SCL_2121475; CM-NEXT: 975668412(6.390323e-04), 1079283712(3.321289e+00)1476; CM-NEXT: TRUNC T3.X, T1.Z,1477; CM-NEXT: RNDNE T1.Y, PV.W,1478; CM-NEXT: MULADD_IEEE T0.Z, T2.Y, literal.x, PV.Z,1479; CM-NEXT: ADD * T2.W, PV.Y, PV.X,1480; CM-NEXT: 1079283712(3.321289e+00), 0(0.000000e+00)1481; CM-NEXT: EXP_IEEE T0.X (MASKED), T2.W,1482; CM-NEXT: EXP_IEEE T0.Y, T2.W,1483; CM-NEXT: EXP_IEEE T0.Z (MASKED), T2.W,1484; CM-NEXT: EXP_IEEE * T0.W (MASKED), T2.W,1485; CM-NEXT: MULADD_IEEE T2.X, T1.W, literal.x, T0.Z,1486; CM-NEXT: ADD T2.Y, T0.W, -T1.Y, BS:VEC_120/SCL_2121487; CM-NEXT: FLT_TO_INT T0.Z, T3.X,1488; CM-NEXT: MUL_IEEE * T0.W, PV.Y, literal.y,1489; CM-NEXT: 975668412(6.390323e-04), 209715200(1.972152e-31)1490; CM-NEXT: MUL_IEEE T3.X, PV.W, literal.x,1491; CM-NEXT: SETGT_UINT T3.Y, PV.Z, literal.y,1492; CM-NEXT: TRUNC T1.Z, T1.Y,1493; CM-NEXT: ADD * T1.W, PV.Y, PV.X,1494; CM-NEXT: 209715200(1.972152e-31), -229(nan)1495; CM-NEXT: EXP_IEEE T1.X (MASKED), T1.W,1496; CM-NEXT: EXP_IEEE T1.Y, T1.W,1497; CM-NEXT: EXP_IEEE T1.Z (MASKED), T1.W,1498; CM-NEXT: EXP_IEEE * T1.W (MASKED), T1.W,1499; CM-NEXT: FLT_TO_INT T2.X, T1.Z,1500; CM-NEXT: MUL_IEEE T2.Y, PV.Y, literal.x,1501; CM-NEXT: CNDE_INT T1.Z, T3.Y, T3.X, T0.W,1502; CM-NEXT: SETGT_INT * T0.W, T0.Z, literal.y, BS:VEC_120/SCL_2121503; CM-NEXT: 209715200(1.972152e-31), -127(nan)1504; CM-NEXT: CNDE_INT T3.X, PV.W, PV.Z, T0.Y,1505; CM-NEXT: MUL_IEEE * T4.Y, PV.Y, literal.x,1506; CM-NEXT: 209715200(1.972152e-31), 0(0.000000e+00)1507; CM-NEXT: ALU clause starting at 108:1508; CM-NEXT: SETGT_UINT T1.Z, T2.X, literal.x,1509; CM-NEXT: MAX_INT * T1.W, T0.Z, literal.y,1510; CM-NEXT: -229(nan), -330(nan)1511; CM-NEXT: ADD_INT T4.X, PV.W, literal.x,1512; CM-NEXT: ADD_INT T5.Y, T0.Z, literal.y,1513; CM-NEXT: CNDE_INT T2.Z, PV.Z, T4.Y, T2.Y,1514; CM-NEXT: SETGT_INT * T1.W, T2.X, literal.z,1515; CM-NEXT: 204(2.858649e-43), 102(1.429324e-43)1516; CM-NEXT: -127(nan), 0(0.000000e+00)1517; CM-NEXT: CNDE_INT T5.X, PV.W, PV.Z, T1.Y,1518; CM-NEXT: MUL_IEEE T0.Y, T0.Y, literal.x,1519; CM-NEXT: MAX_INT T2.Z, T2.X, literal.y,1520; CM-NEXT: CNDE_INT * T2.W, T3.Y, PV.X, PV.Y, BS:VEC_120/SCL_2121521; CM-NEXT: 2130706432(1.701412e+38), -330(nan)1522; CM-NEXT: CNDE_INT T4.X, T0.W, PV.W, T0.Z,1523; CM-NEXT: ADD_INT T2.Y, PV.Z, literal.x,1524; CM-NEXT: ADD_INT T2.Z, T2.X, literal.y,1525; CM-NEXT: MIN_INT * T0.W, T2.X, literal.z,1526; CM-NEXT: 204(2.858649e-43), 102(1.429324e-43)1527; CM-NEXT: 381(5.338947e-43), 0(0.000000e+00)1528; CM-NEXT: ADD_INT T6.X, PV.W, literal.x,1529; CM-NEXT: ADD_INT T3.Y, T2.X, literal.y,1530; CM-NEXT: SETGT_UINT T3.Z, T2.X, literal.z,1531; CM-NEXT: CNDE_INT * T0.W, T1.Z, PV.Y, PV.Z,1532; CM-NEXT: -254(nan), -127(nan)1533; CM-NEXT: 254(3.559298e-43), 0(0.000000e+00)1534; CM-NEXT: MUL_IEEE T7.X, T1.Y, literal.x,1535; CM-NEXT: CNDE_INT T1.Y, T1.W, PV.W, T2.X,1536; CM-NEXT: CNDE_INT T1.Z, PV.Z, PV.Y, PV.X,1537; CM-NEXT: MIN_INT * T0.W, T0.Z, literal.y,1538; CM-NEXT: 2130706432(1.701412e+38), 381(5.338947e-43)1539; CM-NEXT: SETGT_INT T2.X, T2.X, literal.x,1540; CM-NEXT: ADD_INT T2.Y, PV.W, literal.y,1541; CM-NEXT: ADD_INT T2.Z, T0.Z, literal.z,1542; CM-NEXT: SETGT_UINT * T0.W, T0.Z, literal.w,1543; CM-NEXT: 127(1.779649e-43), -254(nan)1544; CM-NEXT: -127(nan), 254(3.559298e-43)1545; CM-NEXT: CNDE_INT T6.X, PV.W, PV.Z, PV.Y,1546; CM-NEXT: SETGT_INT T2.Y, T0.Z, literal.x,1547; CM-NEXT: CNDE_INT T0.Z, PV.X, T1.Y, T1.Z,1548; CM-NEXT: MUL_IEEE * T1.W, T7.X, literal.y,1549; CM-NEXT: 127(1.779649e-43), 2130706432(1.701412e+38)1550; CM-NEXT: CNDE_INT T7.X, T3.Z, T7.X, PV.W,1551; CM-NEXT: LSHL T1.Y, PV.Z, literal.x,1552; CM-NEXT: CNDE_INT T0.Z, PV.Y, T4.X, PV.X, BS:VEC_021/SCL_1221553; CM-NEXT: MUL_IEEE * T1.W, T0.Y, literal.y,1554; CM-NEXT: 23(3.222986e-44), 2130706432(1.701412e+38)1555; CM-NEXT: CNDE_INT T4.X, T0.W, T0.Y, PV.W,1556; CM-NEXT: LSHL T0.Y, PV.Z, literal.x,1557; CM-NEXT: ADD_INT T0.Z, PV.Y, literal.y,1558; CM-NEXT: CNDE_INT * T0.W, T2.X, T5.X, PV.X,1559; CM-NEXT: 23(3.222986e-44), 1065353216(1.000000e+00)1560; CM-NEXT: MUL_IEEE T2.X, PV.W, PV.Z,1561; CM-NEXT: SETGT T1.Y, literal.x, KC0[3].W,1562; CM-NEXT: ADD_INT T0.Z, PV.Y, literal.y,1563; CM-NEXT: CNDE_INT * T0.W, T2.Y, T3.X, PV.X,1564; CM-NEXT: -1036817932(-4.485347e+01), 1065353216(1.000000e+00)1565; CM-NEXT: MUL_IEEE T3.X, PV.W, PV.Z,1566; CM-NEXT: SETGT T0.Y, literal.x, KC0[3].Z,1567; CM-NEXT: CNDE T0.Z, PV.Y, PV.X, 0.0,1568; CM-NEXT: SETGT * T0.W, KC0[3].W, literal.y,1569; CM-NEXT: -1036817932(-4.485347e+01), 1109008539(3.853184e+01)1570; CM-NEXT: CNDE T2.X, PV.W, PV.Z, literal.x,1571; CM-NEXT: CNDE T0.Y, PV.Y, PV.X, 0.0,1572; CM-NEXT: SETGT T0.Z, KC0[3].Z, literal.y,1573; CM-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.z,1574; CM-NEXT: 2139095040(INF), 1109008539(3.853184e+01)1575; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00)1576; CM-NEXT: LSHR T3.X, PV.W, literal.x,1577; CM-NEXT: CNDE T0.Y, PV.Z, PV.Y, literal.y,1578; CM-NEXT: CNDE T0.Z, T1.X, T0.X, 0.0,1579; CM-NEXT: SETGT * T0.W, KC0[3].Y, literal.z,1580; CM-NEXT: 2(2.802597e-45), 2139095040(INF)1581; CM-NEXT: 1109008539(3.853184e+01), 0(0.000000e+00)1582; CM-NEXT: CNDE * T0.X, PV.W, PV.Z, literal.x,1583; CM-NEXT: 2139095040(INF), 0(0.000000e+00)1584; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,1585; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)1586 %result = call <3 x float> @llvm.exp10.v3f32(<3 x float> %in)1587 store <3 x float> %result, ptr addrspace(1) %out1588 ret void1589}1590 1591; FIXME: We should be able to merge these packets together on Cayman so we1592; have a maximum of 4 instructions.1593define amdgpu_kernel void @s_exp10_v4f32(ptr addrspace(1) %out, <4 x float> %in) {1594; VI-SDAG-LABEL: s_exp10_v4f32:1595; VI-SDAG: ; %bb.0:1596; VI-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x341597; VI-SDAG-NEXT: v_mov_b32_e32 v0, 0x405490001598; VI-SDAG-NEXT: v_mov_b32_e32 v6, 0x421a209b1599; VI-SDAG-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x241600; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)1601; VI-SDAG-NEXT: s_and_b32 s6, s3, 0xfffff0001602; VI-SDAG-NEXT: v_mov_b32_e32 v2, s61603; VI-SDAG-NEXT: v_sub_f32_e32 v2, s3, v21604; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x3a2784bc, v21605; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x40549000, v21606; VI-SDAG-NEXT: v_mul_f32_e32 v1, s6, v01607; VI-SDAG-NEXT: v_add_f32_e32 v2, v2, v41608; VI-SDAG-NEXT: v_mov_b32_e32 v4, 0x3a2784bc1609; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v11610; VI-SDAG-NEXT: v_mul_f32_e32 v5, s6, v41611; VI-SDAG-NEXT: v_sub_f32_e32 v1, v1, v31612; VI-SDAG-NEXT: v_add_f32_e32 v2, v5, v21613; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v21614; VI-SDAG-NEXT: v_exp_f32_e32 v1, v11615; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v31616; VI-SDAG-NEXT: s_and_b32 s6, s2, 0xfffff0001617; VI-SDAG-NEXT: v_mov_b32_e32 v7, s61618; VI-SDAG-NEXT: v_sub_f32_e32 v7, s2, v71619; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v21620; VI-SDAG-NEXT: v_mul_f32_e32 v2, s6, v01621; VI-SDAG-NEXT: v_mul_f32_e32 v8, 0x3a2784bc, v71622; VI-SDAG-NEXT: v_mul_f32_e32 v7, 0x40549000, v71623; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v21624; VI-SDAG-NEXT: v_add_f32_e32 v7, v7, v81625; VI-SDAG-NEXT: v_mul_f32_e32 v8, s6, v41626; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v31627; VI-SDAG-NEXT: v_add_f32_e32 v7, v8, v71628; VI-SDAG-NEXT: v_mov_b32_e32 v5, 0xc23369f41629; VI-SDAG-NEXT: v_add_f32_e32 v2, v2, v71630; VI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s3, v51631; VI-SDAG-NEXT: v_exp_f32_e32 v2, v21632; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v7, v31633; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc1634; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s3, v61635; VI-SDAG-NEXT: s_and_b32 s3, s1, 0xfffff0001636; VI-SDAG-NEXT: v_mov_b32_e32 v9, s31637; VI-SDAG-NEXT: v_mov_b32_e32 v8, 0x7f8000001638; VI-SDAG-NEXT: v_sub_f32_e32 v9, s1, v91639; VI-SDAG-NEXT: v_cndmask_b32_e32 v3, v8, v1, vcc1640; VI-SDAG-NEXT: v_ldexp_f32 v1, v2, v71641; VI-SDAG-NEXT: v_mul_f32_e32 v2, s3, v01642; VI-SDAG-NEXT: v_mul_f32_e32 v10, 0x3a2784bc, v91643; VI-SDAG-NEXT: v_mul_f32_e32 v9, 0x40549000, v91644; VI-SDAG-NEXT: v_rndne_f32_e32 v7, v21645; VI-SDAG-NEXT: v_add_f32_e32 v9, v9, v101646; VI-SDAG-NEXT: v_mul_f32_e32 v10, s3, v41647; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v71648; VI-SDAG-NEXT: v_add_f32_e32 v9, v10, v91649; VI-SDAG-NEXT: v_add_f32_e32 v2, v2, v91650; VI-SDAG-NEXT: v_exp_f32_e32 v9, v21651; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v7, v71652; VI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s2, v51653; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc1654; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s2, v61655; VI-SDAG-NEXT: s_and_b32 s2, s0, 0xfffff0001656; VI-SDAG-NEXT: v_cndmask_b32_e32 v2, v8, v1, vcc1657; VI-SDAG-NEXT: v_ldexp_f32 v1, v9, v71658; VI-SDAG-NEXT: v_mov_b32_e32 v9, s21659; VI-SDAG-NEXT: v_sub_f32_e32 v9, s0, v91660; VI-SDAG-NEXT: v_mul_f32_e32 v0, s2, v01661; VI-SDAG-NEXT: v_mul_f32_e32 v10, 0x3a2784bc, v91662; VI-SDAG-NEXT: v_mul_f32_e32 v9, 0x40549000, v91663; VI-SDAG-NEXT: v_rndne_f32_e32 v7, v01664; VI-SDAG-NEXT: v_add_f32_e32 v9, v9, v101665; VI-SDAG-NEXT: v_mul_f32_e32 v4, s2, v41666; VI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v71667; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v91668; VI-SDAG-NEXT: v_add_f32_e32 v0, v0, v41669; VI-SDAG-NEXT: v_exp_f32_e32 v0, v01670; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v4, v71671; VI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s1, v51672; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc1673; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s1, v61674; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc1675; VI-SDAG-NEXT: v_ldexp_f32 v0, v0, v41676; VI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s0, v51677; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc1678; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s0, v61679; VI-SDAG-NEXT: v_mov_b32_e32 v4, s41680; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc1681; VI-SDAG-NEXT: v_mov_b32_e32 v5, s51682; VI-SDAG-NEXT: flat_store_dwordx4 v[4:5], v[0:3]1683; VI-SDAG-NEXT: s_endpgm1684;1685; VI-GISEL-LABEL: s_exp10_v4f32:1686; VI-GISEL: ; %bb.0:1687; VI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x341688; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x405490001689; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x3a2784bc1690; VI-GISEL-NEXT: v_mov_b32_e32 v5, 0x421a209b1691; VI-GISEL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x241692; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)1693; VI-GISEL-NEXT: s_and_b32 s6, s0, 0xfffff0001694; VI-GISEL-NEXT: v_mov_b32_e32 v0, s61695; VI-GISEL-NEXT: v_sub_f32_e32 v0, s0, v01696; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3a2784bc, v01697; VI-GISEL-NEXT: v_mul_f32_e32 v0, 0x40549000, v01698; VI-GISEL-NEXT: v_mul_f32_e32 v1, s6, v21699; VI-GISEL-NEXT: v_add_f32_e32 v0, v0, v41700; VI-GISEL-NEXT: v_mul_f32_e32 v4, s6, v31701; VI-GISEL-NEXT: v_add_f32_e32 v0, v4, v01702; VI-GISEL-NEXT: v_rndne_f32_e32 v4, v11703; VI-GISEL-NEXT: v_sub_f32_e32 v1, v1, v41704; VI-GISEL-NEXT: v_add_f32_e32 v0, v1, v01705; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v1, v41706; VI-GISEL-NEXT: v_exp_f32_e32 v0, v01707; VI-GISEL-NEXT: s_and_b32 s6, s1, 0xfffff0001708; VI-GISEL-NEXT: v_mul_f32_e32 v6, s6, v21709; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0xc23369f41710; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v11711; VI-GISEL-NEXT: v_mov_b32_e32 v1, s61712; VI-GISEL-NEXT: v_sub_f32_e32 v1, s1, v11713; VI-GISEL-NEXT: v_mul_f32_e32 v7, 0x3a2784bc, v11714; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x40549000, v11715; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v71716; VI-GISEL-NEXT: v_mul_f32_e32 v7, s6, v31717; VI-GISEL-NEXT: v_add_f32_e32 v1, v7, v11718; VI-GISEL-NEXT: v_rndne_f32_e32 v7, v61719; VI-GISEL-NEXT: v_sub_f32_e32 v6, v6, v71720; VI-GISEL-NEXT: v_add_f32_e32 v1, v6, v11721; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v6, v71722; VI-GISEL-NEXT: v_exp_f32_e32 v1, v11723; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s0, v41724; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc1725; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s0, v51726; VI-GISEL-NEXT: s_and_b32 s0, s2, 0xfffff0001727; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v61728; VI-GISEL-NEXT: v_mov_b32_e32 v6, s01729; VI-GISEL-NEXT: v_sub_f32_e32 v6, s2, v61730; VI-GISEL-NEXT: v_mul_f32_e32 v9, 0x3a2784bc, v61731; VI-GISEL-NEXT: v_mul_f32_e32 v6, 0x40549000, v61732; VI-GISEL-NEXT: v_mul_f32_e32 v8, s0, v21733; VI-GISEL-NEXT: v_add_f32_e32 v6, v6, v91734; VI-GISEL-NEXT: v_mul_f32_e32 v9, s0, v31735; VI-GISEL-NEXT: v_add_f32_e32 v6, v9, v61736; VI-GISEL-NEXT: v_rndne_f32_e32 v9, v81737; VI-GISEL-NEXT: v_sub_f32_e32 v8, v8, v91738; VI-GISEL-NEXT: v_add_f32_e32 v6, v8, v61739; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v8, v91740; VI-GISEL-NEXT: v_exp_f32_e32 v6, v61741; VI-GISEL-NEXT: s_and_b32 s0, s3, 0xfffff0001742; VI-GISEL-NEXT: v_mul_f32_e32 v2, s0, v21743; VI-GISEL-NEXT: v_mul_f32_e32 v3, s0, v31744; VI-GISEL-NEXT: v_ldexp_f32 v6, v6, v81745; VI-GISEL-NEXT: v_mov_b32_e32 v8, s01746; VI-GISEL-NEXT: v_sub_f32_e32 v8, s3, v81747; VI-GISEL-NEXT: v_mul_f32_e32 v9, 0x3a2784bc, v81748; VI-GISEL-NEXT: v_mul_f32_e32 v8, 0x40549000, v81749; VI-GISEL-NEXT: v_add_f32_e32 v8, v8, v91750; VI-GISEL-NEXT: v_add_f32_e32 v3, v3, v81751; VI-GISEL-NEXT: v_rndne_f32_e32 v8, v21752; VI-GISEL-NEXT: v_sub_f32_e32 v2, v2, v81753; VI-GISEL-NEXT: v_mov_b32_e32 v7, 0x7f8000001754; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v31755; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc1756; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s1, v41757; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v3, v81758; VI-GISEL-NEXT: v_exp_f32_e32 v8, v21759; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc1760; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s1, v51761; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc1762; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v41763; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, v6, 0, vcc1764; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s2, v51765; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc1766; VI-GISEL-NEXT: v_ldexp_f32 v3, v8, v31767; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s3, v41768; VI-GISEL-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc1769; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s3, v51770; VI-GISEL-NEXT: v_mov_b32_e32 v4, s41771; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc1772; VI-GISEL-NEXT: v_mov_b32_e32 v5, s51773; VI-GISEL-NEXT: flat_store_dwordx4 v[4:5], v[0:3]1774; VI-GISEL-NEXT: s_endpgm1775;1776; GFX900-SDAG-LABEL: s_exp10_v4f32:1777; GFX900-SDAG: ; %bb.0:1778; GFX900-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x341779; GFX900-SDAG-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x241780; GFX900-SDAG-NEXT: v_mov_b32_e32 v0, 0x40549a781781; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x33979a371782; GFX900-SDAG-NEXT: v_mov_b32_e32 v5, 0xc23369f41783; GFX900-SDAG-NEXT: s_waitcnt lgkmcnt(0)1784; GFX900-SDAG-NEXT: v_mul_f32_e32 v2, s3, v01785; GFX900-SDAG-NEXT: v_rndne_f32_e32 v3, v21786; GFX900-SDAG-NEXT: v_fma_f32 v4, s3, v0, -v21787; GFX900-SDAG-NEXT: v_sub_f32_e32 v2, v2, v31788; GFX900-SDAG-NEXT: v_fma_f32 v4, s3, v1, v41789; GFX900-SDAG-NEXT: v_add_f32_e32 v2, v2, v41790; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v3, v31791; GFX900-SDAG-NEXT: v_exp_f32_e32 v2, v21792; GFX900-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s3, v51793; GFX900-SDAG-NEXT: v_mov_b32_e32 v6, 0x421a209b1794; GFX900-SDAG-NEXT: v_mov_b32_e32 v9, 0x7f8000001795; GFX900-SDAG-NEXT: v_ldexp_f32 v2, v2, v31796; GFX900-SDAG-NEXT: v_mul_f32_e32 v3, s2, v01797; GFX900-SDAG-NEXT: v_rndne_f32_e32 v7, v31798; GFX900-SDAG-NEXT: v_sub_f32_e32 v8, v3, v71799; GFX900-SDAG-NEXT: v_fma_f32 v3, s2, v0, -v31800; GFX900-SDAG-NEXT: v_fma_f32 v3, s2, v1, v31801; GFX900-SDAG-NEXT: v_add_f32_e32 v3, v8, v31802; GFX900-SDAG-NEXT: v_exp_f32_e32 v8, v31803; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v7, v71804; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc1805; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s3, v61806; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v3, v9, v2, vcc1807; GFX900-SDAG-NEXT: v_ldexp_f32 v2, v8, v71808; GFX900-SDAG-NEXT: v_mul_f32_e32 v7, s1, v01809; GFX900-SDAG-NEXT: v_rndne_f32_e32 v8, v71810; GFX900-SDAG-NEXT: v_sub_f32_e32 v10, v7, v81811; GFX900-SDAG-NEXT: v_fma_f32 v7, s1, v0, -v71812; GFX900-SDAG-NEXT: v_fma_f32 v7, s1, v1, v71813; GFX900-SDAG-NEXT: v_add_f32_e32 v7, v10, v71814; GFX900-SDAG-NEXT: v_exp_f32_e32 v7, v71815; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v8, v81816; GFX900-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s2, v51817; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc1818; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s2, v61819; GFX900-SDAG-NEXT: v_ldexp_f32 v7, v7, v81820; GFX900-SDAG-NEXT: v_mul_f32_e32 v8, s0, v01821; GFX900-SDAG-NEXT: v_rndne_f32_e32 v10, v81822; GFX900-SDAG-NEXT: v_fma_f32 v0, s0, v0, -v81823; GFX900-SDAG-NEXT: v_sub_f32_e32 v11, v8, v101824; GFX900-SDAG-NEXT: v_fma_f32 v0, s0, v1, v01825; GFX900-SDAG-NEXT: v_add_f32_e32 v0, v11, v01826; GFX900-SDAG-NEXT: v_exp_f32_e32 v0, v01827; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v8, v101828; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v2, v9, v2, vcc1829; GFX900-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s1, v51830; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v7, vcc1831; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s1, v61832; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc1833; GFX900-SDAG-NEXT: v_ldexp_f32 v0, v0, v81834; GFX900-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s0, v51835; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc1836; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s0, v61837; GFX900-SDAG-NEXT: v_mov_b32_e32 v4, 01838; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v9, v0, vcc1839; GFX900-SDAG-NEXT: global_store_dwordx4 v4, v[0:3], s[6:7]1840; GFX900-SDAG-NEXT: s_endpgm1841;1842; GFX900-GISEL-LABEL: s_exp10_v4f32:1843; GFX900-GISEL: ; %bb.0:1844; GFX900-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x341845; GFX900-GISEL-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x241846; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x40549a781847; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x33979a371848; GFX900-GISEL-NEXT: v_mov_b32_e32 v5, 0x421a209b1849; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0)1850; GFX900-GISEL-NEXT: v_mul_f32_e32 v0, s0, v21851; GFX900-GISEL-NEXT: v_fma_f32 v1, s0, v2, -v01852; GFX900-GISEL-NEXT: v_rndne_f32_e32 v4, v01853; GFX900-GISEL-NEXT: v_fma_f32 v1, s0, v3, v11854; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v41855; GFX900-GISEL-NEXT: v_add_f32_e32 v0, v0, v11856; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v1, v41857; GFX900-GISEL-NEXT: v_exp_f32_e32 v0, v01858; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0xc23369f41859; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s0, v41860; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v11861; GFX900-GISEL-NEXT: v_mul_f32_e32 v1, s1, v21862; GFX900-GISEL-NEXT: v_fma_f32 v6, s1, v2, -v11863; GFX900-GISEL-NEXT: v_rndne_f32_e32 v7, v11864; GFX900-GISEL-NEXT: v_fma_f32 v6, s1, v3, v61865; GFX900-GISEL-NEXT: v_sub_f32_e32 v1, v1, v71866; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v1, v61867; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v6, v71868; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, v11869; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc1870; GFX900-GISEL-NEXT: v_mov_b32_e32 v7, 0x7f8000001871; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s0, v51872; GFX900-GISEL-NEXT: v_ldexp_f32 v1, v1, v61873; GFX900-GISEL-NEXT: v_mul_f32_e32 v6, s2, v21874; GFX900-GISEL-NEXT: v_fma_f32 v8, s2, v2, -v61875; GFX900-GISEL-NEXT: v_rndne_f32_e32 v9, v61876; GFX900-GISEL-NEXT: v_fma_f32 v8, s2, v3, v81877; GFX900-GISEL-NEXT: v_sub_f32_e32 v6, v6, v91878; GFX900-GISEL-NEXT: v_add_f32_e32 v6, v6, v81879; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v8, v91880; GFX900-GISEL-NEXT: v_exp_f32_e32 v6, v61881; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc1882; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s1, v41883; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc1884; GFX900-GISEL-NEXT: v_ldexp_f32 v6, v6, v81885; GFX900-GISEL-NEXT: v_mul_f32_e32 v8, s3, v21886; GFX900-GISEL-NEXT: v_fma_f32 v2, s3, v2, -v81887; GFX900-GISEL-NEXT: v_fma_f32 v2, s3, v3, v21888; GFX900-GISEL-NEXT: v_rndne_f32_e32 v3, v81889; GFX900-GISEL-NEXT: v_sub_f32_e32 v8, v8, v31890; GFX900-GISEL-NEXT: v_add_f32_e32 v2, v8, v21891; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v3, v31892; GFX900-GISEL-NEXT: v_exp_f32_e32 v8, v21893; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s1, v51894; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc1895; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v41896; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v2, v6, 0, vcc1897; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s2, v51898; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc1899; GFX900-GISEL-NEXT: v_ldexp_f32 v3, v8, v31900; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s3, v41901; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc1902; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s3, v51903; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc1904; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 01905; GFX900-GISEL-NEXT: global_store_dwordx4 v4, v[0:3], s[6:7]1906; GFX900-GISEL-NEXT: s_endpgm1907;1908; SI-SDAG-LABEL: s_exp10_v4f32:1909; SI-SDAG: ; %bb.0:1910; SI-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xd1911; SI-SDAG-NEXT: v_mov_b32_e32 v0, 0x40549a781912; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x33979a371913; SI-SDAG-NEXT: v_mov_b32_e32 v5, 0x421a209b1914; SI-SDAG-NEXT: v_mov_b32_e32 v8, 0x7f8000001915; SI-SDAG-NEXT: s_waitcnt lgkmcnt(0)1916; SI-SDAG-NEXT: v_mul_f32_e32 v2, s3, v01917; SI-SDAG-NEXT: v_rndne_f32_e32 v3, v21918; SI-SDAG-NEXT: v_fma_f32 v4, s3, v0, -v21919; SI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v31920; SI-SDAG-NEXT: v_fma_f32 v4, s3, v1, v41921; SI-SDAG-NEXT: v_add_f32_e32 v2, v2, v41922; SI-SDAG-NEXT: v_exp_f32_e32 v2, v21923; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v3, v31924; SI-SDAG-NEXT: v_mov_b32_e32 v4, 0xc23369f41925; SI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s3, v41926; SI-SDAG-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x91927; SI-SDAG-NEXT: v_ldexp_f32_e32 v2, v2, v31928; SI-SDAG-NEXT: v_mul_f32_e32 v3, s2, v01929; SI-SDAG-NEXT: v_rndne_f32_e32 v6, v31930; SI-SDAG-NEXT: v_sub_f32_e32 v7, v3, v61931; SI-SDAG-NEXT: v_fma_f32 v3, s2, v0, -v31932; SI-SDAG-NEXT: v_fma_f32 v3, s2, v1, v31933; SI-SDAG-NEXT: v_add_f32_e32 v3, v7, v31934; SI-SDAG-NEXT: v_exp_f32_e32 v7, v31935; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v6, v61936; SI-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc1937; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s3, v51938; SI-SDAG-NEXT: v_cndmask_b32_e32 v3, v8, v2, vcc1939; SI-SDAG-NEXT: v_ldexp_f32_e32 v2, v7, v61940; SI-SDAG-NEXT: v_mul_f32_e32 v6, s1, v01941; SI-SDAG-NEXT: v_rndne_f32_e32 v7, v61942; SI-SDAG-NEXT: v_sub_f32_e32 v9, v6, v71943; SI-SDAG-NEXT: v_fma_f32 v6, s1, v0, -v61944; SI-SDAG-NEXT: v_fma_f32 v6, s1, v1, v61945; SI-SDAG-NEXT: v_add_f32_e32 v6, v9, v61946; SI-SDAG-NEXT: v_exp_f32_e32 v6, v61947; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v7, v71948; SI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s2, v41949; SI-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc1950; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s2, v51951; SI-SDAG-NEXT: v_ldexp_f32_e32 v6, v6, v71952; SI-SDAG-NEXT: v_mul_f32_e32 v7, s0, v01953; SI-SDAG-NEXT: v_rndne_f32_e32 v9, v71954; SI-SDAG-NEXT: v_fma_f32 v0, s0, v0, -v71955; SI-SDAG-NEXT: v_sub_f32_e32 v10, v7, v91956; SI-SDAG-NEXT: v_fma_f32 v0, s0, v1, v01957; SI-SDAG-NEXT: v_add_f32_e32 v0, v10, v01958; SI-SDAG-NEXT: v_exp_f32_e32 v0, v01959; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v7, v91960; SI-SDAG-NEXT: v_cndmask_b32_e32 v2, v8, v2, vcc1961; SI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s1, v41962; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v6, vcc1963; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s1, v51964; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc1965; SI-SDAG-NEXT: v_ldexp_f32_e32 v0, v0, v71966; SI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s0, v41967; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc1968; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s0, v51969; SI-SDAG-NEXT: s_mov_b32 s7, 0xf0001970; SI-SDAG-NEXT: s_mov_b32 s6, -11971; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc1972; SI-SDAG-NEXT: s_waitcnt lgkmcnt(0)1973; SI-SDAG-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 01974; SI-SDAG-NEXT: s_endpgm1975;1976; SI-GISEL-LABEL: s_exp10_v4f32:1977; SI-GISEL: ; %bb.0:1978; SI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xd1979; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x40549a781980; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x33979a371981; SI-GISEL-NEXT: v_mov_b32_e32 v5, 0x421a209b1982; SI-GISEL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x91983; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)1984; SI-GISEL-NEXT: v_mul_f32_e32 v0, s0, v21985; SI-GISEL-NEXT: v_fma_f32 v1, s0, v2, -v01986; SI-GISEL-NEXT: v_rndne_f32_e32 v4, v01987; SI-GISEL-NEXT: v_fma_f32 v1, s0, v3, v11988; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v41989; SI-GISEL-NEXT: v_add_f32_e32 v0, v0, v11990; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v1, v41991; SI-GISEL-NEXT: v_exp_f32_e32 v0, v01992; SI-GISEL-NEXT: v_mov_b32_e32 v4, 0xc23369f41993; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s0, v41994; SI-GISEL-NEXT: s_mov_b32 s6, -11995; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v11996; SI-GISEL-NEXT: v_mul_f32_e32 v1, s1, v21997; SI-GISEL-NEXT: v_fma_f32 v6, s1, v2, -v11998; SI-GISEL-NEXT: v_rndne_f32_e32 v7, v11999; SI-GISEL-NEXT: v_fma_f32 v6, s1, v3, v62000; SI-GISEL-NEXT: v_sub_f32_e32 v1, v1, v72001; SI-GISEL-NEXT: v_add_f32_e32 v1, v1, v62002; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v6, v72003; SI-GISEL-NEXT: v_exp_f32_e32 v1, v12004; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc2005; SI-GISEL-NEXT: v_mov_b32_e32 v7, 0x7f8000002006; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s0, v52007; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, v1, v62008; SI-GISEL-NEXT: v_mul_f32_e32 v6, s2, v22009; SI-GISEL-NEXT: v_fma_f32 v8, s2, v2, -v62010; SI-GISEL-NEXT: v_rndne_f32_e32 v9, v62011; SI-GISEL-NEXT: v_fma_f32 v8, s2, v3, v82012; SI-GISEL-NEXT: v_sub_f32_e32 v6, v6, v92013; SI-GISEL-NEXT: v_add_f32_e32 v6, v6, v82014; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v8, v92015; SI-GISEL-NEXT: v_exp_f32_e32 v6, v62016; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc2017; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s1, v42018; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc2019; SI-GISEL-NEXT: v_ldexp_f32_e32 v6, v6, v82020; SI-GISEL-NEXT: v_mul_f32_e32 v8, s3, v22021; SI-GISEL-NEXT: v_fma_f32 v2, s3, v2, -v82022; SI-GISEL-NEXT: v_fma_f32 v2, s3, v3, v22023; SI-GISEL-NEXT: v_rndne_f32_e32 v3, v82024; SI-GISEL-NEXT: v_sub_f32_e32 v8, v8, v32025; SI-GISEL-NEXT: v_add_f32_e32 v2, v8, v22026; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v3, v32027; SI-GISEL-NEXT: v_exp_f32_e32 v8, v22028; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s1, v52029; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc2030; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v42031; SI-GISEL-NEXT: v_cndmask_b32_e64 v2, v6, 0, vcc2032; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s2, v52033; SI-GISEL-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc2034; SI-GISEL-NEXT: v_ldexp_f32_e32 v3, v8, v32035; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s3, v42036; SI-GISEL-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc2037; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s3, v52038; SI-GISEL-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc2039; SI-GISEL-NEXT: s_mov_b32 s7, 0xf0002040; SI-GISEL-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 02041; SI-GISEL-NEXT: s_endpgm2042;2043; R600-LABEL: s_exp10_v4f32:2044; R600: ; %bb.0:2045; R600-NEXT: ALU 98, @6, KC0[CB0:0-32], KC1[]2046; R600-NEXT: ALU 95, @105, KC0[CB0:0-32], KC1[]2047; R600-NEXT: ALU 24, @201, KC0[CB0:0-32], KC1[]2048; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.XYZW, T0.X, 12049; R600-NEXT: CF_END2050; R600-NEXT: PAD2051; R600-NEXT: ALU clause starting at 6:2052; R600-NEXT: AND_INT * T0.W, KC0[3].Z, literal.x,2053; R600-NEXT: -4096(nan), 0(0.000000e+00)2054; R600-NEXT: ADD * T1.W, KC0[3].Z, -PV.W,2055; R600-NEXT: MUL_IEEE T2.W, PV.W, literal.x,2056; R600-NEXT: MUL_IEEE * T3.W, T0.W, literal.y,2057; R600-NEXT: 975668412(6.390323e-04), 1079283712(3.321289e+00)2058; R600-NEXT: RNDNE T4.W, PS,2059; R600-NEXT: MULADD_IEEE * T1.W, T1.W, literal.x, PV.W, BS:VEC_021/SCL_1222060; R600-NEXT: 1079283712(3.321289e+00), 0(0.000000e+00)2061; R600-NEXT: MULADD_IEEE T0.W, T0.W, literal.x, PS,2062; R600-NEXT: ADD * T1.W, T3.W, -PV.W,2063; R600-NEXT: 975668412(6.390323e-04), 0(0.000000e+00)2064; R600-NEXT: ADD T0.W, PS, PV.W,2065; R600-NEXT: TRUNC * T1.W, T4.W,2066; R600-NEXT: FLT_TO_INT T1.W, PS,2067; R600-NEXT: EXP_IEEE * T0.X, PV.W,2068; R600-NEXT: MUL_IEEE T0.Z, PS, literal.x,2069; R600-NEXT: MAX_INT T0.W, PV.W, literal.y,2070; R600-NEXT: MIN_INT * T2.W, PV.W, literal.z,2071; R600-NEXT: 209715200(1.972152e-31), -330(nan)2072; R600-NEXT: 381(5.338947e-43), 0(0.000000e+00)2073; R600-NEXT: ADD_INT T1.X, PS, literal.x,2074; R600-NEXT: AND_INT T0.Y, KC0[4].X, literal.y,2075; R600-NEXT: ADD_INT T1.Z, PV.W, literal.z,2076; R600-NEXT: ADD_INT * T0.W, T1.W, literal.w,2077; R600-NEXT: -254(nan), -4096(nan)2078; R600-NEXT: 204(2.858649e-43), 102(1.429324e-43)2079; R600-NEXT: SETGT_UINT * T2.W, T1.W, literal.x,2080; R600-NEXT: -229(nan), 0(0.000000e+00)2081; R600-NEXT: ADD_INT T2.X, T1.W, literal.x,2082; R600-NEXT: SETGT_UINT T1.Y, T1.W, literal.y,2083; R600-NEXT: CNDE_INT T1.Z, PV.W, T1.Z, T0.W,2084; R600-NEXT: SETGT_INT T0.W, T1.W, literal.x,2085; R600-NEXT: ADD * T3.W, KC0[4].X, -T0.Y,2086; R600-NEXT: -127(nan), 254(3.559298e-43)2087; R600-NEXT: MUL_IEEE T3.X, PS, literal.x,2088; R600-NEXT: MUL_IEEE T2.Y, T0.Y, literal.y,2089; R600-NEXT: CNDE_INT T1.Z, PV.W, PV.Z, T1.W,2090; R600-NEXT: CNDE_INT T4.W, PV.Y, PV.X, T1.X,2091; R600-NEXT: SETGT_INT * T1.W, T1.W, literal.z,2092; R600-NEXT: 975668412(6.390323e-04), 1079283712(3.321289e+00)2093; R600-NEXT: 127(1.779649e-43), 0(0.000000e+00)2094; R600-NEXT: CNDE_INT T1.X, PS, PV.Z, PV.W,2095; R600-NEXT: RNDNE T3.Y, PV.Y,2096; R600-NEXT: MULADD_IEEE T1.Z, T3.W, literal.x, PV.X,2097; R600-NEXT: MUL_IEEE T3.W, T0.Z, literal.y,2098; R600-NEXT: MUL_IEEE * T4.W, T0.X, literal.z,2099; R600-NEXT: 1079283712(3.321289e+00), 209715200(1.972152e-31)2100; R600-NEXT: 2130706432(1.701412e+38), 0(0.000000e+00)2101; R600-NEXT: MUL_IEEE T2.X, PS, literal.x,2102; R600-NEXT: CNDE_INT T4.Y, T2.W, PV.W, T0.Z,2103; R600-NEXT: MULADD_IEEE T0.Z, T0.Y, literal.y, PV.Z,2104; R600-NEXT: ADD T2.W, T2.Y, -PV.Y, BS:VEC_120/SCL_2122105; R600-NEXT: AND_INT * T3.W, KC0[3].Y, literal.z,2106; R600-NEXT: 2130706432(1.701412e+38), 975668412(6.390323e-04)2107; R600-NEXT: -4096(nan), 0(0.000000e+00)2108; R600-NEXT: MUL_IEEE T3.X, PS, literal.x,2109; R600-NEXT: ADD T0.Y, PV.W, PV.Z,2110; R600-NEXT: CNDE_INT T0.Z, T0.W, PV.Y, T0.X, BS:VEC_021/SCL_1222111; R600-NEXT: CNDE_INT T0.W, T1.Y, T4.W, PV.X,2112; R600-NEXT: LSHL * T2.W, T1.X, literal.y,2113; R600-NEXT: 1079283712(3.321289e+00), 23(3.222986e-44)2114; R600-NEXT: AND_INT T0.X, KC0[3].W, literal.x,2115; R600-NEXT: TRUNC T1.Y, T3.Y,2116; R600-NEXT: ADD_INT T1.Z, PS, literal.y,2117; R600-NEXT: CNDE_INT T0.W, T1.W, PV.Z, PV.W,2118; R600-NEXT: EXP_IEEE * T0.Y, PV.Y,2119; R600-NEXT: -4096(nan), 1065353216(1.000000e+00)2120; R600-NEXT: MUL_IEEE T1.X, PV.W, PV.Z,2121; R600-NEXT: FLT_TO_INT T1.Y, PV.Y,2122; R600-NEXT: MUL_IEEE T0.Z, PS, literal.x,2123; R600-NEXT: ADD T0.W, KC0[3].W, -PV.X,2124; R600-NEXT: RNDNE * T1.W, T3.X,2125; R600-NEXT: 209715200(1.972152e-31), 0(0.000000e+00)2126; R600-NEXT: SETGT T2.X, literal.x, KC0[3].Z,2127; R600-NEXT: TRUNC T2.Y, PS,2128; R600-NEXT: MUL_IEEE T1.Z, PV.W, literal.y,2129; R600-NEXT: MUL_IEEE T2.W, PV.Z, literal.z,2130; R600-NEXT: MAX_INT * T4.W, PV.Y, literal.w,2131; R600-NEXT: -1036817932(-4.485347e+01), 975668412(6.390323e-04)2132; R600-NEXT: 209715200(1.972152e-31), -330(nan)2133; R600-NEXT: ADD T4.X, KC0[3].Y, -T3.W,2134; R600-NEXT: ADD_INT T3.Y, PS, literal.x,2135; R600-NEXT: ADD_INT T2.Z, T1.Y, literal.y,2136; R600-NEXT: SETGT_UINT T4.W, T1.Y, literal.z,2137; R600-NEXT: MIN_INT * T5.W, T1.Y, literal.w,2138; R600-NEXT: 204(2.858649e-43), 102(1.429324e-43)2139; R600-NEXT: -229(nan), 381(5.338947e-43)2140; R600-NEXT: ADD_INT T5.X, PS, literal.x,2141; R600-NEXT: ADD_INT T4.Y, T1.Y, literal.y,2142; R600-NEXT: SETGT_UINT T3.Z, T1.Y, literal.z,2143; R600-NEXT: CNDE_INT T5.W, PV.W, PV.Y, PV.Z,2144; R600-NEXT: SETGT_INT * T6.W, T1.Y, literal.y,2145; R600-NEXT: -254(nan), -127(nan)2146; R600-NEXT: 254(3.559298e-43), 0(0.000000e+00)2147; R600-NEXT: MUL_IEEE T6.X, T0.Y, literal.x,2148; R600-NEXT: CNDE_INT T3.Y, PS, PV.W, T1.Y,2149; R600-NEXT: CNDE_INT * T2.Z, PV.Z, PV.Y, PV.X,2150; R600-NEXT: 2130706432(1.701412e+38), 0(0.000000e+00)2151; R600-NEXT: ALU clause starting at 105:2152; R600-NEXT: SETGT_INT T5.W, T1.Y, literal.x,2153; R600-NEXT: MUL_IEEE * T7.W, T4.X, literal.y,2154; R600-NEXT: 127(1.779649e-43), 975668412(6.390323e-04)2155; R600-NEXT: MUL_IEEE T5.X, T0.X, literal.x,2156; R600-NEXT: MULADD_IEEE T1.Y, T4.X, literal.x, PS, BS:VEC_120/SCL_2122157; R600-NEXT: CNDE_INT T2.Z, PV.W, T3.Y, T2.Z,2158; R600-NEXT: MUL_IEEE T7.W, T6.X, literal.y, BS:VEC_2012159; R600-NEXT: CNDE_INT * T2.W, T4.W, T2.W, T0.Z,2160; R600-NEXT: 1079283712(3.321289e+00), 2130706432(1.701412e+38)2161; R600-NEXT: CNDE_INT T4.X, T6.W, PS, T0.Y,2162; R600-NEXT: CNDE_INT T0.Y, T3.Z, T6.X, PV.W,2163; R600-NEXT: LSHL T0.Z, PV.Z, literal.x,2164; R600-NEXT: MULADD_IEEE T2.W, T3.W, literal.y, PV.Y, BS:VEC_2012165; R600-NEXT: ADD * T1.W, T3.X, -T1.W,2166; R600-NEXT: 23(3.222986e-44), 975668412(6.390323e-04)2167; R600-NEXT: ADD T3.X, PS, PV.W,2168; R600-NEXT: ADD_INT T1.Y, PV.Z, literal.x,2169; R600-NEXT: CNDE_INT T0.Z, T5.W, PV.X, PV.Y,2170; R600-NEXT: RNDNE T1.W, T5.X,2171; R600-NEXT: MULADD_IEEE * T0.W, T0.W, literal.y, T1.Z, BS:VEC_021/SCL_1222172; R600-NEXT: 1065353216(1.000000e+00), 1079283712(3.321289e+00)2173; R600-NEXT: MULADD_IEEE T0.X, T0.X, literal.x, PS,2174; R600-NEXT: ADD T0.Y, T5.X, -PV.W, BS:VEC_120/SCL_2122175; R600-NEXT: MUL_IEEE T0.Z, PV.Z, PV.Y,2176; R600-NEXT: SETGT T0.W, literal.y, KC0[4].X,2177; R600-NEXT: EXP_IEEE * T1.Y, PV.X,2178; R600-NEXT: 975668412(6.390323e-04), -1036817932(-4.485347e+01)2179; R600-NEXT: CNDE T3.X, PV.W, PV.Z, 0.0,2180; R600-NEXT: ADD T0.Y, PV.Y, PV.X,2181; R600-NEXT: FLT_TO_INT T0.Z, T2.Y,2182; R600-NEXT: TRUNC T0.W, T1.W,2183; R600-NEXT: MUL_IEEE * T1.W, PS, literal.x,2184; R600-NEXT: 209715200(1.972152e-31), 0(0.000000e+00)2185; R600-NEXT: SETGT T0.X, KC0[4].X, literal.x,2186; R600-NEXT: MUL_IEEE T2.Y, PS, literal.y,2187; R600-NEXT: FLT_TO_INT T1.Z, PV.W,2188; R600-NEXT: MAX_INT T0.W, PV.Z, literal.z,2189; R600-NEXT: EXP_IEEE * T0.Y, PV.Y,2190; R600-NEXT: 1109008539(3.853184e+01), 209715200(1.972152e-31)2191; R600-NEXT: -330(nan), 0(0.000000e+00)2192; R600-NEXT: MUL_IEEE T4.X, T1.Y, literal.x,2193; R600-NEXT: MUL_IEEE T3.Y, PS, literal.y,2194; R600-NEXT: ADD_INT T2.Z, PV.W, literal.z,2195; R600-NEXT: ADD_INT * T0.W, T0.Z, literal.w,2196; R600-NEXT: 2130706432(1.701412e+38), 209715200(1.972152e-31)2197; R600-NEXT: 204(2.858649e-43), 102(1.429324e-43)2198; R600-NEXT: MAX_INT * T2.W, T1.Z, literal.x,2199; R600-NEXT: -330(nan), 0(0.000000e+00)2200; R600-NEXT: SETGT_UINT T5.X, T0.Z, literal.x,2201; R600-NEXT: ADD_INT T4.Y, PV.W, literal.y,2202; R600-NEXT: ADD_INT T3.Z, T1.Z, literal.z, BS:VEC_120/SCL_2122203; R600-NEXT: SETGT_UINT T2.W, T1.Z, literal.x, BS:VEC_120/SCL_2122204; R600-NEXT: MIN_INT * T3.W, T1.Z, literal.w,2205; R600-NEXT: -229(nan), 204(2.858649e-43)2206; R600-NEXT: 102(1.429324e-43), 381(5.338947e-43)2207; R600-NEXT: ADD_INT T6.X, PS, literal.x,2208; R600-NEXT: ADD_INT T5.Y, T1.Z, literal.y,2209; R600-NEXT: SETGT_UINT T4.Z, T1.Z, literal.z,2210; R600-NEXT: CNDE_INT T3.W, PV.W, PV.Y, PV.Z,2211; R600-NEXT: SETGT_INT * T4.W, T1.Z, literal.y,2212; R600-NEXT: -254(nan), -127(nan)2213; R600-NEXT: 254(3.559298e-43), 0(0.000000e+00)2214; R600-NEXT: CNDE_INT T7.X, PS, PV.W, T1.Z, BS:VEC_021/SCL_1222215; R600-NEXT: CNDE_INT T4.Y, PV.Z, PV.Y, PV.X,2216; R600-NEXT: SETGT_INT T1.Z, T1.Z, literal.x, BS:VEC_120/SCL_2122217; R600-NEXT: CNDE_INT T0.W, T5.X, T2.Z, T0.W, BS:VEC_102/SCL_2212218; R600-NEXT: SETGT_INT * T3.W, T0.Z, literal.y,2219; R600-NEXT: 127(1.779649e-43), -127(nan)2220; R600-NEXT: CNDE_INT T6.X, PS, PV.W, T0.Z,2221; R600-NEXT: CNDE_INT T4.Y, PV.Z, PV.X, PV.Y,2222; R600-NEXT: MIN_INT T2.Z, T0.Z, literal.x,2223; R600-NEXT: MUL_IEEE T0.W, T3.Y, literal.y,2224; R600-NEXT: MUL_IEEE * T5.W, T0.Y, literal.z,2225; R600-NEXT: 381(5.338947e-43), 209715200(1.972152e-31)2226; R600-NEXT: 2130706432(1.701412e+38), 0(0.000000e+00)2227; R600-NEXT: MUL_IEEE T7.X, PS, literal.x,2228; R600-NEXT: CNDE_INT T3.Y, T2.W, PV.W, T3.Y,2229; R600-NEXT: ADD_INT T2.Z, PV.Z, literal.y,2230; R600-NEXT: ADD_INT T0.W, T0.Z, literal.z,2231; R600-NEXT: SETGT_UINT * T2.W, T0.Z, literal.w,2232; R600-NEXT: 2130706432(1.701412e+38), -254(nan)2233; R600-NEXT: -127(nan), 254(3.559298e-43)2234; R600-NEXT: CNDE_INT T8.X, PS, PV.W, PV.Z,2235; R600-NEXT: SETGT_INT T5.Y, T0.Z, literal.x,2236; R600-NEXT: CNDE_INT T0.Z, T4.W, PV.Y, T0.Y, BS:VEC_021/SCL_1222237; R600-NEXT: CNDE_INT T0.W, T4.Z, T5.W, PV.X, BS:VEC_120/SCL_2122238; R600-NEXT: LSHL * T4.W, T4.Y, literal.y,2239; R600-NEXT: 127(1.779649e-43), 23(3.222986e-44)2240; R600-NEXT: ADD_INT T7.X, PS, literal.x,2241; R600-NEXT: CNDE_INT T0.Y, T1.Z, PV.Z, PV.W,2242; R600-NEXT: CNDE_INT T0.Z, PV.Y, T6.X, PV.X,2243; R600-NEXT: MUL_IEEE T0.W, T4.X, literal.y,2244; R600-NEXT: CNDE_INT * T1.W, T5.X, T2.Y, T1.W,2245; R600-NEXT: 1065353216(1.000000e+00), 2130706432(1.701412e+38)2246; R600-NEXT: CNDE_INT T5.X, T3.W, PS, T1.Y,2247; R600-NEXT: CNDE_INT * T1.Y, T2.W, T4.X, PV.W, BS:VEC_120/SCL_2122248; R600-NEXT: ALU clause starting at 201:2249; R600-NEXT: LSHL T0.Z, T0.Z, literal.x,2250; R600-NEXT: MUL_IEEE T0.W, T0.Y, T7.X,2251; R600-NEXT: SETGT * T1.W, literal.y, KC0[3].W,2252; R600-NEXT: 23(3.222986e-44), -1036817932(-4.485347e+01)2253; R600-NEXT: CNDE T4.X, PS, PV.W, 0.0,2254; R600-NEXT: SETGT T0.Y, KC0[3].W, literal.x,2255; R600-NEXT: ADD_INT T0.Z, PV.Z, literal.y,2256; R600-NEXT: CNDE_INT T0.W, T5.Y, T5.X, T1.Y, BS:VEC_102/SCL_2212257; R600-NEXT: CNDE * T1.W, T0.X, T3.X, literal.z,2258; R600-NEXT: 1109008539(3.853184e+01), 1065353216(1.000000e+00)2259; R600-NEXT: 2139095040(INF), 0(0.000000e+00)2260; R600-NEXT: MUL_IEEE T0.X, PV.W, PV.Z,2261; R600-NEXT: SETGT T2.Y, literal.x, KC0[3].Y,2262; R600-NEXT: CNDE T1.Z, PV.Y, PV.X, literal.y,2263; R600-NEXT: CNDE T0.W, T2.X, T1.X, 0.0,2264; R600-NEXT: SETGT * T2.W, KC0[3].Z, literal.z,2265; R600-NEXT: -1036817932(-4.485347e+01), 2139095040(INF)2266; R600-NEXT: 1109008539(3.853184e+01), 0(0.000000e+00)2267; R600-NEXT: CNDE T1.Y, PS, PV.W, literal.x,2268; R600-NEXT: CNDE T0.W, PV.Y, PV.X, 0.0,2269; R600-NEXT: SETGT * T2.W, KC0[3].Y, literal.y,2270; R600-NEXT: 2139095040(INF), 1109008539(3.853184e+01)2271; R600-NEXT: CNDE T1.X, PS, PV.W, literal.x,2272; R600-NEXT: LSHR * T0.X, KC0[2].Y, literal.y,2273; R600-NEXT: 2139095040(INF), 2(2.802597e-45)2274;2275; CM-LABEL: s_exp10_v4f32:2276; CM: ; %bb.0:2277; CM-NEXT: ALU 97, @6, KC0[CB0:0-32], KC1[]2278; CM-NEXT: ALU 97, @104, KC0[CB0:0-32], KC1[]2279; CM-NEXT: ALU 35, @202, KC0[CB0:0-32], KC1[]2280; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0, T1.X2281; CM-NEXT: CF_END2282; CM-NEXT: PAD2283; CM-NEXT: ALU clause starting at 6:2284; CM-NEXT: AND_INT * T0.W, KC0[3].Y, literal.x,2285; CM-NEXT: -4096(nan), 0(0.000000e+00)2286; CM-NEXT: ADD * T1.W, KC0[3].Y, -PV.W,2287; CM-NEXT: MUL_IEEE T0.Y, PV.W, literal.x,2288; CM-NEXT: MUL_IEEE T0.Z, T0.W, literal.y,2289; CM-NEXT: AND_INT * T2.W, KC0[3].W, literal.z,2290; CM-NEXT: 975668412(6.390323e-04), 1079283712(3.321289e+00)2291; CM-NEXT: -4096(nan), 0(0.000000e+00)2292; CM-NEXT: ADD T1.Y, KC0[3].W, -PV.W,2293; CM-NEXT: RNDNE T1.Z, PV.Z,2294; CM-NEXT: MULADD_IEEE * T1.W, T1.W, literal.x, PV.Y,2295; CM-NEXT: 1079283712(3.321289e+00), 0(0.000000e+00)2296; CM-NEXT: MULADD_IEEE T0.X, T0.W, literal.x, PV.W,2297; CM-NEXT: ADD T0.Y, T0.Z, -PV.Z,2298; CM-NEXT: MUL_IEEE T0.Z, T2.W, literal.y, BS:VEC_120/SCL_2122299; CM-NEXT: MUL_IEEE * T0.W, PV.Y, literal.x,2300; CM-NEXT: 975668412(6.390323e-04), 1079283712(3.321289e+00)2301; CM-NEXT: TRUNC T1.X, T1.Z,2302; CM-NEXT: MULADD_IEEE T1.Y, T1.Y, literal.x, PV.W,2303; CM-NEXT: RNDNE T1.Z, PV.Z,2304; CM-NEXT: ADD * T0.W, PV.Y, PV.X,2305; CM-NEXT: 1079283712(3.321289e+00), 0(0.000000e+00)2306; CM-NEXT: EXP_IEEE T0.X, T0.W,2307; CM-NEXT: EXP_IEEE T0.Y (MASKED), T0.W,2308; CM-NEXT: EXP_IEEE T0.Z (MASKED), T0.W,2309; CM-NEXT: EXP_IEEE * T0.W (MASKED), T0.W,2310; CM-NEXT: TRUNC T2.X, T1.Z,2311; CM-NEXT: MULADD_IEEE T0.Y, T2.W, literal.x, T1.Y,2312; CM-NEXT: FLT_TO_INT T2.Z, T1.X,2313; CM-NEXT: MUL_IEEE * T0.W, PV.X, literal.y,2314; CM-NEXT: 975668412(6.390323e-04), 209715200(1.972152e-31)2315; CM-NEXT: ADD T1.X, T0.Z, -T1.Z,2316; CM-NEXT: MUL_IEEE T1.Y, PV.W, literal.x,2317; CM-NEXT: MAX_INT T0.Z, PV.Z, literal.y,2318; CM-NEXT: MIN_INT * T1.W, PV.Z, literal.z,2319; CM-NEXT: 209715200(1.972152e-31), -330(nan)2320; CM-NEXT: 381(5.338947e-43), 0(0.000000e+00)2321; CM-NEXT: ADD_INT T3.X, PV.W, literal.x,2322; CM-NEXT: ADD_INT T2.Y, PV.Z, literal.y,2323; CM-NEXT: ADD_INT T0.Z, T2.Z, literal.z,2324; CM-NEXT: SETGT_UINT * T1.W, T2.Z, literal.w,2325; CM-NEXT: -254(nan), 204(2.858649e-43)2326; CM-NEXT: 102(1.429324e-43), -229(nan)2327; CM-NEXT: ADD_INT T4.X, T2.Z, literal.x,2328; CM-NEXT: SETGT_UINT T3.Y, T2.Z, literal.y,2329; CM-NEXT: CNDE_INT T0.Z, PV.W, PV.Y, PV.Z,2330; CM-NEXT: SETGT_INT * T2.W, T2.Z, literal.x,2331; CM-NEXT: -127(nan), 254(3.559298e-43)2332; CM-NEXT: MUL_IEEE T5.X, T0.X, literal.x,2333; CM-NEXT: CNDE_INT T2.Y, PV.W, PV.Z, T2.Z,2334; CM-NEXT: CNDE_INT T0.Z, PV.Y, PV.X, T3.X,2335; CM-NEXT: SETGT_INT * T3.W, T2.Z, literal.y,2336; CM-NEXT: 2130706432(1.701412e+38), 127(1.779649e-43)2337; CM-NEXT: AND_INT T3.X, KC0[3].Z, literal.x,2338; CM-NEXT: CNDE_INT T2.Y, PV.W, PV.Y, PV.Z,2339; CM-NEXT: MUL_IEEE T0.Z, PV.X, literal.y,2340; CM-NEXT: CNDE_INT * T0.W, T1.W, T1.Y, T0.W,2341; CM-NEXT: -4096(nan), 2130706432(1.701412e+38)2342; CM-NEXT: CNDE_INT T0.X, T2.W, PV.W, T0.X,2343; CM-NEXT: CNDE_INT T1.Y, T3.Y, T5.X, PV.Z,2344; CM-NEXT: LSHL T0.Z, PV.Y, literal.x,2345; CM-NEXT: MUL_IEEE * T0.W, PV.X, literal.y,2346; CM-NEXT: 23(3.222986e-44), 1079283712(3.321289e+00)2347; CM-NEXT: RNDNE T4.X, PV.W,2348; CM-NEXT: ADD_INT T2.Y, PV.Z, literal.x,2349; CM-NEXT: CNDE_INT T0.Z, T3.W, PV.X, PV.Y,2350; CM-NEXT: ADD * T1.W, T1.X, T0.Y,2351; CM-NEXT: 1065353216(1.000000e+00), 0(0.000000e+00)2352; CM-NEXT: EXP_IEEE T0.X, T1.W,2353; CM-NEXT: EXP_IEEE T0.Y (MASKED), T1.W,2354; CM-NEXT: EXP_IEEE T0.Z (MASKED), T1.W,2355; CM-NEXT: EXP_IEEE * T0.W (MASKED), T1.W,2356; CM-NEXT: MUL_IEEE T1.X, T0.Z, T2.Y,2357; CM-NEXT: TRUNC T0.Y, T4.X,2358; CM-NEXT: FLT_TO_INT T0.Z, T2.X, BS:VEC_120/SCL_2122359; CM-NEXT: MUL_IEEE * T1.W, PV.X, literal.x,2360; CM-NEXT: 209715200(1.972152e-31), 0(0.000000e+00)2361; CM-NEXT: MUL_IEEE T2.X, PV.W, literal.x,2362; CM-NEXT: MUL_IEEE T1.Y, T0.X, literal.y,2363; CM-NEXT: MAX_INT T1.Z, PV.Z, literal.z,2364; CM-NEXT: MIN_INT * T2.W, PV.Z, literal.w,2365; CM-NEXT: 209715200(1.972152e-31), 2130706432(1.701412e+38)2366; CM-NEXT: -330(nan), 381(5.338947e-43)2367; CM-NEXT: ADD_INT T5.X, PV.W, literal.x,2368; CM-NEXT: ADD_INT T2.Y, PV.Z, literal.y,2369; CM-NEXT: ADD_INT T1.Z, T0.Z, literal.z,2370; CM-NEXT: SETGT_UINT * T2.W, T0.Z, literal.w,2371; CM-NEXT: -254(nan), 204(2.858649e-43)2372; CM-NEXT: 102(1.429324e-43), -229(nan)2373; CM-NEXT: ADD_INT T6.X, T0.Z, literal.x,2374; CM-NEXT: SETGT_UINT T3.Y, T0.Z, literal.y,2375; CM-NEXT: CNDE_INT T1.Z, PV.W, PV.Y, PV.Z,2376; CM-NEXT: SETGT_INT * T3.W, T0.Z, literal.x,2377; CM-NEXT: -127(nan), 254(3.559298e-43)2378; CM-NEXT: CNDE_INT T7.X, PV.W, PV.Z, T0.Z,2379; CM-NEXT: CNDE_INT T2.Y, PV.Y, PV.X, T5.X,2380; CM-NEXT: SETGT_INT * T0.Z, T0.Z, literal.x,2381; CM-NEXT: 127(1.779649e-43), 0(0.000000e+00)2382; CM-NEXT: ALU clause starting at 104:2383; CM-NEXT: ADD * T4.W, KC0[3].Z, -T3.X,2384; CM-NEXT: MUL_IEEE T5.X, PV.W, literal.x,2385; CM-NEXT: CNDE_INT T2.Y, T0.Z, T7.X, T2.Y,2386; CM-NEXT: MUL_IEEE T1.Z, T1.Y, literal.y,2387; CM-NEXT: CNDE_INT * T1.W, T2.W, T2.X, T1.W, BS:VEC_021/SCL_1222388; CM-NEXT: 975668412(6.390323e-04), 2130706432(1.701412e+38)2389; CM-NEXT: CNDE_INT T0.X, T3.W, PV.W, T0.X,2390; CM-NEXT: CNDE_INT T1.Y, T3.Y, T1.Y, PV.Z,2391; CM-NEXT: LSHL T1.Z, PV.Y, literal.x,2392; CM-NEXT: MULADD_IEEE * T1.W, T4.W, literal.y, PV.X, BS:VEC_120/SCL_2122393; CM-NEXT: 23(3.222986e-44), 1079283712(3.321289e+00)2394; CM-NEXT: MULADD_IEEE T2.X, T3.X, literal.x, PV.W,2395; CM-NEXT: ADD T2.Y, T0.W, -T4.X,2396; CM-NEXT: ADD_INT T1.Z, PV.Z, literal.y,2397; CM-NEXT: CNDE_INT * T0.W, T0.Z, PV.X, PV.Y,2398; CM-NEXT: 975668412(6.390323e-04), 1065353216(1.000000e+00)2399; CM-NEXT: AND_INT T0.X, KC0[4].X, literal.x,2400; CM-NEXT: MUL_IEEE T1.Y, PV.W, PV.Z,2401; CM-NEXT: SETGT T0.Z, literal.y, KC0[3].W,2402; CM-NEXT: ADD * T0.W, PV.Y, PV.X,2403; CM-NEXT: -4096(nan), -1036817932(-4.485347e+01)2404; CM-NEXT: EXP_IEEE T0.X (MASKED), T0.W,2405; CM-NEXT: EXP_IEEE T0.Y (MASKED), T0.W,2406; CM-NEXT: EXP_IEEE T0.Z (MASKED), T0.W,2407; CM-NEXT: EXP_IEEE * T0.W, T0.W,2408; CM-NEXT: CNDE T2.X, T0.Z, T1.Y, 0.0,2409; CM-NEXT: ADD T1.Y, KC0[4].X, -T0.X,2410; CM-NEXT: FLT_TO_INT T0.Z, T0.Y,2411; CM-NEXT: MUL_IEEE * T1.W, PV.W, literal.x,2412; CM-NEXT: 209715200(1.972152e-31), 0(0.000000e+00)2413; CM-NEXT: MUL_IEEE T3.X, PV.W, literal.x,2414; CM-NEXT: SETGT_UINT T0.Y, PV.Z, literal.y,2415; CM-NEXT: MUL_IEEE T1.Z, PV.Y, literal.z,2416; CM-NEXT: MUL_IEEE * T2.W, T0.X, literal.w,2417; CM-NEXT: 209715200(1.972152e-31), -229(nan)2418; CM-NEXT: 975668412(6.390323e-04), 1079283712(3.321289e+00)2419; CM-NEXT: RNDNE T4.X, PV.W,2420; CM-NEXT: MULADD_IEEE T1.Y, T1.Y, literal.x, PV.Z,2421; CM-NEXT: CNDE_INT T1.Z, PV.Y, PV.X, T1.W,2422; CM-NEXT: SETGT_INT * T1.W, T0.Z, literal.y,2423; CM-NEXT: 1079283712(3.321289e+00), -127(nan)2424; CM-NEXT: CNDE_INT T3.X, PV.W, PV.Z, T0.W,2425; CM-NEXT: MULADD_IEEE T1.Y, T0.X, literal.x, PV.Y,2426; CM-NEXT: ADD T1.Z, T2.W, -PV.X,2427; CM-NEXT: MAX_INT * T2.W, T0.Z, literal.y,2428; CM-NEXT: 975668412(6.390323e-04), -330(nan)2429; CM-NEXT: ADD_INT T0.X, PV.W, literal.x,2430; CM-NEXT: ADD_INT T2.Y, T0.Z, literal.y,2431; CM-NEXT: TRUNC T2.Z, T4.X,2432; CM-NEXT: ADD * T2.W, PV.Z, PV.Y,2433; CM-NEXT: 204(2.858649e-43), 102(1.429324e-43)2434; CM-NEXT: EXP_IEEE T1.X (MASKED), T2.W,2435; CM-NEXT: EXP_IEEE T1.Y, T2.W,2436; CM-NEXT: EXP_IEEE T1.Z (MASKED), T2.W,2437; CM-NEXT: EXP_IEEE * T1.W (MASKED), T2.W,2438; CM-NEXT: MUL_IEEE T4.X, T0.W, literal.x,2439; CM-NEXT: FLT_TO_INT T3.Y, T2.Z,2440; CM-NEXT: MUL_IEEE T1.Z, PV.Y, literal.y,2441; CM-NEXT: CNDE_INT * T0.W, T0.Y, T0.X, T2.Y,2442; CM-NEXT: 2130706432(1.701412e+38), 209715200(1.972152e-31)2443; CM-NEXT: CNDE_INT T0.X, T1.W, PV.W, T0.Z,2444; CM-NEXT: MUL_IEEE T0.Y, PV.Z, literal.x,2445; CM-NEXT: MAX_INT T2.Z, PV.Y, literal.y,2446; CM-NEXT: MIN_INT * T0.W, PV.Y, literal.z,2447; CM-NEXT: 209715200(1.972152e-31), -330(nan)2448; CM-NEXT: 381(5.338947e-43), 0(0.000000e+00)2449; CM-NEXT: ADD_INT T5.X, PV.W, literal.x,2450; CM-NEXT: ADD_INT T2.Y, PV.Z, literal.y,2451; CM-NEXT: ADD_INT T2.Z, T3.Y, literal.z,2452; CM-NEXT: SETGT_UINT * T0.W, T3.Y, literal.w,2453; CM-NEXT: -254(nan), 204(2.858649e-43)2454; CM-NEXT: 102(1.429324e-43), -229(nan)2455; CM-NEXT: ADD_INT T6.X, T3.Y, literal.x,2456; CM-NEXT: SETGT_UINT T4.Y, T3.Y, literal.y,2457; CM-NEXT: CNDE_INT T2.Z, PV.W, PV.Y, PV.Z,2458; CM-NEXT: SETGT_INT * T1.W, T3.Y, literal.x,2459; CM-NEXT: -127(nan), 254(3.559298e-43)2460; CM-NEXT: MUL_IEEE T7.X, T1.Y, literal.x,2461; CM-NEXT: CNDE_INT T2.Y, PV.W, PV.Z, T3.Y,2462; CM-NEXT: CNDE_INT T2.Z, PV.Y, PV.X, T5.X,2463; CM-NEXT: MIN_INT * T2.W, T0.Z, literal.y,2464; CM-NEXT: 2130706432(1.701412e+38), 381(5.338947e-43)2465; CM-NEXT: SETGT_INT T5.X, T3.Y, literal.x,2466; CM-NEXT: ADD_INT T3.Y, PV.W, literal.y,2467; CM-NEXT: ADD_INT T3.Z, T0.Z, literal.z,2468; CM-NEXT: SETGT_UINT * T2.W, T0.Z, literal.w,2469; CM-NEXT: 127(1.779649e-43), -254(nan)2470; CM-NEXT: -127(nan), 254(3.559298e-43)2471; CM-NEXT: CNDE_INT T6.X, PV.W, PV.Z, PV.Y,2472; CM-NEXT: CNDE_INT T2.Y, PV.X, T2.Y, T2.Z,2473; CM-NEXT: MUL_IEEE T2.Z, T7.X, literal.x,2474; CM-NEXT: CNDE_INT * T0.W, T0.W, T0.Y, T1.Z, BS:VEC_021/SCL_1222475; CM-NEXT: 2130706432(1.701412e+38), 0(0.000000e+00)2476; CM-NEXT: SETGT_INT T8.X, T0.Z, literal.x,2477; CM-NEXT: CNDE_INT T0.Y, T1.W, PV.W, T1.Y,2478; CM-NEXT: CNDE_INT T0.Z, T4.Y, T7.X, PV.Z,2479; CM-NEXT: LSHL * T0.W, PV.Y, literal.y,2480; CM-NEXT: 127(1.779649e-43), 23(3.222986e-44)2481; CM-NEXT: ALU clause starting at 202:2482; CM-NEXT: ADD_INT T7.X, T0.W, literal.x,2483; CM-NEXT: CNDE_INT * T0.Y, T5.X, T0.Y, T0.Z,2484; CM-NEXT: 1065353216(1.000000e+00), 0(0.000000e+00)2485; CM-NEXT: CNDE_INT * T0.Z, T8.X, T0.X, T6.X,2486; CM-NEXT: MUL_IEEE * T0.W, T4.X, literal.x,2487; CM-NEXT: 2130706432(1.701412e+38), 0(0.000000e+00)2488; CM-NEXT: CNDE_INT T0.X, T2.W, T4.X, PV.W,2489; CM-NEXT: LSHL T1.Y, T0.Z, literal.x,2490; CM-NEXT: MUL_IEEE T0.Z, T0.Y, T7.X, BS:VEC_021/SCL_1222491; CM-NEXT: SETGT * T0.W, literal.y, KC0[4].X,2492; CM-NEXT: 23(3.222986e-44), -1036817932(-4.485347e+01)2493; CM-NEXT: CNDE T4.X, PV.W, PV.Z, 0.0,2494; CM-NEXT: SETGT T0.Y, KC0[4].X, literal.x,2495; CM-NEXT: ADD_INT T0.Z, PV.Y, literal.y,2496; CM-NEXT: CNDE_INT * T0.W, T8.X, T3.X, PV.X,2497; CM-NEXT: 1109008539(3.853184e+01), 1065353216(1.000000e+00)2498; CM-NEXT: SETGT T0.X, KC0[3].W, literal.x,2499; CM-NEXT: MUL_IEEE T1.Y, PV.W, PV.Z,2500; CM-NEXT: SETGT T0.Z, literal.y, KC0[3].Z,2501; CM-NEXT: CNDE * T0.W, PV.Y, PV.X, literal.z,2502; CM-NEXT: 1109008539(3.853184e+01), -1036817932(-4.485347e+01)2503; CM-NEXT: 2139095040(INF), 0(0.000000e+00)2504; CM-NEXT: SETGT T3.X, literal.x, KC0[3].Y,2505; CM-NEXT: CNDE T0.Y, PV.Z, PV.Y, 0.0,2506; CM-NEXT: CNDE T0.Z, PV.X, T2.X, literal.y,2507; CM-NEXT: SETGT * T1.W, KC0[3].Z, literal.z,2508; CM-NEXT: -1036817932(-4.485347e+01), 2139095040(INF)2509; CM-NEXT: 1109008539(3.853184e+01), 0(0.000000e+00)2510; CM-NEXT: CNDE T0.Y, PV.W, PV.Y, literal.x,2511; CM-NEXT: CNDE T1.Z, PV.X, T1.X, 0.0,2512; CM-NEXT: SETGT * T1.W, KC0[3].Y, literal.y,2513; CM-NEXT: 2139095040(INF), 1109008539(3.853184e+01)2514; CM-NEXT: CNDE * T0.X, PV.W, PV.Z, literal.x,2515; CM-NEXT: 2139095040(INF), 0(0.000000e+00)2516; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,2517; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)2518 %result = call <4 x float> @llvm.exp10.v4f32(<4 x float> %in)2519 store <4 x float> %result, ptr addrspace(1) %out2520 ret void2521}2522 2523define float @v_exp10_f32(float %in) {2524; VI-SDAG-LABEL: v_exp10_f32:2525; VI-SDAG: ; %bb.0:2526; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2527; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v02528; VI-SDAG-NEXT: v_sub_f32_e32 v4, v0, v12529; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x40549000, v12530; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x3a2784bc, v42531; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x40549000, v42532; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v22533; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v52534; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v12535; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v32536; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v42537; VI-SDAG-NEXT: v_add_f32_e32 v1, v2, v12538; VI-SDAG-NEXT: v_exp_f32_e32 v1, v12539; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v32540; VI-SDAG-NEXT: s_mov_b32 s4, 0xc23369f42541; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v02542; VI-SDAG-NEXT: s_mov_b32 s4, 0x421a209b2543; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v22544; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc2545; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f8000002546; VI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v02547; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc2548; VI-SDAG-NEXT: s_setpc_b64 s[30:31]2549;2550; VI-GISEL-LABEL: v_exp10_f32:2551; VI-GISEL: ; %bb.0:2552; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2553; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v02554; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v12555; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3a2784bc, v22556; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549000, v22557; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x40549000, v12558; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v42559; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v12560; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v22561; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v32562; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v22563; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v12564; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v22565; VI-GISEL-NEXT: v_exp_f32_e32 v1, v12566; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f8000002567; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v22568; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f42569; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v22570; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x421a209b2571; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc2572; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v22573; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc2574; VI-GISEL-NEXT: s_setpc_b64 s[30:31]2575;2576; GFX900-SDAG-LABEL: v_exp10_f32:2577; GFX900-SDAG: ; %bb.0:2578; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2579; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x40549a78, v02580; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x40549a782581; GFX900-SDAG-NEXT: v_rndne_f32_e32 v2, v12582; GFX900-SDAG-NEXT: v_sub_f32_e32 v3, v1, v22583; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v12584; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x33979a372585; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, v12586; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v3, v12587; GFX900-SDAG-NEXT: v_exp_f32_e32 v1, v12588; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v22589; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xc23369f42590; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v02591; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x421a209b2592; GFX900-SDAG-NEXT: v_ldexp_f32 v1, v1, v22593; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc2594; GFX900-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f8000002595; GFX900-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v02596; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc2597; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]2598;2599; GFX900-GISEL-LABEL: v_exp10_f32:2600; GFX900-GISEL: ; %bb.0:2601; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2602; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x40549a782603; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549a78, v02604; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v22605; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x33979a372606; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v3, v12607; GFX900-GISEL-NEXT: v_rndne_f32_e32 v3, v22608; GFX900-GISEL-NEXT: v_sub_f32_e32 v2, v2, v32609; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v2, v12610; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v32611; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, v12612; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f8000002613; GFX900-GISEL-NEXT: v_ldexp_f32 v1, v1, v22614; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f42615; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v22616; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x421a209b2617; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc2618; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v22619; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc2620; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]2621;2622; SI-SDAG-LABEL: v_exp10_f32:2623; SI-SDAG: ; %bb.0:2624; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2625; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x40549a78, v02626; SI-SDAG-NEXT: s_mov_b32 s4, 0x40549a782627; SI-SDAG-NEXT: v_rndne_f32_e32 v2, v12628; SI-SDAG-NEXT: v_sub_f32_e32 v3, v1, v22629; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v12630; SI-SDAG-NEXT: s_mov_b32 s4, 0x33979a372631; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, v12632; SI-SDAG-NEXT: v_add_f32_e32 v1, v3, v12633; SI-SDAG-NEXT: v_exp_f32_e32 v1, v12634; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v22635; SI-SDAG-NEXT: s_mov_b32 s4, 0xc23369f42636; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v02637; SI-SDAG-NEXT: s_mov_b32 s4, 0x421a209b2638; SI-SDAG-NEXT: v_ldexp_f32_e32 v1, v1, v22639; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc2640; SI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f8000002641; SI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v02642; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc2643; SI-SDAG-NEXT: s_setpc_b64 s[30:31]2644;2645; SI-GISEL-LABEL: v_exp10_f32:2646; SI-GISEL: ; %bb.0:2647; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2648; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x40549a782649; SI-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549a78, v02650; SI-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v22651; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x33979a372652; SI-GISEL-NEXT: v_fma_f32 v1, v0, v3, v12653; SI-GISEL-NEXT: v_rndne_f32_e32 v3, v22654; SI-GISEL-NEXT: v_sub_f32_e32 v2, v2, v32655; SI-GISEL-NEXT: v_add_f32_e32 v1, v2, v12656; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v32657; SI-GISEL-NEXT: v_exp_f32_e32 v1, v12658; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f8000002659; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, v1, v22660; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f42661; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v22662; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x421a209b2663; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc2664; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v22665; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc2666; SI-GISEL-NEXT: s_setpc_b64 s[30:31]2667;2668; R600-LABEL: v_exp10_f32:2669; R600: ; %bb.0:2670; R600-NEXT: CF_END2671; R600-NEXT: PAD2672;2673; CM-LABEL: v_exp10_f32:2674; CM: ; %bb.0:2675; CM-NEXT: CF_END2676; CM-NEXT: PAD2677 %result = call float @llvm.exp10.f32(float %in)2678 ret float %result2679}2680 2681define float @v_exp10_fabs_f32(float %in) {2682; VI-SDAG-LABEL: v_exp10_fabs_f32:2683; VI-SDAG: ; %bb.0:2684; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2685; VI-SDAG-NEXT: v_and_b32_e32 v1, 0x7fffffff, v02686; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v12687; VI-SDAG-NEXT: v_sub_f32_e64 v4, |v0|, v12688; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x40549000, v12689; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x3a2784bc, v42690; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x40549000, v42691; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v22692; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v52693; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v12694; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v32695; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v42696; VI-SDAG-NEXT: v_add_f32_e32 v1, v2, v12697; VI-SDAG-NEXT: v_exp_f32_e32 v1, v12698; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v32699; VI-SDAG-NEXT: s_mov_b32 s4, 0xc23369f42700; VI-SDAG-NEXT: v_cmp_nlt_f32_e64 vcc, |v0|, s42701; VI-SDAG-NEXT: s_mov_b32 s4, 0x421a209b2702; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v22703; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc2704; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f8000002705; VI-SDAG-NEXT: v_cmp_ngt_f32_e64 vcc, |v0|, s42706; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc2707; VI-SDAG-NEXT: s_setpc_b64 s[30:31]2708;2709; VI-GISEL-LABEL: v_exp10_fabs_f32:2710; VI-GISEL: ; %bb.0:2711; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2712; VI-GISEL-NEXT: v_and_b32_e32 v1, 0x7fffffff, v02713; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v12714; VI-GISEL-NEXT: v_sub_f32_e64 v2, |v0|, v12715; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3a2784bc, v22716; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549000, v22717; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x40549000, v12718; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v42719; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v12720; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v22721; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v32722; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v22723; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v12724; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v22725; VI-GISEL-NEXT: v_exp_f32_e32 v1, v12726; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f8000002727; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v22728; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f42729; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v22730; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x421a209b2731; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[4:5]2732; VI-GISEL-NEXT: v_cmp_gt_f32_e64 vcc, |v0|, v22733; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc2734; VI-GISEL-NEXT: s_setpc_b64 s[30:31]2735;2736; GFX900-SDAG-LABEL: v_exp10_fabs_f32:2737; GFX900-SDAG: ; %bb.0:2738; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2739; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x40549a782740; GFX900-SDAG-NEXT: v_mul_f32_e64 v1, |v0|, s42741; GFX900-SDAG-NEXT: v_rndne_f32_e32 v2, v12742; GFX900-SDAG-NEXT: v_sub_f32_e32 v3, v1, v22743; GFX900-SDAG-NEXT: v_fma_f32 v1, |v0|, s4, -v12744; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x33979a372745; GFX900-SDAG-NEXT: v_fma_f32 v1, |v0|, s4, v12746; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v3, v12747; GFX900-SDAG-NEXT: v_exp_f32_e32 v1, v12748; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v22749; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xc23369f42750; GFX900-SDAG-NEXT: v_cmp_nlt_f32_e64 vcc, |v0|, s42751; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x421a209b2752; GFX900-SDAG-NEXT: v_ldexp_f32 v1, v1, v22753; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc2754; GFX900-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f8000002755; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e64 vcc, |v0|, s42756; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc2757; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]2758;2759; GFX900-GISEL-LABEL: v_exp10_fabs_f32:2760; GFX900-GISEL: ; %bb.0:2761; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2762; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x40549a782763; GFX900-GISEL-NEXT: v_mul_f32_e64 v2, |v0|, v12764; GFX900-GISEL-NEXT: v_fma_f32 v1, |v0|, v1, -v22765; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x33979a372766; GFX900-GISEL-NEXT: v_fma_f32 v1, |v0|, v3, v12767; GFX900-GISEL-NEXT: v_rndne_f32_e32 v3, v22768; GFX900-GISEL-NEXT: v_sub_f32_e32 v2, v2, v32769; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v2, v12770; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v32771; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, v12772; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f8000002773; GFX900-GISEL-NEXT: v_ldexp_f32 v1, v1, v22774; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f42775; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v22776; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x421a209b2777; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[4:5]2778; GFX900-GISEL-NEXT: v_cmp_gt_f32_e64 vcc, |v0|, v22779; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc2780; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]2781;2782; SI-SDAG-LABEL: v_exp10_fabs_f32:2783; SI-SDAG: ; %bb.0:2784; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2785; SI-SDAG-NEXT: s_mov_b32 s4, 0x40549a782786; SI-SDAG-NEXT: v_mul_f32_e64 v1, |v0|, s42787; SI-SDAG-NEXT: v_rndne_f32_e32 v2, v12788; SI-SDAG-NEXT: v_sub_f32_e32 v3, v1, v22789; SI-SDAG-NEXT: v_fma_f32 v1, |v0|, s4, -v12790; SI-SDAG-NEXT: s_mov_b32 s4, 0x33979a372791; SI-SDAG-NEXT: v_fma_f32 v1, |v0|, s4, v12792; SI-SDAG-NEXT: v_add_f32_e32 v1, v3, v12793; SI-SDAG-NEXT: v_exp_f32_e32 v1, v12794; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v22795; SI-SDAG-NEXT: s_mov_b32 s4, 0xc23369f42796; SI-SDAG-NEXT: v_cmp_nlt_f32_e64 vcc, |v0|, s42797; SI-SDAG-NEXT: s_mov_b32 s4, 0x421a209b2798; SI-SDAG-NEXT: v_ldexp_f32_e32 v1, v1, v22799; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc2800; SI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f8000002801; SI-SDAG-NEXT: v_cmp_ngt_f32_e64 vcc, |v0|, s42802; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc2803; SI-SDAG-NEXT: s_setpc_b64 s[30:31]2804;2805; SI-GISEL-LABEL: v_exp10_fabs_f32:2806; SI-GISEL: ; %bb.0:2807; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2808; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x40549a782809; SI-GISEL-NEXT: v_mul_f32_e64 v2, |v0|, v12810; SI-GISEL-NEXT: v_fma_f32 v1, |v0|, v1, -v22811; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x33979a372812; SI-GISEL-NEXT: v_fma_f32 v1, |v0|, v3, v12813; SI-GISEL-NEXT: v_rndne_f32_e32 v3, v22814; SI-GISEL-NEXT: v_sub_f32_e32 v2, v2, v32815; SI-GISEL-NEXT: v_add_f32_e32 v1, v2, v12816; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v32817; SI-GISEL-NEXT: v_exp_f32_e32 v1, v12818; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f8000002819; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, v1, v22820; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f42821; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v22822; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x421a209b2823; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[4:5]2824; SI-GISEL-NEXT: v_cmp_gt_f32_e64 vcc, |v0|, v22825; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc2826; SI-GISEL-NEXT: s_setpc_b64 s[30:31]2827;2828; R600-LABEL: v_exp10_fabs_f32:2829; R600: ; %bb.0:2830; R600-NEXT: CF_END2831; R600-NEXT: PAD2832;2833; CM-LABEL: v_exp10_fabs_f32:2834; CM: ; %bb.0:2835; CM-NEXT: CF_END2836; CM-NEXT: PAD2837 %fabs = call float @llvm.fabs.f32(float %in)2838 %result = call float @llvm.exp10.f32(float %fabs)2839 ret float %result2840}2841 2842define float @v_exp10_fneg_fabs_f32(float %in) {2843; VI-SDAG-LABEL: v_exp10_fneg_fabs_f32:2844; VI-SDAG: ; %bb.0:2845; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2846; VI-SDAG-NEXT: v_or_b32_e32 v1, 0x80000000, v02847; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v12848; VI-SDAG-NEXT: v_sub_f32_e64 v4, -|v0|, v12849; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x40549000, v12850; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x3a2784bc, v42851; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x40549000, v42852; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v22853; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v52854; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v12855; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v32856; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v42857; VI-SDAG-NEXT: v_add_f32_e32 v1, v2, v12858; VI-SDAG-NEXT: v_exp_f32_e32 v1, v12859; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v32860; VI-SDAG-NEXT: s_mov_b32 s4, 0x423369f42861; VI-SDAG-NEXT: v_cmp_ngt_f32_e64 vcc, |v0|, s42862; VI-SDAG-NEXT: s_mov_b32 s4, 0xc21a209b2863; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v22864; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc2865; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f8000002866; VI-SDAG-NEXT: v_cmp_nlt_f32_e64 vcc, |v0|, s42867; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc2868; VI-SDAG-NEXT: s_setpc_b64 s[30:31]2869;2870; VI-GISEL-LABEL: v_exp10_fneg_fabs_f32:2871; VI-GISEL: ; %bb.0:2872; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2873; VI-GISEL-NEXT: v_or_b32_e32 v1, 0x80000000, v02874; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v12875; VI-GISEL-NEXT: v_sub_f32_e64 v2, -|v0|, v12876; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3a2784bc, v22877; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549000, v22878; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x40549000, v12879; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v42880; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v12881; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v22882; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v32883; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v22884; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v12885; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v22886; VI-GISEL-NEXT: v_exp_f32_e32 v1, v12887; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f8000002888; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v22889; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f42890; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], -|v0|, v22891; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x421a209b2892; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[4:5]2893; VI-GISEL-NEXT: v_cmp_gt_f32_e64 vcc, -|v0|, v22894; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc2895; VI-GISEL-NEXT: s_setpc_b64 s[30:31]2896;2897; GFX900-SDAG-LABEL: v_exp10_fneg_fabs_f32:2898; GFX900-SDAG: ; %bb.0:2899; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2900; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xc0549a782901; GFX900-SDAG-NEXT: v_mul_f32_e64 v1, |v0|, s42902; GFX900-SDAG-NEXT: v_rndne_f32_e32 v2, v12903; GFX900-SDAG-NEXT: v_sub_f32_e32 v3, v1, v22904; GFX900-SDAG-NEXT: v_fma_f32 v1, |v0|, s4, -v12905; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xb3979a372906; GFX900-SDAG-NEXT: v_fma_f32 v1, |v0|, s4, v12907; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v3, v12908; GFX900-SDAG-NEXT: v_exp_f32_e32 v1, v12909; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v22910; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x423369f42911; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e64 vcc, |v0|, s42912; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xc21a209b2913; GFX900-SDAG-NEXT: v_ldexp_f32 v1, v1, v22914; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc2915; GFX900-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f8000002916; GFX900-SDAG-NEXT: v_cmp_nlt_f32_e64 vcc, |v0|, s42917; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc2918; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]2919;2920; GFX900-GISEL-LABEL: v_exp10_fneg_fabs_f32:2921; GFX900-GISEL: ; %bb.0:2922; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2923; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x40549a782924; GFX900-GISEL-NEXT: v_mul_f32_e64 v2, -|v0|, v12925; GFX900-GISEL-NEXT: v_fma_f32 v1, -|v0|, v1, -v22926; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x33979a372927; GFX900-GISEL-NEXT: v_fma_f32 v1, -|v0|, v3, v12928; GFX900-GISEL-NEXT: v_rndne_f32_e32 v3, v22929; GFX900-GISEL-NEXT: v_sub_f32_e32 v2, v2, v32930; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v2, v12931; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v32932; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, v12933; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f8000002934; GFX900-GISEL-NEXT: v_ldexp_f32 v1, v1, v22935; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f42936; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], -|v0|, v22937; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x421a209b2938; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[4:5]2939; GFX900-GISEL-NEXT: v_cmp_gt_f32_e64 vcc, -|v0|, v22940; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc2941; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]2942;2943; SI-SDAG-LABEL: v_exp10_fneg_fabs_f32:2944; SI-SDAG: ; %bb.0:2945; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2946; SI-SDAG-NEXT: s_mov_b32 s4, 0xc0549a782947; SI-SDAG-NEXT: v_mul_f32_e64 v1, |v0|, s42948; SI-SDAG-NEXT: v_rndne_f32_e32 v2, v12949; SI-SDAG-NEXT: v_sub_f32_e32 v3, v1, v22950; SI-SDAG-NEXT: v_fma_f32 v1, |v0|, s4, -v12951; SI-SDAG-NEXT: s_mov_b32 s4, 0xb3979a372952; SI-SDAG-NEXT: v_fma_f32 v1, |v0|, s4, v12953; SI-SDAG-NEXT: v_add_f32_e32 v1, v3, v12954; SI-SDAG-NEXT: v_exp_f32_e32 v1, v12955; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v22956; SI-SDAG-NEXT: s_mov_b32 s4, 0x423369f42957; SI-SDAG-NEXT: v_cmp_ngt_f32_e64 vcc, |v0|, s42958; SI-SDAG-NEXT: s_mov_b32 s4, 0xc21a209b2959; SI-SDAG-NEXT: v_ldexp_f32_e32 v1, v1, v22960; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc2961; SI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f8000002962; SI-SDAG-NEXT: v_cmp_nlt_f32_e64 vcc, |v0|, s42963; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc2964; SI-SDAG-NEXT: s_setpc_b64 s[30:31]2965;2966; SI-GISEL-LABEL: v_exp10_fneg_fabs_f32:2967; SI-GISEL: ; %bb.0:2968; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2969; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x40549a782970; SI-GISEL-NEXT: v_mul_f32_e64 v2, -|v0|, v12971; SI-GISEL-NEXT: v_fma_f32 v1, -|v0|, v1, -v22972; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x33979a372973; SI-GISEL-NEXT: v_fma_f32 v1, -|v0|, v3, v12974; SI-GISEL-NEXT: v_rndne_f32_e32 v3, v22975; SI-GISEL-NEXT: v_sub_f32_e32 v2, v2, v32976; SI-GISEL-NEXT: v_add_f32_e32 v1, v2, v12977; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v32978; SI-GISEL-NEXT: v_exp_f32_e32 v1, v12979; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f8000002980; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, v1, v22981; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f42982; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], -|v0|, v22983; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x421a209b2984; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[4:5]2985; SI-GISEL-NEXT: v_cmp_gt_f32_e64 vcc, -|v0|, v22986; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc2987; SI-GISEL-NEXT: s_setpc_b64 s[30:31]2988;2989; R600-LABEL: v_exp10_fneg_fabs_f32:2990; R600: ; %bb.0:2991; R600-NEXT: CF_END2992; R600-NEXT: PAD2993;2994; CM-LABEL: v_exp10_fneg_fabs_f32:2995; CM: ; %bb.0:2996; CM-NEXT: CF_END2997; CM-NEXT: PAD2998 %fabs = call float @llvm.fabs.f32(float %in)2999 %fneg.fabs = fneg float %fabs3000 %result = call float @llvm.exp10.f32(float %fneg.fabs)3001 ret float %result3002}3003 3004define float @v_exp10_fneg_f32(float %in) {3005; VI-SDAG-LABEL: v_exp10_fneg_f32:3006; VI-SDAG: ; %bb.0:3007; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3008; VI-SDAG-NEXT: v_xor_b32_e32 v1, 0x80000000, v03009; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v13010; VI-SDAG-NEXT: v_sub_f32_e64 v4, -v0, v13011; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x40549000, v13012; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x3a2784bc, v43013; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x40549000, v43014; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v23015; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v53016; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v13017; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v33018; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v43019; VI-SDAG-NEXT: v_add_f32_e32 v1, v2, v13020; VI-SDAG-NEXT: v_exp_f32_e32 v1, v13021; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v33022; VI-SDAG-NEXT: s_mov_b32 s4, 0x423369f43023; VI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v03024; VI-SDAG-NEXT: s_mov_b32 s4, 0xc21a209b3025; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v23026; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc3027; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f8000003028; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v03029; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc3030; VI-SDAG-NEXT: s_setpc_b64 s[30:31]3031;3032; VI-GISEL-LABEL: v_exp10_fneg_f32:3033; VI-GISEL: ; %bb.0:3034; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3035; VI-GISEL-NEXT: v_xor_b32_e32 v1, 0x80000000, v03036; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v13037; VI-GISEL-NEXT: v_sub_f32_e64 v2, -v0, v13038; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3a2784bc, v23039; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549000, v23040; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x40549000, v13041; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v43042; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v13043; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v23044; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v33045; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v23046; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v13047; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v23048; VI-GISEL-NEXT: v_exp_f32_e32 v1, v13049; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f8000003050; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v23051; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f43052; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], -v0, v23053; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x421a209b3054; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[4:5]3055; VI-GISEL-NEXT: v_cmp_gt_f32_e64 vcc, -v0, v23056; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc3057; VI-GISEL-NEXT: s_setpc_b64 s[30:31]3058;3059; GFX900-SDAG-LABEL: v_exp10_fneg_f32:3060; GFX900-SDAG: ; %bb.0:3061; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3062; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0xc0549a78, v03063; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xc0549a783064; GFX900-SDAG-NEXT: v_rndne_f32_e32 v2, v13065; GFX900-SDAG-NEXT: v_sub_f32_e32 v3, v1, v23066; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v13067; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xb3979a373068; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, v13069; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v3, v13070; GFX900-SDAG-NEXT: v_exp_f32_e32 v1, v13071; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v23072; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x423369f43073; GFX900-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v03074; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xc21a209b3075; GFX900-SDAG-NEXT: v_ldexp_f32 v1, v1, v23076; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc3077; GFX900-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f8000003078; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v03079; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc3080; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]3081;3082; GFX900-GISEL-LABEL: v_exp10_fneg_f32:3083; GFX900-GISEL: ; %bb.0:3084; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3085; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x40549a783086; GFX900-GISEL-NEXT: v_mul_f32_e64 v2, -v0, v13087; GFX900-GISEL-NEXT: v_fma_f32 v1, -v0, v1, -v23088; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x33979a373089; GFX900-GISEL-NEXT: v_fma_f32 v1, -v0, v3, v13090; GFX900-GISEL-NEXT: v_rndne_f32_e32 v3, v23091; GFX900-GISEL-NEXT: v_sub_f32_e32 v2, v2, v33092; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v2, v13093; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v33094; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, v13095; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f8000003096; GFX900-GISEL-NEXT: v_ldexp_f32 v1, v1, v23097; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f43098; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], -v0, v23099; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x421a209b3100; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[4:5]3101; GFX900-GISEL-NEXT: v_cmp_gt_f32_e64 vcc, -v0, v23102; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc3103; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]3104;3105; SI-SDAG-LABEL: v_exp10_fneg_f32:3106; SI-SDAG: ; %bb.0:3107; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3108; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0xc0549a78, v03109; SI-SDAG-NEXT: s_mov_b32 s4, 0xc0549a783110; SI-SDAG-NEXT: v_rndne_f32_e32 v2, v13111; SI-SDAG-NEXT: v_sub_f32_e32 v3, v1, v23112; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v13113; SI-SDAG-NEXT: s_mov_b32 s4, 0xb3979a373114; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, v13115; SI-SDAG-NEXT: v_add_f32_e32 v1, v3, v13116; SI-SDAG-NEXT: v_exp_f32_e32 v1, v13117; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v23118; SI-SDAG-NEXT: s_mov_b32 s4, 0x423369f43119; SI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v03120; SI-SDAG-NEXT: s_mov_b32 s4, 0xc21a209b3121; SI-SDAG-NEXT: v_ldexp_f32_e32 v1, v1, v23122; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc3123; SI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f8000003124; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v03125; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc3126; SI-SDAG-NEXT: s_setpc_b64 s[30:31]3127;3128; SI-GISEL-LABEL: v_exp10_fneg_f32:3129; SI-GISEL: ; %bb.0:3130; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3131; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x40549a783132; SI-GISEL-NEXT: v_mul_f32_e64 v2, -v0, v13133; SI-GISEL-NEXT: v_fma_f32 v1, -v0, v1, -v23134; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x33979a373135; SI-GISEL-NEXT: v_fma_f32 v1, -v0, v3, v13136; SI-GISEL-NEXT: v_rndne_f32_e32 v3, v23137; SI-GISEL-NEXT: v_sub_f32_e32 v2, v2, v33138; SI-GISEL-NEXT: v_add_f32_e32 v1, v2, v13139; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v33140; SI-GISEL-NEXT: v_exp_f32_e32 v1, v13141; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f8000003142; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, v1, v23143; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f43144; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], -v0, v23145; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x421a209b3146; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[4:5]3147; SI-GISEL-NEXT: v_cmp_gt_f32_e64 vcc, -v0, v23148; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc3149; SI-GISEL-NEXT: s_setpc_b64 s[30:31]3150;3151; R600-LABEL: v_exp10_fneg_f32:3152; R600: ; %bb.0:3153; R600-NEXT: CF_END3154; R600-NEXT: PAD3155;3156; CM-LABEL: v_exp10_fneg_f32:3157; CM: ; %bb.0:3158; CM-NEXT: CF_END3159; CM-NEXT: PAD3160 %fneg = fneg float %in3161 %result = call float @llvm.exp10.f32(float %fneg)3162 ret float %result3163}3164 3165define float @v_exp10_f32_fast(float %in) {3166; GCN-SDAG-LABEL: v_exp10_f32_fast:3167; GCN-SDAG: ; %bb.0:3168; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3169; GCN-SDAG-NEXT: s_mov_b32 s4, 0xc217b8183170; GCN-SDAG-NEXT: v_add_f32_e32 v1, 0x42000000, v03171; GCN-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v03172; GCN-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc3173; GCN-SDAG-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v03174; GCN-SDAG-NEXT: v_mul_f32_e32 v0, 0x40549000, v03175; GCN-SDAG-NEXT: v_exp_f32_e32 v1, v13176; GCN-SDAG-NEXT: v_exp_f32_e32 v0, v03177; GCN-SDAG-NEXT: v_mul_f32_e32 v0, v0, v13178; GCN-SDAG-NEXT: v_mul_f32_e32 v1, 0xa4fb11f, v03179; GCN-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc3180; GCN-SDAG-NEXT: s_setpc_b64 s[30:31]3181;3182; GCN-GISEL-LABEL: v_exp10_f32_fast:3183; GCN-GISEL: ; %bb.0:3184; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3185; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2aeac503186; GCN-GISEL-NEXT: v_add_f32_e32 v2, 0x42800000, v03187; GCN-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v13188; GCN-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc3189; GCN-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v03190; GCN-GISEL-NEXT: v_exp_f32_e32 v0, v03191; GCN-GISEL-NEXT: v_mul_f32_e32 v1, 0x114b4ea4, v03192; GCN-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc3193; GCN-GISEL-NEXT: s_setpc_b64 s[30:31]3194;3195; SI-SDAG-LABEL: v_exp10_f32_fast:3196; SI-SDAG: ; %bb.0:3197; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3198; SI-SDAG-NEXT: s_mov_b32 s4, 0xc217b8183199; SI-SDAG-NEXT: v_add_f32_e32 v1, 0x42000000, v03200; SI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v03201; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc3202; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v03203; SI-SDAG-NEXT: v_mul_f32_e32 v0, 0x40549000, v03204; SI-SDAG-NEXT: v_exp_f32_e32 v1, v13205; SI-SDAG-NEXT: v_exp_f32_e32 v0, v03206; SI-SDAG-NEXT: v_mul_f32_e32 v0, v0, v13207; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0xa4fb11f, v03208; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc3209; SI-SDAG-NEXT: s_setpc_b64 s[30:31]3210;3211; SI-GISEL-LABEL: v_exp10_f32_fast:3212; SI-GISEL: ; %bb.0:3213; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3214; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2aeac503215; SI-GISEL-NEXT: v_add_f32_e32 v2, 0x42800000, v03216; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v13217; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc3218; SI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v03219; SI-GISEL-NEXT: v_exp_f32_e32 v0, v03220; SI-GISEL-NEXT: v_mul_f32_e32 v1, 0x114b4ea4, v03221; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc3222; SI-GISEL-NEXT: s_setpc_b64 s[30:31]3223;3224; R600-LABEL: v_exp10_f32_fast:3225; R600: ; %bb.0:3226; R600-NEXT: CF_END3227; R600-NEXT: PAD3228;3229; CM-LABEL: v_exp10_f32_fast:3230; CM: ; %bb.0:3231; CM-NEXT: CF_END3232; CM-NEXT: PAD3233 %result = call fast float @llvm.exp10.f32(float %in)3234 ret float %result3235}3236 3237define float @v_exp10_f32_ninf(float %in) {3238; VI-SDAG-LABEL: v_exp10_f32_ninf:3239; VI-SDAG: ; %bb.0:3240; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3241; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v03242; VI-SDAG-NEXT: v_sub_f32_e32 v4, v0, v13243; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x40549000, v13244; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x3a2784bc, v43245; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x40549000, v43246; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v23247; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v53248; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v13249; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v33250; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v43251; VI-SDAG-NEXT: v_add_f32_e32 v1, v2, v13252; VI-SDAG-NEXT: v_exp_f32_e32 v1, v13253; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v33254; VI-SDAG-NEXT: s_mov_b32 s4, 0xc23369f43255; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v03256; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v23257; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc3258; VI-SDAG-NEXT: s_setpc_b64 s[30:31]3259;3260; VI-GISEL-LABEL: v_exp10_f32_ninf:3261; VI-GISEL: ; %bb.0:3262; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3263; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v03264; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v13265; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3a2784bc, v23266; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549000, v23267; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x40549000, v13268; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v43269; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v13270; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v23271; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v33272; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v23273; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v13274; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v23275; VI-GISEL-NEXT: v_exp_f32_e32 v1, v13276; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v23277; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f43278; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v23279; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc3280; VI-GISEL-NEXT: s_setpc_b64 s[30:31]3281;3282; GFX900-SDAG-LABEL: v_exp10_f32_ninf:3283; GFX900-SDAG: ; %bb.0:3284; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3285; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x40549a78, v03286; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x40549a783287; GFX900-SDAG-NEXT: v_rndne_f32_e32 v2, v13288; GFX900-SDAG-NEXT: v_sub_f32_e32 v3, v1, v23289; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v13290; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x33979a373291; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, v13292; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v3, v13293; GFX900-SDAG-NEXT: v_exp_f32_e32 v1, v13294; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v23295; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xc23369f43296; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v03297; GFX900-SDAG-NEXT: v_ldexp_f32 v1, v1, v23298; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc3299; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]3300;3301; GFX900-GISEL-LABEL: v_exp10_f32_ninf:3302; GFX900-GISEL: ; %bb.0:3303; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3304; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x40549a783305; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549a78, v03306; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v23307; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x33979a373308; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v3, v13309; GFX900-GISEL-NEXT: v_rndne_f32_e32 v3, v23310; GFX900-GISEL-NEXT: v_sub_f32_e32 v2, v2, v33311; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v2, v13312; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v33313; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, v13314; GFX900-GISEL-NEXT: v_ldexp_f32 v1, v1, v23315; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f43316; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v23317; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc3318; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]3319;3320; SI-SDAG-LABEL: v_exp10_f32_ninf:3321; SI-SDAG: ; %bb.0:3322; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3323; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x40549a78, v03324; SI-SDAG-NEXT: s_mov_b32 s4, 0x40549a783325; SI-SDAG-NEXT: v_rndne_f32_e32 v2, v13326; SI-SDAG-NEXT: v_sub_f32_e32 v3, v1, v23327; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v13328; SI-SDAG-NEXT: s_mov_b32 s4, 0x33979a373329; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, v13330; SI-SDAG-NEXT: v_add_f32_e32 v1, v3, v13331; SI-SDAG-NEXT: v_exp_f32_e32 v1, v13332; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v23333; SI-SDAG-NEXT: s_mov_b32 s4, 0xc23369f43334; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v03335; SI-SDAG-NEXT: v_ldexp_f32_e32 v1, v1, v23336; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc3337; SI-SDAG-NEXT: s_setpc_b64 s[30:31]3338;3339; SI-GISEL-LABEL: v_exp10_f32_ninf:3340; SI-GISEL: ; %bb.0:3341; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3342; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x40549a783343; SI-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549a78, v03344; SI-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v23345; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x33979a373346; SI-GISEL-NEXT: v_fma_f32 v1, v0, v3, v13347; SI-GISEL-NEXT: v_rndne_f32_e32 v3, v23348; SI-GISEL-NEXT: v_sub_f32_e32 v2, v2, v33349; SI-GISEL-NEXT: v_add_f32_e32 v1, v2, v13350; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v33351; SI-GISEL-NEXT: v_exp_f32_e32 v1, v13352; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, v1, v23353; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f43354; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v23355; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc3356; SI-GISEL-NEXT: s_setpc_b64 s[30:31]3357;3358; R600-LABEL: v_exp10_f32_ninf:3359; R600: ; %bb.0:3360; R600-NEXT: CF_END3361; R600-NEXT: PAD3362;3363; CM-LABEL: v_exp10_f32_ninf:3364; CM: ; %bb.0:3365; CM-NEXT: CF_END3366; CM-NEXT: PAD3367 %result = call ninf float @llvm.exp10.f32(float %in)3368 ret float %result3369}3370 3371define float @v_exp10_f32_afn(float %in) {3372; GCN-SDAG-LABEL: v_exp10_f32_afn:3373; GCN-SDAG: ; %bb.0:3374; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3375; GCN-SDAG-NEXT: s_mov_b32 s4, 0xc217b8183376; GCN-SDAG-NEXT: v_add_f32_e32 v1, 0x42000000, v03377; GCN-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v03378; GCN-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc3379; GCN-SDAG-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v03380; GCN-SDAG-NEXT: v_mul_f32_e32 v0, 0x40549000, v03381; GCN-SDAG-NEXT: v_exp_f32_e32 v1, v13382; GCN-SDAG-NEXT: v_exp_f32_e32 v0, v03383; GCN-SDAG-NEXT: v_mul_f32_e32 v0, v0, v13384; GCN-SDAG-NEXT: v_mul_f32_e32 v1, 0xa4fb11f, v03385; GCN-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc3386; GCN-SDAG-NEXT: s_setpc_b64 s[30:31]3387;3388; GCN-GISEL-LABEL: v_exp10_f32_afn:3389; GCN-GISEL: ; %bb.0:3390; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3391; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2aeac503392; GCN-GISEL-NEXT: v_add_f32_e32 v2, 0x42800000, v03393; GCN-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v13394; GCN-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc3395; GCN-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v03396; GCN-GISEL-NEXT: v_exp_f32_e32 v0, v03397; GCN-GISEL-NEXT: v_mul_f32_e32 v1, 0x114b4ea4, v03398; GCN-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc3399; GCN-GISEL-NEXT: s_setpc_b64 s[30:31]3400;3401; SI-SDAG-LABEL: v_exp10_f32_afn:3402; SI-SDAG: ; %bb.0:3403; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3404; SI-SDAG-NEXT: s_mov_b32 s4, 0xc217b8183405; SI-SDAG-NEXT: v_add_f32_e32 v1, 0x42000000, v03406; SI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v03407; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc3408; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v03409; SI-SDAG-NEXT: v_mul_f32_e32 v0, 0x40549000, v03410; SI-SDAG-NEXT: v_exp_f32_e32 v1, v13411; SI-SDAG-NEXT: v_exp_f32_e32 v0, v03412; SI-SDAG-NEXT: v_mul_f32_e32 v0, v0, v13413; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0xa4fb11f, v03414; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc3415; SI-SDAG-NEXT: s_setpc_b64 s[30:31]3416;3417; SI-GISEL-LABEL: v_exp10_f32_afn:3418; SI-GISEL: ; %bb.0:3419; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3420; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2aeac503421; SI-GISEL-NEXT: v_add_f32_e32 v2, 0x42800000, v03422; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v13423; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc3424; SI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v03425; SI-GISEL-NEXT: v_exp_f32_e32 v0, v03426; SI-GISEL-NEXT: v_mul_f32_e32 v1, 0x114b4ea4, v03427; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc3428; SI-GISEL-NEXT: s_setpc_b64 s[30:31]3429;3430; R600-LABEL: v_exp10_f32_afn:3431; R600: ; %bb.0:3432; R600-NEXT: CF_END3433; R600-NEXT: PAD3434;3435; CM-LABEL: v_exp10_f32_afn:3436; CM: ; %bb.0:3437; CM-NEXT: CF_END3438; CM-NEXT: PAD3439 %result = call afn float @llvm.exp10.f32(float %in)3440 ret float %result3441}3442 3443define float @v_exp10_f32_afn_daz(float %in) #0 {3444; GCN-SDAG-LABEL: v_exp10_f32_afn_daz:3445; GCN-SDAG: ; %bb.0:3446; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3447; GCN-SDAG-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v03448; GCN-SDAG-NEXT: v_mul_f32_e32 v0, 0x40549000, v03449; GCN-SDAG-NEXT: v_exp_f32_e32 v1, v13450; GCN-SDAG-NEXT: v_exp_f32_e32 v0, v03451; GCN-SDAG-NEXT: v_mul_f32_e32 v0, v0, v13452; GCN-SDAG-NEXT: s_setpc_b64 s[30:31]3453;3454; GCN-GISEL-LABEL: v_exp10_f32_afn_daz:3455; GCN-GISEL: ; %bb.0:3456; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3457; GCN-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v03458; GCN-GISEL-NEXT: v_exp_f32_e32 v0, v03459; GCN-GISEL-NEXT: s_setpc_b64 s[30:31]3460;3461; SI-SDAG-LABEL: v_exp10_f32_afn_daz:3462; SI-SDAG: ; %bb.0:3463; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3464; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v03465; SI-SDAG-NEXT: v_mul_f32_e32 v0, 0x40549000, v03466; SI-SDAG-NEXT: v_exp_f32_e32 v1, v13467; SI-SDAG-NEXT: v_exp_f32_e32 v0, v03468; SI-SDAG-NEXT: v_mul_f32_e32 v0, v0, v13469; SI-SDAG-NEXT: s_setpc_b64 s[30:31]3470;3471; SI-GISEL-LABEL: v_exp10_f32_afn_daz:3472; SI-GISEL: ; %bb.0:3473; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3474; SI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v03475; SI-GISEL-NEXT: v_exp_f32_e32 v0, v03476; SI-GISEL-NEXT: s_setpc_b64 s[30:31]3477;3478; R600-LABEL: v_exp10_f32_afn_daz:3479; R600: ; %bb.0:3480; R600-NEXT: CF_END3481; R600-NEXT: PAD3482;3483; CM-LABEL: v_exp10_f32_afn_daz:3484; CM: ; %bb.0:3485; CM-NEXT: CF_END3486; CM-NEXT: PAD3487 %result = call afn float @llvm.exp10.f32(float %in)3488 ret float %result3489}3490 3491define float @v_exp10_f32_afn_dynamic(float %in) #1 {3492; GCN-SDAG-LABEL: v_exp10_f32_afn_dynamic:3493; GCN-SDAG: ; %bb.0:3494; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3495; GCN-SDAG-NEXT: s_mov_b32 s4, 0xc217b8183496; GCN-SDAG-NEXT: v_add_f32_e32 v1, 0x42000000, v03497; GCN-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v03498; GCN-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc3499; GCN-SDAG-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v03500; GCN-SDAG-NEXT: v_mul_f32_e32 v0, 0x40549000, v03501; GCN-SDAG-NEXT: v_exp_f32_e32 v1, v13502; GCN-SDAG-NEXT: v_exp_f32_e32 v0, v03503; GCN-SDAG-NEXT: v_mul_f32_e32 v0, v0, v13504; GCN-SDAG-NEXT: v_mul_f32_e32 v1, 0xa4fb11f, v03505; GCN-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc3506; GCN-SDAG-NEXT: s_setpc_b64 s[30:31]3507;3508; GCN-GISEL-LABEL: v_exp10_f32_afn_dynamic:3509; GCN-GISEL: ; %bb.0:3510; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3511; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2aeac503512; GCN-GISEL-NEXT: v_add_f32_e32 v2, 0x42800000, v03513; GCN-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v13514; GCN-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc3515; GCN-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v03516; GCN-GISEL-NEXT: v_exp_f32_e32 v0, v03517; GCN-GISEL-NEXT: v_mul_f32_e32 v1, 0x114b4ea4, v03518; GCN-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc3519; GCN-GISEL-NEXT: s_setpc_b64 s[30:31]3520;3521; SI-SDAG-LABEL: v_exp10_f32_afn_dynamic:3522; SI-SDAG: ; %bb.0:3523; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3524; SI-SDAG-NEXT: s_mov_b32 s4, 0xc217b8183525; SI-SDAG-NEXT: v_add_f32_e32 v1, 0x42000000, v03526; SI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v03527; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc3528; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v03529; SI-SDAG-NEXT: v_mul_f32_e32 v0, 0x40549000, v03530; SI-SDAG-NEXT: v_exp_f32_e32 v1, v13531; SI-SDAG-NEXT: v_exp_f32_e32 v0, v03532; SI-SDAG-NEXT: v_mul_f32_e32 v0, v0, v13533; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0xa4fb11f, v03534; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc3535; SI-SDAG-NEXT: s_setpc_b64 s[30:31]3536;3537; SI-GISEL-LABEL: v_exp10_f32_afn_dynamic:3538; SI-GISEL: ; %bb.0:3539; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3540; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2aeac503541; SI-GISEL-NEXT: v_add_f32_e32 v2, 0x42800000, v03542; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v13543; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc3544; SI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v03545; SI-GISEL-NEXT: v_exp_f32_e32 v0, v03546; SI-GISEL-NEXT: v_mul_f32_e32 v1, 0x114b4ea4, v03547; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc3548; SI-GISEL-NEXT: s_setpc_b64 s[30:31]3549;3550; R600-LABEL: v_exp10_f32_afn_dynamic:3551; R600: ; %bb.0:3552; R600-NEXT: CF_END3553; R600-NEXT: PAD3554;3555; CM-LABEL: v_exp10_f32_afn_dynamic:3556; CM: ; %bb.0:3557; CM-NEXT: CF_END3558; CM-NEXT: PAD3559 %result = call afn float @llvm.exp10.f32(float %in)3560 ret float %result3561}3562 3563define float @v_fabs_exp10_f32_afn(float %in) {3564; GCN-SDAG-LABEL: v_fabs_exp10_f32_afn:3565; GCN-SDAG: ; %bb.0:3566; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3567; GCN-SDAG-NEXT: s_mov_b32 s4, 0xc217b8183568; GCN-SDAG-NEXT: s_mov_b32 s5, 0x420000003569; GCN-SDAG-NEXT: v_add_f32_e64 v1, |v0|, s53570; GCN-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s43571; GCN-SDAG-NEXT: v_cndmask_b32_e64 v0, |v0|, v1, vcc3572; GCN-SDAG-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v03573; GCN-SDAG-NEXT: v_mul_f32_e32 v0, 0x40549000, v03574; GCN-SDAG-NEXT: v_exp_f32_e32 v1, v13575; GCN-SDAG-NEXT: v_exp_f32_e32 v0, v03576; GCN-SDAG-NEXT: v_mul_f32_e32 v0, v0, v13577; GCN-SDAG-NEXT: v_mul_f32_e32 v1, 0xa4fb11f, v03578; GCN-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc3579; GCN-SDAG-NEXT: s_setpc_b64 s[30:31]3580;3581; GCN-GISEL-LABEL: v_fabs_exp10_f32_afn:3582; GCN-GISEL: ; %bb.0:3583; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3584; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2aeac503585; GCN-GISEL-NEXT: v_mov_b32_e32 v2, 0x428000003586; GCN-GISEL-NEXT: v_add_f32_e64 v2, |v0|, v23587; GCN-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v13588; GCN-GISEL-NEXT: v_cndmask_b32_e64 v0, |v0|, v2, vcc3589; GCN-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v03590; GCN-GISEL-NEXT: v_exp_f32_e32 v0, v03591; GCN-GISEL-NEXT: v_mul_f32_e32 v1, 0x114b4ea4, v03592; GCN-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc3593; GCN-GISEL-NEXT: s_setpc_b64 s[30:31]3594;3595; SI-SDAG-LABEL: v_fabs_exp10_f32_afn:3596; SI-SDAG: ; %bb.0:3597; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3598; SI-SDAG-NEXT: s_mov_b32 s4, 0xc217b8183599; SI-SDAG-NEXT: s_mov_b32 s5, 0x420000003600; SI-SDAG-NEXT: v_add_f32_e64 v1, |v0|, s53601; SI-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s43602; SI-SDAG-NEXT: v_cndmask_b32_e64 v0, |v0|, v1, vcc3603; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v03604; SI-SDAG-NEXT: v_mul_f32_e32 v0, 0x40549000, v03605; SI-SDAG-NEXT: v_exp_f32_e32 v1, v13606; SI-SDAG-NEXT: v_exp_f32_e32 v0, v03607; SI-SDAG-NEXT: v_mul_f32_e32 v0, v0, v13608; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0xa4fb11f, v03609; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc3610; SI-SDAG-NEXT: s_setpc_b64 s[30:31]3611;3612; SI-GISEL-LABEL: v_fabs_exp10_f32_afn:3613; SI-GISEL: ; %bb.0:3614; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3615; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2aeac503616; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x428000003617; SI-GISEL-NEXT: v_add_f32_e64 v2, |v0|, v23618; SI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v13619; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, |v0|, v2, vcc3620; SI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v03621; SI-GISEL-NEXT: v_exp_f32_e32 v0, v03622; SI-GISEL-NEXT: v_mul_f32_e32 v1, 0x114b4ea4, v03623; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc3624; SI-GISEL-NEXT: s_setpc_b64 s[30:31]3625;3626; R600-LABEL: v_fabs_exp10_f32_afn:3627; R600: ; %bb.0:3628; R600-NEXT: CF_END3629; R600-NEXT: PAD3630;3631; CM-LABEL: v_fabs_exp10_f32_afn:3632; CM: ; %bb.0:3633; CM-NEXT: CF_END3634; CM-NEXT: PAD3635 %fabs = call float @llvm.fabs.f32(float %in)3636 %result = call afn float @llvm.exp10.f32(float %fabs)3637 ret float %result3638}3639 3640define float @v_exp10_f32_daz(float %in) #0 {3641; VI-SDAG-LABEL: v_exp10_f32_daz:3642; VI-SDAG: ; %bb.0:3643; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3644; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v03645; VI-SDAG-NEXT: v_sub_f32_e32 v4, v0, v13646; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x40549000, v13647; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x3a2784bc, v43648; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x40549000, v43649; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v23650; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v53651; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v13652; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v33653; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v43654; VI-SDAG-NEXT: v_add_f32_e32 v1, v2, v13655; VI-SDAG-NEXT: v_exp_f32_e32 v1, v13656; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v33657; VI-SDAG-NEXT: s_mov_b32 s4, 0xc23369f43658; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v03659; VI-SDAG-NEXT: s_mov_b32 s4, 0x421a209b3660; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v23661; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc3662; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f8000003663; VI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v03664; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc3665; VI-SDAG-NEXT: s_setpc_b64 s[30:31]3666;3667; VI-GISEL-LABEL: v_exp10_f32_daz:3668; VI-GISEL: ; %bb.0:3669; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3670; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v03671; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v13672; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3a2784bc, v23673; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549000, v23674; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x40549000, v13675; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v43676; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v13677; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v23678; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v33679; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v23680; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v13681; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v23682; VI-GISEL-NEXT: v_exp_f32_e32 v1, v13683; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f8000003684; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v23685; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f43686; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v23687; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x421a209b3688; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc3689; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v23690; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc3691; VI-GISEL-NEXT: s_setpc_b64 s[30:31]3692;3693; GFX900-SDAG-LABEL: v_exp10_f32_daz:3694; GFX900-SDAG: ; %bb.0:3695; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3696; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x40549a78, v03697; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x40549a783698; GFX900-SDAG-NEXT: v_rndne_f32_e32 v2, v13699; GFX900-SDAG-NEXT: v_sub_f32_e32 v3, v1, v23700; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v13701; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x33979a373702; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, v13703; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v3, v13704; GFX900-SDAG-NEXT: v_exp_f32_e32 v1, v13705; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v23706; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xc23369f43707; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v03708; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x421a209b3709; GFX900-SDAG-NEXT: v_ldexp_f32 v1, v1, v23710; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc3711; GFX900-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f8000003712; GFX900-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v03713; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc3714; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]3715;3716; GFX900-GISEL-LABEL: v_exp10_f32_daz:3717; GFX900-GISEL: ; %bb.0:3718; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3719; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x40549a783720; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549a78, v03721; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v23722; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x33979a373723; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v3, v13724; GFX900-GISEL-NEXT: v_rndne_f32_e32 v3, v23725; GFX900-GISEL-NEXT: v_sub_f32_e32 v2, v2, v33726; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v2, v13727; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v33728; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, v13729; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f8000003730; GFX900-GISEL-NEXT: v_ldexp_f32 v1, v1, v23731; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f43732; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v23733; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x421a209b3734; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc3735; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v23736; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc3737; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]3738;3739; SI-SDAG-LABEL: v_exp10_f32_daz:3740; SI-SDAG: ; %bb.0:3741; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3742; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x40549a78, v03743; SI-SDAG-NEXT: s_mov_b32 s4, 0x40549a783744; SI-SDAG-NEXT: v_rndne_f32_e32 v2, v13745; SI-SDAG-NEXT: v_sub_f32_e32 v3, v1, v23746; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v13747; SI-SDAG-NEXT: s_mov_b32 s4, 0x33979a373748; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, v13749; SI-SDAG-NEXT: v_add_f32_e32 v1, v3, v13750; SI-SDAG-NEXT: v_exp_f32_e32 v1, v13751; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v23752; SI-SDAG-NEXT: s_mov_b32 s4, 0xc23369f43753; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v03754; SI-SDAG-NEXT: s_mov_b32 s4, 0x421a209b3755; SI-SDAG-NEXT: v_ldexp_f32_e32 v1, v1, v23756; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc3757; SI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f8000003758; SI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v03759; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc3760; SI-SDAG-NEXT: s_setpc_b64 s[30:31]3761;3762; SI-GISEL-LABEL: v_exp10_f32_daz:3763; SI-GISEL: ; %bb.0:3764; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3765; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x40549a783766; SI-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549a78, v03767; SI-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v23768; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x33979a373769; SI-GISEL-NEXT: v_fma_f32 v1, v0, v3, v13770; SI-GISEL-NEXT: v_rndne_f32_e32 v3, v23771; SI-GISEL-NEXT: v_sub_f32_e32 v2, v2, v33772; SI-GISEL-NEXT: v_add_f32_e32 v1, v2, v13773; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v33774; SI-GISEL-NEXT: v_exp_f32_e32 v1, v13775; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f8000003776; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, v1, v23777; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f43778; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v23779; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x421a209b3780; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc3781; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v23782; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc3783; SI-GISEL-NEXT: s_setpc_b64 s[30:31]3784;3785; R600-LABEL: v_exp10_f32_daz:3786; R600: ; %bb.0:3787; R600-NEXT: CF_END3788; R600-NEXT: PAD3789;3790; CM-LABEL: v_exp10_f32_daz:3791; CM: ; %bb.0:3792; CM-NEXT: CF_END3793; CM-NEXT: PAD3794 %result = call float @llvm.exp10.f32(float %in)3795 ret float %result3796}3797 3798define float @v_exp10_f32_nnan(float %in) {3799; VI-SDAG-LABEL: v_exp10_f32_nnan:3800; VI-SDAG: ; %bb.0:3801; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3802; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v03803; VI-SDAG-NEXT: v_sub_f32_e32 v4, v0, v13804; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x40549000, v13805; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x3a2784bc, v43806; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x40549000, v43807; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v23808; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v53809; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v13810; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v33811; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v43812; VI-SDAG-NEXT: v_add_f32_e32 v1, v2, v13813; VI-SDAG-NEXT: v_exp_f32_e32 v1, v13814; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v33815; VI-SDAG-NEXT: s_mov_b32 s4, 0xc23369f43816; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v03817; VI-SDAG-NEXT: s_mov_b32 s4, 0x421a209b3818; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v23819; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc3820; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f8000003821; VI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v03822; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc3823; VI-SDAG-NEXT: s_setpc_b64 s[30:31]3824;3825; VI-GISEL-LABEL: v_exp10_f32_nnan:3826; VI-GISEL: ; %bb.0:3827; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3828; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v03829; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v13830; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3a2784bc, v23831; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549000, v23832; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x40549000, v13833; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v43834; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v13835; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v23836; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v33837; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v23838; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v13839; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v23840; VI-GISEL-NEXT: v_exp_f32_e32 v1, v13841; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f8000003842; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v23843; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f43844; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v23845; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x421a209b3846; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc3847; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v23848; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc3849; VI-GISEL-NEXT: s_setpc_b64 s[30:31]3850;3851; GFX900-SDAG-LABEL: v_exp10_f32_nnan:3852; GFX900-SDAG: ; %bb.0:3853; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3854; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x40549a78, v03855; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x40549a783856; GFX900-SDAG-NEXT: v_rndne_f32_e32 v2, v13857; GFX900-SDAG-NEXT: v_sub_f32_e32 v3, v1, v23858; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v13859; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x33979a373860; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, v13861; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v3, v13862; GFX900-SDAG-NEXT: v_exp_f32_e32 v1, v13863; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v23864; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xc23369f43865; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v03866; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x421a209b3867; GFX900-SDAG-NEXT: v_ldexp_f32 v1, v1, v23868; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc3869; GFX900-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f8000003870; GFX900-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v03871; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc3872; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]3873;3874; GFX900-GISEL-LABEL: v_exp10_f32_nnan:3875; GFX900-GISEL: ; %bb.0:3876; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3877; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x40549a783878; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549a78, v03879; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v23880; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x33979a373881; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v3, v13882; GFX900-GISEL-NEXT: v_rndne_f32_e32 v3, v23883; GFX900-GISEL-NEXT: v_sub_f32_e32 v2, v2, v33884; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v2, v13885; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v33886; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, v13887; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f8000003888; GFX900-GISEL-NEXT: v_ldexp_f32 v1, v1, v23889; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f43890; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v23891; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x421a209b3892; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc3893; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v23894; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc3895; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]3896;3897; SI-SDAG-LABEL: v_exp10_f32_nnan:3898; SI-SDAG: ; %bb.0:3899; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3900; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x40549a78, v03901; SI-SDAG-NEXT: s_mov_b32 s4, 0x40549a783902; SI-SDAG-NEXT: v_rndne_f32_e32 v2, v13903; SI-SDAG-NEXT: v_sub_f32_e32 v3, v1, v23904; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v13905; SI-SDAG-NEXT: s_mov_b32 s4, 0x33979a373906; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, v13907; SI-SDAG-NEXT: v_add_f32_e32 v1, v3, v13908; SI-SDAG-NEXT: v_exp_f32_e32 v1, v13909; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v23910; SI-SDAG-NEXT: s_mov_b32 s4, 0xc23369f43911; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v03912; SI-SDAG-NEXT: s_mov_b32 s4, 0x421a209b3913; SI-SDAG-NEXT: v_ldexp_f32_e32 v1, v1, v23914; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc3915; SI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f8000003916; SI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v03917; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc3918; SI-SDAG-NEXT: s_setpc_b64 s[30:31]3919;3920; SI-GISEL-LABEL: v_exp10_f32_nnan:3921; SI-GISEL: ; %bb.0:3922; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3923; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x40549a783924; SI-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549a78, v03925; SI-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v23926; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x33979a373927; SI-GISEL-NEXT: v_fma_f32 v1, v0, v3, v13928; SI-GISEL-NEXT: v_rndne_f32_e32 v3, v23929; SI-GISEL-NEXT: v_sub_f32_e32 v2, v2, v33930; SI-GISEL-NEXT: v_add_f32_e32 v1, v2, v13931; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v33932; SI-GISEL-NEXT: v_exp_f32_e32 v1, v13933; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f8000003934; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, v1, v23935; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f43936; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v23937; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x421a209b3938; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc3939; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v23940; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc3941; SI-GISEL-NEXT: s_setpc_b64 s[30:31]3942;3943; R600-LABEL: v_exp10_f32_nnan:3944; R600: ; %bb.0:3945; R600-NEXT: CF_END3946; R600-NEXT: PAD3947;3948; CM-LABEL: v_exp10_f32_nnan:3949; CM: ; %bb.0:3950; CM-NEXT: CF_END3951; CM-NEXT: PAD3952 %result = call nnan float @llvm.exp10.f32(float %in)3953 ret float %result3954}3955 3956define float @v_exp10_f32_nnan_daz(float %in) #0 {3957; VI-SDAG-LABEL: v_exp10_f32_nnan_daz:3958; VI-SDAG: ; %bb.0:3959; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3960; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v03961; VI-SDAG-NEXT: v_sub_f32_e32 v4, v0, v13962; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x40549000, v13963; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x3a2784bc, v43964; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x40549000, v43965; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v23966; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v53967; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v13968; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v33969; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v43970; VI-SDAG-NEXT: v_add_f32_e32 v1, v2, v13971; VI-SDAG-NEXT: v_exp_f32_e32 v1, v13972; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v33973; VI-SDAG-NEXT: s_mov_b32 s4, 0xc23369f43974; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v03975; VI-SDAG-NEXT: s_mov_b32 s4, 0x421a209b3976; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v23977; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc3978; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f8000003979; VI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v03980; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc3981; VI-SDAG-NEXT: s_setpc_b64 s[30:31]3982;3983; VI-GISEL-LABEL: v_exp10_f32_nnan_daz:3984; VI-GISEL: ; %bb.0:3985; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3986; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v03987; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v13988; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3a2784bc, v23989; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549000, v23990; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x40549000, v13991; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v43992; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v13993; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v23994; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v33995; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v23996; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v13997; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v23998; VI-GISEL-NEXT: v_exp_f32_e32 v1, v13999; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f8000004000; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v24001; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f44002; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v24003; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x421a209b4004; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc4005; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v24006; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc4007; VI-GISEL-NEXT: s_setpc_b64 s[30:31]4008;4009; GFX900-SDAG-LABEL: v_exp10_f32_nnan_daz:4010; GFX900-SDAG: ; %bb.0:4011; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4012; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x40549a78, v04013; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x40549a784014; GFX900-SDAG-NEXT: v_rndne_f32_e32 v2, v14015; GFX900-SDAG-NEXT: v_sub_f32_e32 v3, v1, v24016; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v14017; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x33979a374018; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, v14019; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v3, v14020; GFX900-SDAG-NEXT: v_exp_f32_e32 v1, v14021; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v24022; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xc23369f44023; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v04024; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x421a209b4025; GFX900-SDAG-NEXT: v_ldexp_f32 v1, v1, v24026; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc4027; GFX900-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f8000004028; GFX900-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v04029; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc4030; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]4031;4032; GFX900-GISEL-LABEL: v_exp10_f32_nnan_daz:4033; GFX900-GISEL: ; %bb.0:4034; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4035; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x40549a784036; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549a78, v04037; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v24038; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x33979a374039; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v3, v14040; GFX900-GISEL-NEXT: v_rndne_f32_e32 v3, v24041; GFX900-GISEL-NEXT: v_sub_f32_e32 v2, v2, v34042; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v2, v14043; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v34044; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, v14045; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f8000004046; GFX900-GISEL-NEXT: v_ldexp_f32 v1, v1, v24047; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f44048; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v24049; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x421a209b4050; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc4051; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v24052; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc4053; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]4054;4055; SI-SDAG-LABEL: v_exp10_f32_nnan_daz:4056; SI-SDAG: ; %bb.0:4057; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4058; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x40549a78, v04059; SI-SDAG-NEXT: s_mov_b32 s4, 0x40549a784060; SI-SDAG-NEXT: v_rndne_f32_e32 v2, v14061; SI-SDAG-NEXT: v_sub_f32_e32 v3, v1, v24062; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v14063; SI-SDAG-NEXT: s_mov_b32 s4, 0x33979a374064; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, v14065; SI-SDAG-NEXT: v_add_f32_e32 v1, v3, v14066; SI-SDAG-NEXT: v_exp_f32_e32 v1, v14067; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v24068; SI-SDAG-NEXT: s_mov_b32 s4, 0xc23369f44069; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v04070; SI-SDAG-NEXT: s_mov_b32 s4, 0x421a209b4071; SI-SDAG-NEXT: v_ldexp_f32_e32 v1, v1, v24072; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc4073; SI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f8000004074; SI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v04075; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc4076; SI-SDAG-NEXT: s_setpc_b64 s[30:31]4077;4078; SI-GISEL-LABEL: v_exp10_f32_nnan_daz:4079; SI-GISEL: ; %bb.0:4080; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4081; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x40549a784082; SI-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549a78, v04083; SI-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v24084; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x33979a374085; SI-GISEL-NEXT: v_fma_f32 v1, v0, v3, v14086; SI-GISEL-NEXT: v_rndne_f32_e32 v3, v24087; SI-GISEL-NEXT: v_sub_f32_e32 v2, v2, v34088; SI-GISEL-NEXT: v_add_f32_e32 v1, v2, v14089; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v34090; SI-GISEL-NEXT: v_exp_f32_e32 v1, v14091; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f8000004092; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, v1, v24093; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f44094; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v24095; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x421a209b4096; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc4097; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v24098; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc4099; SI-GISEL-NEXT: s_setpc_b64 s[30:31]4100;4101; R600-LABEL: v_exp10_f32_nnan_daz:4102; R600: ; %bb.0:4103; R600-NEXT: CF_END4104; R600-NEXT: PAD4105;4106; CM-LABEL: v_exp10_f32_nnan_daz:4107; CM: ; %bb.0:4108; CM-NEXT: CF_END4109; CM-NEXT: PAD4110 %result = call nnan float @llvm.exp10.f32(float %in)4111 ret float %result4112}4113 4114define float @v_exp10_f32_nnan_dynamic(float %in) #1 {4115; VI-SDAG-LABEL: v_exp10_f32_nnan_dynamic:4116; VI-SDAG: ; %bb.0:4117; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4118; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v04119; VI-SDAG-NEXT: v_sub_f32_e32 v4, v0, v14120; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x40549000, v14121; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x3a2784bc, v44122; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x40549000, v44123; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v24124; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v54125; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v14126; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v34127; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v44128; VI-SDAG-NEXT: v_add_f32_e32 v1, v2, v14129; VI-SDAG-NEXT: v_exp_f32_e32 v1, v14130; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v34131; VI-SDAG-NEXT: s_mov_b32 s4, 0xc23369f44132; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v04133; VI-SDAG-NEXT: s_mov_b32 s4, 0x421a209b4134; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v24135; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc4136; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f8000004137; VI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v04138; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc4139; VI-SDAG-NEXT: s_setpc_b64 s[30:31]4140;4141; VI-GISEL-LABEL: v_exp10_f32_nnan_dynamic:4142; VI-GISEL: ; %bb.0:4143; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4144; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v04145; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v14146; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3a2784bc, v24147; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549000, v24148; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x40549000, v14149; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v44150; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v14151; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v24152; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v34153; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v24154; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v14155; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v24156; VI-GISEL-NEXT: v_exp_f32_e32 v1, v14157; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f8000004158; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v24159; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f44160; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v24161; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x421a209b4162; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc4163; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v24164; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc4165; VI-GISEL-NEXT: s_setpc_b64 s[30:31]4166;4167; GFX900-SDAG-LABEL: v_exp10_f32_nnan_dynamic:4168; GFX900-SDAG: ; %bb.0:4169; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4170; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x40549a78, v04171; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x40549a784172; GFX900-SDAG-NEXT: v_rndne_f32_e32 v2, v14173; GFX900-SDAG-NEXT: v_sub_f32_e32 v3, v1, v24174; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v14175; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x33979a374176; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, v14177; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v3, v14178; GFX900-SDAG-NEXT: v_exp_f32_e32 v1, v14179; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v24180; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xc23369f44181; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v04182; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x421a209b4183; GFX900-SDAG-NEXT: v_ldexp_f32 v1, v1, v24184; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc4185; GFX900-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f8000004186; GFX900-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v04187; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc4188; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]4189;4190; GFX900-GISEL-LABEL: v_exp10_f32_nnan_dynamic:4191; GFX900-GISEL: ; %bb.0:4192; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4193; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x40549a784194; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549a78, v04195; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v24196; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x33979a374197; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v3, v14198; GFX900-GISEL-NEXT: v_rndne_f32_e32 v3, v24199; GFX900-GISEL-NEXT: v_sub_f32_e32 v2, v2, v34200; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v2, v14201; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v34202; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, v14203; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f8000004204; GFX900-GISEL-NEXT: v_ldexp_f32 v1, v1, v24205; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f44206; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v24207; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x421a209b4208; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc4209; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v24210; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc4211; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]4212;4213; SI-SDAG-LABEL: v_exp10_f32_nnan_dynamic:4214; SI-SDAG: ; %bb.0:4215; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4216; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x40549a78, v04217; SI-SDAG-NEXT: s_mov_b32 s4, 0x40549a784218; SI-SDAG-NEXT: v_rndne_f32_e32 v2, v14219; SI-SDAG-NEXT: v_sub_f32_e32 v3, v1, v24220; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v14221; SI-SDAG-NEXT: s_mov_b32 s4, 0x33979a374222; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, v14223; SI-SDAG-NEXT: v_add_f32_e32 v1, v3, v14224; SI-SDAG-NEXT: v_exp_f32_e32 v1, v14225; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v24226; SI-SDAG-NEXT: s_mov_b32 s4, 0xc23369f44227; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v04228; SI-SDAG-NEXT: s_mov_b32 s4, 0x421a209b4229; SI-SDAG-NEXT: v_ldexp_f32_e32 v1, v1, v24230; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc4231; SI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f8000004232; SI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v04233; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc4234; SI-SDAG-NEXT: s_setpc_b64 s[30:31]4235;4236; SI-GISEL-LABEL: v_exp10_f32_nnan_dynamic:4237; SI-GISEL: ; %bb.0:4238; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4239; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x40549a784240; SI-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549a78, v04241; SI-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v24242; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x33979a374243; SI-GISEL-NEXT: v_fma_f32 v1, v0, v3, v14244; SI-GISEL-NEXT: v_rndne_f32_e32 v3, v24245; SI-GISEL-NEXT: v_sub_f32_e32 v2, v2, v34246; SI-GISEL-NEXT: v_add_f32_e32 v1, v2, v14247; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v34248; SI-GISEL-NEXT: v_exp_f32_e32 v1, v14249; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f8000004250; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, v1, v24251; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f44252; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v24253; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x421a209b4254; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc4255; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v24256; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc4257; SI-GISEL-NEXT: s_setpc_b64 s[30:31]4258;4259; R600-LABEL: v_exp10_f32_nnan_dynamic:4260; R600: ; %bb.0:4261; R600-NEXT: CF_END4262; R600-NEXT: PAD4263;4264; CM-LABEL: v_exp10_f32_nnan_dynamic:4265; CM: ; %bb.0:4266; CM-NEXT: CF_END4267; CM-NEXT: PAD4268 %result = call nnan float @llvm.exp10.f32(float %in)4269 ret float %result4270}4271 4272define float @v_exp10_f32_ninf_daz(float %in) #0 {4273; VI-SDAG-LABEL: v_exp10_f32_ninf_daz:4274; VI-SDAG: ; %bb.0:4275; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4276; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v04277; VI-SDAG-NEXT: v_sub_f32_e32 v4, v0, v14278; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x40549000, v14279; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x3a2784bc, v44280; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x40549000, v44281; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v24282; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v54283; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v14284; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v34285; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v44286; VI-SDAG-NEXT: v_add_f32_e32 v1, v2, v14287; VI-SDAG-NEXT: v_exp_f32_e32 v1, v14288; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v34289; VI-SDAG-NEXT: s_mov_b32 s4, 0xc23369f44290; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v04291; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v24292; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc4293; VI-SDAG-NEXT: s_setpc_b64 s[30:31]4294;4295; VI-GISEL-LABEL: v_exp10_f32_ninf_daz:4296; VI-GISEL: ; %bb.0:4297; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4298; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v04299; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v14300; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3a2784bc, v24301; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549000, v24302; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x40549000, v14303; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v44304; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v14305; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v24306; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v34307; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v24308; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v14309; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v24310; VI-GISEL-NEXT: v_exp_f32_e32 v1, v14311; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v24312; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f44313; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v24314; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc4315; VI-GISEL-NEXT: s_setpc_b64 s[30:31]4316;4317; GFX900-SDAG-LABEL: v_exp10_f32_ninf_daz:4318; GFX900-SDAG: ; %bb.0:4319; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4320; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x40549a78, v04321; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x40549a784322; GFX900-SDAG-NEXT: v_rndne_f32_e32 v2, v14323; GFX900-SDAG-NEXT: v_sub_f32_e32 v3, v1, v24324; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v14325; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x33979a374326; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, v14327; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v3, v14328; GFX900-SDAG-NEXT: v_exp_f32_e32 v1, v14329; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v24330; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xc23369f44331; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v04332; GFX900-SDAG-NEXT: v_ldexp_f32 v1, v1, v24333; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc4334; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]4335;4336; GFX900-GISEL-LABEL: v_exp10_f32_ninf_daz:4337; GFX900-GISEL: ; %bb.0:4338; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4339; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x40549a784340; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549a78, v04341; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v24342; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x33979a374343; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v3, v14344; GFX900-GISEL-NEXT: v_rndne_f32_e32 v3, v24345; GFX900-GISEL-NEXT: v_sub_f32_e32 v2, v2, v34346; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v2, v14347; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v34348; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, v14349; GFX900-GISEL-NEXT: v_ldexp_f32 v1, v1, v24350; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f44351; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v24352; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc4353; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]4354;4355; SI-SDAG-LABEL: v_exp10_f32_ninf_daz:4356; SI-SDAG: ; %bb.0:4357; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4358; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x40549a78, v04359; SI-SDAG-NEXT: s_mov_b32 s4, 0x40549a784360; SI-SDAG-NEXT: v_rndne_f32_e32 v2, v14361; SI-SDAG-NEXT: v_sub_f32_e32 v3, v1, v24362; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v14363; SI-SDAG-NEXT: s_mov_b32 s4, 0x33979a374364; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, v14365; SI-SDAG-NEXT: v_add_f32_e32 v1, v3, v14366; SI-SDAG-NEXT: v_exp_f32_e32 v1, v14367; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v24368; SI-SDAG-NEXT: s_mov_b32 s4, 0xc23369f44369; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v04370; SI-SDAG-NEXT: v_ldexp_f32_e32 v1, v1, v24371; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc4372; SI-SDAG-NEXT: s_setpc_b64 s[30:31]4373;4374; SI-GISEL-LABEL: v_exp10_f32_ninf_daz:4375; SI-GISEL: ; %bb.0:4376; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4377; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x40549a784378; SI-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549a78, v04379; SI-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v24380; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x33979a374381; SI-GISEL-NEXT: v_fma_f32 v1, v0, v3, v14382; SI-GISEL-NEXT: v_rndne_f32_e32 v3, v24383; SI-GISEL-NEXT: v_sub_f32_e32 v2, v2, v34384; SI-GISEL-NEXT: v_add_f32_e32 v1, v2, v14385; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v34386; SI-GISEL-NEXT: v_exp_f32_e32 v1, v14387; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, v1, v24388; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f44389; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v24390; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc4391; SI-GISEL-NEXT: s_setpc_b64 s[30:31]4392;4393; R600-LABEL: v_exp10_f32_ninf_daz:4394; R600: ; %bb.0:4395; R600-NEXT: CF_END4396; R600-NEXT: PAD4397;4398; CM-LABEL: v_exp10_f32_ninf_daz:4399; CM: ; %bb.0:4400; CM-NEXT: CF_END4401; CM-NEXT: PAD4402 %result = call ninf float @llvm.exp10.f32(float %in)4403 ret float %result4404}4405 4406define float @v_exp10_f32_ninf_dynamic(float %in) #1 {4407; VI-SDAG-LABEL: v_exp10_f32_ninf_dynamic:4408; VI-SDAG: ; %bb.0:4409; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4410; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v04411; VI-SDAG-NEXT: v_sub_f32_e32 v4, v0, v14412; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x40549000, v14413; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x3a2784bc, v44414; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x40549000, v44415; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v24416; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v54417; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v14418; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v34419; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v44420; VI-SDAG-NEXT: v_add_f32_e32 v1, v2, v14421; VI-SDAG-NEXT: v_exp_f32_e32 v1, v14422; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v34423; VI-SDAG-NEXT: s_mov_b32 s4, 0xc23369f44424; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v04425; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v24426; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc4427; VI-SDAG-NEXT: s_setpc_b64 s[30:31]4428;4429; VI-GISEL-LABEL: v_exp10_f32_ninf_dynamic:4430; VI-GISEL: ; %bb.0:4431; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4432; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v04433; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v14434; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3a2784bc, v24435; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549000, v24436; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x40549000, v14437; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v44438; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v14439; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v24440; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v34441; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v24442; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v14443; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v24444; VI-GISEL-NEXT: v_exp_f32_e32 v1, v14445; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v24446; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f44447; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v24448; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc4449; VI-GISEL-NEXT: s_setpc_b64 s[30:31]4450;4451; GFX900-SDAG-LABEL: v_exp10_f32_ninf_dynamic:4452; GFX900-SDAG: ; %bb.0:4453; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4454; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x40549a78, v04455; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x40549a784456; GFX900-SDAG-NEXT: v_rndne_f32_e32 v2, v14457; GFX900-SDAG-NEXT: v_sub_f32_e32 v3, v1, v24458; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v14459; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x33979a374460; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, v14461; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v3, v14462; GFX900-SDAG-NEXT: v_exp_f32_e32 v1, v14463; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v24464; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xc23369f44465; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v04466; GFX900-SDAG-NEXT: v_ldexp_f32 v1, v1, v24467; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc4468; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]4469;4470; GFX900-GISEL-LABEL: v_exp10_f32_ninf_dynamic:4471; GFX900-GISEL: ; %bb.0:4472; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4473; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x40549a784474; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549a78, v04475; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v24476; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x33979a374477; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v3, v14478; GFX900-GISEL-NEXT: v_rndne_f32_e32 v3, v24479; GFX900-GISEL-NEXT: v_sub_f32_e32 v2, v2, v34480; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v2, v14481; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v34482; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, v14483; GFX900-GISEL-NEXT: v_ldexp_f32 v1, v1, v24484; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f44485; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v24486; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc4487; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]4488;4489; SI-SDAG-LABEL: v_exp10_f32_ninf_dynamic:4490; SI-SDAG: ; %bb.0:4491; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4492; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x40549a78, v04493; SI-SDAG-NEXT: s_mov_b32 s4, 0x40549a784494; SI-SDAG-NEXT: v_rndne_f32_e32 v2, v14495; SI-SDAG-NEXT: v_sub_f32_e32 v3, v1, v24496; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v14497; SI-SDAG-NEXT: s_mov_b32 s4, 0x33979a374498; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, v14499; SI-SDAG-NEXT: v_add_f32_e32 v1, v3, v14500; SI-SDAG-NEXT: v_exp_f32_e32 v1, v14501; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v24502; SI-SDAG-NEXT: s_mov_b32 s4, 0xc23369f44503; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v04504; SI-SDAG-NEXT: v_ldexp_f32_e32 v1, v1, v24505; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc4506; SI-SDAG-NEXT: s_setpc_b64 s[30:31]4507;4508; SI-GISEL-LABEL: v_exp10_f32_ninf_dynamic:4509; SI-GISEL: ; %bb.0:4510; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4511; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x40549a784512; SI-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549a78, v04513; SI-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v24514; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x33979a374515; SI-GISEL-NEXT: v_fma_f32 v1, v0, v3, v14516; SI-GISEL-NEXT: v_rndne_f32_e32 v3, v24517; SI-GISEL-NEXT: v_sub_f32_e32 v2, v2, v34518; SI-GISEL-NEXT: v_add_f32_e32 v1, v2, v14519; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v34520; SI-GISEL-NEXT: v_exp_f32_e32 v1, v14521; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, v1, v24522; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f44523; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v24524; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc4525; SI-GISEL-NEXT: s_setpc_b64 s[30:31]4526;4527; R600-LABEL: v_exp10_f32_ninf_dynamic:4528; R600: ; %bb.0:4529; R600-NEXT: CF_END4530; R600-NEXT: PAD4531;4532; CM-LABEL: v_exp10_f32_ninf_dynamic:4533; CM: ; %bb.0:4534; CM-NEXT: CF_END4535; CM-NEXT: PAD4536 %result = call ninf float @llvm.exp10.f32(float %in)4537 ret float %result4538}4539 4540define float @v_exp10_f32_nnan_ninf(float %in) {4541; VI-SDAG-LABEL: v_exp10_f32_nnan_ninf:4542; VI-SDAG: ; %bb.0:4543; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4544; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v04545; VI-SDAG-NEXT: v_sub_f32_e32 v4, v0, v14546; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x40549000, v14547; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x3a2784bc, v44548; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x40549000, v44549; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v24550; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v54551; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v14552; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v34553; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v44554; VI-SDAG-NEXT: v_add_f32_e32 v1, v2, v14555; VI-SDAG-NEXT: v_exp_f32_e32 v1, v14556; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v34557; VI-SDAG-NEXT: s_mov_b32 s4, 0xc23369f44558; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v04559; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v24560; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc4561; VI-SDAG-NEXT: s_setpc_b64 s[30:31]4562;4563; VI-GISEL-LABEL: v_exp10_f32_nnan_ninf:4564; VI-GISEL: ; %bb.0:4565; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4566; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v04567; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v14568; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3a2784bc, v24569; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549000, v24570; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x40549000, v14571; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v44572; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v14573; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v24574; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v34575; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v24576; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v14577; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v24578; VI-GISEL-NEXT: v_exp_f32_e32 v1, v14579; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v24580; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f44581; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v24582; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc4583; VI-GISEL-NEXT: s_setpc_b64 s[30:31]4584;4585; GFX900-SDAG-LABEL: v_exp10_f32_nnan_ninf:4586; GFX900-SDAG: ; %bb.0:4587; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4588; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x40549a78, v04589; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x40549a784590; GFX900-SDAG-NEXT: v_rndne_f32_e32 v2, v14591; GFX900-SDAG-NEXT: v_sub_f32_e32 v3, v1, v24592; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v14593; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x33979a374594; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, v14595; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v3, v14596; GFX900-SDAG-NEXT: v_exp_f32_e32 v1, v14597; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v24598; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xc23369f44599; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v04600; GFX900-SDAG-NEXT: v_ldexp_f32 v1, v1, v24601; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc4602; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]4603;4604; GFX900-GISEL-LABEL: v_exp10_f32_nnan_ninf:4605; GFX900-GISEL: ; %bb.0:4606; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4607; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x40549a784608; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549a78, v04609; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v24610; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x33979a374611; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v3, v14612; GFX900-GISEL-NEXT: v_rndne_f32_e32 v3, v24613; GFX900-GISEL-NEXT: v_sub_f32_e32 v2, v2, v34614; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v2, v14615; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v34616; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, v14617; GFX900-GISEL-NEXT: v_ldexp_f32 v1, v1, v24618; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f44619; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v24620; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc4621; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]4622;4623; SI-SDAG-LABEL: v_exp10_f32_nnan_ninf:4624; SI-SDAG: ; %bb.0:4625; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4626; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x40549a78, v04627; SI-SDAG-NEXT: s_mov_b32 s4, 0x40549a784628; SI-SDAG-NEXT: v_rndne_f32_e32 v2, v14629; SI-SDAG-NEXT: v_sub_f32_e32 v3, v1, v24630; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v14631; SI-SDAG-NEXT: s_mov_b32 s4, 0x33979a374632; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, v14633; SI-SDAG-NEXT: v_add_f32_e32 v1, v3, v14634; SI-SDAG-NEXT: v_exp_f32_e32 v1, v14635; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v24636; SI-SDAG-NEXT: s_mov_b32 s4, 0xc23369f44637; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v04638; SI-SDAG-NEXT: v_ldexp_f32_e32 v1, v1, v24639; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc4640; SI-SDAG-NEXT: s_setpc_b64 s[30:31]4641;4642; SI-GISEL-LABEL: v_exp10_f32_nnan_ninf:4643; SI-GISEL: ; %bb.0:4644; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4645; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x40549a784646; SI-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549a78, v04647; SI-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v24648; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x33979a374649; SI-GISEL-NEXT: v_fma_f32 v1, v0, v3, v14650; SI-GISEL-NEXT: v_rndne_f32_e32 v3, v24651; SI-GISEL-NEXT: v_sub_f32_e32 v2, v2, v34652; SI-GISEL-NEXT: v_add_f32_e32 v1, v2, v14653; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v34654; SI-GISEL-NEXT: v_exp_f32_e32 v1, v14655; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, v1, v24656; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f44657; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v24658; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc4659; SI-GISEL-NEXT: s_setpc_b64 s[30:31]4660;4661; R600-LABEL: v_exp10_f32_nnan_ninf:4662; R600: ; %bb.0:4663; R600-NEXT: CF_END4664; R600-NEXT: PAD4665;4666; CM-LABEL: v_exp10_f32_nnan_ninf:4667; CM: ; %bb.0:4668; CM-NEXT: CF_END4669; CM-NEXT: PAD4670 %result = call nnan ninf float @llvm.exp10.f32(float %in)4671 ret float %result4672}4673 4674define float @v_exp10_f32_nnan_ninf_daz(float %in) #0 {4675; VI-SDAG-LABEL: v_exp10_f32_nnan_ninf_daz:4676; VI-SDAG: ; %bb.0:4677; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4678; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v04679; VI-SDAG-NEXT: v_sub_f32_e32 v4, v0, v14680; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x40549000, v14681; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x3a2784bc, v44682; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x40549000, v44683; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v24684; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v54685; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v14686; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v34687; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v44688; VI-SDAG-NEXT: v_add_f32_e32 v1, v2, v14689; VI-SDAG-NEXT: v_exp_f32_e32 v1, v14690; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v34691; VI-SDAG-NEXT: s_mov_b32 s4, 0xc23369f44692; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v04693; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v24694; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc4695; VI-SDAG-NEXT: s_setpc_b64 s[30:31]4696;4697; VI-GISEL-LABEL: v_exp10_f32_nnan_ninf_daz:4698; VI-GISEL: ; %bb.0:4699; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4700; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v04701; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v14702; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3a2784bc, v24703; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549000, v24704; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x40549000, v14705; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v44706; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v14707; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v24708; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v34709; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v24710; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v14711; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v24712; VI-GISEL-NEXT: v_exp_f32_e32 v1, v14713; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v24714; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f44715; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v24716; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc4717; VI-GISEL-NEXT: s_setpc_b64 s[30:31]4718;4719; GFX900-SDAG-LABEL: v_exp10_f32_nnan_ninf_daz:4720; GFX900-SDAG: ; %bb.0:4721; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4722; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x40549a78, v04723; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x40549a784724; GFX900-SDAG-NEXT: v_rndne_f32_e32 v2, v14725; GFX900-SDAG-NEXT: v_sub_f32_e32 v3, v1, v24726; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v14727; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x33979a374728; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, v14729; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v3, v14730; GFX900-SDAG-NEXT: v_exp_f32_e32 v1, v14731; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v24732; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xc23369f44733; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v04734; GFX900-SDAG-NEXT: v_ldexp_f32 v1, v1, v24735; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc4736; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]4737;4738; GFX900-GISEL-LABEL: v_exp10_f32_nnan_ninf_daz:4739; GFX900-GISEL: ; %bb.0:4740; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4741; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x40549a784742; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549a78, v04743; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v24744; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x33979a374745; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v3, v14746; GFX900-GISEL-NEXT: v_rndne_f32_e32 v3, v24747; GFX900-GISEL-NEXT: v_sub_f32_e32 v2, v2, v34748; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v2, v14749; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v34750; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, v14751; GFX900-GISEL-NEXT: v_ldexp_f32 v1, v1, v24752; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f44753; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v24754; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc4755; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]4756;4757; SI-SDAG-LABEL: v_exp10_f32_nnan_ninf_daz:4758; SI-SDAG: ; %bb.0:4759; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4760; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x40549a78, v04761; SI-SDAG-NEXT: s_mov_b32 s4, 0x40549a784762; SI-SDAG-NEXT: v_rndne_f32_e32 v2, v14763; SI-SDAG-NEXT: v_sub_f32_e32 v3, v1, v24764; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v14765; SI-SDAG-NEXT: s_mov_b32 s4, 0x33979a374766; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, v14767; SI-SDAG-NEXT: v_add_f32_e32 v1, v3, v14768; SI-SDAG-NEXT: v_exp_f32_e32 v1, v14769; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v24770; SI-SDAG-NEXT: s_mov_b32 s4, 0xc23369f44771; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v04772; SI-SDAG-NEXT: v_ldexp_f32_e32 v1, v1, v24773; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc4774; SI-SDAG-NEXT: s_setpc_b64 s[30:31]4775;4776; SI-GISEL-LABEL: v_exp10_f32_nnan_ninf_daz:4777; SI-GISEL: ; %bb.0:4778; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4779; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x40549a784780; SI-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549a78, v04781; SI-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v24782; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x33979a374783; SI-GISEL-NEXT: v_fma_f32 v1, v0, v3, v14784; SI-GISEL-NEXT: v_rndne_f32_e32 v3, v24785; SI-GISEL-NEXT: v_sub_f32_e32 v2, v2, v34786; SI-GISEL-NEXT: v_add_f32_e32 v1, v2, v14787; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v34788; SI-GISEL-NEXT: v_exp_f32_e32 v1, v14789; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, v1, v24790; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f44791; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v24792; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc4793; SI-GISEL-NEXT: s_setpc_b64 s[30:31]4794;4795; R600-LABEL: v_exp10_f32_nnan_ninf_daz:4796; R600: ; %bb.0:4797; R600-NEXT: CF_END4798; R600-NEXT: PAD4799;4800; CM-LABEL: v_exp10_f32_nnan_ninf_daz:4801; CM: ; %bb.0:4802; CM-NEXT: CF_END4803; CM-NEXT: PAD4804 %result = call nnan ninf float @llvm.exp10.f32(float %in)4805 ret float %result4806}4807 4808define float @v_exp10_f32_nnan_ninf_dynamic(float %in) #1 {4809; VI-SDAG-LABEL: v_exp10_f32_nnan_ninf_dynamic:4810; VI-SDAG: ; %bb.0:4811; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4812; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v04813; VI-SDAG-NEXT: v_sub_f32_e32 v4, v0, v14814; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x40549000, v14815; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x3a2784bc, v44816; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x40549000, v44817; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v24818; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v54819; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v14820; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v34821; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v44822; VI-SDAG-NEXT: v_add_f32_e32 v1, v2, v14823; VI-SDAG-NEXT: v_exp_f32_e32 v1, v14824; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v34825; VI-SDAG-NEXT: s_mov_b32 s4, 0xc23369f44826; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v04827; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v24828; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc4829; VI-SDAG-NEXT: s_setpc_b64 s[30:31]4830;4831; VI-GISEL-LABEL: v_exp10_f32_nnan_ninf_dynamic:4832; VI-GISEL: ; %bb.0:4833; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4834; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v04835; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v14836; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3a2784bc, v24837; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549000, v24838; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x40549000, v14839; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v44840; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v14841; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v24842; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v34843; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v24844; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v14845; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v24846; VI-GISEL-NEXT: v_exp_f32_e32 v1, v14847; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v24848; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f44849; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v24850; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc4851; VI-GISEL-NEXT: s_setpc_b64 s[30:31]4852;4853; GFX900-SDAG-LABEL: v_exp10_f32_nnan_ninf_dynamic:4854; GFX900-SDAG: ; %bb.0:4855; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4856; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x40549a78, v04857; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x40549a784858; GFX900-SDAG-NEXT: v_rndne_f32_e32 v2, v14859; GFX900-SDAG-NEXT: v_sub_f32_e32 v3, v1, v24860; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v14861; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x33979a374862; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, v14863; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v3, v14864; GFX900-SDAG-NEXT: v_exp_f32_e32 v1, v14865; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v24866; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xc23369f44867; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v04868; GFX900-SDAG-NEXT: v_ldexp_f32 v1, v1, v24869; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc4870; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]4871;4872; GFX900-GISEL-LABEL: v_exp10_f32_nnan_ninf_dynamic:4873; GFX900-GISEL: ; %bb.0:4874; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4875; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x40549a784876; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549a78, v04877; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v24878; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x33979a374879; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v3, v14880; GFX900-GISEL-NEXT: v_rndne_f32_e32 v3, v24881; GFX900-GISEL-NEXT: v_sub_f32_e32 v2, v2, v34882; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v2, v14883; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v34884; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, v14885; GFX900-GISEL-NEXT: v_ldexp_f32 v1, v1, v24886; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f44887; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v24888; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc4889; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]4890;4891; SI-SDAG-LABEL: v_exp10_f32_nnan_ninf_dynamic:4892; SI-SDAG: ; %bb.0:4893; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4894; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x40549a78, v04895; SI-SDAG-NEXT: s_mov_b32 s4, 0x40549a784896; SI-SDAG-NEXT: v_rndne_f32_e32 v2, v14897; SI-SDAG-NEXT: v_sub_f32_e32 v3, v1, v24898; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v14899; SI-SDAG-NEXT: s_mov_b32 s4, 0x33979a374900; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, v14901; SI-SDAG-NEXT: v_add_f32_e32 v1, v3, v14902; SI-SDAG-NEXT: v_exp_f32_e32 v1, v14903; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v24904; SI-SDAG-NEXT: s_mov_b32 s4, 0xc23369f44905; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v04906; SI-SDAG-NEXT: v_ldexp_f32_e32 v1, v1, v24907; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc4908; SI-SDAG-NEXT: s_setpc_b64 s[30:31]4909;4910; SI-GISEL-LABEL: v_exp10_f32_nnan_ninf_dynamic:4911; SI-GISEL: ; %bb.0:4912; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4913; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x40549a784914; SI-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549a78, v04915; SI-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v24916; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x33979a374917; SI-GISEL-NEXT: v_fma_f32 v1, v0, v3, v14918; SI-GISEL-NEXT: v_rndne_f32_e32 v3, v24919; SI-GISEL-NEXT: v_sub_f32_e32 v2, v2, v34920; SI-GISEL-NEXT: v_add_f32_e32 v1, v2, v14921; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v34922; SI-GISEL-NEXT: v_exp_f32_e32 v1, v14923; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, v1, v24924; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f44925; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v24926; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc4927; SI-GISEL-NEXT: s_setpc_b64 s[30:31]4928;4929; R600-LABEL: v_exp10_f32_nnan_ninf_dynamic:4930; R600: ; %bb.0:4931; R600-NEXT: CF_END4932; R600-NEXT: PAD4933;4934; CM-LABEL: v_exp10_f32_nnan_ninf_dynamic:4935; CM: ; %bb.0:4936; CM-NEXT: CF_END4937; CM-NEXT: PAD4938 %result = call nnan ninf float @llvm.exp10.f32(float %in)4939 ret float %result4940}4941 4942define float @v_exp10_f32_fast_daz(float %in) #0 {4943; GCN-SDAG-LABEL: v_exp10_f32_fast_daz:4944; GCN-SDAG: ; %bb.0:4945; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4946; GCN-SDAG-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v04947; GCN-SDAG-NEXT: v_mul_f32_e32 v0, 0x40549000, v04948; GCN-SDAG-NEXT: v_exp_f32_e32 v1, v14949; GCN-SDAG-NEXT: v_exp_f32_e32 v0, v04950; GCN-SDAG-NEXT: v_mul_f32_e32 v0, v0, v14951; GCN-SDAG-NEXT: s_setpc_b64 s[30:31]4952;4953; GCN-GISEL-LABEL: v_exp10_f32_fast_daz:4954; GCN-GISEL: ; %bb.0:4955; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4956; GCN-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v04957; GCN-GISEL-NEXT: v_exp_f32_e32 v0, v04958; GCN-GISEL-NEXT: s_setpc_b64 s[30:31]4959;4960; SI-SDAG-LABEL: v_exp10_f32_fast_daz:4961; SI-SDAG: ; %bb.0:4962; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4963; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v04964; SI-SDAG-NEXT: v_mul_f32_e32 v0, 0x40549000, v04965; SI-SDAG-NEXT: v_exp_f32_e32 v1, v14966; SI-SDAG-NEXT: v_exp_f32_e32 v0, v04967; SI-SDAG-NEXT: v_mul_f32_e32 v0, v0, v14968; SI-SDAG-NEXT: s_setpc_b64 s[30:31]4969;4970; SI-GISEL-LABEL: v_exp10_f32_fast_daz:4971; SI-GISEL: ; %bb.0:4972; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4973; SI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v04974; SI-GISEL-NEXT: v_exp_f32_e32 v0, v04975; SI-GISEL-NEXT: s_setpc_b64 s[30:31]4976;4977; R600-LABEL: v_exp10_f32_fast_daz:4978; R600: ; %bb.0:4979; R600-NEXT: CF_END4980; R600-NEXT: PAD4981;4982; CM-LABEL: v_exp10_f32_fast_daz:4983; CM: ; %bb.0:4984; CM-NEXT: CF_END4985; CM-NEXT: PAD4986 %result = call fast float @llvm.exp10.f32(float %in)4987 ret float %result4988}4989 4990define float @v_exp10_f32_dynamic_mode(float %in) #1 {4991; VI-SDAG-LABEL: v_exp10_f32_dynamic_mode:4992; VI-SDAG: ; %bb.0:4993; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4994; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v04995; VI-SDAG-NEXT: v_sub_f32_e32 v4, v0, v14996; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x40549000, v14997; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x3a2784bc, v44998; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x40549000, v44999; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v25000; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v55001; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v15002; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v35003; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v45004; VI-SDAG-NEXT: v_add_f32_e32 v1, v2, v15005; VI-SDAG-NEXT: v_exp_f32_e32 v1, v15006; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v35007; VI-SDAG-NEXT: s_mov_b32 s4, 0xc23369f45008; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v05009; VI-SDAG-NEXT: s_mov_b32 s4, 0x421a209b5010; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v25011; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc5012; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f8000005013; VI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v05014; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc5015; VI-SDAG-NEXT: s_setpc_b64 s[30:31]5016;5017; VI-GISEL-LABEL: v_exp10_f32_dynamic_mode:5018; VI-GISEL: ; %bb.0:5019; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5020; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v05021; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v15022; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3a2784bc, v25023; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549000, v25024; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x40549000, v15025; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v45026; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v15027; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v25028; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v35029; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v25030; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v15031; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v25032; VI-GISEL-NEXT: v_exp_f32_e32 v1, v15033; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f8000005034; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v25035; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f45036; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v25037; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x421a209b5038; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc5039; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v25040; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc5041; VI-GISEL-NEXT: s_setpc_b64 s[30:31]5042;5043; GFX900-SDAG-LABEL: v_exp10_f32_dynamic_mode:5044; GFX900-SDAG: ; %bb.0:5045; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5046; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x40549a78, v05047; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x40549a785048; GFX900-SDAG-NEXT: v_rndne_f32_e32 v2, v15049; GFX900-SDAG-NEXT: v_sub_f32_e32 v3, v1, v25050; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v15051; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x33979a375052; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, v15053; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v3, v15054; GFX900-SDAG-NEXT: v_exp_f32_e32 v1, v15055; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v25056; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xc23369f45057; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v05058; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x421a209b5059; GFX900-SDAG-NEXT: v_ldexp_f32 v1, v1, v25060; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc5061; GFX900-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f8000005062; GFX900-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v05063; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc5064; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]5065;5066; GFX900-GISEL-LABEL: v_exp10_f32_dynamic_mode:5067; GFX900-GISEL: ; %bb.0:5068; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5069; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x40549a785070; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549a78, v05071; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v25072; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x33979a375073; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v3, v15074; GFX900-GISEL-NEXT: v_rndne_f32_e32 v3, v25075; GFX900-GISEL-NEXT: v_sub_f32_e32 v2, v2, v35076; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v2, v15077; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v35078; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, v15079; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f8000005080; GFX900-GISEL-NEXT: v_ldexp_f32 v1, v1, v25081; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f45082; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v25083; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x421a209b5084; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc5085; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v25086; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc5087; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]5088;5089; SI-SDAG-LABEL: v_exp10_f32_dynamic_mode:5090; SI-SDAG: ; %bb.0:5091; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5092; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x40549a78, v05093; SI-SDAG-NEXT: s_mov_b32 s4, 0x40549a785094; SI-SDAG-NEXT: v_rndne_f32_e32 v2, v15095; SI-SDAG-NEXT: v_sub_f32_e32 v3, v1, v25096; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v15097; SI-SDAG-NEXT: s_mov_b32 s4, 0x33979a375098; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, v15099; SI-SDAG-NEXT: v_add_f32_e32 v1, v3, v15100; SI-SDAG-NEXT: v_exp_f32_e32 v1, v15101; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v25102; SI-SDAG-NEXT: s_mov_b32 s4, 0xc23369f45103; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v05104; SI-SDAG-NEXT: s_mov_b32 s4, 0x421a209b5105; SI-SDAG-NEXT: v_ldexp_f32_e32 v1, v1, v25106; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc5107; SI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f8000005108; SI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v05109; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc5110; SI-SDAG-NEXT: s_setpc_b64 s[30:31]5111;5112; SI-GISEL-LABEL: v_exp10_f32_dynamic_mode:5113; SI-GISEL: ; %bb.0:5114; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5115; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x40549a785116; SI-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549a78, v05117; SI-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v25118; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x33979a375119; SI-GISEL-NEXT: v_fma_f32 v1, v0, v3, v15120; SI-GISEL-NEXT: v_rndne_f32_e32 v3, v25121; SI-GISEL-NEXT: v_sub_f32_e32 v2, v2, v35122; SI-GISEL-NEXT: v_add_f32_e32 v1, v2, v15123; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v35124; SI-GISEL-NEXT: v_exp_f32_e32 v1, v15125; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f8000005126; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, v1, v25127; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f45128; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v25129; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x421a209b5130; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc5131; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v25132; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc5133; SI-GISEL-NEXT: s_setpc_b64 s[30:31]5134;5135; R600-LABEL: v_exp10_f32_dynamic_mode:5136; R600: ; %bb.0:5137; R600-NEXT: CF_END5138; R600-NEXT: PAD5139;5140; CM-LABEL: v_exp10_f32_dynamic_mode:5141; CM: ; %bb.0:5142; CM-NEXT: CF_END5143; CM-NEXT: PAD5144 %result = call float @llvm.exp10.f32(float %in)5145 ret float %result5146}5147 5148define float @v_exp10_f32_undef() {5149; GCN-LABEL: v_exp10_f32_undef:5150; GCN: ; %bb.0:5151; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5152; GCN-NEXT: s_setpc_b64 s[30:31]5153;5154; SI-LABEL: v_exp10_f32_undef:5155; SI: ; %bb.0:5156; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5157; SI-NEXT: s_setpc_b64 s[30:31]5158;5159; R600-LABEL: v_exp10_f32_undef:5160; R600: ; %bb.0:5161; R600-NEXT: CF_END5162; R600-NEXT: PAD5163;5164; CM-LABEL: v_exp10_f32_undef:5165; CM: ; %bb.0:5166; CM-NEXT: CF_END5167; CM-NEXT: PAD5168 %result = call float @llvm.exp10.f32(float poison)5169 ret float %result5170}5171 5172define float @v_exp10_f32_0() {5173; GCN-LABEL: v_exp10_f32_0:5174; GCN: ; %bb.0:5175; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5176; GCN-NEXT: v_mov_b32_e32 v0, 1.05177; GCN-NEXT: s_setpc_b64 s[30:31]5178;5179; SI-LABEL: v_exp10_f32_0:5180; SI: ; %bb.0:5181; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5182; SI-NEXT: v_mov_b32_e32 v0, 1.05183; SI-NEXT: s_setpc_b64 s[30:31]5184;5185; R600-LABEL: v_exp10_f32_0:5186; R600: ; %bb.0:5187; R600-NEXT: CF_END5188; R600-NEXT: PAD5189;5190; CM-LABEL: v_exp10_f32_0:5191; CM: ; %bb.0:5192; CM-NEXT: CF_END5193; CM-NEXT: PAD5194 %result = call float @llvm.exp10.f32(float 0.0)5195 ret float %result5196}5197 5198define float @v_exp10_f32_from_fpext_f16(i16 %src.i) {5199; VI-SDAG-LABEL: v_exp10_f32_from_fpext_f16:5200; VI-SDAG: ; %bb.0:5201; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5202; VI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v05203; VI-SDAG-NEXT: s_mov_b32 s4, 0xc23369f45204; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v05205; VI-SDAG-NEXT: v_sub_f32_e32 v3, v0, v15206; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x40549000, v15207; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x3a2784bc, v35208; VI-SDAG-NEXT: v_mul_f32_e32 v3, 0x40549000, v35209; VI-SDAG-NEXT: v_rndne_f32_e32 v4, v25210; VI-SDAG-NEXT: v_add_f32_e32 v3, v3, v55211; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v15212; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v45213; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v35214; VI-SDAG-NEXT: v_add_f32_e32 v1, v2, v15215; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v45216; VI-SDAG-NEXT: v_exp_f32_e32 v1, v15217; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v05218; VI-SDAG-NEXT: s_mov_b32 s4, 0x421a209b5219; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v25220; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc5221; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f8000005222; VI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v05223; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc5224; VI-SDAG-NEXT: s_setpc_b64 s[30:31]5225;5226; VI-GISEL-LABEL: v_exp10_f32_from_fpext_f16:5227; VI-GISEL: ; %bb.0:5228; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5229; VI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v05230; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v05231; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v15232; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3a2784bc, v25233; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549000, v25234; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x40549000, v15235; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v15236; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v45237; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v25238; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v35239; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v25240; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v15241; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v25242; VI-GISEL-NEXT: v_exp_f32_e32 v1, v15243; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f8000005244; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v25245; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f45246; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v25247; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x421a209b5248; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc5249; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v25250; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc5251; VI-GISEL-NEXT: s_setpc_b64 s[30:31]5252;5253; GFX900-SDAG-LABEL: v_exp10_f32_from_fpext_f16:5254; GFX900-SDAG: ; %bb.0:5255; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5256; GFX900-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v05257; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x40549a785258; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x33979a375259; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x40549a78, v05260; GFX900-SDAG-NEXT: v_rndne_f32_e32 v2, v15261; GFX900-SDAG-NEXT: v_fma_f32 v3, v0, s4, -v15262; GFX900-SDAG-NEXT: v_sub_f32_e32 v1, v1, v25263; GFX900-SDAG-NEXT: v_fma_f32 v3, v0, s5, v35264; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v1, v35265; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v25266; GFX900-SDAG-NEXT: v_exp_f32_e32 v1, v15267; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xc23369f45268; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v05269; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x421a209b5270; GFX900-SDAG-NEXT: v_ldexp_f32 v1, v1, v25271; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc5272; GFX900-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f8000005273; GFX900-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v05274; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc5275; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]5276;5277; GFX900-GISEL-LABEL: v_exp10_f32_from_fpext_f16:5278; GFX900-GISEL: ; %bb.0:5279; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5280; GFX900-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v05281; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x40549a785282; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x33979a375283; GFX900-GISEL-NEXT: v_mul_f32_e32 v3, 0x40549a78, v05284; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v35285; GFX900-GISEL-NEXT: v_rndne_f32_e32 v4, v35286; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v2, v15287; GFX900-GISEL-NEXT: v_sub_f32_e32 v2, v3, v45288; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v2, v15289; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v45290; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, v15291; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0xc23369f45292; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v35293; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f8000005294; GFX900-GISEL-NEXT: v_ldexp_f32 v1, v1, v25295; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x421a209b5296; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc5297; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v25298; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc5299; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]5300;5301; SI-SDAG-LABEL: v_exp10_f32_from_fpext_f16:5302; SI-SDAG: ; %bb.0:5303; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5304; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v05305; SI-SDAG-NEXT: s_mov_b32 s4, 0x40549a785306; SI-SDAG-NEXT: s_mov_b32 s5, 0x33979a375307; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x40549a78, v05308; SI-SDAG-NEXT: v_rndne_f32_e32 v2, v15309; SI-SDAG-NEXT: v_fma_f32 v3, v0, s4, -v15310; SI-SDAG-NEXT: v_sub_f32_e32 v1, v1, v25311; SI-SDAG-NEXT: v_fma_f32 v3, v0, s5, v35312; SI-SDAG-NEXT: v_add_f32_e32 v1, v1, v35313; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v25314; SI-SDAG-NEXT: v_exp_f32_e32 v1, v15315; SI-SDAG-NEXT: s_mov_b32 s4, 0xc23369f45316; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v05317; SI-SDAG-NEXT: s_mov_b32 s4, 0x421a209b5318; SI-SDAG-NEXT: v_ldexp_f32_e32 v1, v1, v25319; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc5320; SI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f8000005321; SI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v05322; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc5323; SI-SDAG-NEXT: s_setpc_b64 s[30:31]5324;5325; SI-GISEL-LABEL: v_exp10_f32_from_fpext_f16:5326; SI-GISEL: ; %bb.0:5327; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5328; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v05329; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x40549a785330; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x33979a375331; SI-GISEL-NEXT: v_mul_f32_e32 v3, 0x40549a78, v05332; SI-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v35333; SI-GISEL-NEXT: v_rndne_f32_e32 v4, v35334; SI-GISEL-NEXT: v_fma_f32 v1, v0, v2, v15335; SI-GISEL-NEXT: v_sub_f32_e32 v2, v3, v45336; SI-GISEL-NEXT: v_add_f32_e32 v1, v2, v15337; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v45338; SI-GISEL-NEXT: v_exp_f32_e32 v1, v15339; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0xc23369f45340; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v35341; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f8000005342; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, v1, v25343; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x421a209b5344; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc5345; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v25346; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc5347; SI-GISEL-NEXT: s_setpc_b64 s[30:31]5348;5349; R600-LABEL: v_exp10_f32_from_fpext_f16:5350; R600: ; %bb.0:5351; R600-NEXT: CF_END5352; R600-NEXT: PAD5353;5354; CM-LABEL: v_exp10_f32_from_fpext_f16:5355; CM: ; %bb.0:5356; CM-NEXT: CF_END5357; CM-NEXT: PAD5358 %src = bitcast i16 %src.i to half5359 %fpext = fpext half %src to float5360 %result = call float @llvm.exp10.f32(float %fpext)5361 ret float %result5362}5363 5364define float @v_exp10_f32_from_fpext_math_f16(i16 %src0.i, i16 %src1.i) {5365; VI-SDAG-LABEL: v_exp10_f32_from_fpext_math_f16:5366; VI-SDAG: ; %bb.0:5367; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5368; VI-SDAG-NEXT: v_add_f16_e32 v0, v0, v15369; VI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v05370; VI-SDAG-NEXT: s_mov_b32 s4, 0xc23369f45371; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v05372; VI-SDAG-NEXT: v_sub_f32_e32 v2, v0, v15373; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x3a2784bc, v25374; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x40549000, v25375; VI-SDAG-NEXT: v_mul_f32_e32 v3, 0x3a2784bc, v15376; VI-SDAG-NEXT: v_add_f32_e32 v2, v2, v45377; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x40549000, v15378; VI-SDAG-NEXT: v_add_f32_e32 v2, v3, v25379; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v15380; VI-SDAG-NEXT: v_sub_f32_e32 v1, v1, v35381; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v25382; VI-SDAG-NEXT: v_exp_f32_e32 v1, v15383; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v35384; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v05385; VI-SDAG-NEXT: s_mov_b32 s4, 0x421a209b5386; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v25387; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc5388; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f8000005389; VI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v05390; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc5391; VI-SDAG-NEXT: s_setpc_b64 s[30:31]5392;5393; VI-GISEL-LABEL: v_exp10_f32_from_fpext_math_f16:5394; VI-GISEL: ; %bb.0:5395; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5396; VI-GISEL-NEXT: v_add_f16_e32 v0, v0, v15397; VI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v05398; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v05399; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v15400; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3a2784bc, v25401; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549000, v25402; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x40549000, v15403; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v45404; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v15405; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v25406; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v35407; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v25408; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v15409; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v25410; VI-GISEL-NEXT: v_exp_f32_e32 v1, v15411; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f8000005412; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v25413; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f45414; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v25415; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x421a209b5416; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc5417; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v25418; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc5419; VI-GISEL-NEXT: s_setpc_b64 s[30:31]5420;5421; GFX900-SDAG-LABEL: v_exp10_f32_from_fpext_math_f16:5422; GFX900-SDAG: ; %bb.0:5423; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5424; GFX900-SDAG-NEXT: v_add_f16_e32 v0, v0, v15425; GFX900-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v05426; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x40549a785427; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x33979a375428; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x40549a78, v05429; GFX900-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v15430; GFX900-SDAG-NEXT: v_rndne_f32_e32 v3, v15431; GFX900-SDAG-NEXT: v_fma_f32 v2, v0, s5, v25432; GFX900-SDAG-NEXT: v_sub_f32_e32 v1, v1, v35433; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v1, v25434; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v35435; GFX900-SDAG-NEXT: v_exp_f32_e32 v1, v15436; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xc23369f45437; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v05438; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x421a209b5439; GFX900-SDAG-NEXT: v_ldexp_f32 v1, v1, v25440; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc5441; GFX900-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f8000005442; GFX900-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v05443; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc5444; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]5445;5446; GFX900-GISEL-LABEL: v_exp10_f32_from_fpext_math_f16:5447; GFX900-GISEL: ; %bb.0:5448; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5449; GFX900-GISEL-NEXT: v_add_f16_e32 v0, v0, v15450; GFX900-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v05451; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x40549a785452; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x33979a375453; GFX900-GISEL-NEXT: v_mul_f32_e32 v3, 0x40549a78, v05454; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v35455; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v2, v15456; GFX900-GISEL-NEXT: v_rndne_f32_e32 v2, v35457; GFX900-GISEL-NEXT: v_sub_f32_e32 v3, v3, v25458; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v3, v15459; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v25460; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, v15461; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f8000005462; GFX900-GISEL-NEXT: v_ldexp_f32 v1, v1, v25463; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f45464; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v25465; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x421a209b5466; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc5467; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v25468; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc5469; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]5470;5471; SI-SDAG-LABEL: v_exp10_f32_from_fpext_math_f16:5472; SI-SDAG: ; %bb.0:5473; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5474; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v05475; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v15476; SI-SDAG-NEXT: s_mov_b32 s4, 0x40549a785477; SI-SDAG-NEXT: v_add_f32_e32 v0, v0, v15478; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x40549a78, v05479; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v15480; SI-SDAG-NEXT: s_mov_b32 s4, 0x33979a375481; SI-SDAG-NEXT: v_rndne_f32_e32 v3, v15482; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, v25483; SI-SDAG-NEXT: v_sub_f32_e32 v1, v1, v35484; SI-SDAG-NEXT: v_add_f32_e32 v1, v1, v25485; SI-SDAG-NEXT: v_exp_f32_e32 v1, v15486; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v35487; SI-SDAG-NEXT: s_mov_b32 s4, 0xc23369f45488; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v05489; SI-SDAG-NEXT: s_mov_b32 s4, 0x421a209b5490; SI-SDAG-NEXT: v_ldexp_f32_e32 v1, v1, v25491; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc5492; SI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f8000005493; SI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v05494; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc5495; SI-SDAG-NEXT: s_setpc_b64 s[30:31]5496;5497; SI-GISEL-LABEL: v_exp10_f32_from_fpext_math_f16:5498; SI-GISEL: ; %bb.0:5499; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5500; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v05501; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v15502; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x33979a375503; SI-GISEL-NEXT: v_mov_b32_e32 v5, 0x7f8000005504; SI-GISEL-NEXT: v_add_f32_e32 v0, v0, v15505; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v05506; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x40549a785507; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v05508; SI-GISEL-NEXT: v_mul_f32_e32 v3, 0x40549a78, v05509; SI-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v35510; SI-GISEL-NEXT: v_rndne_f32_e32 v4, v35511; SI-GISEL-NEXT: v_fma_f32 v1, v0, v2, v15512; SI-GISEL-NEXT: v_sub_f32_e32 v2, v3, v45513; SI-GISEL-NEXT: v_add_f32_e32 v1, v2, v15514; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v3, v45515; SI-GISEL-NEXT: v_exp_f32_e32 v1, v15516; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f45517; SI-GISEL-NEXT: v_mov_b32_e32 v4, 0x421a209b5518; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v25519; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, v1, v35520; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc5521; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v45522; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v5, vcc5523; SI-GISEL-NEXT: s_setpc_b64 s[30:31]5524;5525; R600-LABEL: v_exp10_f32_from_fpext_math_f16:5526; R600: ; %bb.0:5527; R600-NEXT: CF_END5528; R600-NEXT: PAD5529;5530; CM-LABEL: v_exp10_f32_from_fpext_math_f16:5531; CM: ; %bb.0:5532; CM-NEXT: CF_END5533; CM-NEXT: PAD5534 %src0 = bitcast i16 %src0.i to half5535 %src1 = bitcast i16 %src1.i to half5536 %fadd = fadd half %src0, %src15537 %fpext = fpext half %fadd to float5538 %result = call float @llvm.exp10.f32(float %fpext)5539 ret float %result5540}5541 5542define float @v_exp10_f32_from_fpext_bf16(bfloat %src) {5543; VI-LABEL: v_exp10_f32_from_fpext_bf16:5544; VI: ; %bb.0:5545; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5546; VI-NEXT: v_lshlrev_b32_e32 v0, 16, v05547; VI-NEXT: v_sub_f32_e32 v3, v0, v05548; VI-NEXT: v_mul_f32_e32 v1, 0x40549000, v05549; VI-NEXT: v_mul_f32_e32 v4, 0x3a2784bc, v35550; VI-NEXT: v_mul_f32_e32 v3, 0x40549000, v35551; VI-NEXT: v_rndne_f32_e32 v2, v15552; VI-NEXT: v_add_f32_e32 v3, v3, v45553; VI-NEXT: v_mul_f32_e32 v4, 0x3a2784bc, v05554; VI-NEXT: v_sub_f32_e32 v1, v1, v25555; VI-NEXT: v_add_f32_e32 v3, v4, v35556; VI-NEXT: v_add_f32_e32 v1, v1, v35557; VI-NEXT: v_exp_f32_e32 v1, v15558; VI-NEXT: v_cvt_i32_f32_e32 v2, v25559; VI-NEXT: s_mov_b32 s4, 0xc23369f45560; VI-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v05561; VI-NEXT: s_mov_b32 s4, 0x421a209b5562; VI-NEXT: v_ldexp_f32 v1, v1, v25563; VI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc5564; VI-NEXT: v_mov_b32_e32 v2, 0x7f8000005565; VI-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v05566; VI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc5567; VI-NEXT: s_setpc_b64 s[30:31]5568;5569; GFX900-LABEL: v_exp10_f32_from_fpext_bf16:5570; GFX900: ; %bb.0:5571; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5572; GFX900-NEXT: v_lshlrev_b32_e32 v0, 16, v05573; GFX900-NEXT: v_mul_f32_e32 v1, 0x40549a78, v05574; GFX900-NEXT: s_mov_b32 s4, 0x40549a785575; GFX900-NEXT: v_rndne_f32_e32 v2, v15576; GFX900-NEXT: v_sub_f32_e32 v3, v1, v25577; GFX900-NEXT: v_fma_f32 v1, v0, s4, -v15578; GFX900-NEXT: s_mov_b32 s4, 0x33979a375579; GFX900-NEXT: v_fma_f32 v1, v0, s4, v15580; GFX900-NEXT: v_add_f32_e32 v1, v3, v15581; GFX900-NEXT: v_exp_f32_e32 v1, v15582; GFX900-NEXT: v_cvt_i32_f32_e32 v2, v25583; GFX900-NEXT: s_mov_b32 s4, 0xc23369f45584; GFX900-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v05585; GFX900-NEXT: s_mov_b32 s4, 0x421a209b5586; GFX900-NEXT: v_ldexp_f32 v1, v1, v25587; GFX900-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc5588; GFX900-NEXT: v_mov_b32_e32 v2, 0x7f8000005589; GFX900-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v05590; GFX900-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc5591; GFX900-NEXT: s_setpc_b64 s[30:31]5592;5593; SI-LABEL: v_exp10_f32_from_fpext_bf16:5594; SI: ; %bb.0:5595; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5596; SI-NEXT: v_mul_f32_e32 v1, 0x40549a78, v05597; SI-NEXT: s_mov_b32 s4, 0x40549a785598; SI-NEXT: v_rndne_f32_e32 v2, v15599; SI-NEXT: v_sub_f32_e32 v3, v1, v25600; SI-NEXT: v_fma_f32 v1, v0, s4, -v15601; SI-NEXT: s_mov_b32 s4, 0x33979a375602; SI-NEXT: v_fma_f32 v1, v0, s4, v15603; SI-NEXT: v_add_f32_e32 v1, v3, v15604; SI-NEXT: v_exp_f32_e32 v1, v15605; SI-NEXT: v_cvt_i32_f32_e32 v2, v25606; SI-NEXT: s_mov_b32 s4, 0xc23369f45607; SI-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v05608; SI-NEXT: s_mov_b32 s4, 0x421a209b5609; SI-NEXT: v_ldexp_f32_e32 v1, v1, v25610; SI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc5611; SI-NEXT: v_mov_b32_e32 v2, 0x7f8000005612; SI-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v05613; SI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc5614; SI-NEXT: s_setpc_b64 s[30:31]5615;5616; R600-LABEL: v_exp10_f32_from_fpext_bf16:5617; R600: ; %bb.0:5618; R600-NEXT: CF_END5619; R600-NEXT: PAD5620;5621; CM-LABEL: v_exp10_f32_from_fpext_bf16:5622; CM: ; %bb.0:5623; CM-NEXT: CF_END5624; CM-NEXT: PAD5625 %fpext = fpext bfloat %src to float5626 %result = call float @llvm.exp10.f32(float %fpext)5627 ret float %result5628}5629 5630define float @v_exp10_f32_from_fpext_math_f16_fast(i16 %src0.i, i16 %src1.i) {5631; GCN-SDAG-LABEL: v_exp10_f32_from_fpext_math_f16_fast:5632; GCN-SDAG: ; %bb.0:5633; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5634; GCN-SDAG-NEXT: v_add_f16_e32 v0, v0, v15635; GCN-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v05636; GCN-SDAG-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v05637; GCN-SDAG-NEXT: v_mul_f32_e32 v0, 0x40549000, v05638; GCN-SDAG-NEXT: v_exp_f32_e32 v1, v15639; GCN-SDAG-NEXT: v_exp_f32_e32 v0, v05640; GCN-SDAG-NEXT: v_mul_f32_e32 v0, v0, v15641; GCN-SDAG-NEXT: s_setpc_b64 s[30:31]5642;5643; GCN-GISEL-LABEL: v_exp10_f32_from_fpext_math_f16_fast:5644; GCN-GISEL: ; %bb.0:5645; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5646; GCN-GISEL-NEXT: v_add_f16_e32 v0, v0, v15647; GCN-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v05648; GCN-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v05649; GCN-GISEL-NEXT: v_exp_f32_e32 v0, v05650; GCN-GISEL-NEXT: s_setpc_b64 s[30:31]5651;5652; SI-SDAG-LABEL: v_exp10_f32_from_fpext_math_f16_fast:5653; SI-SDAG: ; %bb.0:5654; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5655; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v05656; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v15657; SI-SDAG-NEXT: s_mov_b32 s4, 0xc217b8185658; SI-SDAG-NEXT: v_add_f32_e32 v0, v0, v15659; SI-SDAG-NEXT: v_add_f32_e32 v1, 0x42000000, v05660; SI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v05661; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc5662; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v05663; SI-SDAG-NEXT: v_mul_f32_e32 v0, 0x40549000, v05664; SI-SDAG-NEXT: v_exp_f32_e32 v1, v15665; SI-SDAG-NEXT: v_exp_f32_e32 v0, v05666; SI-SDAG-NEXT: v_mul_f32_e32 v0, v0, v15667; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0xa4fb11f, v05668; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc5669; SI-SDAG-NEXT: s_setpc_b64 s[30:31]5670;5671; SI-GISEL-LABEL: v_exp10_f32_from_fpext_math_f16_fast:5672; SI-GISEL: ; %bb.0:5673; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5674; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v05675; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v15676; SI-GISEL-NEXT: v_add_f32_e32 v0, v0, v15677; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v05678; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v05679; SI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v05680; SI-GISEL-NEXT: v_exp_f32_e32 v0, v05681; SI-GISEL-NEXT: s_setpc_b64 s[30:31]5682;5683; R600-LABEL: v_exp10_f32_from_fpext_math_f16_fast:5684; R600: ; %bb.0:5685; R600-NEXT: CF_END5686; R600-NEXT: PAD5687;5688; CM-LABEL: v_exp10_f32_from_fpext_math_f16_fast:5689; CM: ; %bb.0:5690; CM-NEXT: CF_END5691; CM-NEXT: PAD5692 %src0 = bitcast i16 %src0.i to half5693 %src1 = bitcast i16 %src1.i to half5694 %fadd = fadd half %src0, %src15695 %fpext = fpext half %fadd to float5696 %result = call fast float @llvm.exp10.f32(float %fpext)5697 ret float %result5698}5699 5700define float @v_exp10_f32_from_fpext_math_f16_daz(i16 %src0.i, i16 %src1.i) #0 {5701; VI-SDAG-LABEL: v_exp10_f32_from_fpext_math_f16_daz:5702; VI-SDAG: ; %bb.0:5703; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5704; VI-SDAG-NEXT: v_add_f16_e32 v0, v0, v15705; VI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v05706; VI-SDAG-NEXT: s_mov_b32 s4, 0xc23369f45707; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v05708; VI-SDAG-NEXT: v_sub_f32_e32 v2, v0, v15709; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x3a2784bc, v25710; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x40549000, v25711; VI-SDAG-NEXT: v_mul_f32_e32 v3, 0x3a2784bc, v15712; VI-SDAG-NEXT: v_add_f32_e32 v2, v2, v45713; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x40549000, v15714; VI-SDAG-NEXT: v_add_f32_e32 v2, v3, v25715; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v15716; VI-SDAG-NEXT: v_sub_f32_e32 v1, v1, v35717; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v25718; VI-SDAG-NEXT: v_exp_f32_e32 v1, v15719; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v35720; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v05721; VI-SDAG-NEXT: s_mov_b32 s4, 0x421a209b5722; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v25723; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc5724; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f8000005725; VI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v05726; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc5727; VI-SDAG-NEXT: s_setpc_b64 s[30:31]5728;5729; VI-GISEL-LABEL: v_exp10_f32_from_fpext_math_f16_daz:5730; VI-GISEL: ; %bb.0:5731; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5732; VI-GISEL-NEXT: v_add_f16_e32 v0, v0, v15733; VI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v05734; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v05735; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v15736; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3a2784bc, v25737; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549000, v25738; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x40549000, v15739; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v45740; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v15741; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v25742; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v35743; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v25744; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v15745; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v25746; VI-GISEL-NEXT: v_exp_f32_e32 v1, v15747; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f8000005748; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v25749; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f45750; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v25751; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x421a209b5752; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc5753; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v25754; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc5755; VI-GISEL-NEXT: s_setpc_b64 s[30:31]5756;5757; GFX900-SDAG-LABEL: v_exp10_f32_from_fpext_math_f16_daz:5758; GFX900-SDAG: ; %bb.0:5759; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5760; GFX900-SDAG-NEXT: v_add_f16_e32 v0, v0, v15761; GFX900-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v05762; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x40549a785763; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x33979a375764; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x40549a78, v05765; GFX900-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v15766; GFX900-SDAG-NEXT: v_rndne_f32_e32 v3, v15767; GFX900-SDAG-NEXT: v_fma_f32 v2, v0, s5, v25768; GFX900-SDAG-NEXT: v_sub_f32_e32 v1, v1, v35769; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v1, v25770; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v35771; GFX900-SDAG-NEXT: v_exp_f32_e32 v1, v15772; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xc23369f45773; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v05774; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x421a209b5775; GFX900-SDAG-NEXT: v_ldexp_f32 v1, v1, v25776; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc5777; GFX900-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f8000005778; GFX900-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v05779; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc5780; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]5781;5782; GFX900-GISEL-LABEL: v_exp10_f32_from_fpext_math_f16_daz:5783; GFX900-GISEL: ; %bb.0:5784; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5785; GFX900-GISEL-NEXT: v_add_f16_e32 v0, v0, v15786; GFX900-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v05787; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x40549a785788; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x33979a375789; GFX900-GISEL-NEXT: v_mul_f32_e32 v3, 0x40549a78, v05790; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v35791; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v2, v15792; GFX900-GISEL-NEXT: v_rndne_f32_e32 v2, v35793; GFX900-GISEL-NEXT: v_sub_f32_e32 v3, v3, v25794; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v3, v15795; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v25796; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, v15797; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f8000005798; GFX900-GISEL-NEXT: v_ldexp_f32 v1, v1, v25799; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f45800; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v25801; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x421a209b5802; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc5803; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v25804; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc5805; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]5806;5807; SI-SDAG-LABEL: v_exp10_f32_from_fpext_math_f16_daz:5808; SI-SDAG: ; %bb.0:5809; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5810; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v05811; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v15812; SI-SDAG-NEXT: s_mov_b32 s4, 0x40549a785813; SI-SDAG-NEXT: v_add_f32_e32 v0, v0, v15814; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x40549a78, v05815; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v15816; SI-SDAG-NEXT: s_mov_b32 s4, 0x33979a375817; SI-SDAG-NEXT: v_rndne_f32_e32 v3, v15818; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, v25819; SI-SDAG-NEXT: v_sub_f32_e32 v1, v1, v35820; SI-SDAG-NEXT: v_add_f32_e32 v1, v1, v25821; SI-SDAG-NEXT: v_exp_f32_e32 v1, v15822; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v35823; SI-SDAG-NEXT: s_mov_b32 s4, 0xc23369f45824; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v05825; SI-SDAG-NEXT: s_mov_b32 s4, 0x421a209b5826; SI-SDAG-NEXT: v_ldexp_f32_e32 v1, v1, v25827; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc5828; SI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f8000005829; SI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v05830; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc5831; SI-SDAG-NEXT: s_setpc_b64 s[30:31]5832;5833; SI-GISEL-LABEL: v_exp10_f32_from_fpext_math_f16_daz:5834; SI-GISEL: ; %bb.0:5835; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5836; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v05837; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v15838; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x33979a375839; SI-GISEL-NEXT: v_mov_b32_e32 v5, 0x7f8000005840; SI-GISEL-NEXT: v_add_f32_e32 v0, v0, v15841; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v05842; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x40549a785843; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v05844; SI-GISEL-NEXT: v_mul_f32_e32 v3, 0x40549a78, v05845; SI-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v35846; SI-GISEL-NEXT: v_rndne_f32_e32 v4, v35847; SI-GISEL-NEXT: v_fma_f32 v1, v0, v2, v15848; SI-GISEL-NEXT: v_sub_f32_e32 v2, v3, v45849; SI-GISEL-NEXT: v_add_f32_e32 v1, v2, v15850; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v3, v45851; SI-GISEL-NEXT: v_exp_f32_e32 v1, v15852; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f45853; SI-GISEL-NEXT: v_mov_b32_e32 v4, 0x421a209b5854; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v25855; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, v1, v35856; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc5857; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v45858; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v5, vcc5859; SI-GISEL-NEXT: s_setpc_b64 s[30:31]5860;5861; R600-LABEL: v_exp10_f32_from_fpext_math_f16_daz:5862; R600: ; %bb.0:5863; R600-NEXT: CF_END5864; R600-NEXT: PAD5865;5866; CM-LABEL: v_exp10_f32_from_fpext_math_f16_daz:5867; CM: ; %bb.0:5868; CM-NEXT: CF_END5869; CM-NEXT: PAD5870 %src0 = bitcast i16 %src0.i to half5871 %src1 = bitcast i16 %src1.i to half5872 %fadd = fadd half %src0, %src15873 %fpext = fpext half %fadd to float5874 %result = call float @llvm.exp10.f32(float %fpext)5875 ret float %result5876}5877 5878; FIXME: Fold out fp16_to_fp (FP_TO_FP16) on no-f16 targets5879define half @v_exp10_f16(half %in) {5880; GCN-LABEL: v_exp10_f16:5881; GCN: ; %bb.0:5882; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5883; GCN-NEXT: v_cvt_f32_f16_e32 v0, v05884; GCN-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v05885; GCN-NEXT: v_exp_f32_e32 v0, v05886; GCN-NEXT: v_cvt_f16_f32_e32 v0, v05887; GCN-NEXT: s_setpc_b64 s[30:31]5888;5889; SI-SDAG-LABEL: v_exp10_f16:5890; SI-SDAG: ; %bb.0:5891; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5892; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v05893; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v05894; SI-SDAG-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v05895; SI-SDAG-NEXT: v_exp_f32_e32 v0, v05896; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v05897; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v05898; SI-SDAG-NEXT: s_setpc_b64 s[30:31]5899;5900; SI-GISEL-LABEL: v_exp10_f16:5901; SI-GISEL: ; %bb.0:5902; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5903; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v05904; SI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v05905; SI-GISEL-NEXT: v_exp_f32_e32 v0, v05906; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v05907; SI-GISEL-NEXT: s_setpc_b64 s[30:31]5908;5909; R600-LABEL: v_exp10_f16:5910; R600: ; %bb.0:5911; R600-NEXT: CF_END5912; R600-NEXT: PAD5913;5914; CM-LABEL: v_exp10_f16:5915; CM: ; %bb.0:5916; CM-NEXT: CF_END5917; CM-NEXT: PAD5918 %result = call half @llvm.exp10.f16(half %in)5919 ret half %result5920}5921 5922define half @v_exp10_fabs_f16(half %in) {5923; GCN-LABEL: v_exp10_fabs_f16:5924; GCN: ; %bb.0:5925; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5926; GCN-NEXT: v_cvt_f32_f16_e64 v0, |v0|5927; GCN-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v05928; GCN-NEXT: v_exp_f32_e32 v0, v05929; GCN-NEXT: v_cvt_f16_f32_e32 v0, v05930; GCN-NEXT: s_setpc_b64 s[30:31]5931;5932; SI-SDAG-LABEL: v_exp10_fabs_f16:5933; SI-SDAG: ; %bb.0:5934; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5935; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v05936; SI-SDAG-NEXT: v_cvt_f32_f16_e64 v0, |v0|5937; SI-SDAG-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v05938; SI-SDAG-NEXT: v_exp_f32_e32 v0, v05939; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v05940; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v05941; SI-SDAG-NEXT: s_setpc_b64 s[30:31]5942;5943; SI-GISEL-LABEL: v_exp10_fabs_f16:5944; SI-GISEL: ; %bb.0:5945; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5946; SI-GISEL-NEXT: v_cvt_f32_f16_e64 v0, |v0|5947; SI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v05948; SI-GISEL-NEXT: v_exp_f32_e32 v0, v05949; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v05950; SI-GISEL-NEXT: s_setpc_b64 s[30:31]5951;5952; R600-LABEL: v_exp10_fabs_f16:5953; R600: ; %bb.0:5954; R600-NEXT: CF_END5955; R600-NEXT: PAD5956;5957; CM-LABEL: v_exp10_fabs_f16:5958; CM: ; %bb.0:5959; CM-NEXT: CF_END5960; CM-NEXT: PAD5961 %fabs = call half @llvm.fabs.f16(half %in)5962 %result = call half @llvm.exp10.f16(half %fabs)5963 ret half %result5964}5965 5966define half @v_exp10_fneg_fabs_f16(half %in) {5967; GCN-SDAG-LABEL: v_exp10_fneg_fabs_f16:5968; GCN-SDAG: ; %bb.0:5969; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5970; GCN-SDAG-NEXT: v_cvt_f32_f16_e64 v0, |v0|5971; GCN-SDAG-NEXT: v_mul_f32_e32 v0, 0xbfb8aa3b, v05972; GCN-SDAG-NEXT: v_exp_f32_e32 v0, v05973; GCN-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v05974; GCN-SDAG-NEXT: s_setpc_b64 s[30:31]5975;5976; GCN-GISEL-LABEL: v_exp10_fneg_fabs_f16:5977; GCN-GISEL: ; %bb.0:5978; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5979; GCN-GISEL-NEXT: v_cvt_f32_f16_e64 v0, -|v0|5980; GCN-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v05981; GCN-GISEL-NEXT: v_exp_f32_e32 v0, v05982; GCN-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v05983; GCN-GISEL-NEXT: s_setpc_b64 s[30:31]5984;5985; SI-SDAG-LABEL: v_exp10_fneg_fabs_f16:5986; SI-SDAG: ; %bb.0:5987; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5988; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v05989; SI-SDAG-NEXT: v_cvt_f32_f16_e64 v0, |v0|5990; SI-SDAG-NEXT: v_mul_f32_e32 v0, 0xbfb8aa3b, v05991; SI-SDAG-NEXT: v_exp_f32_e32 v0, v05992; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v05993; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v05994; SI-SDAG-NEXT: s_setpc_b64 s[30:31]5995;5996; SI-GISEL-LABEL: v_exp10_fneg_fabs_f16:5997; SI-GISEL: ; %bb.0:5998; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5999; SI-GISEL-NEXT: v_cvt_f32_f16_e64 v0, -|v0|6000; SI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v06001; SI-GISEL-NEXT: v_exp_f32_e32 v0, v06002; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v06003; SI-GISEL-NEXT: s_setpc_b64 s[30:31]6004;6005; R600-LABEL: v_exp10_fneg_fabs_f16:6006; R600: ; %bb.0:6007; R600-NEXT: CF_END6008; R600-NEXT: PAD6009;6010; CM-LABEL: v_exp10_fneg_fabs_f16:6011; CM: ; %bb.0:6012; CM-NEXT: CF_END6013; CM-NEXT: PAD6014 %fabs = call half @llvm.fabs.f16(half %in)6015 %fneg.fabs = fneg half %fabs6016 %result = call half @llvm.exp10.f16(half %fneg.fabs)6017 ret half %result6018}6019 6020define half @v_exp10_fneg_f16(half %in) {6021; GCN-SDAG-LABEL: v_exp10_fneg_f16:6022; GCN-SDAG: ; %bb.0:6023; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6024; GCN-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v06025; GCN-SDAG-NEXT: v_mul_f32_e32 v0, 0xbfb8aa3b, v06026; GCN-SDAG-NEXT: v_exp_f32_e32 v0, v06027; GCN-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v06028; GCN-SDAG-NEXT: s_setpc_b64 s[30:31]6029;6030; GCN-GISEL-LABEL: v_exp10_fneg_f16:6031; GCN-GISEL: ; %bb.0:6032; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6033; GCN-GISEL-NEXT: v_cvt_f32_f16_e64 v0, -v06034; GCN-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v06035; GCN-GISEL-NEXT: v_exp_f32_e32 v0, v06036; GCN-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v06037; GCN-GISEL-NEXT: s_setpc_b64 s[30:31]6038;6039; SI-SDAG-LABEL: v_exp10_fneg_f16:6040; SI-SDAG: ; %bb.0:6041; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6042; SI-SDAG-NEXT: v_cvt_f16_f32_e64 v0, -v06043; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v06044; SI-SDAG-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v06045; SI-SDAG-NEXT: v_exp_f32_e32 v0, v06046; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v06047; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v06048; SI-SDAG-NEXT: s_setpc_b64 s[30:31]6049;6050; SI-GISEL-LABEL: v_exp10_fneg_f16:6051; SI-GISEL: ; %bb.0:6052; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6053; SI-GISEL-NEXT: v_cvt_f32_f16_e64 v0, -v06054; SI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v06055; SI-GISEL-NEXT: v_exp_f32_e32 v0, v06056; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v06057; SI-GISEL-NEXT: s_setpc_b64 s[30:31]6058;6059; R600-LABEL: v_exp10_fneg_f16:6060; R600: ; %bb.0:6061; R600-NEXT: CF_END6062; R600-NEXT: PAD6063;6064; CM-LABEL: v_exp10_fneg_f16:6065; CM: ; %bb.0:6066; CM-NEXT: CF_END6067; CM-NEXT: PAD6068 %fneg = fneg half %in6069 %result = call half @llvm.exp10.f16(half %fneg)6070 ret half %result6071}6072 6073define half @v_exp10_f16_fast(half %in) {6074; GCN-LABEL: v_exp10_f16_fast:6075; GCN: ; %bb.0:6076; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6077; GCN-NEXT: v_mul_f16_e32 v0, 0x3dc5, v06078; GCN-NEXT: v_exp_f16_e32 v0, v06079; GCN-NEXT: s_setpc_b64 s[30:31]6080;6081; SI-SDAG-LABEL: v_exp10_f16_fast:6082; SI-SDAG: ; %bb.0:6083; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6084; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v06085; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v06086; SI-SDAG-NEXT: v_mul_f32_e32 v0, 0x3fb8a000, v06087; SI-SDAG-NEXT: v_exp_f32_e32 v0, v06088; SI-SDAG-NEXT: s_setpc_b64 s[30:31]6089;6090; SI-GISEL-LABEL: v_exp10_f16_fast:6091; SI-GISEL: ; %bb.0:6092; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6093; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v06094; SI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8a000, v06095; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v06096; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v06097; SI-GISEL-NEXT: v_exp_f32_e32 v0, v06098; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v06099; SI-GISEL-NEXT: s_setpc_b64 s[30:31]6100;6101; R600-LABEL: v_exp10_f16_fast:6102; R600: ; %bb.0:6103; R600-NEXT: CF_END6104; R600-NEXT: PAD6105;6106; CM-LABEL: v_exp10_f16_fast:6107; CM: ; %bb.0:6108; CM-NEXT: CF_END6109; CM-NEXT: PAD6110 %result = call fast half @llvm.exp10.f16(half %in)6111 ret half %result6112}6113 6114define <2 x half> @v_exp10_v2f16(<2 x half> %in) {6115; VI-SDAG-LABEL: v_exp10_v2f16:6116; VI-SDAG: ; %bb.0:6117; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6118; VI-SDAG-NEXT: v_cvt_f32_f16_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_16119; VI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v06120; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v16121; VI-SDAG-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v06122; VI-SDAG-NEXT: v_exp_f32_e32 v1, v16123; VI-SDAG-NEXT: v_exp_f32_e32 v0, v06124; VI-SDAG-NEXT: v_cvt_f16_f32_sdwa v1, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD6125; VI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v06126; VI-SDAG-NEXT: v_or_b32_e32 v0, v0, v16127; VI-SDAG-NEXT: s_setpc_b64 s[30:31]6128;6129; VI-GISEL-LABEL: v_exp10_v2f16:6130; VI-GISEL: ; %bb.0:6131; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6132; VI-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v06133; VI-GISEL-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_16134; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v16135; VI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v06136; VI-GISEL-NEXT: v_exp_f32_e32 v1, v16137; VI-GISEL-NEXT: v_exp_f32_e32 v0, v06138; VI-GISEL-NEXT: v_cvt_f16_f32_e32 v1, v16139; VI-GISEL-NEXT: v_cvt_f16_f32_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD6140; VI-GISEL-NEXT: v_or_b32_e32 v0, v1, v06141; VI-GISEL-NEXT: s_setpc_b64 s[30:31]6142;6143; GFX900-LABEL: v_exp10_v2f16:6144; GFX900: ; %bb.0:6145; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6146; GFX900-NEXT: v_cvt_f32_f16_e32 v1, v06147; GFX900-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_16148; GFX900-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v16149; GFX900-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v06150; GFX900-NEXT: v_exp_f32_e32 v1, v16151; GFX900-NEXT: v_exp_f32_e32 v0, v06152; GFX900-NEXT: v_cvt_f16_f32_e32 v1, v16153; GFX900-NEXT: v_cvt_f16_f32_e32 v0, v06154; GFX900-NEXT: v_pack_b32_f16 v0, v1, v06155; GFX900-NEXT: s_setpc_b64 s[30:31]6156;6157; SI-SDAG-LABEL: v_exp10_v2f16:6158; SI-SDAG: ; %bb.0:6159; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6160; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v06161; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v1, v16162; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v06163; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v16164; SI-SDAG-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v06165; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v16166; SI-SDAG-NEXT: v_exp_f32_e32 v0, v06167; SI-SDAG-NEXT: v_exp_f32_e32 v1, v16168; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v06169; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v1, v16170; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v06171; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v16172; SI-SDAG-NEXT: s_setpc_b64 s[30:31]6173;6174; SI-GISEL-LABEL: v_exp10_v2f16:6175; SI-GISEL: ; %bb.0:6176; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6177; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v06178; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v16179; SI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v06180; SI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v16181; SI-GISEL-NEXT: v_exp_f32_e32 v0, v06182; SI-GISEL-NEXT: v_exp_f32_e32 v1, v16183; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v06184; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v1, v16185; SI-GISEL-NEXT: s_setpc_b64 s[30:31]6186;6187; R600-LABEL: v_exp10_v2f16:6188; R600: ; %bb.0:6189; R600-NEXT: CF_END6190; R600-NEXT: PAD6191;6192; CM-LABEL: v_exp10_v2f16:6193; CM: ; %bb.0:6194; CM-NEXT: CF_END6195; CM-NEXT: PAD6196 %result = call <2 x half> @llvm.exp10.v2f16(<2 x half> %in)6197 ret <2 x half> %result6198}6199 6200define <2 x half> @v_exp10_fabs_v2f16(<2 x half> %in) {6201; VI-SDAG-LABEL: v_exp10_fabs_v2f16:6202; VI-SDAG: ; %bb.0:6203; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6204; VI-SDAG-NEXT: v_cvt_f32_f16_sdwa v1, |v0| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_16205; VI-SDAG-NEXT: v_cvt_f32_f16_e64 v0, |v0|6206; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v16207; VI-SDAG-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v06208; VI-SDAG-NEXT: v_exp_f32_e32 v1, v16209; VI-SDAG-NEXT: v_exp_f32_e32 v0, v06210; VI-SDAG-NEXT: v_cvt_f16_f32_sdwa v1, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD6211; VI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v06212; VI-SDAG-NEXT: v_or_b32_e32 v0, v0, v16213; VI-SDAG-NEXT: s_setpc_b64 s[30:31]6214;6215; VI-GISEL-LABEL: v_exp10_fabs_v2f16:6216; VI-GISEL: ; %bb.0:6217; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6218; VI-GISEL-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v06219; VI-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v06220; VI-GISEL-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_16221; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v16222; VI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v06223; VI-GISEL-NEXT: v_exp_f32_e32 v1, v16224; VI-GISEL-NEXT: v_exp_f32_e32 v0, v06225; VI-GISEL-NEXT: v_cvt_f16_f32_e32 v1, v16226; VI-GISEL-NEXT: v_cvt_f16_f32_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD6227; VI-GISEL-NEXT: v_or_b32_e32 v0, v1, v06228; VI-GISEL-NEXT: s_setpc_b64 s[30:31]6229;6230; GFX900-SDAG-LABEL: v_exp10_fabs_v2f16:6231; GFX900-SDAG: ; %bb.0:6232; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6233; GFX900-SDAG-NEXT: v_cvt_f32_f16_e64 v1, |v0|6234; GFX900-SDAG-NEXT: v_cvt_f32_f16_sdwa v0, |v0| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_16235; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v16236; GFX900-SDAG-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v06237; GFX900-SDAG-NEXT: v_exp_f32_e32 v1, v16238; GFX900-SDAG-NEXT: v_exp_f32_e32 v0, v06239; GFX900-SDAG-NEXT: v_cvt_f16_f32_e32 v1, v16240; GFX900-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v06241; GFX900-SDAG-NEXT: v_pack_b32_f16 v0, v1, v06242; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]6243;6244; GFX900-GISEL-LABEL: v_exp10_fabs_v2f16:6245; GFX900-GISEL: ; %bb.0:6246; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6247; GFX900-GISEL-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v06248; GFX900-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v06249; GFX900-GISEL-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_16250; GFX900-GISEL-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v16251; GFX900-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v06252; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, v16253; GFX900-GISEL-NEXT: v_exp_f32_e32 v0, v06254; GFX900-GISEL-NEXT: v_cvt_f16_f32_e32 v1, v16255; GFX900-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v06256; GFX900-GISEL-NEXT: v_pack_b32_f16 v0, v1, v06257; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]6258;6259; SI-SDAG-LABEL: v_exp10_fabs_v2f16:6260; SI-SDAG: ; %bb.0:6261; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6262; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v06263; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v1, v16264; SI-SDAG-NEXT: v_cvt_f32_f16_e64 v0, |v0|6265; SI-SDAG-NEXT: v_cvt_f32_f16_e64 v1, |v1|6266; SI-SDAG-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v06267; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v16268; SI-SDAG-NEXT: v_exp_f32_e32 v0, v06269; SI-SDAG-NEXT: v_exp_f32_e32 v1, v16270; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v06271; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v1, v16272; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v06273; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v16274; SI-SDAG-NEXT: s_setpc_b64 s[30:31]6275;6276; SI-GISEL-LABEL: v_exp10_fabs_v2f16:6277; SI-GISEL: ; %bb.0:6278; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6279; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v16280; SI-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v06281; SI-GISEL-NEXT: v_or_b32_e32 v0, v1, v06282; SI-GISEL-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v06283; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v06284; SI-GISEL-NEXT: v_lshrrev_b32_e32 v0, 16, v06285; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v06286; SI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v16287; SI-GISEL-NEXT: v_exp_f32_e32 v1, v16288; SI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v06289; SI-GISEL-NEXT: v_exp_f32_e32 v2, v06290; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v16291; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v1, v26292; SI-GISEL-NEXT: s_setpc_b64 s[30:31]6293;6294; R600-LABEL: v_exp10_fabs_v2f16:6295; R600: ; %bb.0:6296; R600-NEXT: CF_END6297; R600-NEXT: PAD6298;6299; CM-LABEL: v_exp10_fabs_v2f16:6300; CM: ; %bb.0:6301; CM-NEXT: CF_END6302; CM-NEXT: PAD6303 %fabs = call <2 x half> @llvm.fabs.v2f16(<2 x half> %in)6304 %result = call <2 x half> @llvm.exp10.v2f16(<2 x half> %fabs)6305 ret <2 x half> %result6306}6307 6308define <2 x half> @v_exp10_fneg_fabs_v2f16(<2 x half> %in) {6309; VI-SDAG-LABEL: v_exp10_fneg_fabs_v2f16:6310; VI-SDAG: ; %bb.0:6311; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6312; VI-SDAG-NEXT: v_cvt_f32_f16_sdwa v1, -|v0| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_16313; VI-SDAG-NEXT: v_cvt_f32_f16_e64 v0, -|v0|6314; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v16315; VI-SDAG-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v06316; VI-SDAG-NEXT: v_exp_f32_e32 v1, v16317; VI-SDAG-NEXT: v_exp_f32_e32 v0, v06318; VI-SDAG-NEXT: v_cvt_f16_f32_sdwa v1, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD6319; VI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v06320; VI-SDAG-NEXT: v_or_b32_e32 v0, v0, v16321; VI-SDAG-NEXT: s_setpc_b64 s[30:31]6322;6323; VI-GISEL-LABEL: v_exp10_fneg_fabs_v2f16:6324; VI-GISEL: ; %bb.0:6325; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6326; VI-GISEL-NEXT: v_or_b32_e32 v0, 0x80008000, v06327; VI-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v06328; VI-GISEL-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_16329; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v16330; VI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v06331; VI-GISEL-NEXT: v_exp_f32_e32 v1, v16332; VI-GISEL-NEXT: v_exp_f32_e32 v0, v06333; VI-GISEL-NEXT: v_cvt_f16_f32_e32 v1, v16334; VI-GISEL-NEXT: v_cvt_f16_f32_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD6335; VI-GISEL-NEXT: v_or_b32_e32 v0, v1, v06336; VI-GISEL-NEXT: s_setpc_b64 s[30:31]6337;6338; GFX900-SDAG-LABEL: v_exp10_fneg_fabs_v2f16:6339; GFX900-SDAG: ; %bb.0:6340; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6341; GFX900-SDAG-NEXT: v_cvt_f32_f16_e64 v1, -|v0|6342; GFX900-SDAG-NEXT: v_cvt_f32_f16_sdwa v0, -|v0| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_16343; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v16344; GFX900-SDAG-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v06345; GFX900-SDAG-NEXT: v_exp_f32_e32 v1, v16346; GFX900-SDAG-NEXT: v_exp_f32_e32 v0, v06347; GFX900-SDAG-NEXT: v_cvt_f16_f32_e32 v1, v16348; GFX900-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v06349; GFX900-SDAG-NEXT: v_pack_b32_f16 v0, v1, v06350; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]6351;6352; GFX900-GISEL-LABEL: v_exp10_fneg_fabs_v2f16:6353; GFX900-GISEL: ; %bb.0:6354; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6355; GFX900-GISEL-NEXT: v_or_b32_e32 v0, 0x80008000, v06356; GFX900-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v06357; GFX900-GISEL-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_16358; GFX900-GISEL-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v16359; GFX900-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v06360; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, v16361; GFX900-GISEL-NEXT: v_exp_f32_e32 v0, v06362; GFX900-GISEL-NEXT: v_cvt_f16_f32_e32 v1, v16363; GFX900-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v06364; GFX900-GISEL-NEXT: v_pack_b32_f16 v0, v1, v06365; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]6366;6367; SI-SDAG-LABEL: v_exp10_fneg_fabs_v2f16:6368; SI-SDAG: ; %bb.0:6369; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6370; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v1, v16371; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v06372; SI-SDAG-NEXT: v_lshlrev_b32_e32 v1, 16, v16373; SI-SDAG-NEXT: v_or_b32_e32 v0, v0, v16374; SI-SDAG-NEXT: v_or_b32_e32 v0, 0x80008000, v06375; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v06376; SI-SDAG-NEXT: v_lshrrev_b32_e32 v0, 16, v06377; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v06378; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v16379; SI-SDAG-NEXT: v_exp_f32_e32 v1, v16380; SI-SDAG-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v06381; SI-SDAG-NEXT: v_exp_f32_e32 v0, v06382; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v1, v16383; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v2, v06384; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v16385; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v26386; SI-SDAG-NEXT: s_setpc_b64 s[30:31]6387;6388; SI-GISEL-LABEL: v_exp10_fneg_fabs_v2f16:6389; SI-GISEL: ; %bb.0:6390; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6391; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v16392; SI-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v06393; SI-GISEL-NEXT: v_or_b32_e32 v0, v1, v06394; SI-GISEL-NEXT: v_or_b32_e32 v0, 0x80008000, v06395; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v06396; SI-GISEL-NEXT: v_lshrrev_b32_e32 v0, 16, v06397; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v06398; SI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v16399; SI-GISEL-NEXT: v_exp_f32_e32 v1, v16400; SI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v06401; SI-GISEL-NEXT: v_exp_f32_e32 v2, v06402; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v16403; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v1, v26404; SI-GISEL-NEXT: s_setpc_b64 s[30:31]6405;6406; R600-LABEL: v_exp10_fneg_fabs_v2f16:6407; R600: ; %bb.0:6408; R600-NEXT: CF_END6409; R600-NEXT: PAD6410;6411; CM-LABEL: v_exp10_fneg_fabs_v2f16:6412; CM: ; %bb.0:6413; CM-NEXT: CF_END6414; CM-NEXT: PAD6415 %fabs = call <2 x half> @llvm.fabs.v2f16(<2 x half> %in)6416 %fneg.fabs = fneg <2 x half> %fabs6417 %result = call <2 x half> @llvm.exp10.v2f16(<2 x half> %fneg.fabs)6418 ret <2 x half> %result6419}6420 6421define <2 x half> @v_exp10_fneg_v2f16(<2 x half> %in) {6422; VI-SDAG-LABEL: v_exp10_fneg_v2f16:6423; VI-SDAG: ; %bb.0:6424; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6425; VI-SDAG-NEXT: v_cvt_f32_f16_sdwa v1, -v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_16426; VI-SDAG-NEXT: v_cvt_f32_f16_e64 v0, -v06427; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v16428; VI-SDAG-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v06429; VI-SDAG-NEXT: v_exp_f32_e32 v1, v16430; VI-SDAG-NEXT: v_exp_f32_e32 v0, v06431; VI-SDAG-NEXT: v_cvt_f16_f32_sdwa v1, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD6432; VI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v06433; VI-SDAG-NEXT: v_or_b32_e32 v0, v0, v16434; VI-SDAG-NEXT: s_setpc_b64 s[30:31]6435;6436; VI-GISEL-LABEL: v_exp10_fneg_v2f16:6437; VI-GISEL: ; %bb.0:6438; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6439; VI-GISEL-NEXT: v_xor_b32_e32 v0, 0x80008000, v06440; VI-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v06441; VI-GISEL-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_16442; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v16443; VI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v06444; VI-GISEL-NEXT: v_exp_f32_e32 v1, v16445; VI-GISEL-NEXT: v_exp_f32_e32 v0, v06446; VI-GISEL-NEXT: v_cvt_f16_f32_e32 v1, v16447; VI-GISEL-NEXT: v_cvt_f16_f32_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD6448; VI-GISEL-NEXT: v_or_b32_e32 v0, v1, v06449; VI-GISEL-NEXT: s_setpc_b64 s[30:31]6450;6451; GFX900-SDAG-LABEL: v_exp10_fneg_v2f16:6452; GFX900-SDAG: ; %bb.0:6453; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6454; GFX900-SDAG-NEXT: v_cvt_f32_f16_e64 v1, -v06455; GFX900-SDAG-NEXT: v_cvt_f32_f16_sdwa v0, -v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_16456; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v16457; GFX900-SDAG-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v06458; GFX900-SDAG-NEXT: v_exp_f32_e32 v1, v16459; GFX900-SDAG-NEXT: v_exp_f32_e32 v0, v06460; GFX900-SDAG-NEXT: v_cvt_f16_f32_e32 v1, v16461; GFX900-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v06462; GFX900-SDAG-NEXT: v_pack_b32_f16 v0, v1, v06463; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]6464;6465; GFX900-GISEL-LABEL: v_exp10_fneg_v2f16:6466; GFX900-GISEL: ; %bb.0:6467; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6468; GFX900-GISEL-NEXT: v_xor_b32_e32 v0, 0x80008000, v06469; GFX900-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v06470; GFX900-GISEL-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_16471; GFX900-GISEL-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v16472; GFX900-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v06473; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, v16474; GFX900-GISEL-NEXT: v_exp_f32_e32 v0, v06475; GFX900-GISEL-NEXT: v_cvt_f16_f32_e32 v1, v16476; GFX900-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v06477; GFX900-GISEL-NEXT: v_pack_b32_f16 v0, v1, v06478; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]6479;6480; SI-SDAG-LABEL: v_exp10_fneg_v2f16:6481; SI-SDAG: ; %bb.0:6482; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6483; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v1, v16484; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v06485; SI-SDAG-NEXT: v_lshlrev_b32_e32 v1, 16, v16486; SI-SDAG-NEXT: v_or_b32_e32 v0, v0, v16487; SI-SDAG-NEXT: v_xor_b32_e32 v0, 0x80008000, v06488; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v06489; SI-SDAG-NEXT: v_lshrrev_b32_e32 v0, 16, v06490; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v06491; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v16492; SI-SDAG-NEXT: v_exp_f32_e32 v1, v16493; SI-SDAG-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v06494; SI-SDAG-NEXT: v_exp_f32_e32 v0, v06495; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v1, v16496; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v2, v06497; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v16498; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v26499; SI-SDAG-NEXT: s_setpc_b64 s[30:31]6500;6501; SI-GISEL-LABEL: v_exp10_fneg_v2f16:6502; SI-GISEL: ; %bb.0:6503; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6504; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v16505; SI-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v06506; SI-GISEL-NEXT: v_or_b32_e32 v0, v1, v06507; SI-GISEL-NEXT: v_xor_b32_e32 v0, 0x80008000, v06508; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v06509; SI-GISEL-NEXT: v_lshrrev_b32_e32 v0, 16, v06510; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v06511; SI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v16512; SI-GISEL-NEXT: v_exp_f32_e32 v1, v16513; SI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v06514; SI-GISEL-NEXT: v_exp_f32_e32 v2, v06515; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v16516; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v1, v26517; SI-GISEL-NEXT: s_setpc_b64 s[30:31]6518;6519; R600-LABEL: v_exp10_fneg_v2f16:6520; R600: ; %bb.0:6521; R600-NEXT: CF_END6522; R600-NEXT: PAD6523;6524; CM-LABEL: v_exp10_fneg_v2f16:6525; CM: ; %bb.0:6526; CM-NEXT: CF_END6527; CM-NEXT: PAD6528 %fneg = fneg <2 x half> %in6529 %result = call <2 x half> @llvm.exp10.v2f16(<2 x half> %fneg)6530 ret <2 x half> %result6531}6532 6533define <2 x half> @v_exp10_v2f16_fast(<2 x half> %in) {6534; VI-SDAG-LABEL: v_exp10_v2f16_fast:6535; VI-SDAG: ; %bb.0:6536; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6537; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x3dc56538; VI-SDAG-NEXT: v_mul_f16_sdwa v1, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD6539; VI-SDAG-NEXT: v_mul_f16_e32 v0, 0x3dc5, v06540; VI-SDAG-NEXT: v_exp_f16_sdwa v1, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD6541; VI-SDAG-NEXT: v_exp_f16_e32 v0, v06542; VI-SDAG-NEXT: v_or_b32_e32 v0, v0, v16543; VI-SDAG-NEXT: s_setpc_b64 s[30:31]6544;6545; VI-GISEL-LABEL: v_exp10_v2f16_fast:6546; VI-GISEL: ; %bb.0:6547; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6548; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3dc56549; VI-GISEL-NEXT: v_mul_f16_e32 v2, 0x3dc5, v06550; VI-GISEL-NEXT: v_mul_f16_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD6551; VI-GISEL-NEXT: v_exp_f16_e32 v2, v26552; VI-GISEL-NEXT: v_exp_f16_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD6553; VI-GISEL-NEXT: v_or_b32_e32 v0, v2, v06554; VI-GISEL-NEXT: s_setpc_b64 s[30:31]6555;6556; GFX900-SDAG-LABEL: v_exp10_v2f16_fast:6557; GFX900-SDAG: ; %bb.0:6558; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6559; GFX900-SDAG-NEXT: s_movk_i32 s4, 0x3dc56560; GFX900-SDAG-NEXT: v_mul_f16_e32 v1, 0x3dc5, v06561; GFX900-SDAG-NEXT: v_mul_f16_sdwa v0, v0, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD6562; GFX900-SDAG-NEXT: v_exp_f16_e32 v1, v16563; GFX900-SDAG-NEXT: v_exp_f16_e32 v0, v06564; GFX900-SDAG-NEXT: v_pack_b32_f16 v0, v1, v06565; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]6566;6567; GFX900-GISEL-LABEL: v_exp10_v2f16_fast:6568; GFX900-GISEL: ; %bb.0:6569; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6570; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3dc56571; GFX900-GISEL-NEXT: v_mul_f16_e32 v2, 0x3dc5, v06572; GFX900-GISEL-NEXT: v_mul_f16_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD6573; GFX900-GISEL-NEXT: v_exp_f16_e32 v2, v26574; GFX900-GISEL-NEXT: v_exp_f16_e32 v0, v06575; GFX900-GISEL-NEXT: v_lshl_or_b32 v0, v0, 16, v26576; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]6577;6578; SI-SDAG-LABEL: v_exp10_v2f16_fast:6579; SI-SDAG: ; %bb.0:6580; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6581; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v06582; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v1, v16583; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v06584; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v16585; SI-SDAG-NEXT: v_mul_f32_e32 v0, 0x3fb8a000, v06586; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8a000, v16587; SI-SDAG-NEXT: v_exp_f32_e32 v0, v06588; SI-SDAG-NEXT: v_exp_f32_e32 v1, v16589; SI-SDAG-NEXT: s_setpc_b64 s[30:31]6590;6591; SI-GISEL-LABEL: v_exp10_v2f16_fast:6592; SI-GISEL: ; %bb.0:6593; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6594; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v06595; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v16596; SI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8a000, v06597; SI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3fb8a000, v16598; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v06599; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v1, v16600; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v06601; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v16602; SI-GISEL-NEXT: v_exp_f32_e32 v0, v06603; SI-GISEL-NEXT: v_exp_f32_e32 v1, v16604; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v06605; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v1, v16606; SI-GISEL-NEXT: s_setpc_b64 s[30:31]6607;6608; R600-LABEL: v_exp10_v2f16_fast:6609; R600: ; %bb.0:6610; R600-NEXT: CF_END6611; R600-NEXT: PAD6612;6613; CM-LABEL: v_exp10_v2f16_fast:6614; CM: ; %bb.0:6615; CM-NEXT: CF_END6616; CM-NEXT: PAD6617 %result = call fast <2 x half> @llvm.exp10.v2f16(<2 x half> %in)6618 ret <2 x half> %result6619}6620 6621define <3 x half> @v_exp10_v3f16(<3 x half> %in) {6622; VI-LABEL: v_exp10_v3f16:6623; VI: ; %bb.0:6624; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6625; VI-NEXT: v_cvt_f32_f16_e32 v2, v06626; VI-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_16627; VI-NEXT: v_cvt_f32_f16_e32 v1, v16628; VI-NEXT: v_mul_f32_e32 v2, 0x3fb8aa3b, v26629; VI-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v06630; VI-NEXT: v_exp_f32_e32 v2, v26631; VI-NEXT: v_exp_f32_e32 v0, v06632; VI-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v16633; VI-NEXT: v_exp_f32_e32 v1, v16634; VI-NEXT: v_cvt_f16_f32_e32 v2, v26635; VI-NEXT: v_cvt_f16_f32_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD6636; VI-NEXT: v_cvt_f16_f32_e32 v1, v16637; VI-NEXT: v_or_b32_e32 v0, v2, v06638; VI-NEXT: s_setpc_b64 s[30:31]6639;6640; GFX900-LABEL: v_exp10_v3f16:6641; GFX900: ; %bb.0:6642; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6643; GFX900-NEXT: v_cvt_f32_f16_e32 v2, v06644; GFX900-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_16645; GFX900-NEXT: v_cvt_f32_f16_e32 v1, v16646; GFX900-NEXT: v_mul_f32_e32 v2, 0x3fb8aa3b, v26647; GFX900-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v06648; GFX900-NEXT: v_exp_f32_e32 v2, v26649; GFX900-NEXT: v_exp_f32_e32 v0, v06650; GFX900-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v16651; GFX900-NEXT: v_exp_f32_e32 v1, v16652; GFX900-NEXT: v_cvt_f16_f32_e32 v2, v26653; GFX900-NEXT: v_cvt_f16_f32_e32 v0, v06654; GFX900-NEXT: v_cvt_f16_f32_e32 v1, v16655; GFX900-NEXT: v_pack_b32_f16 v0, v2, v06656; GFX900-NEXT: s_setpc_b64 s[30:31]6657;6658; SI-SDAG-LABEL: v_exp10_v3f16:6659; SI-SDAG: ; %bb.0:6660; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6661; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v06662; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v1, v16663; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v2, v26664; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v06665; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v16666; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v2, v26667; SI-SDAG-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v06668; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v16669; SI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3fb8aa3b, v26670; SI-SDAG-NEXT: v_exp_f32_e32 v0, v06671; SI-SDAG-NEXT: v_exp_f32_e32 v1, v16672; SI-SDAG-NEXT: v_exp_f32_e32 v2, v26673; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v06674; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v1, v16675; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v2, v26676; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v06677; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v16678; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v2, v26679; SI-SDAG-NEXT: s_setpc_b64 s[30:31]6680;6681; SI-GISEL-LABEL: v_exp10_v3f16:6682; SI-GISEL: ; %bb.0:6683; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6684; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v06685; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v16686; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v2, v26687; SI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v06688; SI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v16689; SI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3fb8aa3b, v26690; SI-GISEL-NEXT: v_exp_f32_e32 v0, v06691; SI-GISEL-NEXT: v_exp_f32_e32 v1, v16692; SI-GISEL-NEXT: v_exp_f32_e32 v2, v26693; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v06694; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v1, v16695; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v2, v26696; SI-GISEL-NEXT: s_setpc_b64 s[30:31]6697;6698; R600-LABEL: v_exp10_v3f16:6699; R600: ; %bb.0:6700; R600-NEXT: CF_END6701; R600-NEXT: PAD6702;6703; CM-LABEL: v_exp10_v3f16:6704; CM: ; %bb.0:6705; CM-NEXT: CF_END6706; CM-NEXT: PAD6707 %result = call <3 x half> @llvm.exp10.v3f16(<3 x half> %in)6708 ret <3 x half> %result6709}6710 6711define <3 x half> @v_exp10_v3f16_afn(<3 x half> %in) {6712; VI-SDAG-LABEL: v_exp10_v3f16_afn:6713; VI-SDAG: ; %bb.0:6714; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6715; VI-SDAG-NEXT: v_mov_b32_e32 v3, 0x3dc56716; VI-SDAG-NEXT: v_mul_f16_e32 v2, 0x3dc5, v06717; VI-SDAG-NEXT: v_mul_f16_sdwa v0, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD6718; VI-SDAG-NEXT: v_exp_f16_e32 v2, v26719; VI-SDAG-NEXT: v_exp_f16_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD6720; VI-SDAG-NEXT: v_mul_f16_e32 v1, 0x3dc5, v16721; VI-SDAG-NEXT: v_exp_f16_e32 v1, v16722; VI-SDAG-NEXT: v_or_b32_e32 v0, v2, v06723; VI-SDAG-NEXT: s_setpc_b64 s[30:31]6724;6725; VI-GISEL-LABEL: v_exp10_v3f16_afn:6726; VI-GISEL: ; %bb.0:6727; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6728; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x3dc56729; VI-GISEL-NEXT: v_mul_f16_e32 v3, 0x3dc5, v06730; VI-GISEL-NEXT: v_mul_f16_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD6731; VI-GISEL-NEXT: v_exp_f16_e32 v3, v36732; VI-GISEL-NEXT: v_exp_f16_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD6733; VI-GISEL-NEXT: v_mul_f16_e32 v1, 0x3dc5, v16734; VI-GISEL-NEXT: v_exp_f16_e32 v1, v16735; VI-GISEL-NEXT: v_or_b32_e32 v0, v3, v06736; VI-GISEL-NEXT: s_setpc_b64 s[30:31]6737;6738; GFX900-SDAG-LABEL: v_exp10_v3f16_afn:6739; GFX900-SDAG: ; %bb.0:6740; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6741; GFX900-SDAG-NEXT: s_movk_i32 s4, 0x3dc56742; GFX900-SDAG-NEXT: v_mul_f16_e32 v2, 0x3dc5, v06743; GFX900-SDAG-NEXT: v_mul_f16_sdwa v0, v0, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD6744; GFX900-SDAG-NEXT: v_exp_f16_e32 v2, v26745; GFX900-SDAG-NEXT: v_exp_f16_e32 v0, v06746; GFX900-SDAG-NEXT: v_mul_f16_e32 v1, 0x3dc5, v16747; GFX900-SDAG-NEXT: v_exp_f16_e32 v1, v16748; GFX900-SDAG-NEXT: v_pack_b32_f16 v0, v2, v06749; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]6750;6751; GFX900-GISEL-LABEL: v_exp10_v3f16_afn:6752; GFX900-GISEL: ; %bb.0:6753; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6754; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x3dc56755; GFX900-GISEL-NEXT: v_mul_f16_e32 v3, 0x3dc5, v06756; GFX900-GISEL-NEXT: v_mul_f16_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD6757; GFX900-GISEL-NEXT: v_exp_f16_e32 v3, v36758; GFX900-GISEL-NEXT: v_exp_f16_e32 v0, v06759; GFX900-GISEL-NEXT: v_mul_f16_e32 v1, 0x3dc5, v16760; GFX900-GISEL-NEXT: v_exp_f16_e32 v1, v16761; GFX900-GISEL-NEXT: v_lshl_or_b32 v0, v0, 16, v36762; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]6763;6764; SI-SDAG-LABEL: v_exp10_v3f16_afn:6765; SI-SDAG: ; %bb.0:6766; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6767; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v06768; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v1, v16769; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v2, v26770; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v06771; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v16772; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v2, v26773; SI-SDAG-NEXT: v_mul_f32_e32 v0, 0x3fb8a000, v06774; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8a000, v16775; SI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v26776; SI-SDAG-NEXT: v_exp_f32_e32 v0, v06777; SI-SDAG-NEXT: v_exp_f32_e32 v1, v16778; SI-SDAG-NEXT: v_exp_f32_e32 v2, v26779; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v06780; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v1, v16781; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v2, v26782; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v06783; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v16784; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v2, v26785; SI-SDAG-NEXT: s_setpc_b64 s[30:31]6786;6787; SI-GISEL-LABEL: v_exp10_v3f16_afn:6788; SI-GISEL: ; %bb.0:6789; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6790; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v06791; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v16792; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v2, v26793; SI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8a000, v06794; SI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3fb8a000, v16795; SI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v26796; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v06797; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v1, v16798; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v2, v26799; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v06800; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v16801; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v2, v26802; SI-GISEL-NEXT: v_exp_f32_e32 v0, v06803; SI-GISEL-NEXT: v_exp_f32_e32 v1, v16804; SI-GISEL-NEXT: v_exp_f32_e32 v2, v26805; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v06806; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v1, v16807; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v2, v26808; SI-GISEL-NEXT: s_setpc_b64 s[30:31]6809;6810; R600-LABEL: v_exp10_v3f16_afn:6811; R600: ; %bb.0:6812; R600-NEXT: CF_END6813; R600-NEXT: PAD6814;6815; CM-LABEL: v_exp10_v3f16_afn:6816; CM: ; %bb.0:6817; CM-NEXT: CF_END6818; CM-NEXT: PAD6819 %result = call afn <3 x half> @llvm.exp10.v3f16(<3 x half> %in)6820 ret <3 x half> %result6821}6822 6823define float @v_exp10_f32_contract(float %in) {6824; VI-SDAG-LABEL: v_exp10_f32_contract:6825; VI-SDAG: ; %bb.0:6826; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6827; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v06828; VI-SDAG-NEXT: v_sub_f32_e32 v4, v0, v16829; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x40549000, v16830; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x3a2784bc, v46831; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x40549000, v46832; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v26833; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v56834; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v16835; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v36836; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v46837; VI-SDAG-NEXT: v_add_f32_e32 v1, v2, v16838; VI-SDAG-NEXT: v_exp_f32_e32 v1, v16839; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v36840; VI-SDAG-NEXT: s_mov_b32 s4, 0xc23369f46841; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v06842; VI-SDAG-NEXT: s_mov_b32 s4, 0x421a209b6843; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v26844; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc6845; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f8000006846; VI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v06847; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc6848; VI-SDAG-NEXT: s_setpc_b64 s[30:31]6849;6850; VI-GISEL-LABEL: v_exp10_f32_contract:6851; VI-GISEL: ; %bb.0:6852; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6853; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v06854; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v16855; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3a2784bc, v26856; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549000, v26857; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x40549000, v16858; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v46859; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v16860; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v26861; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v36862; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v26863; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v16864; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v26865; VI-GISEL-NEXT: v_exp_f32_e32 v1, v16866; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f8000006867; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v26868; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f46869; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v26870; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x421a209b6871; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc6872; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v26873; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc6874; VI-GISEL-NEXT: s_setpc_b64 s[30:31]6875;6876; GFX900-SDAG-LABEL: v_exp10_f32_contract:6877; GFX900-SDAG: ; %bb.0:6878; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6879; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x40549a78, v06880; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x40549a786881; GFX900-SDAG-NEXT: v_rndne_f32_e32 v2, v16882; GFX900-SDAG-NEXT: v_sub_f32_e32 v3, v1, v26883; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v16884; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x33979a376885; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, v16886; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v3, v16887; GFX900-SDAG-NEXT: v_exp_f32_e32 v1, v16888; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v26889; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xc23369f46890; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v06891; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x421a209b6892; GFX900-SDAG-NEXT: v_ldexp_f32 v1, v1, v26893; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc6894; GFX900-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f8000006895; GFX900-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v06896; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc6897; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]6898;6899; GFX900-GISEL-LABEL: v_exp10_f32_contract:6900; GFX900-GISEL: ; %bb.0:6901; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6902; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x40549a786903; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549a78, v06904; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v26905; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x33979a376906; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v3, v16907; GFX900-GISEL-NEXT: v_rndne_f32_e32 v3, v26908; GFX900-GISEL-NEXT: v_sub_f32_e32 v2, v2, v36909; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v2, v16910; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v36911; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, v16912; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f8000006913; GFX900-GISEL-NEXT: v_ldexp_f32 v1, v1, v26914; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f46915; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v26916; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x421a209b6917; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc6918; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v26919; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc6920; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]6921;6922; SI-SDAG-LABEL: v_exp10_f32_contract:6923; SI-SDAG: ; %bb.0:6924; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6925; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x40549a78, v06926; SI-SDAG-NEXT: s_mov_b32 s4, 0x40549a786927; SI-SDAG-NEXT: v_rndne_f32_e32 v2, v16928; SI-SDAG-NEXT: v_sub_f32_e32 v3, v1, v26929; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v16930; SI-SDAG-NEXT: s_mov_b32 s4, 0x33979a376931; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, v16932; SI-SDAG-NEXT: v_add_f32_e32 v1, v3, v16933; SI-SDAG-NEXT: v_exp_f32_e32 v1, v16934; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v26935; SI-SDAG-NEXT: s_mov_b32 s4, 0xc23369f46936; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v06937; SI-SDAG-NEXT: s_mov_b32 s4, 0x421a209b6938; SI-SDAG-NEXT: v_ldexp_f32_e32 v1, v1, v26939; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc6940; SI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f8000006941; SI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v06942; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc6943; SI-SDAG-NEXT: s_setpc_b64 s[30:31]6944;6945; SI-GISEL-LABEL: v_exp10_f32_contract:6946; SI-GISEL: ; %bb.0:6947; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6948; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x40549a786949; SI-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549a78, v06950; SI-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v26951; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x33979a376952; SI-GISEL-NEXT: v_fma_f32 v1, v0, v3, v16953; SI-GISEL-NEXT: v_rndne_f32_e32 v3, v26954; SI-GISEL-NEXT: v_sub_f32_e32 v2, v2, v36955; SI-GISEL-NEXT: v_add_f32_e32 v1, v2, v16956; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v36957; SI-GISEL-NEXT: v_exp_f32_e32 v1, v16958; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f8000006959; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, v1, v26960; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f46961; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v26962; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x421a209b6963; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc6964; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v26965; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc6966; SI-GISEL-NEXT: s_setpc_b64 s[30:31]6967;6968; R600-LABEL: v_exp10_f32_contract:6969; R600: ; %bb.0:6970; R600-NEXT: CF_END6971; R600-NEXT: PAD6972;6973; CM-LABEL: v_exp10_f32_contract:6974; CM: ; %bb.0:6975; CM-NEXT: CF_END6976; CM-NEXT: PAD6977 %result = call contract float @llvm.exp10.f32(float %in)6978 ret float %result6979}6980 6981define float @v_exp10_f32_contract_daz(float %in) #0 {6982; VI-SDAG-LABEL: v_exp10_f32_contract_daz:6983; VI-SDAG: ; %bb.0:6984; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6985; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v06986; VI-SDAG-NEXT: v_sub_f32_e32 v4, v0, v16987; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x40549000, v16988; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x3a2784bc, v46989; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x40549000, v46990; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v26991; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v56992; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v16993; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v36994; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v46995; VI-SDAG-NEXT: v_add_f32_e32 v1, v2, v16996; VI-SDAG-NEXT: v_exp_f32_e32 v1, v16997; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v36998; VI-SDAG-NEXT: s_mov_b32 s4, 0xc23369f46999; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v07000; VI-SDAG-NEXT: s_mov_b32 s4, 0x421a209b7001; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v27002; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc7003; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f8000007004; VI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v07005; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc7006; VI-SDAG-NEXT: s_setpc_b64 s[30:31]7007;7008; VI-GISEL-LABEL: v_exp10_f32_contract_daz:7009; VI-GISEL: ; %bb.0:7010; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7011; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v07012; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v17013; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3a2784bc, v27014; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549000, v27015; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x40549000, v17016; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v47017; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v17018; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v27019; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v37020; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v27021; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v17022; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v27023; VI-GISEL-NEXT: v_exp_f32_e32 v1, v17024; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f8000007025; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v27026; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f47027; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v27028; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x421a209b7029; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc7030; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v27031; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc7032; VI-GISEL-NEXT: s_setpc_b64 s[30:31]7033;7034; GFX900-SDAG-LABEL: v_exp10_f32_contract_daz:7035; GFX900-SDAG: ; %bb.0:7036; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7037; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x40549a78, v07038; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x40549a787039; GFX900-SDAG-NEXT: v_rndne_f32_e32 v2, v17040; GFX900-SDAG-NEXT: v_sub_f32_e32 v3, v1, v27041; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v17042; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x33979a377043; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, v17044; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v3, v17045; GFX900-SDAG-NEXT: v_exp_f32_e32 v1, v17046; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v27047; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xc23369f47048; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v07049; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x421a209b7050; GFX900-SDAG-NEXT: v_ldexp_f32 v1, v1, v27051; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc7052; GFX900-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f8000007053; GFX900-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v07054; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc7055; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]7056;7057; GFX900-GISEL-LABEL: v_exp10_f32_contract_daz:7058; GFX900-GISEL: ; %bb.0:7059; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7060; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x40549a787061; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549a78, v07062; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v27063; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x33979a377064; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v3, v17065; GFX900-GISEL-NEXT: v_rndne_f32_e32 v3, v27066; GFX900-GISEL-NEXT: v_sub_f32_e32 v2, v2, v37067; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v2, v17068; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v37069; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, v17070; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f8000007071; GFX900-GISEL-NEXT: v_ldexp_f32 v1, v1, v27072; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f47073; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v27074; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x421a209b7075; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc7076; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v27077; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc7078; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]7079;7080; SI-SDAG-LABEL: v_exp10_f32_contract_daz:7081; SI-SDAG: ; %bb.0:7082; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7083; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x40549a78, v07084; SI-SDAG-NEXT: s_mov_b32 s4, 0x40549a787085; SI-SDAG-NEXT: v_rndne_f32_e32 v2, v17086; SI-SDAG-NEXT: v_sub_f32_e32 v3, v1, v27087; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v17088; SI-SDAG-NEXT: s_mov_b32 s4, 0x33979a377089; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, v17090; SI-SDAG-NEXT: v_add_f32_e32 v1, v3, v17091; SI-SDAG-NEXT: v_exp_f32_e32 v1, v17092; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v27093; SI-SDAG-NEXT: s_mov_b32 s4, 0xc23369f47094; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v07095; SI-SDAG-NEXT: s_mov_b32 s4, 0x421a209b7096; SI-SDAG-NEXT: v_ldexp_f32_e32 v1, v1, v27097; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc7098; SI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f8000007099; SI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v07100; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc7101; SI-SDAG-NEXT: s_setpc_b64 s[30:31]7102;7103; SI-GISEL-LABEL: v_exp10_f32_contract_daz:7104; SI-GISEL: ; %bb.0:7105; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7106; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x40549a787107; SI-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549a78, v07108; SI-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v27109; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x33979a377110; SI-GISEL-NEXT: v_fma_f32 v1, v0, v3, v17111; SI-GISEL-NEXT: v_rndne_f32_e32 v3, v27112; SI-GISEL-NEXT: v_sub_f32_e32 v2, v2, v37113; SI-GISEL-NEXT: v_add_f32_e32 v1, v2, v17114; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v37115; SI-GISEL-NEXT: v_exp_f32_e32 v1, v17116; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f8000007117; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, v1, v27118; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f47119; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v27120; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x421a209b7121; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc7122; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v27123; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc7124; SI-GISEL-NEXT: s_setpc_b64 s[30:31]7125;7126; R600-LABEL: v_exp10_f32_contract_daz:7127; R600: ; %bb.0:7128; R600-NEXT: CF_END7129; R600-NEXT: PAD7130;7131; CM-LABEL: v_exp10_f32_contract_daz:7132; CM: ; %bb.0:7133; CM-NEXT: CF_END7134; CM-NEXT: PAD7135 %result = call contract float @llvm.exp10.f32(float %in)7136 ret float %result7137}7138 7139define float @v_exp10_f32_contract_nnan_ninf(float %in) {7140; VI-SDAG-LABEL: v_exp10_f32_contract_nnan_ninf:7141; VI-SDAG: ; %bb.0:7142; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7143; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v07144; VI-SDAG-NEXT: v_sub_f32_e32 v4, v0, v17145; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x40549000, v17146; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x3a2784bc, v47147; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x40549000, v47148; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v27149; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v57150; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v17151; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v37152; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v47153; VI-SDAG-NEXT: v_add_f32_e32 v1, v2, v17154; VI-SDAG-NEXT: v_exp_f32_e32 v1, v17155; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v37156; VI-SDAG-NEXT: s_mov_b32 s4, 0xc23369f47157; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v07158; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v27159; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc7160; VI-SDAG-NEXT: s_setpc_b64 s[30:31]7161;7162; VI-GISEL-LABEL: v_exp10_f32_contract_nnan_ninf:7163; VI-GISEL: ; %bb.0:7164; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7165; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v07166; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v17167; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3a2784bc, v27168; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549000, v27169; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x40549000, v17170; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v47171; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v17172; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v27173; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v37174; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v27175; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v17176; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v27177; VI-GISEL-NEXT: v_exp_f32_e32 v1, v17178; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v27179; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f47180; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v27181; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc7182; VI-GISEL-NEXT: s_setpc_b64 s[30:31]7183;7184; GFX900-SDAG-LABEL: v_exp10_f32_contract_nnan_ninf:7185; GFX900-SDAG: ; %bb.0:7186; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7187; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x40549a78, v07188; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x40549a787189; GFX900-SDAG-NEXT: v_rndne_f32_e32 v2, v17190; GFX900-SDAG-NEXT: v_sub_f32_e32 v3, v1, v27191; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v17192; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x33979a377193; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, v17194; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v3, v17195; GFX900-SDAG-NEXT: v_exp_f32_e32 v1, v17196; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v27197; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xc23369f47198; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v07199; GFX900-SDAG-NEXT: v_ldexp_f32 v1, v1, v27200; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc7201; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]7202;7203; GFX900-GISEL-LABEL: v_exp10_f32_contract_nnan_ninf:7204; GFX900-GISEL: ; %bb.0:7205; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7206; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x40549a787207; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549a78, v07208; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v27209; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x33979a377210; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v3, v17211; GFX900-GISEL-NEXT: v_rndne_f32_e32 v3, v27212; GFX900-GISEL-NEXT: v_sub_f32_e32 v2, v2, v37213; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v2, v17214; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v37215; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, v17216; GFX900-GISEL-NEXT: v_ldexp_f32 v1, v1, v27217; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f47218; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v27219; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc7220; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]7221;7222; SI-SDAG-LABEL: v_exp10_f32_contract_nnan_ninf:7223; SI-SDAG: ; %bb.0:7224; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7225; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x40549a78, v07226; SI-SDAG-NEXT: s_mov_b32 s4, 0x40549a787227; SI-SDAG-NEXT: v_rndne_f32_e32 v2, v17228; SI-SDAG-NEXT: v_sub_f32_e32 v3, v1, v27229; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v17230; SI-SDAG-NEXT: s_mov_b32 s4, 0x33979a377231; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, v17232; SI-SDAG-NEXT: v_add_f32_e32 v1, v3, v17233; SI-SDAG-NEXT: v_exp_f32_e32 v1, v17234; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v27235; SI-SDAG-NEXT: s_mov_b32 s4, 0xc23369f47236; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v07237; SI-SDAG-NEXT: v_ldexp_f32_e32 v1, v1, v27238; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc7239; SI-SDAG-NEXT: s_setpc_b64 s[30:31]7240;7241; SI-GISEL-LABEL: v_exp10_f32_contract_nnan_ninf:7242; SI-GISEL: ; %bb.0:7243; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7244; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x40549a787245; SI-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549a78, v07246; SI-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v27247; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x33979a377248; SI-GISEL-NEXT: v_fma_f32 v1, v0, v3, v17249; SI-GISEL-NEXT: v_rndne_f32_e32 v3, v27250; SI-GISEL-NEXT: v_sub_f32_e32 v2, v2, v37251; SI-GISEL-NEXT: v_add_f32_e32 v1, v2, v17252; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v37253; SI-GISEL-NEXT: v_exp_f32_e32 v1, v17254; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, v1, v27255; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f47256; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v27257; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc7258; SI-GISEL-NEXT: s_setpc_b64 s[30:31]7259;7260; R600-LABEL: v_exp10_f32_contract_nnan_ninf:7261; R600: ; %bb.0:7262; R600-NEXT: CF_END7263; R600-NEXT: PAD7264;7265; CM-LABEL: v_exp10_f32_contract_nnan_ninf:7266; CM: ; %bb.0:7267; CM-NEXT: CF_END7268; CM-NEXT: PAD7269 %result = call contract nnan ninf float @llvm.exp10.f32(float %in)7270 ret float %result7271}7272 7273declare float @llvm.fabs.f32(float) #27274declare float @llvm.exp10.f32(float) #27275declare <2 x float> @llvm.exp10.v2f32(<2 x float>) #27276declare <3 x float> @llvm.exp10.v3f32(<3 x float>) #27277declare <4 x float> @llvm.exp10.v4f32(<4 x float>) #27278declare half @llvm.fabs.f16(half) #27279declare half @llvm.exp10.f16(half) #27280declare <2 x half> @llvm.exp10.v2f16(<2 x half>) #27281declare <3 x half> @llvm.exp10.v3f16(<3 x half>) #27282declare <2 x half> @llvm.fabs.v2f16(<2 x half>) #27283 7284attributes #0 = { "denormal-fp-math-f32"="ieee,preserve-sign" }7285attributes #1 = { "denormal-fp-math-f32"="dynamic,dynamic" }7286attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }7287