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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1030 < %s | FileCheck -check-prefixes=CHECK,SDAG %s3; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefixes=CHECK,SDAG %s4; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1030 < %s | FileCheck -check-prefixes=CHECK,GISEL %s5 6define amdgpu_gs half @v_fptrunc_round_f32_to_f16_tonearest(float %a) {7; CHECK-LABEL: v_fptrunc_round_f32_to_f16_tonearest:8; CHECK: ; %bb.0:9; CHECK-NEXT: v_cvt_f16_f32_e32 v0, v010; CHECK-NEXT: ; return to shader part epilog11 %res = call half @llvm.fptrunc.round.f16.f32(float %a, metadata !"round.tonearest")12 ret half %res13}14 15define amdgpu_gs half @v_fptrunc_round_f32_to_f16_upward(float %a) {16; CHECK-LABEL: v_fptrunc_round_f32_to_f16_upward:17; CHECK: ; %bb.0:18; CHECK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 1), 119; CHECK-NEXT: v_cvt_f16_f32_e32 v0, v020; CHECK-NEXT: ; return to shader part epilog21 %res = call half @llvm.fptrunc.round.f16.f32(float %a, metadata !"round.upward")22 ret half %res23}24 25define amdgpu_gs half @v_fptrunc_round_f32_to_f16_downward(float %a) {26; CHECK-LABEL: v_fptrunc_round_f32_to_f16_downward:27; CHECK: ; %bb.0:28; CHECK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 3, 1), 129; CHECK-NEXT: v_cvt_f16_f32_e32 v0, v030; CHECK-NEXT: ; return to shader part epilog31 %res = call half @llvm.fptrunc.round.f16.f32(float %a, metadata !"round.downward")32 ret half %res33}34 35define amdgpu_gs half @v_fptrunc_round_f32_to_f16_towardzero(float %a) {36; CHECK-LABEL: v_fptrunc_round_f32_to_f16_towardzero:37; CHECK: ; %bb.0:38; CHECK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 339; CHECK-NEXT: v_cvt_f16_f32_e32 v0, v040; CHECK-NEXT: ; return to shader part epilog41 %res = call half @llvm.fptrunc.round.f16.f32(float %a, metadata !"round.towardzero")42 ret half %res43}44 45define amdgpu_gs void @v_fptrunc_round_f32_to_f16_upward_multiple_calls(float %a, float %b, ptr addrspace(1) %out) {46; CHECK-LABEL: v_fptrunc_round_f32_to_f16_upward_multiple_calls:47; CHECK: ; %bb.0:48; CHECK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 1), 149; CHECK-NEXT: v_cvt_f16_f32_e32 v0, v050; CHECK-NEXT: v_cvt_f16_f32_e32 v4, v151; CHECK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 252; CHECK-NEXT: v_cvt_f16_f32_e32 v1, v153; CHECK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 3, 1), 054; CHECK-NEXT: v_add_f16_e32 v0, v0, v455; CHECK-NEXT: v_add_f16_e32 v0, v1, v056; CHECK-NEXT: global_store_short v[2:3], v0, off57; CHECK-NEXT: s_endpgm58 %res1 = call half @llvm.fptrunc.round.f16.f32(float %a, metadata !"round.upward")59 %res2 = call half @llvm.fptrunc.round.f16.f32(float %b, metadata !"round.upward")60 %res3 = call half @llvm.fptrunc.round.f16.f32(float %b, metadata !"round.downward")61 %res4 = fadd half %res1, %res262 %res5 = fadd half %res3, %res463 store half %res5, ptr addrspace(1) %out, align 464 ret void65}66 67define amdgpu_gs void @v_fptrunc_round_f32_to_f16_downward_multiple_calls(float %a, float %b, ptr addrspace(1) %out) {68; CHECK-LABEL: v_fptrunc_round_f32_to_f16_downward_multiple_calls:69; CHECK: ; %bb.0:70; CHECK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 1), 171; CHECK-NEXT: v_cvt_f16_f32_e32 v4, v072; CHECK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 273; CHECK-NEXT: v_cvt_f16_f32_e32 v0, v074; CHECK-NEXT: v_cvt_f16_f32_e32 v1, v175; CHECK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 3, 1), 076; CHECK-NEXT: v_add_f16_e32 v0, v4, v077; CHECK-NEXT: v_add_f16_e32 v0, v1, v078; CHECK-NEXT: global_store_short v[2:3], v0, off79; CHECK-NEXT: s_endpgm80 %res1 = call half @llvm.fptrunc.round.f16.f32(float %a, metadata !"round.upward")81 %res2 = call half @llvm.fptrunc.round.f16.f32(float %a, metadata !"round.downward")82 %res3 = call half @llvm.fptrunc.round.f16.f32(float %b, metadata !"round.downward")83 %res4 = fadd half %res1, %res284 %res5 = fadd half %res3, %res485 store half %res5, ptr addrspace(1) %out, align 486 ret void87}88 89define amdgpu_gs void @v_fptrunc_round_f32_to_f16_towardzero_multiple_calls(float %a, float %b, ptr addrspace(1) %out) {90; CHECK-LABEL: v_fptrunc_round_f32_to_f16_towardzero_multiple_calls:91; CHECK: ; %bb.0:92; CHECK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 393; CHECK-NEXT: v_cvt_f16_f32_e32 v0, v094; CHECK-NEXT: v_cvt_f16_f32_e32 v4, v195; CHECK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 196; CHECK-NEXT: v_cvt_f16_f32_e32 v1, v197; CHECK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 1), 098; CHECK-NEXT: v_add_f16_e32 v0, v0, v499; CHECK-NEXT: v_add_f16_e32 v0, v1, v0100; CHECK-NEXT: global_store_short v[2:3], v0, off101; CHECK-NEXT: s_endpgm102 %res1 = call half @llvm.fptrunc.round.f16.f32(float %a, metadata !"round.towardzero")103 %res2 = call half @llvm.fptrunc.round.f16.f32(float %b, metadata !"round.towardzero")104 %res3 = call half @llvm.fptrunc.round.f16.f32(float %b, metadata !"round.upward")105 %res4 = fadd half %res1, %res2106 %res5 = fadd half %res3, %res4107 store half %res5, ptr addrspace(1) %out, align 4108 ret void109}110 111define amdgpu_gs i32 @s_fptrunc_round_f32_to_f16_upward(float inreg %a, ptr addrspace(1) %out) {112; CHECK-LABEL: s_fptrunc_round_f32_to_f16_upward:113; CHECK: ; %bb.0:114; CHECK-NEXT: v_mov_b32_e32 v0, s0115; CHECK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 1), 1116; CHECK-NEXT: v_cvt_f16_f32_e32 v0, v0117; CHECK-NEXT: v_and_b32_e32 v0, 0xffff, v0118; CHECK-NEXT: v_readfirstlane_b32 s0, v0119; CHECK-NEXT: ; return to shader part epilog120 %res = call half @llvm.fptrunc.round.f16.f32(float %a, metadata !"round.upward")121 %bitcast = bitcast half %res to i16122 %ret = zext i16 %bitcast to i32123 ret i32 %ret124}125 126define amdgpu_gs i32 @s_fptrunc_round_f32_to_f16_downward(float inreg %a, ptr addrspace(1) %out) {127; CHECK-LABEL: s_fptrunc_round_f32_to_f16_downward:128; CHECK: ; %bb.0:129; CHECK-NEXT: v_mov_b32_e32 v0, s0130; CHECK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 3, 1), 1131; CHECK-NEXT: v_cvt_f16_f32_e32 v0, v0132; CHECK-NEXT: v_and_b32_e32 v0, 0xffff, v0133; CHECK-NEXT: v_readfirstlane_b32 s0, v0134; CHECK-NEXT: ; return to shader part epilog135 %res = call half @llvm.fptrunc.round.f16.f32(float %a, metadata !"round.downward")136 %bitcast = bitcast half %res to i16137 %ret = zext i16 %bitcast to i32138 ret i32 %ret139}140 141define amdgpu_gs void @s_fptrunc_round_f32_to_f16_upward_multiple_calls(float inreg %a, float inreg %b, ptr addrspace(1) %out) {142; CHECK-LABEL: s_fptrunc_round_f32_to_f16_upward_multiple_calls:143; CHECK: ; %bb.0:144; CHECK-NEXT: v_mov_b32_e32 v2, s0145; CHECK-NEXT: v_mov_b32_e32 v3, s1146; CHECK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 1), 1147; CHECK-NEXT: v_cvt_f16_f32_e32 v2, v2148; CHECK-NEXT: v_cvt_f16_f32_e32 v4, v3149; CHECK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 2150; CHECK-NEXT: v_cvt_f16_f32_e32 v3, v3151; CHECK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 3, 1), 0152; CHECK-NEXT: v_add_f16_e32 v2, v2, v4153; CHECK-NEXT: v_add_f16_e32 v2, v3, v2154; CHECK-NEXT: global_store_short v[0:1], v2, off155; CHECK-NEXT: s_endpgm156 %res1 = call half @llvm.fptrunc.round.f16.f32(float %a, metadata !"round.upward")157 %res2 = call half @llvm.fptrunc.round.f16.f32(float %b, metadata !"round.upward")158 %res3 = call half @llvm.fptrunc.round.f16.f32(float %b, metadata !"round.downward")159 %res4 = fadd half %res1, %res2160 %res5 = fadd half %res3, %res4161 store half %res5, ptr addrspace(1) %out, align 4162 ret void163}164 165define amdgpu_gs <2 x half> @v_fptrunc_round_v2f32_to_v2f16_upward(<2 x float> %a) {166; SDAG-LABEL: v_fptrunc_round_v2f32_to_v2f16_upward:167; SDAG: ; %bb.0:168; SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 1), 1169; SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0170; SDAG-NEXT: v_cvt_f16_f32_e32 v1, v1171; SDAG-NEXT: v_perm_b32 v0, v1, v0, 0x5040100172; SDAG-NEXT: ; return to shader part epilog173;174; GISEL-LABEL: v_fptrunc_round_v2f32_to_v2f16_upward:175; GISEL: ; %bb.0:176; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 1), 1177; GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0178; GISEL-NEXT: v_cvt_f16_f32_e32 v1, v1179; GISEL-NEXT: v_pack_b32_f16 v0, v0, v1180; GISEL-NEXT: ; return to shader part epilog181 %res = call <2 x half> @llvm.fptrunc.round.v2f16.v2f32(<2 x float> %a, metadata !"round.upward")182 ret <2 x half> %res183}184 185define amdgpu_gs <2 x half> @v_fptrunc_round_v2f32_to_v2f16_downward(<2 x float> %a) {186; SDAG-LABEL: v_fptrunc_round_v2f32_to_v2f16_downward:187; SDAG: ; %bb.0:188; SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 3, 1), 1189; SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0190; SDAG-NEXT: v_cvt_f16_f32_e32 v1, v1191; SDAG-NEXT: v_perm_b32 v0, v1, v0, 0x5040100192; SDAG-NEXT: ; return to shader part epilog193;194; GISEL-LABEL: v_fptrunc_round_v2f32_to_v2f16_downward:195; GISEL: ; %bb.0:196; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 3, 1), 1197; GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0198; GISEL-NEXT: v_cvt_f16_f32_e32 v1, v1199; GISEL-NEXT: v_pack_b32_f16 v0, v0, v1200; GISEL-NEXT: ; return to shader part epilog201 %res = call <2 x half> @llvm.fptrunc.round.v2f16.v2f32(<2 x float> %a, metadata !"round.downward")202 ret <2 x half> %res203}204 205define amdgpu_gs void @v_fptrunc_round_v2f32_to_v2f16_upward_multiple_calls(<2 x float> %a, <2 x float> %b, ptr addrspace(1) %out) {206; SDAG-LABEL: v_fptrunc_round_v2f32_to_v2f16_upward_multiple_calls:207; SDAG: ; %bb.0:208; SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 1), 1209; SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0210; SDAG-NEXT: v_cvt_f16_f32_e32 v1, v1211; SDAG-NEXT: v_cvt_f16_f32_e32 v6, v2212; SDAG-NEXT: v_cvt_f16_f32_e32 v7, v3213; SDAG-NEXT: v_perm_b32 v0, v1, v0, 0x5040100214; SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 2215; SDAG-NEXT: v_cvt_f16_f32_e32 v1, v2216; SDAG-NEXT: v_cvt_f16_f32_e32 v2, v3217; SDAG-NEXT: v_perm_b32 v3, v7, v6, 0x5040100218; SDAG-NEXT: v_perm_b32 v1, v2, v1, 0x5040100219; SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 3, 1), 0220; SDAG-NEXT: v_pk_add_f16 v0, v0, v3221; SDAG-NEXT: v_pk_add_f16 v0, v1, v0222; SDAG-NEXT: global_store_dword v[4:5], v0, off223; SDAG-NEXT: s_endpgm224;225; GISEL-LABEL: v_fptrunc_round_v2f32_to_v2f16_upward_multiple_calls:226; GISEL: ; %bb.0:227; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 1), 1228; GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0229; GISEL-NEXT: v_cvt_f16_f32_e32 v1, v1230; GISEL-NEXT: v_cvt_f16_f32_e32 v6, v2231; GISEL-NEXT: v_cvt_f16_f32_e32 v7, v3232; GISEL-NEXT: v_pack_b32_f16 v0, v0, v1233; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 2234; GISEL-NEXT: v_cvt_f16_f32_e32 v1, v2235; GISEL-NEXT: v_cvt_f16_f32_e32 v2, v3236; GISEL-NEXT: v_pack_b32_f16 v3, v6, v7237; GISEL-NEXT: v_pack_b32_f16 v1, v1, v2238; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 3, 1), 0239; GISEL-NEXT: v_pk_add_f16 v0, v0, v3240; GISEL-NEXT: v_pk_add_f16 v0, v1, v0241; GISEL-NEXT: global_store_dword v[4:5], v0, off242; GISEL-NEXT: s_endpgm243 %res1 = call <2 x half> @llvm.fptrunc.round.v2f16.v2f32(<2 x float> %a, metadata !"round.upward")244 %res2 = call <2 x half> @llvm.fptrunc.round.v2f16.v2f32(<2 x float> %b, metadata !"round.upward")245 %res3 = call <2 x half> @llvm.fptrunc.round.v2f16.v2f32(<2 x float> %b, metadata !"round.downward")246 %res4 = fadd <2 x half> %res1, %res2247 %res5 = fadd <2 x half> %res3, %res4248 store <2 x half> %res5, ptr addrspace(1) %out, align 4249 ret void250}251 252define amdgpu_gs <2 x i32> @s_fptrunc_round_v2f32_to_v2f16_upward(<2 x float> inreg %a, ptr addrspace(1) %out) {253; CHECK-LABEL: s_fptrunc_round_v2f32_to_v2f16_upward:254; CHECK: ; %bb.0:255; CHECK-NEXT: v_mov_b32_e32 v0, s0256; CHECK-NEXT: v_mov_b32_e32 v1, s1257; CHECK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 1), 1258; CHECK-NEXT: v_cvt_f16_f32_e32 v0, v0259; CHECK-NEXT: v_cvt_f16_f32_e32 v1, v1260; CHECK-NEXT: v_and_b32_e32 v0, 0xffff, v0261; CHECK-NEXT: v_and_b32_e32 v1, 0xffff, v1262; CHECK-NEXT: v_readfirstlane_b32 s0, v0263; CHECK-NEXT: v_readfirstlane_b32 s1, v1264; CHECK-NEXT: ; return to shader part epilog265 %res = call <2 x half> @llvm.fptrunc.round.v2f16.v2f32(<2 x float> %a, metadata !"round.upward")266 %bitcast = bitcast <2 x half> %res to <2 x i16>267 %ret = zext <2 x i16> %bitcast to <2 x i32>268 ret <2 x i32> %ret269}270 271define amdgpu_gs <2 x i32> @s_fptrunc_round_v2f32_to_v2f16_downward(<2 x float> inreg %a, ptr addrspace(1) %out) {272; CHECK-LABEL: s_fptrunc_round_v2f32_to_v2f16_downward:273; CHECK: ; %bb.0:274; CHECK-NEXT: v_mov_b32_e32 v0, s0275; CHECK-NEXT: v_mov_b32_e32 v1, s1276; CHECK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 3, 1), 1277; CHECK-NEXT: v_cvt_f16_f32_e32 v0, v0278; CHECK-NEXT: v_cvt_f16_f32_e32 v1, v1279; CHECK-NEXT: v_and_b32_e32 v0, 0xffff, v0280; CHECK-NEXT: v_and_b32_e32 v1, 0xffff, v1281; CHECK-NEXT: v_readfirstlane_b32 s0, v0282; CHECK-NEXT: v_readfirstlane_b32 s1, v1283; CHECK-NEXT: ; return to shader part epilog284 %res = call <2 x half> @llvm.fptrunc.round.v2f16.v2f32(<2 x float> %a, metadata !"round.downward")285 %bitcast = bitcast <2 x half> %res to <2 x i16>286 %ret = zext <2 x i16> %bitcast to <2 x i32>287 ret <2 x i32> %ret288}289 290define amdgpu_gs void @s_fptrunc_round_v2f32_to_v2f16_upward_multiple_calls(<2 x float> inreg %a, <2 x float> inreg %b, ptr addrspace(1) %out) {291; SDAG-LABEL: s_fptrunc_round_v2f32_to_v2f16_upward_multiple_calls:292; SDAG: ; %bb.0:293; SDAG-NEXT: v_mov_b32_e32 v2, s0294; SDAG-NEXT: v_mov_b32_e32 v3, s2295; SDAG-NEXT: v_mov_b32_e32 v4, s1296; SDAG-NEXT: v_mov_b32_e32 v5, s3297; SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 1), 1298; SDAG-NEXT: v_cvt_f16_f32_e32 v2, v2299; SDAG-NEXT: v_cvt_f16_f32_e32 v6, v3300; SDAG-NEXT: v_cvt_f16_f32_e32 v4, v4301; SDAG-NEXT: v_cvt_f16_f32_e32 v7, v5302; SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 2303; SDAG-NEXT: v_cvt_f16_f32_e32 v3, v3304; SDAG-NEXT: v_and_b32_e32 v2, 0xffff, v2305; SDAG-NEXT: v_and_b32_e32 v6, 0xffff, v6306; SDAG-NEXT: v_and_b32_e32 v3, 0xffff, v3307; SDAG-NEXT: v_lshl_or_b32 v2, v4, 16, v2308; SDAG-NEXT: v_cvt_f16_f32_e32 v4, v5309; SDAG-NEXT: v_lshl_or_b32 v5, v7, 16, v6310; SDAG-NEXT: v_lshl_or_b32 v3, v4, 16, v3311; SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 3, 1), 0312; SDAG-NEXT: v_pk_add_f16 v2, v2, v5313; SDAG-NEXT: v_pk_add_f16 v2, v3, v2314; SDAG-NEXT: global_store_dword v[0:1], v2, off315; SDAG-NEXT: s_endpgm316;317; GISEL-LABEL: s_fptrunc_round_v2f32_to_v2f16_upward_multiple_calls:318; GISEL: ; %bb.0:319; GISEL-NEXT: v_mov_b32_e32 v2, s0320; GISEL-NEXT: v_mov_b32_e32 v3, s1321; GISEL-NEXT: v_mov_b32_e32 v4, s2322; GISEL-NEXT: v_mov_b32_e32 v5, s3323; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 1), 1324; GISEL-NEXT: v_cvt_f16_f32_e32 v2, v2325; GISEL-NEXT: v_cvt_f16_f32_e32 v3, v3326; GISEL-NEXT: v_cvt_f16_f32_e32 v6, v4327; GISEL-NEXT: v_cvt_f16_f32_e32 v7, v5328; GISEL-NEXT: v_pack_b32_f16 v2, v2, v3329; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 2330; GISEL-NEXT: v_cvt_f16_f32_e32 v3, v4331; GISEL-NEXT: v_cvt_f16_f32_e32 v4, v5332; GISEL-NEXT: v_pack_b32_f16 v5, v6, v7333; GISEL-NEXT: v_pack_b32_f16 v3, v3, v4334; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 3, 1), 0335; GISEL-NEXT: v_pk_add_f16 v2, v2, v5336; GISEL-NEXT: v_pk_add_f16 v2, v3, v2337; GISEL-NEXT: global_store_dword v[0:1], v2, off338; GISEL-NEXT: s_endpgm339 %res1 = call <2 x half> @llvm.fptrunc.round.v2f16.v2f32(<2 x float> %a, metadata !"round.upward")340 %res2 = call <2 x half> @llvm.fptrunc.round.v2f16.v2f32(<2 x float> %b, metadata !"round.upward")341 %res3 = call <2 x half> @llvm.fptrunc.round.v2f16.v2f32(<2 x float> %b, metadata !"round.downward")342 %res4 = fadd <2 x half> %res1, %res2343 %res5 = fadd <2 x half> %res3, %res4344 store <2 x half> %res5, ptr addrspace(1) %out, align 4345 ret void346}347 348define amdgpu_gs <3 x half> @v_fptrunc_round_v3f32_to_v3f16_upward(<3 x float> %a) {349; SDAG-LABEL: v_fptrunc_round_v3f32_to_v3f16_upward:350; SDAG: ; %bb.0:351; SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 1), 1352; SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0353; SDAG-NEXT: v_cvt_f16_f32_e32 v1, v1354; SDAG-NEXT: v_perm_b32 v0, v1, v0, 0x5040100355; SDAG-NEXT: v_cvt_f16_f32_e32 v1, v2356; SDAG-NEXT: ; return to shader part epilog357;358; GISEL-LABEL: v_fptrunc_round_v3f32_to_v3f16_upward:359; GISEL: ; %bb.0:360; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 1), 1361; GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0362; GISEL-NEXT: v_cvt_f16_f32_e32 v1, v1363; GISEL-NEXT: v_pack_b32_f16 v0, v0, v1364; GISEL-NEXT: v_cvt_f16_f32_e32 v1, v2365; GISEL-NEXT: ; return to shader part epilog366 %res = call <3 x half> @llvm.fptrunc.round.v3f16.v3f32(<3 x float> %a, metadata !"round.upward")367 ret <3 x half> %res368}369 370define amdgpu_gs <3 x half> @v_fptrunc_round_v3f32_to_v3f16_downward(<3 x float> %a) {371; SDAG-LABEL: v_fptrunc_round_v3f32_to_v3f16_downward:372; SDAG: ; %bb.0:373; SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 3, 1), 1374; SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0375; SDAG-NEXT: v_cvt_f16_f32_e32 v1, v1376; SDAG-NEXT: v_perm_b32 v0, v1, v0, 0x5040100377; SDAG-NEXT: v_cvt_f16_f32_e32 v1, v2378; SDAG-NEXT: ; return to shader part epilog379;380; GISEL-LABEL: v_fptrunc_round_v3f32_to_v3f16_downward:381; GISEL: ; %bb.0:382; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 3, 1), 1383; GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0384; GISEL-NEXT: v_cvt_f16_f32_e32 v1, v1385; GISEL-NEXT: v_pack_b32_f16 v0, v0, v1386; GISEL-NEXT: v_cvt_f16_f32_e32 v1, v2387; GISEL-NEXT: ; return to shader part epilog388 %res = call <3 x half> @llvm.fptrunc.round.v3f16.v3f32(<3 x float> %a, metadata !"round.downward")389 ret <3 x half> %res390}391 392define amdgpu_gs <4 x half> @v_fptrunc_round_v4f32_to_v4f16_upward(<4 x float> %a) {393; SDAG-LABEL: v_fptrunc_round_v4f32_to_v4f16_upward:394; SDAG: ; %bb.0:395; SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 1), 1396; SDAG-NEXT: v_cvt_f16_f32_e32 v2, v2397; SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0398; SDAG-NEXT: v_cvt_f16_f32_e32 v1, v1399; SDAG-NEXT: v_cvt_f16_f32_e32 v3, v3400; SDAG-NEXT: v_perm_b32 v0, v1, v0, 0x5040100401; SDAG-NEXT: v_perm_b32 v1, v3, v2, 0x5040100402; SDAG-NEXT: ; return to shader part epilog403;404; GISEL-LABEL: v_fptrunc_round_v4f32_to_v4f16_upward:405; GISEL: ; %bb.0:406; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 1), 1407; GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0408; GISEL-NEXT: v_cvt_f16_f32_e32 v1, v1409; GISEL-NEXT: v_cvt_f16_f32_e32 v2, v2410; GISEL-NEXT: v_cvt_f16_f32_e32 v3, v3411; GISEL-NEXT: v_pack_b32_f16 v0, v0, v1412; GISEL-NEXT: v_pack_b32_f16 v1, v2, v3413; GISEL-NEXT: ; return to shader part epilog414 %res = call <4 x half> @llvm.fptrunc.round.v4f16.v4f32(<4 x float> %a, metadata !"round.upward")415 ret <4 x half> %res416}417 418define amdgpu_gs <4 x half> @v_fptrunc_round_v4f32_to_v4f16_downward(<4 x float> %a) {419; SDAG-LABEL: v_fptrunc_round_v4f32_to_v4f16_downward:420; SDAG: ; %bb.0:421; SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 3, 1), 1422; SDAG-NEXT: v_cvt_f16_f32_e32 v2, v2423; SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0424; SDAG-NEXT: v_cvt_f16_f32_e32 v1, v1425; SDAG-NEXT: v_cvt_f16_f32_e32 v3, v3426; SDAG-NEXT: v_perm_b32 v0, v1, v0, 0x5040100427; SDAG-NEXT: v_perm_b32 v1, v3, v2, 0x5040100428; SDAG-NEXT: ; return to shader part epilog429;430; GISEL-LABEL: v_fptrunc_round_v4f32_to_v4f16_downward:431; GISEL: ; %bb.0:432; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 3, 1), 1433; GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0434; GISEL-NEXT: v_cvt_f16_f32_e32 v1, v1435; GISEL-NEXT: v_cvt_f16_f32_e32 v2, v2436; GISEL-NEXT: v_cvt_f16_f32_e32 v3, v3437; GISEL-NEXT: v_pack_b32_f16 v0, v0, v1438; GISEL-NEXT: v_pack_b32_f16 v1, v2, v3439; GISEL-NEXT: ; return to shader part epilog440 %res = call <4 x half> @llvm.fptrunc.round.v4f16.v4f32(<4 x float> %a, metadata !"round.downward")441 ret <4 x half> %res442}443 444define amdgpu_gs <8 x half> @v_fptrunc_round_v8f32_to_v8f16_upward(<8 x float> %a) {445; SDAG-LABEL: v_fptrunc_round_v8f32_to_v8f16_upward:446; SDAG: ; %bb.0:447; SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 1), 1448; SDAG-NEXT: v_cvt_f16_f32_e32 v6, v6449; SDAG-NEXT: v_cvt_f16_f32_e32 v4, v4450; SDAG-NEXT: v_cvt_f16_f32_e32 v2, v2451; SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0452; SDAG-NEXT: v_cvt_f16_f32_e32 v1, v1453; SDAG-NEXT: v_cvt_f16_f32_e32 v3, v3454; SDAG-NEXT: v_cvt_f16_f32_e32 v5, v5455; SDAG-NEXT: v_cvt_f16_f32_e32 v7, v7456; SDAG-NEXT: v_perm_b32 v0, v1, v0, 0x5040100457; SDAG-NEXT: v_perm_b32 v1, v3, v2, 0x5040100458; SDAG-NEXT: v_perm_b32 v2, v5, v4, 0x5040100459; SDAG-NEXT: v_perm_b32 v3, v7, v6, 0x5040100460; SDAG-NEXT: ; return to shader part epilog461;462; GISEL-LABEL: v_fptrunc_round_v8f32_to_v8f16_upward:463; GISEL: ; %bb.0:464; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 1), 1465; GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0466; GISEL-NEXT: v_cvt_f16_f32_e32 v1, v1467; GISEL-NEXT: v_cvt_f16_f32_e32 v2, v2468; GISEL-NEXT: v_cvt_f16_f32_e32 v3, v3469; GISEL-NEXT: v_cvt_f16_f32_e32 v4, v4470; GISEL-NEXT: v_cvt_f16_f32_e32 v5, v5471; GISEL-NEXT: v_cvt_f16_f32_e32 v6, v6472; GISEL-NEXT: v_cvt_f16_f32_e32 v7, v7473; GISEL-NEXT: v_pack_b32_f16 v0, v0, v1474; GISEL-NEXT: v_pack_b32_f16 v1, v2, v3475; GISEL-NEXT: v_pack_b32_f16 v2, v4, v5476; GISEL-NEXT: v_pack_b32_f16 v3, v6, v7477; GISEL-NEXT: ; return to shader part epilog478 %res = call <8 x half> @llvm.fptrunc.round.v8f16.v8f32(<8 x float> %a, metadata !"round.upward")479 ret <8 x half> %res480}481 482define amdgpu_gs <8 x half> @v_fptrunc_round_v8f32_to_v8f16_downward(<8 x float> %a) {483; SDAG-LABEL: v_fptrunc_round_v8f32_to_v8f16_downward:484; SDAG: ; %bb.0:485; SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 3, 1), 1486; SDAG-NEXT: v_cvt_f16_f32_e32 v6, v6487; SDAG-NEXT: v_cvt_f16_f32_e32 v4, v4488; SDAG-NEXT: v_cvt_f16_f32_e32 v2, v2489; SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0490; SDAG-NEXT: v_cvt_f16_f32_e32 v1, v1491; SDAG-NEXT: v_cvt_f16_f32_e32 v3, v3492; SDAG-NEXT: v_cvt_f16_f32_e32 v5, v5493; SDAG-NEXT: v_cvt_f16_f32_e32 v7, v7494; SDAG-NEXT: v_perm_b32 v0, v1, v0, 0x5040100495; SDAG-NEXT: v_perm_b32 v1, v3, v2, 0x5040100496; SDAG-NEXT: v_perm_b32 v2, v5, v4, 0x5040100497; SDAG-NEXT: v_perm_b32 v3, v7, v6, 0x5040100498; SDAG-NEXT: ; return to shader part epilog499;500; GISEL-LABEL: v_fptrunc_round_v8f32_to_v8f16_downward:501; GISEL: ; %bb.0:502; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 3, 1), 1503; GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0504; GISEL-NEXT: v_cvt_f16_f32_e32 v1, v1505; GISEL-NEXT: v_cvt_f16_f32_e32 v2, v2506; GISEL-NEXT: v_cvt_f16_f32_e32 v3, v3507; GISEL-NEXT: v_cvt_f16_f32_e32 v4, v4508; GISEL-NEXT: v_cvt_f16_f32_e32 v5, v5509; GISEL-NEXT: v_cvt_f16_f32_e32 v6, v6510; GISEL-NEXT: v_cvt_f16_f32_e32 v7, v7511; GISEL-NEXT: v_pack_b32_f16 v0, v0, v1512; GISEL-NEXT: v_pack_b32_f16 v1, v2, v3513; GISEL-NEXT: v_pack_b32_f16 v2, v4, v5514; GISEL-NEXT: v_pack_b32_f16 v3, v6, v7515; GISEL-NEXT: ; return to shader part epilog516 %res = call <8 x half> @llvm.fptrunc.round.v8f16.v8f32(<8 x float> %a, metadata !"round.downward")517 ret <8 x half> %res518}519 520define amdgpu_gs float @v_fptrunc_round_f64_to_f32_tonearest(double %a) {521; CHECK-LABEL: v_fptrunc_round_f64_to_f32_tonearest:522; CHECK: ; %bb.0:523; CHECK-NEXT: v_cvt_f32_f64_e32 v0, v[0:1]524; CHECK-NEXT: ; return to shader part epilog525 %res = call float @llvm.fptrunc.round.f32.f64(double %a, metadata !"round.tonearest")526 ret float %res527}528 529define amdgpu_gs float @v_fptrunc_round_f64_to_f32_upward(double %a) {530; CHECK-LABEL: v_fptrunc_round_f64_to_f32_upward:531; CHECK: ; %bb.0:532; CHECK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 1), 1533; CHECK-NEXT: v_cvt_f32_f64_e32 v0, v[0:1]534; CHECK-NEXT: ; return to shader part epilog535 %res = call float @llvm.fptrunc.round.f32.f64(double %a, metadata !"round.upward")536 ret float %res537}538 539define amdgpu_gs float @v_fptrunc_round_f64_to_f32_downward(double %a) {540; CHECK-LABEL: v_fptrunc_round_f64_to_f32_downward:541; CHECK: ; %bb.0:542; CHECK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 3, 1), 1543; CHECK-NEXT: v_cvt_f32_f64_e32 v0, v[0:1]544; CHECK-NEXT: ; return to shader part epilog545 %res = call float @llvm.fptrunc.round.f32.f64(double %a, metadata !"round.downward")546 ret float %res547}548 549define amdgpu_gs float @v_fptrunc_round_f64_to_f32_towardzero(double %a) {550; CHECK-LABEL: v_fptrunc_round_f64_to_f32_towardzero:551; CHECK: ; %bb.0:552; CHECK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 3553; CHECK-NEXT: v_cvt_f32_f64_e32 v0, v[0:1]554; CHECK-NEXT: ; return to shader part epilog555 %res = call float @llvm.fptrunc.round.f32.f64(double %a, metadata !"round.towardzero")556 ret float %res557}558