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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx703 < %s | FileCheck -check-prefixes=GCN,GFX7 %s3; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 < %s | FileCheck -check-prefixes=GCN,GFX8 %s4; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9 %s5; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9,GFX900 %s6; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx950 < %s | FileCheck -check-prefixes=GCN,GFX9,GFX950 %s7; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1030 < %s | FileCheck -check-prefixes=GCN,GFX10 %s8; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GCN,GFX11 %s9; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GCN,GFX12 %s10 11define float @v_minimum_f32(float %src0, float %src1) {12; GFX7-LABEL: v_minimum_f32:13; GFX7:       ; %bb.0:14; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)15; GFX7-NEXT:    v_min_f32_e32 v2, v0, v116; GFX7-NEXT:    v_mov_b32_e32 v3, 0x7fc0000017; GFX7-NEXT:    v_cmp_o_f32_e32 vcc, v0, v118; GFX7-NEXT:    v_cndmask_b32_e32 v0, v3, v2, vcc19; GFX7-NEXT:    s_setpc_b64 s[30:31]20;21; GFX8-LABEL: v_minimum_f32:22; GFX8:       ; %bb.0:23; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)24; GFX8-NEXT:    v_min_f32_e32 v2, v0, v125; GFX8-NEXT:    v_mov_b32_e32 v3, 0x7fc0000026; GFX8-NEXT:    v_cmp_o_f32_e32 vcc, v0, v127; GFX8-NEXT:    v_cndmask_b32_e32 v0, v3, v2, vcc28; GFX8-NEXT:    s_setpc_b64 s[30:31]29;30; GFX900-LABEL: v_minimum_f32:31; GFX900:       ; %bb.0:32; GFX900-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)33; GFX900-NEXT:    v_min_f32_e32 v2, v0, v134; GFX900-NEXT:    v_mov_b32_e32 v3, 0x7fc0000035; GFX900-NEXT:    v_cmp_o_f32_e32 vcc, v0, v136; GFX900-NEXT:    v_cndmask_b32_e32 v0, v3, v2, vcc37; GFX900-NEXT:    s_setpc_b64 s[30:31]38;39; GFX950-LABEL: v_minimum_f32:40; GFX950:       ; %bb.0:41; GFX950-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)42; GFX950-NEXT:    v_minimum3_f32 v0, v0, v1, v143; GFX950-NEXT:    s_setpc_b64 s[30:31]44;45; GFX10-LABEL: v_minimum_f32:46; GFX10:       ; %bb.0:47; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)48; GFX10-NEXT:    v_min_f32_e32 v2, v0, v149; GFX10-NEXT:    v_cmp_o_f32_e32 vcc_lo, v0, v150; GFX10-NEXT:    v_cndmask_b32_e32 v0, 0x7fc00000, v2, vcc_lo51; GFX10-NEXT:    s_setpc_b64 s[30:31]52;53; GFX11-LABEL: v_minimum_f32:54; GFX11:       ; %bb.0:55; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)56; GFX11-NEXT:    v_min_f32_e32 v2, v0, v157; GFX11-NEXT:    v_cmp_o_f32_e32 vcc_lo, v0, v158; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)59; GFX11-NEXT:    v_cndmask_b32_e32 v0, 0x7fc00000, v2, vcc_lo60; GFX11-NEXT:    s_setpc_b64 s[30:31]61;62; GFX12-LABEL: v_minimum_f32:63; GFX12:       ; %bb.0:64; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x065; GFX12-NEXT:    s_wait_expcnt 0x066; GFX12-NEXT:    s_wait_samplecnt 0x067; GFX12-NEXT:    s_wait_bvhcnt 0x068; GFX12-NEXT:    s_wait_kmcnt 0x069; GFX12-NEXT:    v_minimum_f32 v0, v0, v170; GFX12-NEXT:    s_setpc_b64 s[30:31]71  %op = call float @llvm.minimum.f32(float %src0, float %src1)72  ret float %op73}74 75define float @v_minimum_f32__nnan(float %src0, float %src1) {76; GFX7-LABEL: v_minimum_f32__nnan:77; GFX7:       ; %bb.0:78; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)79; GFX7-NEXT:    v_min_f32_e32 v0, v0, v180; GFX7-NEXT:    s_setpc_b64 s[30:31]81;82; GFX8-LABEL: v_minimum_f32__nnan:83; GFX8:       ; %bb.0:84; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)85; GFX8-NEXT:    v_min_f32_e32 v0, v0, v186; GFX8-NEXT:    s_setpc_b64 s[30:31]87;88; GFX9-LABEL: v_minimum_f32__nnan:89; GFX9:       ; %bb.0:90; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)91; GFX9-NEXT:    v_min_f32_e32 v0, v0, v192; GFX9-NEXT:    s_setpc_b64 s[30:31]93;94; GFX10-LABEL: v_minimum_f32__nnan:95; GFX10:       ; %bb.0:96; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)97; GFX10-NEXT:    v_min_f32_e32 v0, v0, v198; GFX10-NEXT:    s_setpc_b64 s[30:31]99;100; GFX11-LABEL: v_minimum_f32__nnan:101; GFX11:       ; %bb.0:102; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)103; GFX11-NEXT:    v_min_f32_e32 v0, v0, v1104; GFX11-NEXT:    s_setpc_b64 s[30:31]105;106; GFX12-LABEL: v_minimum_f32__nnan:107; GFX12:       ; %bb.0:108; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0109; GFX12-NEXT:    s_wait_expcnt 0x0110; GFX12-NEXT:    s_wait_samplecnt 0x0111; GFX12-NEXT:    s_wait_bvhcnt 0x0112; GFX12-NEXT:    s_wait_kmcnt 0x0113; GFX12-NEXT:    v_minimum_f32 v0, v0, v1114; GFX12-NEXT:    s_setpc_b64 s[30:31]115  %op = call nnan float @llvm.minimum.f32(float %src0, float %src1)116  ret float %op117}118 119define float @v_minimum_f32__nsz(float %src0, float %src1) {120; GFX7-LABEL: v_minimum_f32__nsz:121; GFX7:       ; %bb.0:122; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)123; GFX7-NEXT:    v_min_f32_e32 v2, v0, v1124; GFX7-NEXT:    v_mov_b32_e32 v3, 0x7fc00000125; GFX7-NEXT:    v_cmp_o_f32_e32 vcc, v0, v1126; GFX7-NEXT:    v_cndmask_b32_e32 v0, v3, v2, vcc127; GFX7-NEXT:    s_setpc_b64 s[30:31]128;129; GFX8-LABEL: v_minimum_f32__nsz:130; GFX8:       ; %bb.0:131; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)132; GFX8-NEXT:    v_min_f32_e32 v2, v0, v1133; GFX8-NEXT:    v_mov_b32_e32 v3, 0x7fc00000134; GFX8-NEXT:    v_cmp_o_f32_e32 vcc, v0, v1135; GFX8-NEXT:    v_cndmask_b32_e32 v0, v3, v2, vcc136; GFX8-NEXT:    s_setpc_b64 s[30:31]137;138; GFX900-LABEL: v_minimum_f32__nsz:139; GFX900:       ; %bb.0:140; GFX900-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)141; GFX900-NEXT:    v_min_f32_e32 v2, v0, v1142; GFX900-NEXT:    v_mov_b32_e32 v3, 0x7fc00000143; GFX900-NEXT:    v_cmp_o_f32_e32 vcc, v0, v1144; GFX900-NEXT:    v_cndmask_b32_e32 v0, v3, v2, vcc145; GFX900-NEXT:    s_setpc_b64 s[30:31]146;147; GFX950-LABEL: v_minimum_f32__nsz:148; GFX950:       ; %bb.0:149; GFX950-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)150; GFX950-NEXT:    v_minimum3_f32 v0, v0, v1, v1151; GFX950-NEXT:    s_setpc_b64 s[30:31]152;153; GFX10-LABEL: v_minimum_f32__nsz:154; GFX10:       ; %bb.0:155; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)156; GFX10-NEXT:    v_min_f32_e32 v2, v0, v1157; GFX10-NEXT:    v_cmp_o_f32_e32 vcc_lo, v0, v1158; GFX10-NEXT:    v_cndmask_b32_e32 v0, 0x7fc00000, v2, vcc_lo159; GFX10-NEXT:    s_setpc_b64 s[30:31]160;161; GFX11-LABEL: v_minimum_f32__nsz:162; GFX11:       ; %bb.0:163; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)164; GFX11-NEXT:    v_min_f32_e32 v2, v0, v1165; GFX11-NEXT:    v_cmp_o_f32_e32 vcc_lo, v0, v1166; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)167; GFX11-NEXT:    v_cndmask_b32_e32 v0, 0x7fc00000, v2, vcc_lo168; GFX11-NEXT:    s_setpc_b64 s[30:31]169;170; GFX12-LABEL: v_minimum_f32__nsz:171; GFX12:       ; %bb.0:172; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0173; GFX12-NEXT:    s_wait_expcnt 0x0174; GFX12-NEXT:    s_wait_samplecnt 0x0175; GFX12-NEXT:    s_wait_bvhcnt 0x0176; GFX12-NEXT:    s_wait_kmcnt 0x0177; GFX12-NEXT:    v_minimum_f32 v0, v0, v1178; GFX12-NEXT:    s_setpc_b64 s[30:31]179  %op = call nsz float @llvm.minimum.f32(float %src0, float %src1)180  ret float %op181}182 183define float @v_minimum_f32__nnan_nsz(float %src0, float %src1) {184; GFX7-LABEL: v_minimum_f32__nnan_nsz:185; GFX7:       ; %bb.0:186; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)187; GFX7-NEXT:    v_min_f32_e32 v0, v0, v1188; GFX7-NEXT:    s_setpc_b64 s[30:31]189;190; GFX8-LABEL: v_minimum_f32__nnan_nsz:191; GFX8:       ; %bb.0:192; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)193; GFX8-NEXT:    v_min_f32_e32 v0, v0, v1194; GFX8-NEXT:    s_setpc_b64 s[30:31]195;196; GFX9-LABEL: v_minimum_f32__nnan_nsz:197; GFX9:       ; %bb.0:198; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)199; GFX9-NEXT:    v_min_f32_e32 v0, v0, v1200; GFX9-NEXT:    s_setpc_b64 s[30:31]201;202; GFX10-LABEL: v_minimum_f32__nnan_nsz:203; GFX10:       ; %bb.0:204; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)205; GFX10-NEXT:    v_min_f32_e32 v0, v0, v1206; GFX10-NEXT:    s_setpc_b64 s[30:31]207;208; GFX11-LABEL: v_minimum_f32__nnan_nsz:209; GFX11:       ; %bb.0:210; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)211; GFX11-NEXT:    v_min_f32_e32 v0, v0, v1212; GFX11-NEXT:    s_setpc_b64 s[30:31]213;214; GFX12-LABEL: v_minimum_f32__nnan_nsz:215; GFX12:       ; %bb.0:216; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0217; GFX12-NEXT:    s_wait_expcnt 0x0218; GFX12-NEXT:    s_wait_samplecnt 0x0219; GFX12-NEXT:    s_wait_bvhcnt 0x0220; GFX12-NEXT:    s_wait_kmcnt 0x0221; GFX12-NEXT:    v_minimum_f32 v0, v0, v1222; GFX12-NEXT:    s_setpc_b64 s[30:31]223  %op = call nnan nsz float @llvm.minimum.f32(float %src0, float %src1)224  ret float %op225}226 227define float @v_minimum_f32__nnan_src0(float %arg0, float %src1) {228; GFX7-LABEL: v_minimum_f32__nnan_src0:229; GFX7:       ; %bb.0:230; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)231; GFX7-NEXT:    v_add_f32_e32 v0, 1.0, v0232; GFX7-NEXT:    v_min_f32_e32 v2, v0, v1233; GFX7-NEXT:    v_mov_b32_e32 v3, 0x7fc00000234; GFX7-NEXT:    v_cmp_o_f32_e32 vcc, v0, v1235; GFX7-NEXT:    v_cndmask_b32_e32 v0, v3, v2, vcc236; GFX7-NEXT:    s_setpc_b64 s[30:31]237;238; GFX8-LABEL: v_minimum_f32__nnan_src0:239; GFX8:       ; %bb.0:240; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)241; GFX8-NEXT:    v_add_f32_e32 v0, 1.0, v0242; GFX8-NEXT:    v_min_f32_e32 v2, v0, v1243; GFX8-NEXT:    v_mov_b32_e32 v3, 0x7fc00000244; GFX8-NEXT:    v_cmp_o_f32_e32 vcc, v0, v1245; GFX8-NEXT:    v_cndmask_b32_e32 v0, v3, v2, vcc246; GFX8-NEXT:    s_setpc_b64 s[30:31]247;248; GFX900-LABEL: v_minimum_f32__nnan_src0:249; GFX900:       ; %bb.0:250; GFX900-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)251; GFX900-NEXT:    v_add_f32_e32 v0, 1.0, v0252; GFX900-NEXT:    v_min_f32_e32 v2, v0, v1253; GFX900-NEXT:    v_mov_b32_e32 v3, 0x7fc00000254; GFX900-NEXT:    v_cmp_o_f32_e32 vcc, v0, v1255; GFX900-NEXT:    v_cndmask_b32_e32 v0, v3, v2, vcc256; GFX900-NEXT:    s_setpc_b64 s[30:31]257;258; GFX950-LABEL: v_minimum_f32__nnan_src0:259; GFX950:       ; %bb.0:260; GFX950-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)261; GFX950-NEXT:    v_add_f32_e32 v0, 1.0, v0262; GFX950-NEXT:    v_minimum3_f32 v0, v0, v1, v1263; GFX950-NEXT:    s_setpc_b64 s[30:31]264;265; GFX10-LABEL: v_minimum_f32__nnan_src0:266; GFX10:       ; %bb.0:267; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)268; GFX10-NEXT:    v_add_f32_e32 v0, 1.0, v0269; GFX10-NEXT:    v_min_f32_e32 v2, v0, v1270; GFX10-NEXT:    v_cmp_o_f32_e32 vcc_lo, v0, v1271; GFX10-NEXT:    v_cndmask_b32_e32 v0, 0x7fc00000, v2, vcc_lo272; GFX10-NEXT:    s_setpc_b64 s[30:31]273;274; GFX11-LABEL: v_minimum_f32__nnan_src0:275; GFX11:       ; %bb.0:276; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)277; GFX11-NEXT:    v_add_f32_e32 v0, 1.0, v0278; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)279; GFX11-NEXT:    v_min_f32_e32 v2, v0, v1280; GFX11-NEXT:    v_cmp_o_f32_e32 vcc_lo, v0, v1281; GFX11-NEXT:    v_cndmask_b32_e32 v0, 0x7fc00000, v2, vcc_lo282; GFX11-NEXT:    s_setpc_b64 s[30:31]283;284; GFX12-LABEL: v_minimum_f32__nnan_src0:285; GFX12:       ; %bb.0:286; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0287; GFX12-NEXT:    s_wait_expcnt 0x0288; GFX12-NEXT:    s_wait_samplecnt 0x0289; GFX12-NEXT:    s_wait_bvhcnt 0x0290; GFX12-NEXT:    s_wait_kmcnt 0x0291; GFX12-NEXT:    v_add_f32_e32 v0, 1.0, v0292; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)293; GFX12-NEXT:    v_minimum_f32 v0, v0, v1294; GFX12-NEXT:    s_setpc_b64 s[30:31]295  %src0 = fadd nnan float %arg0, 1.0296  %op = call float @llvm.minimum.f32(float %src0, float %src1)297  ret float %op298}299 300define float @v_minimum_f32__nnan_src1(float %src0, float %arg1) {301; GFX7-LABEL: v_minimum_f32__nnan_src1:302; GFX7:       ; %bb.0:303; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)304; GFX7-NEXT:    v_add_f32_e32 v1, 1.0, v1305; GFX7-NEXT:    v_min_f32_e32 v2, v0, v1306; GFX7-NEXT:    v_mov_b32_e32 v3, 0x7fc00000307; GFX7-NEXT:    v_cmp_o_f32_e32 vcc, v0, v1308; GFX7-NEXT:    v_cndmask_b32_e32 v0, v3, v2, vcc309; GFX7-NEXT:    s_setpc_b64 s[30:31]310;311; GFX8-LABEL: v_minimum_f32__nnan_src1:312; GFX8:       ; %bb.0:313; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)314; GFX8-NEXT:    v_add_f32_e32 v1, 1.0, v1315; GFX8-NEXT:    v_min_f32_e32 v2, v0, v1316; GFX8-NEXT:    v_mov_b32_e32 v3, 0x7fc00000317; GFX8-NEXT:    v_cmp_o_f32_e32 vcc, v0, v1318; GFX8-NEXT:    v_cndmask_b32_e32 v0, v3, v2, vcc319; GFX8-NEXT:    s_setpc_b64 s[30:31]320;321; GFX900-LABEL: v_minimum_f32__nnan_src1:322; GFX900:       ; %bb.0:323; GFX900-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)324; GFX900-NEXT:    v_add_f32_e32 v1, 1.0, v1325; GFX900-NEXT:    v_min_f32_e32 v2, v0, v1326; GFX900-NEXT:    v_mov_b32_e32 v3, 0x7fc00000327; GFX900-NEXT:    v_cmp_o_f32_e32 vcc, v0, v1328; GFX900-NEXT:    v_cndmask_b32_e32 v0, v3, v2, vcc329; GFX900-NEXT:    s_setpc_b64 s[30:31]330;331; GFX950-LABEL: v_minimum_f32__nnan_src1:332; GFX950:       ; %bb.0:333; GFX950-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)334; GFX950-NEXT:    v_add_f32_e32 v1, 1.0, v1335; GFX950-NEXT:    v_minimum3_f32 v0, v0, v1, v1336; GFX950-NEXT:    s_setpc_b64 s[30:31]337;338; GFX10-LABEL: v_minimum_f32__nnan_src1:339; GFX10:       ; %bb.0:340; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)341; GFX10-NEXT:    v_add_f32_e32 v1, 1.0, v1342; GFX10-NEXT:    v_min_f32_e32 v2, v0, v1343; GFX10-NEXT:    v_cmp_o_f32_e32 vcc_lo, v0, v1344; GFX10-NEXT:    v_cndmask_b32_e32 v0, 0x7fc00000, v2, vcc_lo345; GFX10-NEXT:    s_setpc_b64 s[30:31]346;347; GFX11-LABEL: v_minimum_f32__nnan_src1:348; GFX11:       ; %bb.0:349; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)350; GFX11-NEXT:    v_add_f32_e32 v1, 1.0, v1351; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)352; GFX11-NEXT:    v_min_f32_e32 v2, v0, v1353; GFX11-NEXT:    v_cmp_o_f32_e32 vcc_lo, v0, v1354; GFX11-NEXT:    v_cndmask_b32_e32 v0, 0x7fc00000, v2, vcc_lo355; GFX11-NEXT:    s_setpc_b64 s[30:31]356;357; GFX12-LABEL: v_minimum_f32__nnan_src1:358; GFX12:       ; %bb.0:359; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0360; GFX12-NEXT:    s_wait_expcnt 0x0361; GFX12-NEXT:    s_wait_samplecnt 0x0362; GFX12-NEXT:    s_wait_bvhcnt 0x0363; GFX12-NEXT:    s_wait_kmcnt 0x0364; GFX12-NEXT:    v_add_f32_e32 v1, 1.0, v1365; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)366; GFX12-NEXT:    v_minimum_f32 v0, v0, v1367; GFX12-NEXT:    s_setpc_b64 s[30:31]368  %src1 = fadd nnan float %arg1, 1.0369  %op = call float @llvm.minimum.f32(float %src0, float %src1)370  ret float %op371}372 373define void @s_minimum_f32(float inreg %src0, float inreg %src1) {374; GFX7-LABEL: s_minimum_f32:375; GFX7:       ; %bb.0:376; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)377; GFX7-NEXT:    v_mov_b32_e32 v0, s17378; GFX7-NEXT:    v_min_f32_e32 v1, s16, v0379; GFX7-NEXT:    v_mov_b32_e32 v2, 0x7fc00000380; GFX7-NEXT:    v_cmp_o_f32_e32 vcc, s16, v0381; GFX7-NEXT:    v_cndmask_b32_e32 v0, v2, v1, vcc382; GFX7-NEXT:    ;;#ASMSTART383; GFX7-NEXT:    ; use v0384; GFX7-NEXT:    ;;#ASMEND385; GFX7-NEXT:    s_setpc_b64 s[30:31]386;387; GFX8-LABEL: s_minimum_f32:388; GFX8:       ; %bb.0:389; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)390; GFX8-NEXT:    v_mov_b32_e32 v0, s17391; GFX8-NEXT:    v_min_f32_e32 v1, s16, v0392; GFX8-NEXT:    v_mov_b32_e32 v2, 0x7fc00000393; GFX8-NEXT:    v_cmp_o_f32_e32 vcc, s16, v0394; GFX8-NEXT:    v_cndmask_b32_e32 v0, v2, v1, vcc395; GFX8-NEXT:    ;;#ASMSTART396; GFX8-NEXT:    ; use v0397; GFX8-NEXT:    ;;#ASMEND398; GFX8-NEXT:    s_setpc_b64 s[30:31]399;400; GFX900-LABEL: s_minimum_f32:401; GFX900:       ; %bb.0:402; GFX900-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)403; GFX900-NEXT:    v_mov_b32_e32 v0, s17404; GFX900-NEXT:    v_min_f32_e32 v1, s16, v0405; GFX900-NEXT:    v_mov_b32_e32 v2, 0x7fc00000406; GFX900-NEXT:    v_cmp_o_f32_e32 vcc, s16, v0407; GFX900-NEXT:    v_cndmask_b32_e32 v0, v2, v1, vcc408; GFX900-NEXT:    ;;#ASMSTART409; GFX900-NEXT:    ; use v0410; GFX900-NEXT:    ;;#ASMEND411; GFX900-NEXT:    s_setpc_b64 s[30:31]412;413; GFX950-LABEL: s_minimum_f32:414; GFX950:       ; %bb.0:415; GFX950-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)416; GFX950-NEXT:    v_mov_b32_e32 v0, s0417; GFX950-NEXT:    v_minimum3_f32 v0, v0, s1, s1418; GFX950-NEXT:    ;;#ASMSTART419; GFX950-NEXT:    ; use v0420; GFX950-NEXT:    ;;#ASMEND421; GFX950-NEXT:    s_setpc_b64 s[30:31]422;423; GFX10-LABEL: s_minimum_f32:424; GFX10:       ; %bb.0:425; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)426; GFX10-NEXT:    v_min_f32_e64 v0, s16, s17427; GFX10-NEXT:    v_cmp_o_f32_e64 vcc_lo, s16, s17428; GFX10-NEXT:    v_cndmask_b32_e32 v0, 0x7fc00000, v0, vcc_lo429; GFX10-NEXT:    ;;#ASMSTART430; GFX10-NEXT:    ; use v0431; GFX10-NEXT:    ;;#ASMEND432; GFX10-NEXT:    s_setpc_b64 s[30:31]433;434; GFX11-LABEL: s_minimum_f32:435; GFX11:       ; %bb.0:436; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)437; GFX11-NEXT:    v_min_f32_e64 v0, s0, s1438; GFX11-NEXT:    v_cmp_o_f32_e64 vcc_lo, s0, s1439; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)440; GFX11-NEXT:    v_cndmask_b32_e32 v0, 0x7fc00000, v0, vcc_lo441; GFX11-NEXT:    ;;#ASMSTART442; GFX11-NEXT:    ; use v0443; GFX11-NEXT:    ;;#ASMEND444; GFX11-NEXT:    s_setpc_b64 s[30:31]445;446; GFX12-LABEL: s_minimum_f32:447; GFX12:       ; %bb.0:448; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0449; GFX12-NEXT:    s_wait_expcnt 0x0450; GFX12-NEXT:    s_wait_samplecnt 0x0451; GFX12-NEXT:    s_wait_bvhcnt 0x0452; GFX12-NEXT:    s_wait_kmcnt 0x0453; GFX12-NEXT:    s_minimum_f32 s0, s0, s1454; GFX12-NEXT:    ;;#ASMSTART455; GFX12-NEXT:    ; use s0456; GFX12-NEXT:    ;;#ASMEND457; GFX12-NEXT:    s_wait_alu depctr_sa_sdst(0)458; GFX12-NEXT:    s_setpc_b64 s[30:31]459  %op = call float @llvm.minimum.f32(float %src0, float %src1)460  call void asm sideeffect "; use $0", "s"(float %op)461  ret void462}463 464define <2 x float> @v_minimum_v2f32(<2 x float> %src0, <2 x float> %src1) {465; GFX7-LABEL: v_minimum_v2f32:466; GFX7:       ; %bb.0:467; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)468; GFX7-NEXT:    v_min_f32_e32 v4, v0, v2469; GFX7-NEXT:    v_mov_b32_e32 v5, 0x7fc00000470; GFX7-NEXT:    v_cmp_o_f32_e32 vcc, v0, v2471; GFX7-NEXT:    v_cndmask_b32_e32 v0, v5, v4, vcc472; GFX7-NEXT:    v_min_f32_e32 v2, v1, v3473; GFX7-NEXT:    v_cmp_o_f32_e32 vcc, v1, v3474; GFX7-NEXT:    v_cndmask_b32_e32 v1, v5, v2, vcc475; GFX7-NEXT:    s_setpc_b64 s[30:31]476;477; GFX8-LABEL: v_minimum_v2f32:478; GFX8:       ; %bb.0:479; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)480; GFX8-NEXT:    v_min_f32_e32 v4, v0, v2481; GFX8-NEXT:    v_mov_b32_e32 v5, 0x7fc00000482; GFX8-NEXT:    v_cmp_o_f32_e32 vcc, v0, v2483; GFX8-NEXT:    v_cndmask_b32_e32 v0, v5, v4, vcc484; GFX8-NEXT:    v_min_f32_e32 v2, v1, v3485; GFX8-NEXT:    v_cmp_o_f32_e32 vcc, v1, v3486; GFX8-NEXT:    v_cndmask_b32_e32 v1, v5, v2, vcc487; GFX8-NEXT:    s_setpc_b64 s[30:31]488;489; GFX900-LABEL: v_minimum_v2f32:490; GFX900:       ; %bb.0:491; GFX900-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)492; GFX900-NEXT:    v_min_f32_e32 v4, v0, v2493; GFX900-NEXT:    v_mov_b32_e32 v5, 0x7fc00000494; GFX900-NEXT:    v_cmp_o_f32_e32 vcc, v0, v2495; GFX900-NEXT:    v_cndmask_b32_e32 v0, v5, v4, vcc496; GFX900-NEXT:    v_min_f32_e32 v2, v1, v3497; GFX900-NEXT:    v_cmp_o_f32_e32 vcc, v1, v3498; GFX900-NEXT:    v_cndmask_b32_e32 v1, v5, v2, vcc499; GFX900-NEXT:    s_setpc_b64 s[30:31]500;501; GFX950-LABEL: v_minimum_v2f32:502; GFX950:       ; %bb.0:503; GFX950-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)504; GFX950-NEXT:    v_minimum3_f32 v0, v0, v2, v2505; GFX950-NEXT:    v_minimum3_f32 v1, v1, v3, v3506; GFX950-NEXT:    s_setpc_b64 s[30:31]507;508; GFX10-LABEL: v_minimum_v2f32:509; GFX10:       ; %bb.0:510; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)511; GFX10-NEXT:    v_min_f32_e32 v4, v0, v2512; GFX10-NEXT:    v_cmp_o_f32_e32 vcc_lo, v0, v2513; GFX10-NEXT:    v_min_f32_e32 v5, v1, v3514; GFX10-NEXT:    v_cndmask_b32_e32 v0, 0x7fc00000, v4, vcc_lo515; GFX10-NEXT:    v_cmp_o_f32_e32 vcc_lo, v1, v3516; GFX10-NEXT:    v_cndmask_b32_e32 v1, 0x7fc00000, v5, vcc_lo517; GFX10-NEXT:    s_setpc_b64 s[30:31]518;519; GFX11-LABEL: v_minimum_v2f32:520; GFX11:       ; %bb.0:521; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)522; GFX11-NEXT:    v_dual_min_f32 v4, v0, v2 :: v_dual_min_f32 v5, v1, v3523; GFX11-NEXT:    v_cmp_o_f32_e32 vcc_lo, v0, v2524; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)525; GFX11-NEXT:    v_cndmask_b32_e32 v0, 0x7fc00000, v4, vcc_lo526; GFX11-NEXT:    v_cmp_o_f32_e32 vcc_lo, v1, v3527; GFX11-NEXT:    v_cndmask_b32_e32 v1, 0x7fc00000, v5, vcc_lo528; GFX11-NEXT:    s_setpc_b64 s[30:31]529;530; GFX12-LABEL: v_minimum_v2f32:531; GFX12:       ; %bb.0:532; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0533; GFX12-NEXT:    s_wait_expcnt 0x0534; GFX12-NEXT:    s_wait_samplecnt 0x0535; GFX12-NEXT:    s_wait_bvhcnt 0x0536; GFX12-NEXT:    s_wait_kmcnt 0x0537; GFX12-NEXT:    v_minimum_f32 v0, v0, v2538; GFX12-NEXT:    v_minimum_f32 v1, v1, v3539; GFX12-NEXT:    s_setpc_b64 s[30:31]540  %op = call <2 x float> @llvm.minimum.v2f32(<2 x float> %src0, <2 x float> %src1)541  ret <2 x float> %op542}543 544define <2 x float> @v_minimum_v2f32__nnan(<2 x float> %src0, <2 x float> %src1) {545; GFX7-LABEL: v_minimum_v2f32__nnan:546; GFX7:       ; %bb.0:547; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)548; GFX7-NEXT:    v_min_f32_e32 v0, v0, v2549; GFX7-NEXT:    v_min_f32_e32 v1, v1, v3550; GFX7-NEXT:    s_setpc_b64 s[30:31]551;552; GFX8-LABEL: v_minimum_v2f32__nnan:553; GFX8:       ; %bb.0:554; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)555; GFX8-NEXT:    v_min_f32_e32 v0, v0, v2556; GFX8-NEXT:    v_min_f32_e32 v1, v1, v3557; GFX8-NEXT:    s_setpc_b64 s[30:31]558;559; GFX9-LABEL: v_minimum_v2f32__nnan:560; GFX9:       ; %bb.0:561; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)562; GFX9-NEXT:    v_min_f32_e32 v0, v0, v2563; GFX9-NEXT:    v_min_f32_e32 v1, v1, v3564; GFX9-NEXT:    s_setpc_b64 s[30:31]565;566; GFX10-LABEL: v_minimum_v2f32__nnan:567; GFX10:       ; %bb.0:568; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)569; GFX10-NEXT:    v_min_f32_e32 v0, v0, v2570; GFX10-NEXT:    v_min_f32_e32 v1, v1, v3571; GFX10-NEXT:    s_setpc_b64 s[30:31]572;573; GFX11-LABEL: v_minimum_v2f32__nnan:574; GFX11:       ; %bb.0:575; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)576; GFX11-NEXT:    v_dual_min_f32 v0, v0, v2 :: v_dual_min_f32 v1, v1, v3577; GFX11-NEXT:    s_setpc_b64 s[30:31]578;579; GFX12-LABEL: v_minimum_v2f32__nnan:580; GFX12:       ; %bb.0:581; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0582; GFX12-NEXT:    s_wait_expcnt 0x0583; GFX12-NEXT:    s_wait_samplecnt 0x0584; GFX12-NEXT:    s_wait_bvhcnt 0x0585; GFX12-NEXT:    s_wait_kmcnt 0x0586; GFX12-NEXT:    v_minimum_f32 v0, v0, v2587; GFX12-NEXT:    v_minimum_f32 v1, v1, v3588; GFX12-NEXT:    s_setpc_b64 s[30:31]589  %op = call nnan <2 x float> @llvm.minimum.v2f32(<2 x float> %src0, <2 x float> %src1)590  ret <2 x float> %op591}592 593define <2 x float> @v_minimum_v2f32__nsz(<2 x float> %src0, <2 x float> %src1) {594; GFX7-LABEL: v_minimum_v2f32__nsz:595; GFX7:       ; %bb.0:596; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)597; GFX7-NEXT:    v_min_f32_e32 v4, v0, v2598; GFX7-NEXT:    v_mov_b32_e32 v5, 0x7fc00000599; GFX7-NEXT:    v_cmp_o_f32_e32 vcc, v0, v2600; GFX7-NEXT:    v_cndmask_b32_e32 v0, v5, v4, vcc601; GFX7-NEXT:    v_min_f32_e32 v2, v1, v3602; GFX7-NEXT:    v_cmp_o_f32_e32 vcc, v1, v3603; GFX7-NEXT:    v_cndmask_b32_e32 v1, v5, v2, vcc604; GFX7-NEXT:    s_setpc_b64 s[30:31]605;606; GFX8-LABEL: v_minimum_v2f32__nsz:607; GFX8:       ; %bb.0:608; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)609; GFX8-NEXT:    v_min_f32_e32 v4, v0, v2610; GFX8-NEXT:    v_mov_b32_e32 v5, 0x7fc00000611; GFX8-NEXT:    v_cmp_o_f32_e32 vcc, v0, v2612; GFX8-NEXT:    v_cndmask_b32_e32 v0, v5, v4, vcc613; GFX8-NEXT:    v_min_f32_e32 v2, v1, v3614; GFX8-NEXT:    v_cmp_o_f32_e32 vcc, v1, v3615; GFX8-NEXT:    v_cndmask_b32_e32 v1, v5, v2, vcc616; GFX8-NEXT:    s_setpc_b64 s[30:31]617;618; GFX900-LABEL: v_minimum_v2f32__nsz:619; GFX900:       ; %bb.0:620; GFX900-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)621; GFX900-NEXT:    v_min_f32_e32 v4, v0, v2622; GFX900-NEXT:    v_mov_b32_e32 v5, 0x7fc00000623; GFX900-NEXT:    v_cmp_o_f32_e32 vcc, v0, v2624; GFX900-NEXT:    v_cndmask_b32_e32 v0, v5, v4, vcc625; GFX900-NEXT:    v_min_f32_e32 v2, v1, v3626; GFX900-NEXT:    v_cmp_o_f32_e32 vcc, v1, v3627; GFX900-NEXT:    v_cndmask_b32_e32 v1, v5, v2, vcc628; GFX900-NEXT:    s_setpc_b64 s[30:31]629;630; GFX950-LABEL: v_minimum_v2f32__nsz:631; GFX950:       ; %bb.0:632; GFX950-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)633; GFX950-NEXT:    v_minimum3_f32 v0, v0, v2, v2634; GFX950-NEXT:    v_minimum3_f32 v1, v1, v3, v3635; GFX950-NEXT:    s_setpc_b64 s[30:31]636;637; GFX10-LABEL: v_minimum_v2f32__nsz:638; GFX10:       ; %bb.0:639; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)640; GFX10-NEXT:    v_min_f32_e32 v4, v0, v2641; GFX10-NEXT:    v_cmp_o_f32_e32 vcc_lo, v0, v2642; GFX10-NEXT:    v_min_f32_e32 v5, v1, v3643; GFX10-NEXT:    v_cndmask_b32_e32 v0, 0x7fc00000, v4, vcc_lo644; GFX10-NEXT:    v_cmp_o_f32_e32 vcc_lo, v1, v3645; GFX10-NEXT:    v_cndmask_b32_e32 v1, 0x7fc00000, v5, vcc_lo646; GFX10-NEXT:    s_setpc_b64 s[30:31]647;648; GFX11-LABEL: v_minimum_v2f32__nsz:649; GFX11:       ; %bb.0:650; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)651; GFX11-NEXT:    v_dual_min_f32 v4, v0, v2 :: v_dual_min_f32 v5, v1, v3652; GFX11-NEXT:    v_cmp_o_f32_e32 vcc_lo, v0, v2653; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)654; GFX11-NEXT:    v_cndmask_b32_e32 v0, 0x7fc00000, v4, vcc_lo655; GFX11-NEXT:    v_cmp_o_f32_e32 vcc_lo, v1, v3656; GFX11-NEXT:    v_cndmask_b32_e32 v1, 0x7fc00000, v5, vcc_lo657; GFX11-NEXT:    s_setpc_b64 s[30:31]658;659; GFX12-LABEL: v_minimum_v2f32__nsz:660; GFX12:       ; %bb.0:661; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0662; GFX12-NEXT:    s_wait_expcnt 0x0663; GFX12-NEXT:    s_wait_samplecnt 0x0664; GFX12-NEXT:    s_wait_bvhcnt 0x0665; GFX12-NEXT:    s_wait_kmcnt 0x0666; GFX12-NEXT:    v_minimum_f32 v0, v0, v2667; GFX12-NEXT:    v_minimum_f32 v1, v1, v3668; GFX12-NEXT:    s_setpc_b64 s[30:31]669  %op = call nsz <2 x float> @llvm.minimum.v2f32(<2 x float> %src0, <2 x float> %src1)670  ret <2 x float> %op671}672 673define <2 x float> @v_minimum_v2f32__nnan_nsz(<2 x float> %src0, <2 x float> %src1) {674; GFX7-LABEL: v_minimum_v2f32__nnan_nsz:675; GFX7:       ; %bb.0:676; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)677; GFX7-NEXT:    v_min_f32_e32 v0, v0, v2678; GFX7-NEXT:    v_min_f32_e32 v1, v1, v3679; GFX7-NEXT:    s_setpc_b64 s[30:31]680;681; GFX8-LABEL: v_minimum_v2f32__nnan_nsz:682; GFX8:       ; %bb.0:683; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)684; GFX8-NEXT:    v_min_f32_e32 v0, v0, v2685; GFX8-NEXT:    v_min_f32_e32 v1, v1, v3686; GFX8-NEXT:    s_setpc_b64 s[30:31]687;688; GFX9-LABEL: v_minimum_v2f32__nnan_nsz:689; GFX9:       ; %bb.0:690; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)691; GFX9-NEXT:    v_min_f32_e32 v0, v0, v2692; GFX9-NEXT:    v_min_f32_e32 v1, v1, v3693; GFX9-NEXT:    s_setpc_b64 s[30:31]694;695; GFX10-LABEL: v_minimum_v2f32__nnan_nsz:696; GFX10:       ; %bb.0:697; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)698; GFX10-NEXT:    v_min_f32_e32 v0, v0, v2699; GFX10-NEXT:    v_min_f32_e32 v1, v1, v3700; GFX10-NEXT:    s_setpc_b64 s[30:31]701;702; GFX11-LABEL: v_minimum_v2f32__nnan_nsz:703; GFX11:       ; %bb.0:704; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)705; GFX11-NEXT:    v_dual_min_f32 v0, v0, v2 :: v_dual_min_f32 v1, v1, v3706; GFX11-NEXT:    s_setpc_b64 s[30:31]707;708; GFX12-LABEL: v_minimum_v2f32__nnan_nsz:709; GFX12:       ; %bb.0:710; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0711; GFX12-NEXT:    s_wait_expcnt 0x0712; GFX12-NEXT:    s_wait_samplecnt 0x0713; GFX12-NEXT:    s_wait_bvhcnt 0x0714; GFX12-NEXT:    s_wait_kmcnt 0x0715; GFX12-NEXT:    v_minimum_f32 v0, v0, v2716; GFX12-NEXT:    v_minimum_f32 v1, v1, v3717; GFX12-NEXT:    s_setpc_b64 s[30:31]718  %op = call nnan nsz <2 x float> @llvm.minimum.v2f32(<2 x float> %src0, <2 x float> %src1)719  ret <2 x float> %op720}721 722define void @s_minimum_v2f32(<2 x float> inreg %src0, <2 x float> inreg %src1) {723; GFX7-LABEL: s_minimum_v2f32:724; GFX7:       ; %bb.0:725; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)726; GFX7-NEXT:    v_mov_b32_e32 v0, s19727; GFX7-NEXT:    v_min_f32_e32 v1, s17, v0728; GFX7-NEXT:    v_mov_b32_e32 v2, 0x7fc00000729; GFX7-NEXT:    v_cmp_o_f32_e32 vcc, s17, v0730; GFX7-NEXT:    v_mov_b32_e32 v0, s18731; GFX7-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc732; GFX7-NEXT:    v_min_f32_e32 v3, s16, v0733; GFX7-NEXT:    v_cmp_o_f32_e32 vcc, s16, v0734; GFX7-NEXT:    v_cndmask_b32_e32 v0, v2, v3, vcc735; GFX7-NEXT:    ;;#ASMSTART736; GFX7-NEXT:    ; use v[0:1]737; GFX7-NEXT:    ;;#ASMEND738; GFX7-NEXT:    s_setpc_b64 s[30:31]739;740; GFX8-LABEL: s_minimum_v2f32:741; GFX8:       ; %bb.0:742; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)743; GFX8-NEXT:    v_mov_b32_e32 v0, s19744; GFX8-NEXT:    v_min_f32_e32 v1, s17, v0745; GFX8-NEXT:    v_mov_b32_e32 v2, 0x7fc00000746; GFX8-NEXT:    v_cmp_o_f32_e32 vcc, s17, v0747; GFX8-NEXT:    v_mov_b32_e32 v0, s18748; GFX8-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc749; GFX8-NEXT:    v_min_f32_e32 v3, s16, v0750; GFX8-NEXT:    v_cmp_o_f32_e32 vcc, s16, v0751; GFX8-NEXT:    v_cndmask_b32_e32 v0, v2, v3, vcc752; GFX8-NEXT:    ;;#ASMSTART753; GFX8-NEXT:    ; use v[0:1]754; GFX8-NEXT:    ;;#ASMEND755; GFX8-NEXT:    s_setpc_b64 s[30:31]756;757; GFX900-LABEL: s_minimum_v2f32:758; GFX900:       ; %bb.0:759; GFX900-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)760; GFX900-NEXT:    v_mov_b32_e32 v0, s19761; GFX900-NEXT:    v_min_f32_e32 v1, s17, v0762; GFX900-NEXT:    v_mov_b32_e32 v2, 0x7fc00000763; GFX900-NEXT:    v_cmp_o_f32_e32 vcc, s17, v0764; GFX900-NEXT:    v_mov_b32_e32 v0, s18765; GFX900-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc766; GFX900-NEXT:    v_min_f32_e32 v3, s16, v0767; GFX900-NEXT:    v_cmp_o_f32_e32 vcc, s16, v0768; GFX900-NEXT:    v_cndmask_b32_e32 v0, v2, v3, vcc769; GFX900-NEXT:    ;;#ASMSTART770; GFX900-NEXT:    ; use v[0:1]771; GFX900-NEXT:    ;;#ASMEND772; GFX900-NEXT:    s_setpc_b64 s[30:31]773;774; GFX950-LABEL: s_minimum_v2f32:775; GFX950:       ; %bb.0:776; GFX950-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)777; GFX950-NEXT:    v_mov_b32_e32 v0, s1778; GFX950-NEXT:    v_minimum3_f32 v1, v0, s3, s3779; GFX950-NEXT:    v_mov_b32_e32 v0, s0780; GFX950-NEXT:    v_minimum3_f32 v0, v0, s2, s2781; GFX950-NEXT:    ;;#ASMSTART782; GFX950-NEXT:    ; use v[0:1]783; GFX950-NEXT:    ;;#ASMEND784; GFX950-NEXT:    s_setpc_b64 s[30:31]785;786; GFX10-LABEL: s_minimum_v2f32:787; GFX10:       ; %bb.0:788; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)789; GFX10-NEXT:    v_min_f32_e64 v0, s17, s19790; GFX10-NEXT:    v_cmp_o_f32_e64 vcc_lo, s17, s19791; GFX10-NEXT:    v_min_f32_e64 v2, s16, s18792; GFX10-NEXT:    v_cndmask_b32_e32 v1, 0x7fc00000, v0, vcc_lo793; GFX10-NEXT:    v_cmp_o_f32_e64 vcc_lo, s16, s18794; GFX10-NEXT:    v_cndmask_b32_e32 v0, 0x7fc00000, v2, vcc_lo795; GFX10-NEXT:    ;;#ASMSTART796; GFX10-NEXT:    ; use v[0:1]797; GFX10-NEXT:    ;;#ASMEND798; GFX10-NEXT:    s_setpc_b64 s[30:31]799;800; GFX11-LABEL: s_minimum_v2f32:801; GFX11:       ; %bb.0:802; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)803; GFX11-NEXT:    v_min_f32_e64 v0, s1, s3804; GFX11-NEXT:    v_cmp_o_f32_e64 vcc_lo, s1, s3805; GFX11-NEXT:    v_min_f32_e64 v2, s0, s2806; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)807; GFX11-NEXT:    v_cndmask_b32_e32 v1, 0x7fc00000, v0, vcc_lo808; GFX11-NEXT:    v_cmp_o_f32_e64 vcc_lo, s0, s2809; GFX11-NEXT:    v_cndmask_b32_e32 v0, 0x7fc00000, v2, vcc_lo810; GFX11-NEXT:    ;;#ASMSTART811; GFX11-NEXT:    ; use v[0:1]812; GFX11-NEXT:    ;;#ASMEND813; GFX11-NEXT:    s_setpc_b64 s[30:31]814;815; GFX12-LABEL: s_minimum_v2f32:816; GFX12:       ; %bb.0:817; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0818; GFX12-NEXT:    s_wait_expcnt 0x0819; GFX12-NEXT:    s_wait_samplecnt 0x0820; GFX12-NEXT:    s_wait_bvhcnt 0x0821; GFX12-NEXT:    s_wait_kmcnt 0x0822; GFX12-NEXT:    s_minimum_f32 s1, s1, s3823; GFX12-NEXT:    s_minimum_f32 s0, s0, s2824; GFX12-NEXT:    ;;#ASMSTART825; GFX12-NEXT:    ; use s[0:1]826; GFX12-NEXT:    ;;#ASMEND827; GFX12-NEXT:    s_wait_alu depctr_sa_sdst(0)828; GFX12-NEXT:    s_setpc_b64 s[30:31]829  %op = call <2 x float> @llvm.minimum.v2f32(<2 x float> %src0, <2 x float> %src1)830  call void asm sideeffect "; use $0", "s"(<2 x float> %op)831  ret void832}833 834define <3 x float> @v_minimum_v3f32(<3 x float> %src0, <3 x float> %src1) {835; GFX7-LABEL: v_minimum_v3f32:836; GFX7:       ; %bb.0:837; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)838; GFX7-NEXT:    v_min_f32_e32 v6, v0, v3839; GFX7-NEXT:    v_mov_b32_e32 v7, 0x7fc00000840; GFX7-NEXT:    v_cmp_o_f32_e32 vcc, v0, v3841; GFX7-NEXT:    v_cndmask_b32_e32 v0, v7, v6, vcc842; GFX7-NEXT:    v_min_f32_e32 v3, v1, v4843; GFX7-NEXT:    v_cmp_o_f32_e32 vcc, v1, v4844; GFX7-NEXT:    v_cndmask_b32_e32 v1, v7, v3, vcc845; GFX7-NEXT:    v_min_f32_e32 v3, v2, v5846; GFX7-NEXT:    v_cmp_o_f32_e32 vcc, v2, v5847; GFX7-NEXT:    v_cndmask_b32_e32 v2, v7, v3, vcc848; GFX7-NEXT:    s_setpc_b64 s[30:31]849;850; GFX8-LABEL: v_minimum_v3f32:851; GFX8:       ; %bb.0:852; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)853; GFX8-NEXT:    v_min_f32_e32 v6, v0, v3854; GFX8-NEXT:    v_mov_b32_e32 v7, 0x7fc00000855; GFX8-NEXT:    v_cmp_o_f32_e32 vcc, v0, v3856; GFX8-NEXT:    v_cndmask_b32_e32 v0, v7, v6, vcc857; GFX8-NEXT:    v_min_f32_e32 v3, v1, v4858; GFX8-NEXT:    v_cmp_o_f32_e32 vcc, v1, v4859; GFX8-NEXT:    v_cndmask_b32_e32 v1, v7, v3, vcc860; GFX8-NEXT:    v_min_f32_e32 v3, v2, v5861; GFX8-NEXT:    v_cmp_o_f32_e32 vcc, v2, v5862; GFX8-NEXT:    v_cndmask_b32_e32 v2, v7, v3, vcc863; GFX8-NEXT:    s_setpc_b64 s[30:31]864;865; GFX900-LABEL: v_minimum_v3f32:866; GFX900:       ; %bb.0:867; GFX900-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)868; GFX900-NEXT:    v_min_f32_e32 v6, v0, v3869; GFX900-NEXT:    v_mov_b32_e32 v7, 0x7fc00000870; GFX900-NEXT:    v_cmp_o_f32_e32 vcc, v0, v3871; GFX900-NEXT:    v_cndmask_b32_e32 v0, v7, v6, vcc872; GFX900-NEXT:    v_min_f32_e32 v3, v1, v4873; GFX900-NEXT:    v_cmp_o_f32_e32 vcc, v1, v4874; GFX900-NEXT:    v_cndmask_b32_e32 v1, v7, v3, vcc875; GFX900-NEXT:    v_min_f32_e32 v3, v2, v5876; GFX900-NEXT:    v_cmp_o_f32_e32 vcc, v2, v5877; GFX900-NEXT:    v_cndmask_b32_e32 v2, v7, v3, vcc878; GFX900-NEXT:    s_setpc_b64 s[30:31]879;880; GFX950-LABEL: v_minimum_v3f32:881; GFX950:       ; %bb.0:882; GFX950-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)883; GFX950-NEXT:    v_minimum3_f32 v0, v0, v3, v3884; GFX950-NEXT:    v_minimum3_f32 v1, v1, v4, v4885; GFX950-NEXT:    v_minimum3_f32 v2, v2, v5, v5886; GFX950-NEXT:    s_setpc_b64 s[30:31]887;888; GFX10-LABEL: v_minimum_v3f32:889; GFX10:       ; %bb.0:890; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)891; GFX10-NEXT:    v_min_f32_e32 v6, v0, v3892; GFX10-NEXT:    v_cmp_o_f32_e32 vcc_lo, v0, v3893; GFX10-NEXT:    v_min_f32_e32 v7, v1, v4894; GFX10-NEXT:    v_min_f32_e32 v8, v2, v5895; GFX10-NEXT:    v_cndmask_b32_e32 v0, 0x7fc00000, v6, vcc_lo896; GFX10-NEXT:    v_cmp_o_f32_e32 vcc_lo, v1, v4897; GFX10-NEXT:    v_cndmask_b32_e32 v1, 0x7fc00000, v7, vcc_lo898; GFX10-NEXT:    v_cmp_o_f32_e32 vcc_lo, v2, v5899; GFX10-NEXT:    v_cndmask_b32_e32 v2, 0x7fc00000, v8, vcc_lo900; GFX10-NEXT:    s_setpc_b64 s[30:31]901;902; GFX11-LABEL: v_minimum_v3f32:903; GFX11:       ; %bb.0:904; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)905; GFX11-NEXT:    v_dual_min_f32 v6, v0, v3 :: v_dual_min_f32 v7, v1, v4906; GFX11-NEXT:    v_cmp_o_f32_e32 vcc_lo, v0, v3907; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)908; GFX11-NEXT:    v_cndmask_b32_e32 v0, 0x7fc00000, v6, vcc_lo909; GFX11-NEXT:    v_cmp_o_f32_e32 vcc_lo, v1, v4910; GFX11-NEXT:    v_dual_min_f32 v8, v2, v5 :: v_dual_cndmask_b32 v1, 0x7fc00000, v7911; GFX11-NEXT:    v_cmp_o_f32_e32 vcc_lo, v2, v5912; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)913; GFX11-NEXT:    v_cndmask_b32_e32 v2, 0x7fc00000, v8, vcc_lo914; GFX11-NEXT:    s_setpc_b64 s[30:31]915;916; GFX12-LABEL: v_minimum_v3f32:917; GFX12:       ; %bb.0:918; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0919; GFX12-NEXT:    s_wait_expcnt 0x0920; GFX12-NEXT:    s_wait_samplecnt 0x0921; GFX12-NEXT:    s_wait_bvhcnt 0x0922; GFX12-NEXT:    s_wait_kmcnt 0x0923; GFX12-NEXT:    v_minimum_f32 v0, v0, v3924; GFX12-NEXT:    v_minimum_f32 v1, v1, v4925; GFX12-NEXT:    v_minimum_f32 v2, v2, v5926; GFX12-NEXT:    s_setpc_b64 s[30:31]927  %op = call <3 x float> @llvm.minimum.v3f32(<3 x float> %src0, <3 x float> %src1)928  ret <3 x float> %op929}930 931define <3 x float> @v_minimum_v3f32__nnan(<3 x float> %src0, <3 x float> %src1) {932; GFX7-LABEL: v_minimum_v3f32__nnan:933; GFX7:       ; %bb.0:934; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)935; GFX7-NEXT:    v_min_f32_e32 v0, v0, v3936; GFX7-NEXT:    v_min_f32_e32 v1, v1, v4937; GFX7-NEXT:    v_min_f32_e32 v2, v2, v5938; GFX7-NEXT:    s_setpc_b64 s[30:31]939;940; GFX8-LABEL: v_minimum_v3f32__nnan:941; GFX8:       ; %bb.0:942; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)943; GFX8-NEXT:    v_min_f32_e32 v0, v0, v3944; GFX8-NEXT:    v_min_f32_e32 v1, v1, v4945; GFX8-NEXT:    v_min_f32_e32 v2, v2, v5946; GFX8-NEXT:    s_setpc_b64 s[30:31]947;948; GFX9-LABEL: v_minimum_v3f32__nnan:949; GFX9:       ; %bb.0:950; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)951; GFX9-NEXT:    v_min_f32_e32 v0, v0, v3952; GFX9-NEXT:    v_min_f32_e32 v1, v1, v4953; GFX9-NEXT:    v_min_f32_e32 v2, v2, v5954; GFX9-NEXT:    s_setpc_b64 s[30:31]955;956; GFX10-LABEL: v_minimum_v3f32__nnan:957; GFX10:       ; %bb.0:958; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)959; GFX10-NEXT:    v_min_f32_e32 v0, v0, v3960; GFX10-NEXT:    v_min_f32_e32 v1, v1, v4961; GFX10-NEXT:    v_min_f32_e32 v2, v2, v5962; GFX10-NEXT:    s_setpc_b64 s[30:31]963;964; GFX11-LABEL: v_minimum_v3f32__nnan:965; GFX11:       ; %bb.0:966; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)967; GFX11-NEXT:    v_dual_min_f32 v0, v0, v3 :: v_dual_min_f32 v1, v1, v4968; GFX11-NEXT:    v_min_f32_e32 v2, v2, v5969; GFX11-NEXT:    s_setpc_b64 s[30:31]970;971; GFX12-LABEL: v_minimum_v3f32__nnan:972; GFX12:       ; %bb.0:973; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0974; GFX12-NEXT:    s_wait_expcnt 0x0975; GFX12-NEXT:    s_wait_samplecnt 0x0976; GFX12-NEXT:    s_wait_bvhcnt 0x0977; GFX12-NEXT:    s_wait_kmcnt 0x0978; GFX12-NEXT:    v_minimum_f32 v0, v0, v3979; GFX12-NEXT:    v_minimum_f32 v1, v1, v4980; GFX12-NEXT:    v_minimum_f32 v2, v2, v5981; GFX12-NEXT:    s_setpc_b64 s[30:31]982  %op = call nnan <3 x float> @llvm.minimum.v3f32(<3 x float> %src0, <3 x float> %src1)983  ret <3 x float> %op984}985 986define <3 x float> @v_minimum_v3f32__nsz(<3 x float> %src0, <3 x float> %src1) {987; GFX7-LABEL: v_minimum_v3f32__nsz:988; GFX7:       ; %bb.0:989; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)990; GFX7-NEXT:    v_min_f32_e32 v6, v0, v3991; GFX7-NEXT:    v_mov_b32_e32 v7, 0x7fc00000992; GFX7-NEXT:    v_cmp_o_f32_e32 vcc, v0, v3993; GFX7-NEXT:    v_cndmask_b32_e32 v0, v7, v6, vcc994; GFX7-NEXT:    v_min_f32_e32 v3, v1, v4995; GFX7-NEXT:    v_cmp_o_f32_e32 vcc, v1, v4996; GFX7-NEXT:    v_cndmask_b32_e32 v1, v7, v3, vcc997; GFX7-NEXT:    v_min_f32_e32 v3, v2, v5998; GFX7-NEXT:    v_cmp_o_f32_e32 vcc, v2, v5999; GFX7-NEXT:    v_cndmask_b32_e32 v2, v7, v3, vcc1000; GFX7-NEXT:    s_setpc_b64 s[30:31]1001;1002; GFX8-LABEL: v_minimum_v3f32__nsz:1003; GFX8:       ; %bb.0:1004; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1005; GFX8-NEXT:    v_min_f32_e32 v6, v0, v31006; GFX8-NEXT:    v_mov_b32_e32 v7, 0x7fc000001007; GFX8-NEXT:    v_cmp_o_f32_e32 vcc, v0, v31008; GFX8-NEXT:    v_cndmask_b32_e32 v0, v7, v6, vcc1009; GFX8-NEXT:    v_min_f32_e32 v3, v1, v41010; GFX8-NEXT:    v_cmp_o_f32_e32 vcc, v1, v41011; GFX8-NEXT:    v_cndmask_b32_e32 v1, v7, v3, vcc1012; GFX8-NEXT:    v_min_f32_e32 v3, v2, v51013; GFX8-NEXT:    v_cmp_o_f32_e32 vcc, v2, v51014; GFX8-NEXT:    v_cndmask_b32_e32 v2, v7, v3, vcc1015; GFX8-NEXT:    s_setpc_b64 s[30:31]1016;1017; GFX900-LABEL: v_minimum_v3f32__nsz:1018; GFX900:       ; %bb.0:1019; GFX900-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1020; GFX900-NEXT:    v_min_f32_e32 v6, v0, v31021; GFX900-NEXT:    v_mov_b32_e32 v7, 0x7fc000001022; GFX900-NEXT:    v_cmp_o_f32_e32 vcc, v0, v31023; GFX900-NEXT:    v_cndmask_b32_e32 v0, v7, v6, vcc1024; GFX900-NEXT:    v_min_f32_e32 v3, v1, v41025; GFX900-NEXT:    v_cmp_o_f32_e32 vcc, v1, v41026; GFX900-NEXT:    v_cndmask_b32_e32 v1, v7, v3, vcc1027; GFX900-NEXT:    v_min_f32_e32 v3, v2, v51028; GFX900-NEXT:    v_cmp_o_f32_e32 vcc, v2, v51029; GFX900-NEXT:    v_cndmask_b32_e32 v2, v7, v3, vcc1030; GFX900-NEXT:    s_setpc_b64 s[30:31]1031;1032; GFX950-LABEL: v_minimum_v3f32__nsz:1033; GFX950:       ; %bb.0:1034; GFX950-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1035; GFX950-NEXT:    v_minimum3_f32 v0, v0, v3, v31036; GFX950-NEXT:    v_minimum3_f32 v1, v1, v4, v41037; GFX950-NEXT:    v_minimum3_f32 v2, v2, v5, v51038; GFX950-NEXT:    s_setpc_b64 s[30:31]1039;1040; GFX10-LABEL: v_minimum_v3f32__nsz:1041; GFX10:       ; %bb.0:1042; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1043; GFX10-NEXT:    v_min_f32_e32 v6, v0, v31044; GFX10-NEXT:    v_cmp_o_f32_e32 vcc_lo, v0, v31045; GFX10-NEXT:    v_min_f32_e32 v7, v1, v41046; GFX10-NEXT:    v_min_f32_e32 v8, v2, v51047; GFX10-NEXT:    v_cndmask_b32_e32 v0, 0x7fc00000, v6, vcc_lo1048; GFX10-NEXT:    v_cmp_o_f32_e32 vcc_lo, v1, v41049; GFX10-NEXT:    v_cndmask_b32_e32 v1, 0x7fc00000, v7, vcc_lo1050; GFX10-NEXT:    v_cmp_o_f32_e32 vcc_lo, v2, v51051; GFX10-NEXT:    v_cndmask_b32_e32 v2, 0x7fc00000, v8, vcc_lo1052; GFX10-NEXT:    s_setpc_b64 s[30:31]1053;1054; GFX11-LABEL: v_minimum_v3f32__nsz:1055; GFX11:       ; %bb.0:1056; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1057; GFX11-NEXT:    v_dual_min_f32 v6, v0, v3 :: v_dual_min_f32 v7, v1, v41058; GFX11-NEXT:    v_cmp_o_f32_e32 vcc_lo, v0, v31059; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)1060; GFX11-NEXT:    v_cndmask_b32_e32 v0, 0x7fc00000, v6, vcc_lo1061; GFX11-NEXT:    v_cmp_o_f32_e32 vcc_lo, v1, v41062; GFX11-NEXT:    v_dual_min_f32 v8, v2, v5 :: v_dual_cndmask_b32 v1, 0x7fc00000, v71063; GFX11-NEXT:    v_cmp_o_f32_e32 vcc_lo, v2, v51064; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)1065; GFX11-NEXT:    v_cndmask_b32_e32 v2, 0x7fc00000, v8, vcc_lo1066; GFX11-NEXT:    s_setpc_b64 s[30:31]1067;1068; GFX12-LABEL: v_minimum_v3f32__nsz:1069; GFX12:       ; %bb.0:1070; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x01071; GFX12-NEXT:    s_wait_expcnt 0x01072; GFX12-NEXT:    s_wait_samplecnt 0x01073; GFX12-NEXT:    s_wait_bvhcnt 0x01074; GFX12-NEXT:    s_wait_kmcnt 0x01075; GFX12-NEXT:    v_minimum_f32 v0, v0, v31076; GFX12-NEXT:    v_minimum_f32 v1, v1, v41077; GFX12-NEXT:    v_minimum_f32 v2, v2, v51078; GFX12-NEXT:    s_setpc_b64 s[30:31]1079  %op = call nsz <3 x float> @llvm.minimum.v3f32(<3 x float> %src0, <3 x float> %src1)1080  ret <3 x float> %op1081}1082 1083define <3 x float> @v_minimum_v3f32__nnan_nsz(<3 x float> %src0, <3 x float> %src1) {1084; GFX7-LABEL: v_minimum_v3f32__nnan_nsz:1085; GFX7:       ; %bb.0:1086; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1087; GFX7-NEXT:    v_min_f32_e32 v0, v0, v31088; GFX7-NEXT:    v_min_f32_e32 v1, v1, v41089; GFX7-NEXT:    v_min_f32_e32 v2, v2, v51090; GFX7-NEXT:    s_setpc_b64 s[30:31]1091;1092; GFX8-LABEL: v_minimum_v3f32__nnan_nsz:1093; GFX8:       ; %bb.0:1094; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1095; GFX8-NEXT:    v_min_f32_e32 v0, v0, v31096; GFX8-NEXT:    v_min_f32_e32 v1, v1, v41097; GFX8-NEXT:    v_min_f32_e32 v2, v2, v51098; GFX8-NEXT:    s_setpc_b64 s[30:31]1099;1100; GFX9-LABEL: v_minimum_v3f32__nnan_nsz:1101; GFX9:       ; %bb.0:1102; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1103; GFX9-NEXT:    v_min_f32_e32 v0, v0, v31104; GFX9-NEXT:    v_min_f32_e32 v1, v1, v41105; GFX9-NEXT:    v_min_f32_e32 v2, v2, v51106; GFX9-NEXT:    s_setpc_b64 s[30:31]1107;1108; GFX10-LABEL: v_minimum_v3f32__nnan_nsz:1109; GFX10:       ; %bb.0:1110; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1111; GFX10-NEXT:    v_min_f32_e32 v0, v0, v31112; GFX10-NEXT:    v_min_f32_e32 v1, v1, v41113; GFX10-NEXT:    v_min_f32_e32 v2, v2, v51114; GFX10-NEXT:    s_setpc_b64 s[30:31]1115;1116; GFX11-LABEL: v_minimum_v3f32__nnan_nsz:1117; GFX11:       ; %bb.0:1118; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1119; GFX11-NEXT:    v_dual_min_f32 v0, v0, v3 :: v_dual_min_f32 v1, v1, v41120; GFX11-NEXT:    v_min_f32_e32 v2, v2, v51121; GFX11-NEXT:    s_setpc_b64 s[30:31]1122;1123; GFX12-LABEL: v_minimum_v3f32__nnan_nsz:1124; GFX12:       ; %bb.0:1125; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x01126; GFX12-NEXT:    s_wait_expcnt 0x01127; GFX12-NEXT:    s_wait_samplecnt 0x01128; GFX12-NEXT:    s_wait_bvhcnt 0x01129; GFX12-NEXT:    s_wait_kmcnt 0x01130; GFX12-NEXT:    v_minimum_f32 v0, v0, v31131; GFX12-NEXT:    v_minimum_f32 v1, v1, v41132; GFX12-NEXT:    v_minimum_f32 v2, v2, v51133; GFX12-NEXT:    s_setpc_b64 s[30:31]1134  %op = call nnan nsz <3 x float> @llvm.minimum.v3f32(<3 x float> %src0, <3 x float> %src1)1135  ret <3 x float> %op1136}1137 1138define <4 x float> @v_minimum_v4f32(<4 x float> %src0, <4 x float> %src1) {1139; GFX7-LABEL: v_minimum_v4f32:1140; GFX7:       ; %bb.0:1141; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1142; GFX7-NEXT:    v_min_f32_e32 v8, v0, v41143; GFX7-NEXT:    v_mov_b32_e32 v9, 0x7fc000001144; GFX7-NEXT:    v_cmp_o_f32_e32 vcc, v0, v41145; GFX7-NEXT:    v_cndmask_b32_e32 v0, v9, v8, vcc1146; GFX7-NEXT:    v_min_f32_e32 v4, v1, v51147; GFX7-NEXT:    v_cmp_o_f32_e32 vcc, v1, v51148; GFX7-NEXT:    v_cndmask_b32_e32 v1, v9, v4, vcc1149; GFX7-NEXT:    v_min_f32_e32 v4, v2, v61150; GFX7-NEXT:    v_cmp_o_f32_e32 vcc, v2, v61151; GFX7-NEXT:    v_cndmask_b32_e32 v2, v9, v4, vcc1152; GFX7-NEXT:    v_min_f32_e32 v4, v3, v71153; GFX7-NEXT:    v_cmp_o_f32_e32 vcc, v3, v71154; GFX7-NEXT:    v_cndmask_b32_e32 v3, v9, v4, vcc1155; GFX7-NEXT:    s_setpc_b64 s[30:31]1156;1157; GFX8-LABEL: v_minimum_v4f32:1158; GFX8:       ; %bb.0:1159; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1160; GFX8-NEXT:    v_min_f32_e32 v8, v0, v41161; GFX8-NEXT:    v_mov_b32_e32 v9, 0x7fc000001162; GFX8-NEXT:    v_cmp_o_f32_e32 vcc, v0, v41163; GFX8-NEXT:    v_cndmask_b32_e32 v0, v9, v8, vcc1164; GFX8-NEXT:    v_min_f32_e32 v4, v1, v51165; GFX8-NEXT:    v_cmp_o_f32_e32 vcc, v1, v51166; GFX8-NEXT:    v_cndmask_b32_e32 v1, v9, v4, vcc1167; GFX8-NEXT:    v_min_f32_e32 v4, v2, v61168; GFX8-NEXT:    v_cmp_o_f32_e32 vcc, v2, v61169; GFX8-NEXT:    v_cndmask_b32_e32 v2, v9, v4, vcc1170; GFX8-NEXT:    v_min_f32_e32 v4, v3, v71171; GFX8-NEXT:    v_cmp_o_f32_e32 vcc, v3, v71172; GFX8-NEXT:    v_cndmask_b32_e32 v3, v9, v4, vcc1173; GFX8-NEXT:    s_setpc_b64 s[30:31]1174;1175; GFX900-LABEL: v_minimum_v4f32:1176; GFX900:       ; %bb.0:1177; GFX900-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1178; GFX900-NEXT:    v_min_f32_e32 v8, v0, v41179; GFX900-NEXT:    v_mov_b32_e32 v9, 0x7fc000001180; GFX900-NEXT:    v_cmp_o_f32_e32 vcc, v0, v41181; GFX900-NEXT:    v_cndmask_b32_e32 v0, v9, v8, vcc1182; GFX900-NEXT:    v_min_f32_e32 v4, v1, v51183; GFX900-NEXT:    v_cmp_o_f32_e32 vcc, v1, v51184; GFX900-NEXT:    v_cndmask_b32_e32 v1, v9, v4, vcc1185; GFX900-NEXT:    v_min_f32_e32 v4, v2, v61186; GFX900-NEXT:    v_cmp_o_f32_e32 vcc, v2, v61187; GFX900-NEXT:    v_cndmask_b32_e32 v2, v9, v4, vcc1188; GFX900-NEXT:    v_min_f32_e32 v4, v3, v71189; GFX900-NEXT:    v_cmp_o_f32_e32 vcc, v3, v71190; GFX900-NEXT:    v_cndmask_b32_e32 v3, v9, v4, vcc1191; GFX900-NEXT:    s_setpc_b64 s[30:31]1192;1193; GFX950-LABEL: v_minimum_v4f32:1194; GFX950:       ; %bb.0:1195; GFX950-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1196; GFX950-NEXT:    v_minimum3_f32 v0, v0, v4, v41197; GFX950-NEXT:    v_minimum3_f32 v1, v1, v5, v51198; GFX950-NEXT:    v_minimum3_f32 v2, v2, v6, v61199; GFX950-NEXT:    v_minimum3_f32 v3, v3, v7, v71200; GFX950-NEXT:    s_setpc_b64 s[30:31]1201;1202; GFX10-LABEL: v_minimum_v4f32:1203; GFX10:       ; %bb.0:1204; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1205; GFX10-NEXT:    v_min_f32_e32 v8, v0, v41206; GFX10-NEXT:    v_cmp_o_f32_e32 vcc_lo, v0, v41207; GFX10-NEXT:    v_min_f32_e32 v9, v1, v51208; GFX10-NEXT:    v_min_f32_e32 v4, v2, v61209; GFX10-NEXT:    v_cndmask_b32_e32 v0, 0x7fc00000, v8, vcc_lo1210; GFX10-NEXT:    v_cmp_o_f32_e32 vcc_lo, v1, v51211; GFX10-NEXT:    v_min_f32_e32 v8, v3, v71212; GFX10-NEXT:    v_cndmask_b32_e32 v1, 0x7fc00000, v9, vcc_lo1213; GFX10-NEXT:    v_cmp_o_f32_e32 vcc_lo, v2, v61214; GFX10-NEXT:    v_cndmask_b32_e32 v2, 0x7fc00000, v4, vcc_lo1215; GFX10-NEXT:    v_cmp_o_f32_e32 vcc_lo, v3, v71216; GFX10-NEXT:    v_cndmask_b32_e32 v3, 0x7fc00000, v8, vcc_lo1217; GFX10-NEXT:    s_setpc_b64 s[30:31]1218;1219; GFX11-LABEL: v_minimum_v4f32:1220; GFX11:       ; %bb.0:1221; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1222; GFX11-NEXT:    v_dual_min_f32 v8, v0, v4 :: v_dual_min_f32 v9, v1, v51223; GFX11-NEXT:    v_cmp_o_f32_e32 vcc_lo, v0, v41224; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_3)1225; GFX11-NEXT:    v_cndmask_b32_e32 v0, 0x7fc00000, v8, vcc_lo1226; GFX11-NEXT:    v_cmp_o_f32_e32 vcc_lo, v1, v51227; GFX11-NEXT:    v_min_f32_e32 v4, v2, v61228; GFX11-NEXT:    v_dual_min_f32 v8, v3, v7 :: v_dual_cndmask_b32 v1, 0x7fc00000, v91229; GFX11-NEXT:    v_cmp_o_f32_e32 vcc_lo, v2, v61230; GFX11-NEXT:    v_cndmask_b32_e32 v2, 0x7fc00000, v4, vcc_lo1231; GFX11-NEXT:    v_cmp_o_f32_e32 vcc_lo, v3, v71232; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4)1233; GFX11-NEXT:    v_cndmask_b32_e32 v3, 0x7fc00000, v8, vcc_lo1234; GFX11-NEXT:    s_setpc_b64 s[30:31]1235;1236; GFX12-LABEL: v_minimum_v4f32:1237; GFX12:       ; %bb.0:1238; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x01239; GFX12-NEXT:    s_wait_expcnt 0x01240; GFX12-NEXT:    s_wait_samplecnt 0x01241; GFX12-NEXT:    s_wait_bvhcnt 0x01242; GFX12-NEXT:    s_wait_kmcnt 0x01243; GFX12-NEXT:    v_minimum_f32 v0, v0, v41244; GFX12-NEXT:    v_minimum_f32 v1, v1, v51245; GFX12-NEXT:    v_minimum_f32 v2, v2, v61246; GFX12-NEXT:    v_minimum_f32 v3, v3, v71247; GFX12-NEXT:    s_setpc_b64 s[30:31]1248  %op = call <4 x float> @llvm.minimum.v4f32(<4 x float> %src0, <4 x float> %src1)1249  ret <4 x float> %op1250}1251 1252define <4 x float> @v_minimum_v4f32__nnan(<4 x float> %src0, <4 x float> %src1) {1253; GFX7-LABEL: v_minimum_v4f32__nnan:1254; GFX7:       ; %bb.0:1255; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1256; GFX7-NEXT:    v_min_f32_e32 v0, v0, v41257; GFX7-NEXT:    v_min_f32_e32 v1, v1, v51258; GFX7-NEXT:    v_min_f32_e32 v2, v2, v61259; GFX7-NEXT:    v_min_f32_e32 v3, v3, v71260; GFX7-NEXT:    s_setpc_b64 s[30:31]1261;1262; GFX8-LABEL: v_minimum_v4f32__nnan:1263; GFX8:       ; %bb.0:1264; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1265; GFX8-NEXT:    v_min_f32_e32 v0, v0, v41266; GFX8-NEXT:    v_min_f32_e32 v1, v1, v51267; GFX8-NEXT:    v_min_f32_e32 v2, v2, v61268; GFX8-NEXT:    v_min_f32_e32 v3, v3, v71269; GFX8-NEXT:    s_setpc_b64 s[30:31]1270;1271; GFX9-LABEL: v_minimum_v4f32__nnan:1272; GFX9:       ; %bb.0:1273; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1274; GFX9-NEXT:    v_min_f32_e32 v0, v0, v41275; GFX9-NEXT:    v_min_f32_e32 v1, v1, v51276; GFX9-NEXT:    v_min_f32_e32 v2, v2, v61277; GFX9-NEXT:    v_min_f32_e32 v3, v3, v71278; GFX9-NEXT:    s_setpc_b64 s[30:31]1279;1280; GFX10-LABEL: v_minimum_v4f32__nnan:1281; GFX10:       ; %bb.0:1282; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1283; GFX10-NEXT:    v_min_f32_e32 v0, v0, v41284; GFX10-NEXT:    v_min_f32_e32 v1, v1, v51285; GFX10-NEXT:    v_min_f32_e32 v2, v2, v61286; GFX10-NEXT:    v_min_f32_e32 v3, v3, v71287; GFX10-NEXT:    s_setpc_b64 s[30:31]1288;1289; GFX11-LABEL: v_minimum_v4f32__nnan:1290; GFX11:       ; %bb.0:1291; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1292; GFX11-NEXT:    v_dual_min_f32 v0, v0, v4 :: v_dual_min_f32 v1, v1, v51293; GFX11-NEXT:    v_dual_min_f32 v2, v2, v6 :: v_dual_min_f32 v3, v3, v71294; GFX11-NEXT:    s_setpc_b64 s[30:31]1295;1296; GFX12-LABEL: v_minimum_v4f32__nnan:1297; GFX12:       ; %bb.0:1298; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x01299; GFX12-NEXT:    s_wait_expcnt 0x01300; GFX12-NEXT:    s_wait_samplecnt 0x01301; GFX12-NEXT:    s_wait_bvhcnt 0x01302; GFX12-NEXT:    s_wait_kmcnt 0x01303; GFX12-NEXT:    v_minimum_f32 v0, v0, v41304; GFX12-NEXT:    v_minimum_f32 v1, v1, v51305; GFX12-NEXT:    v_minimum_f32 v2, v2, v61306; GFX12-NEXT:    v_minimum_f32 v3, v3, v71307; GFX12-NEXT:    s_setpc_b64 s[30:31]1308  %op = call nnan <4 x float> @llvm.minimum.v4f32(<4 x float> %src0, <4 x float> %src1)1309  ret <4 x float> %op1310}1311 1312define <4 x float> @v_minimum_v4f32__nsz(<4 x float> %src0, <4 x float> %src1) {1313; GFX7-LABEL: v_minimum_v4f32__nsz:1314; GFX7:       ; %bb.0:1315; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1316; GFX7-NEXT:    v_min_f32_e32 v8, v0, v41317; GFX7-NEXT:    v_mov_b32_e32 v9, 0x7fc000001318; GFX7-NEXT:    v_cmp_o_f32_e32 vcc, v0, v41319; GFX7-NEXT:    v_cndmask_b32_e32 v0, v9, v8, vcc1320; GFX7-NEXT:    v_min_f32_e32 v4, v1, v51321; GFX7-NEXT:    v_cmp_o_f32_e32 vcc, v1, v51322; GFX7-NEXT:    v_cndmask_b32_e32 v1, v9, v4, vcc1323; GFX7-NEXT:    v_min_f32_e32 v4, v2, v61324; GFX7-NEXT:    v_cmp_o_f32_e32 vcc, v2, v61325; GFX7-NEXT:    v_cndmask_b32_e32 v2, v9, v4, vcc1326; GFX7-NEXT:    v_min_f32_e32 v4, v3, v71327; GFX7-NEXT:    v_cmp_o_f32_e32 vcc, v3, v71328; GFX7-NEXT:    v_cndmask_b32_e32 v3, v9, v4, vcc1329; GFX7-NEXT:    s_setpc_b64 s[30:31]1330;1331; GFX8-LABEL: v_minimum_v4f32__nsz:1332; GFX8:       ; %bb.0:1333; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1334; GFX8-NEXT:    v_min_f32_e32 v8, v0, v41335; GFX8-NEXT:    v_mov_b32_e32 v9, 0x7fc000001336; GFX8-NEXT:    v_cmp_o_f32_e32 vcc, v0, v41337; GFX8-NEXT:    v_cndmask_b32_e32 v0, v9, v8, vcc1338; GFX8-NEXT:    v_min_f32_e32 v4, v1, v51339; GFX8-NEXT:    v_cmp_o_f32_e32 vcc, v1, v51340; GFX8-NEXT:    v_cndmask_b32_e32 v1, v9, v4, vcc1341; GFX8-NEXT:    v_min_f32_e32 v4, v2, v61342; GFX8-NEXT:    v_cmp_o_f32_e32 vcc, v2, v61343; GFX8-NEXT:    v_cndmask_b32_e32 v2, v9, v4, vcc1344; GFX8-NEXT:    v_min_f32_e32 v4, v3, v71345; GFX8-NEXT:    v_cmp_o_f32_e32 vcc, v3, v71346; GFX8-NEXT:    v_cndmask_b32_e32 v3, v9, v4, vcc1347; GFX8-NEXT:    s_setpc_b64 s[30:31]1348;1349; GFX900-LABEL: v_minimum_v4f32__nsz:1350; GFX900:       ; %bb.0:1351; GFX900-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1352; GFX900-NEXT:    v_min_f32_e32 v8, v0, v41353; GFX900-NEXT:    v_mov_b32_e32 v9, 0x7fc000001354; GFX900-NEXT:    v_cmp_o_f32_e32 vcc, v0, v41355; GFX900-NEXT:    v_cndmask_b32_e32 v0, v9, v8, vcc1356; GFX900-NEXT:    v_min_f32_e32 v4, v1, v51357; GFX900-NEXT:    v_cmp_o_f32_e32 vcc, v1, v51358; GFX900-NEXT:    v_cndmask_b32_e32 v1, v9, v4, vcc1359; GFX900-NEXT:    v_min_f32_e32 v4, v2, v61360; GFX900-NEXT:    v_cmp_o_f32_e32 vcc, v2, v61361; GFX900-NEXT:    v_cndmask_b32_e32 v2, v9, v4, vcc1362; GFX900-NEXT:    v_min_f32_e32 v4, v3, v71363; GFX900-NEXT:    v_cmp_o_f32_e32 vcc, v3, v71364; GFX900-NEXT:    v_cndmask_b32_e32 v3, v9, v4, vcc1365; GFX900-NEXT:    s_setpc_b64 s[30:31]1366;1367; GFX950-LABEL: v_minimum_v4f32__nsz:1368; GFX950:       ; %bb.0:1369; GFX950-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1370; GFX950-NEXT:    v_minimum3_f32 v0, v0, v4, v41371; GFX950-NEXT:    v_minimum3_f32 v1, v1, v5, v51372; GFX950-NEXT:    v_minimum3_f32 v2, v2, v6, v61373; GFX950-NEXT:    v_minimum3_f32 v3, v3, v7, v71374; GFX950-NEXT:    s_setpc_b64 s[30:31]1375;1376; GFX10-LABEL: v_minimum_v4f32__nsz:1377; GFX10:       ; %bb.0:1378; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1379; GFX10-NEXT:    v_min_f32_e32 v8, v0, v41380; GFX10-NEXT:    v_cmp_o_f32_e32 vcc_lo, v0, v41381; GFX10-NEXT:    v_min_f32_e32 v9, v1, v51382; GFX10-NEXT:    v_min_f32_e32 v4, v2, v61383; GFX10-NEXT:    v_cndmask_b32_e32 v0, 0x7fc00000, v8, vcc_lo1384; GFX10-NEXT:    v_cmp_o_f32_e32 vcc_lo, v1, v51385; GFX10-NEXT:    v_min_f32_e32 v8, v3, v71386; GFX10-NEXT:    v_cndmask_b32_e32 v1, 0x7fc00000, v9, vcc_lo1387; GFX10-NEXT:    v_cmp_o_f32_e32 vcc_lo, v2, v61388; GFX10-NEXT:    v_cndmask_b32_e32 v2, 0x7fc00000, v4, vcc_lo1389; GFX10-NEXT:    v_cmp_o_f32_e32 vcc_lo, v3, v71390; GFX10-NEXT:    v_cndmask_b32_e32 v3, 0x7fc00000, v8, vcc_lo1391; GFX10-NEXT:    s_setpc_b64 s[30:31]1392;1393; GFX11-LABEL: v_minimum_v4f32__nsz:1394; GFX11:       ; %bb.0:1395; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1396; GFX11-NEXT:    v_dual_min_f32 v8, v0, v4 :: v_dual_min_f32 v9, v1, v51397; GFX11-NEXT:    v_cmp_o_f32_e32 vcc_lo, v0, v41398; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_3)1399; GFX11-NEXT:    v_cndmask_b32_e32 v0, 0x7fc00000, v8, vcc_lo1400; GFX11-NEXT:    v_cmp_o_f32_e32 vcc_lo, v1, v51401; GFX11-NEXT:    v_min_f32_e32 v4, v2, v61402; GFX11-NEXT:    v_dual_min_f32 v8, v3, v7 :: v_dual_cndmask_b32 v1, 0x7fc00000, v91403; GFX11-NEXT:    v_cmp_o_f32_e32 vcc_lo, v2, v61404; GFX11-NEXT:    v_cndmask_b32_e32 v2, 0x7fc00000, v4, vcc_lo1405; GFX11-NEXT:    v_cmp_o_f32_e32 vcc_lo, v3, v71406; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4)1407; GFX11-NEXT:    v_cndmask_b32_e32 v3, 0x7fc00000, v8, vcc_lo1408; GFX11-NEXT:    s_setpc_b64 s[30:31]1409;1410; GFX12-LABEL: v_minimum_v4f32__nsz:1411; GFX12:       ; %bb.0:1412; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x01413; GFX12-NEXT:    s_wait_expcnt 0x01414; GFX12-NEXT:    s_wait_samplecnt 0x01415; GFX12-NEXT:    s_wait_bvhcnt 0x01416; GFX12-NEXT:    s_wait_kmcnt 0x01417; GFX12-NEXT:    v_minimum_f32 v0, v0, v41418; GFX12-NEXT:    v_minimum_f32 v1, v1, v51419; GFX12-NEXT:    v_minimum_f32 v2, v2, v61420; GFX12-NEXT:    v_minimum_f32 v3, v3, v71421; GFX12-NEXT:    s_setpc_b64 s[30:31]1422  %op = call nsz <4 x float> @llvm.minimum.v4f32(<4 x float> %src0, <4 x float> %src1)1423  ret <4 x float> %op1424}1425 1426define <4 x float> @v_minimum_v4f32__nnan_nsz(<4 x float> %src0, <4 x float> %src1) {1427; GFX7-LABEL: v_minimum_v4f32__nnan_nsz:1428; GFX7:       ; %bb.0:1429; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1430; GFX7-NEXT:    v_min_f32_e32 v0, v0, v41431; GFX7-NEXT:    v_min_f32_e32 v1, v1, v51432; GFX7-NEXT:    v_min_f32_e32 v2, v2, v61433; GFX7-NEXT:    v_min_f32_e32 v3, v3, v71434; GFX7-NEXT:    s_setpc_b64 s[30:31]1435;1436; GFX8-LABEL: v_minimum_v4f32__nnan_nsz:1437; GFX8:       ; %bb.0:1438; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1439; GFX8-NEXT:    v_min_f32_e32 v0, v0, v41440; GFX8-NEXT:    v_min_f32_e32 v1, v1, v51441; GFX8-NEXT:    v_min_f32_e32 v2, v2, v61442; GFX8-NEXT:    v_min_f32_e32 v3, v3, v71443; GFX8-NEXT:    s_setpc_b64 s[30:31]1444;1445; GFX9-LABEL: v_minimum_v4f32__nnan_nsz:1446; GFX9:       ; %bb.0:1447; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1448; GFX9-NEXT:    v_min_f32_e32 v0, v0, v41449; GFX9-NEXT:    v_min_f32_e32 v1, v1, v51450; GFX9-NEXT:    v_min_f32_e32 v2, v2, v61451; GFX9-NEXT:    v_min_f32_e32 v3, v3, v71452; GFX9-NEXT:    s_setpc_b64 s[30:31]1453;1454; GFX10-LABEL: v_minimum_v4f32__nnan_nsz:1455; GFX10:       ; %bb.0:1456; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1457; GFX10-NEXT:    v_min_f32_e32 v0, v0, v41458; GFX10-NEXT:    v_min_f32_e32 v1, v1, v51459; GFX10-NEXT:    v_min_f32_e32 v2, v2, v61460; GFX10-NEXT:    v_min_f32_e32 v3, v3, v71461; GFX10-NEXT:    s_setpc_b64 s[30:31]1462;1463; GFX11-LABEL: v_minimum_v4f32__nnan_nsz:1464; GFX11:       ; %bb.0:1465; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1466; GFX11-NEXT:    v_dual_min_f32 v0, v0, v4 :: v_dual_min_f32 v1, v1, v51467; GFX11-NEXT:    v_dual_min_f32 v2, v2, v6 :: v_dual_min_f32 v3, v3, v71468; GFX11-NEXT:    s_setpc_b64 s[30:31]1469;1470; GFX12-LABEL: v_minimum_v4f32__nnan_nsz:1471; GFX12:       ; %bb.0:1472; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x01473; GFX12-NEXT:    s_wait_expcnt 0x01474; GFX12-NEXT:    s_wait_samplecnt 0x01475; GFX12-NEXT:    s_wait_bvhcnt 0x01476; GFX12-NEXT:    s_wait_kmcnt 0x01477; GFX12-NEXT:    v_minimum_f32 v0, v0, v41478; GFX12-NEXT:    v_minimum_f32 v1, v1, v51479; GFX12-NEXT:    v_minimum_f32 v2, v2, v61480; GFX12-NEXT:    v_minimum_f32 v3, v3, v71481; GFX12-NEXT:    s_setpc_b64 s[30:31]1482  %op = call nnan nsz <4 x float> @llvm.minimum.v4f32(<4 x float> %src0, <4 x float> %src1)1483  ret <4 x float> %op1484}1485 1486define <8 x float> @v_minimum_v8f32(<8 x float> %src0, <8 x float> %src1) {1487; GFX7-LABEL: v_minimum_v8f32:1488; GFX7:       ; %bb.0:1489; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1490; GFX7-NEXT:    v_min_f32_e32 v16, v0, v81491; GFX7-NEXT:    v_mov_b32_e32 v17, 0x7fc000001492; GFX7-NEXT:    v_cmp_o_f32_e32 vcc, v0, v81493; GFX7-NEXT:    v_cndmask_b32_e32 v0, v17, v16, vcc1494; GFX7-NEXT:    v_min_f32_e32 v8, v1, v91495; GFX7-NEXT:    v_cmp_o_f32_e32 vcc, v1, v91496; GFX7-NEXT:    v_cndmask_b32_e32 v1, v17, v8, vcc1497; GFX7-NEXT:    v_min_f32_e32 v8, v2, v101498; GFX7-NEXT:    v_cmp_o_f32_e32 vcc, v2, v101499; GFX7-NEXT:    v_cndmask_b32_e32 v2, v17, v8, vcc1500; GFX7-NEXT:    v_min_f32_e32 v8, v3, v111501; GFX7-NEXT:    v_cmp_o_f32_e32 vcc, v3, v111502; GFX7-NEXT:    v_cndmask_b32_e32 v3, v17, v8, vcc1503; GFX7-NEXT:    v_min_f32_e32 v8, v4, v121504; GFX7-NEXT:    v_cmp_o_f32_e32 vcc, v4, v121505; GFX7-NEXT:    v_cndmask_b32_e32 v4, v17, v8, vcc1506; GFX7-NEXT:    v_min_f32_e32 v8, v5, v131507; GFX7-NEXT:    v_cmp_o_f32_e32 vcc, v5, v131508; GFX7-NEXT:    v_cndmask_b32_e32 v5, v17, v8, vcc1509; GFX7-NEXT:    v_min_f32_e32 v8, v6, v141510; GFX7-NEXT:    v_cmp_o_f32_e32 vcc, v6, v141511; GFX7-NEXT:    v_cndmask_b32_e32 v6, v17, v8, vcc1512; GFX7-NEXT:    v_min_f32_e32 v8, v7, v151513; GFX7-NEXT:    v_cmp_o_f32_e32 vcc, v7, v151514; GFX7-NEXT:    v_cndmask_b32_e32 v7, v17, v8, vcc1515; GFX7-NEXT:    s_setpc_b64 s[30:31]1516;1517; GFX8-LABEL: v_minimum_v8f32:1518; GFX8:       ; %bb.0:1519; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1520; GFX8-NEXT:    v_min_f32_e32 v16, v0, v81521; GFX8-NEXT:    v_mov_b32_e32 v17, 0x7fc000001522; GFX8-NEXT:    v_cmp_o_f32_e32 vcc, v0, v81523; GFX8-NEXT:    v_cndmask_b32_e32 v0, v17, v16, vcc1524; GFX8-NEXT:    v_min_f32_e32 v8, v1, v91525; GFX8-NEXT:    v_cmp_o_f32_e32 vcc, v1, v91526; GFX8-NEXT:    v_cndmask_b32_e32 v1, v17, v8, vcc1527; GFX8-NEXT:    v_min_f32_e32 v8, v2, v101528; GFX8-NEXT:    v_cmp_o_f32_e32 vcc, v2, v101529; GFX8-NEXT:    v_cndmask_b32_e32 v2, v17, v8, vcc1530; GFX8-NEXT:    v_min_f32_e32 v8, v3, v111531; GFX8-NEXT:    v_cmp_o_f32_e32 vcc, v3, v111532; GFX8-NEXT:    v_cndmask_b32_e32 v3, v17, v8, vcc1533; GFX8-NEXT:    v_min_f32_e32 v8, v4, v121534; GFX8-NEXT:    v_cmp_o_f32_e32 vcc, v4, v121535; GFX8-NEXT:    v_cndmask_b32_e32 v4, v17, v8, vcc1536; GFX8-NEXT:    v_min_f32_e32 v8, v5, v131537; GFX8-NEXT:    v_cmp_o_f32_e32 vcc, v5, v131538; GFX8-NEXT:    v_cndmask_b32_e32 v5, v17, v8, vcc1539; GFX8-NEXT:    v_min_f32_e32 v8, v6, v141540; GFX8-NEXT:    v_cmp_o_f32_e32 vcc, v6, v141541; GFX8-NEXT:    v_cndmask_b32_e32 v6, v17, v8, vcc1542; GFX8-NEXT:    v_min_f32_e32 v8, v7, v151543; GFX8-NEXT:    v_cmp_o_f32_e32 vcc, v7, v151544; GFX8-NEXT:    v_cndmask_b32_e32 v7, v17, v8, vcc1545; GFX8-NEXT:    s_setpc_b64 s[30:31]1546;1547; GFX900-LABEL: v_minimum_v8f32:1548; GFX900:       ; %bb.0:1549; GFX900-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1550; GFX900-NEXT:    v_min_f32_e32 v16, v0, v81551; GFX900-NEXT:    v_mov_b32_e32 v17, 0x7fc000001552; GFX900-NEXT:    v_cmp_o_f32_e32 vcc, v0, v81553; GFX900-NEXT:    v_cndmask_b32_e32 v0, v17, v16, vcc1554; GFX900-NEXT:    v_min_f32_e32 v8, v1, v91555; GFX900-NEXT:    v_cmp_o_f32_e32 vcc, v1, v91556; GFX900-NEXT:    v_cndmask_b32_e32 v1, v17, v8, vcc1557; GFX900-NEXT:    v_min_f32_e32 v8, v2, v101558; GFX900-NEXT:    v_cmp_o_f32_e32 vcc, v2, v101559; GFX900-NEXT:    v_cndmask_b32_e32 v2, v17, v8, vcc1560; GFX900-NEXT:    v_min_f32_e32 v8, v3, v111561; GFX900-NEXT:    v_cmp_o_f32_e32 vcc, v3, v111562; GFX900-NEXT:    v_cndmask_b32_e32 v3, v17, v8, vcc1563; GFX900-NEXT:    v_min_f32_e32 v8, v4, v121564; GFX900-NEXT:    v_cmp_o_f32_e32 vcc, v4, v121565; GFX900-NEXT:    v_cndmask_b32_e32 v4, v17, v8, vcc1566; GFX900-NEXT:    v_min_f32_e32 v8, v5, v131567; GFX900-NEXT:    v_cmp_o_f32_e32 vcc, v5, v131568; GFX900-NEXT:    v_cndmask_b32_e32 v5, v17, v8, vcc1569; GFX900-NEXT:    v_min_f32_e32 v8, v6, v141570; GFX900-NEXT:    v_cmp_o_f32_e32 vcc, v6, v141571; GFX900-NEXT:    v_cndmask_b32_e32 v6, v17, v8, vcc1572; GFX900-NEXT:    v_min_f32_e32 v8, v7, v151573; GFX900-NEXT:    v_cmp_o_f32_e32 vcc, v7, v151574; GFX900-NEXT:    v_cndmask_b32_e32 v7, v17, v8, vcc1575; GFX900-NEXT:    s_setpc_b64 s[30:31]1576;1577; GFX950-LABEL: v_minimum_v8f32:1578; GFX950:       ; %bb.0:1579; GFX950-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1580; GFX950-NEXT:    v_minimum3_f32 v0, v0, v8, v81581; GFX950-NEXT:    v_minimum3_f32 v1, v1, v9, v91582; GFX950-NEXT:    v_minimum3_f32 v2, v2, v10, v101583; GFX950-NEXT:    v_minimum3_f32 v3, v3, v11, v111584; GFX950-NEXT:    v_minimum3_f32 v4, v4, v12, v121585; GFX950-NEXT:    v_minimum3_f32 v5, v5, v13, v131586; GFX950-NEXT:    v_minimum3_f32 v6, v6, v14, v141587; GFX950-NEXT:    v_minimum3_f32 v7, v7, v15, v151588; GFX950-NEXT:    s_setpc_b64 s[30:31]1589;1590; GFX10-LABEL: v_minimum_v8f32:1591; GFX10:       ; %bb.0:1592; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1593; GFX10-NEXT:    v_min_f32_e32 v16, v0, v81594; GFX10-NEXT:    v_cmp_o_f32_e32 vcc_lo, v0, v81595; GFX10-NEXT:    v_min_f32_e32 v17, v1, v91596; GFX10-NEXT:    v_min_f32_e32 v8, v2, v101597; GFX10-NEXT:    v_cndmask_b32_e32 v0, 0x7fc00000, v16, vcc_lo1598; GFX10-NEXT:    v_cmp_o_f32_e32 vcc_lo, v1, v91599; GFX10-NEXT:    v_min_f32_e32 v9, v3, v111600; GFX10-NEXT:    v_cndmask_b32_e32 v1, 0x7fc00000, v17, vcc_lo1601; GFX10-NEXT:    v_cmp_o_f32_e32 vcc_lo, v2, v101602; GFX10-NEXT:    v_min_f32_e32 v10, v7, v151603; GFX10-NEXT:    v_cndmask_b32_e32 v2, 0x7fc00000, v8, vcc_lo1604; GFX10-NEXT:    v_cmp_o_f32_e32 vcc_lo, v3, v111605; GFX10-NEXT:    v_min_f32_e32 v8, v4, v121606; GFX10-NEXT:    v_cndmask_b32_e32 v3, 0x7fc00000, v9, vcc_lo1607; GFX10-NEXT:    v_cmp_o_f32_e32 vcc_lo, v4, v121608; GFX10-NEXT:    v_min_f32_e32 v9, v5, v131609; GFX10-NEXT:    v_cndmask_b32_e32 v4, 0x7fc00000, v8, vcc_lo1610; GFX10-NEXT:    v_cmp_o_f32_e32 vcc_lo, v5, v131611; GFX10-NEXT:    v_min_f32_e32 v8, v6, v141612; GFX10-NEXT:    v_cndmask_b32_e32 v5, 0x7fc00000, v9, vcc_lo1613; GFX10-NEXT:    v_cmp_o_f32_e32 vcc_lo, v6, v141614; GFX10-NEXT:    v_cndmask_b32_e32 v6, 0x7fc00000, v8, vcc_lo1615; GFX10-NEXT:    v_cmp_o_f32_e32 vcc_lo, v7, v151616; GFX10-NEXT:    v_cndmask_b32_e32 v7, 0x7fc00000, v10, vcc_lo1617; GFX10-NEXT:    s_setpc_b64 s[30:31]1618;1619; GFX11-LABEL: v_minimum_v8f32:1620; GFX11:       ; %bb.0:1621; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1622; GFX11-NEXT:    v_dual_min_f32 v16, v0, v8 :: v_dual_min_f32 v17, v1, v91623; GFX11-NEXT:    v_cmp_o_f32_e32 vcc_lo, v0, v81624; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)1625; GFX11-NEXT:    v_cndmask_b32_e32 v0, 0x7fc00000, v16, vcc_lo1626; GFX11-NEXT:    v_cmp_o_f32_e32 vcc_lo, v1, v91627; GFX11-NEXT:    v_dual_min_f32 v8, v2, v10 :: v_dual_min_f32 v9, v3, v111628; GFX11-NEXT:    v_cndmask_b32_e32 v1, 0x7fc00000, v17, vcc_lo1629; GFX11-NEXT:    v_cmp_o_f32_e32 vcc_lo, v2, v101630; GFX11-NEXT:    v_min_f32_e32 v10, v7, v151631; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_2)1632; GFX11-NEXT:    v_cndmask_b32_e32 v2, 0x7fc00000, v8, vcc_lo1633; GFX11-NEXT:    v_cmp_o_f32_e32 vcc_lo, v3, v111634; GFX11-NEXT:    v_dual_min_f32 v8, v4, v12 :: v_dual_cndmask_b32 v3, 0x7fc00000, v91635; GFX11-NEXT:    v_cmp_o_f32_e32 vcc_lo, v4, v121636; GFX11-NEXT:    v_dual_min_f32 v9, v5, v13 :: v_dual_cndmask_b32 v4, 0x7fc00000, v81637; GFX11-NEXT:    v_cmp_o_f32_e32 vcc_lo, v5, v131638; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)1639; GFX11-NEXT:    v_dual_min_f32 v8, v6, v14 :: v_dual_cndmask_b32 v5, 0x7fc00000, v91640; GFX11-NEXT:    v_cmp_o_f32_e32 vcc_lo, v6, v141641; GFX11-NEXT:    v_cndmask_b32_e32 v6, 0x7fc00000, v8, vcc_lo1642; GFX11-NEXT:    v_cmp_o_f32_e32 vcc_lo, v7, v151643; GFX11-NEXT:    v_cndmask_b32_e32 v7, 0x7fc00000, v10, vcc_lo1644; GFX11-NEXT:    s_setpc_b64 s[30:31]1645;1646; GFX12-LABEL: v_minimum_v8f32:1647; GFX12:       ; %bb.0:1648; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x01649; GFX12-NEXT:    s_wait_expcnt 0x01650; GFX12-NEXT:    s_wait_samplecnt 0x01651; GFX12-NEXT:    s_wait_bvhcnt 0x01652; GFX12-NEXT:    s_wait_kmcnt 0x01653; GFX12-NEXT:    v_minimum_f32 v0, v0, v81654; GFX12-NEXT:    v_minimum_f32 v1, v1, v91655; GFX12-NEXT:    v_minimum_f32 v2, v2, v101656; GFX12-NEXT:    v_minimum_f32 v3, v3, v111657; GFX12-NEXT:    v_minimum_f32 v4, v4, v121658; GFX12-NEXT:    v_minimum_f32 v5, v5, v131659; GFX12-NEXT:    v_minimum_f32 v6, v6, v141660; GFX12-NEXT:    v_minimum_f32 v7, v7, v151661; GFX12-NEXT:    s_setpc_b64 s[30:31]1662  %op = call <8 x float> @llvm.minimum.v8f32(<8 x float> %src0, <8 x float> %src1)1663  ret <8 x float> %op1664}1665 1666define <16 x float> @v_minimum_v16f32(<16 x float> %src0, <16 x float> %src1) {1667; GFX7-LABEL: v_minimum_v16f32:1668; GFX7:       ; %bb.0:1669; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1670; GFX7-NEXT:    v_cmp_o_f32_e32 vcc, v0, v161671; GFX7-NEXT:    v_min_f32_e32 v0, v0, v161672; GFX7-NEXT:    buffer_load_dword v16, off, s[0:3], s321673; GFX7-NEXT:    v_cmp_o_f32_e64 s[4:5], v1, v171674; GFX7-NEXT:    v_min_f32_e32 v1, v1, v171675; GFX7-NEXT:    v_cmp_o_f32_e64 s[6:7], v2, v181676; GFX7-NEXT:    v_min_f32_e32 v2, v2, v181677; GFX7-NEXT:    v_mov_b32_e32 v17, 0x7fc000001678; GFX7-NEXT:    v_min_f32_e32 v18, v13, v291679; GFX7-NEXT:    v_cmp_o_f32_e64 s[28:29], v13, v291680; GFX7-NEXT:    v_cmp_o_f32_e64 s[8:9], v3, v191681; GFX7-NEXT:    v_min_f32_e32 v3, v3, v191682; GFX7-NEXT:    v_cmp_o_f32_e64 s[10:11], v4, v201683; GFX7-NEXT:    v_min_f32_e32 v4, v4, v201684; GFX7-NEXT:    v_cmp_o_f32_e64 s[12:13], v5, v211685; GFX7-NEXT:    v_min_f32_e32 v5, v5, v211686; GFX7-NEXT:    v_cmp_o_f32_e64 s[14:15], v6, v221687; GFX7-NEXT:    v_min_f32_e32 v6, v6, v221688; GFX7-NEXT:    v_cmp_o_f32_e64 s[16:17], v7, v231689; GFX7-NEXT:    v_min_f32_e32 v7, v7, v231690; GFX7-NEXT:    v_cmp_o_f32_e64 s[18:19], v8, v241691; GFX7-NEXT:    v_min_f32_e32 v8, v8, v241692; GFX7-NEXT:    v_cmp_o_f32_e64 s[20:21], v9, v251693; GFX7-NEXT:    v_min_f32_e32 v9, v9, v251694; GFX7-NEXT:    v_cmp_o_f32_e64 s[22:23], v10, v261695; GFX7-NEXT:    v_min_f32_e32 v10, v10, v261696; GFX7-NEXT:    v_cmp_o_f32_e64 s[24:25], v11, v271697; GFX7-NEXT:    v_min_f32_e32 v11, v11, v271698; GFX7-NEXT:    v_cmp_o_f32_e64 s[26:27], v12, v281699; GFX7-NEXT:    v_min_f32_e32 v12, v12, v281700; GFX7-NEXT:    v_min_f32_e32 v19, v14, v301701; GFX7-NEXT:    v_cmp_o_f32_e64 s[40:41], v14, v301702; GFX7-NEXT:    v_cndmask_b32_e32 v0, v17, v0, vcc1703; GFX7-NEXT:    v_cndmask_b32_e64 v13, v17, v18, s[28:29]1704; GFX7-NEXT:    v_cndmask_b32_e64 v1, v17, v1, s[4:5]1705; GFX7-NEXT:    v_cndmask_b32_e64 v2, v17, v2, s[6:7]1706; GFX7-NEXT:    v_cndmask_b32_e64 v3, v17, v3, s[8:9]1707; GFX7-NEXT:    v_cndmask_b32_e64 v4, v17, v4, s[10:11]1708; GFX7-NEXT:    v_cndmask_b32_e64 v5, v17, v5, s[12:13]1709; GFX7-NEXT:    v_cndmask_b32_e64 v6, v17, v6, s[14:15]1710; GFX7-NEXT:    v_cndmask_b32_e64 v7, v17, v7, s[16:17]1711; GFX7-NEXT:    v_cndmask_b32_e64 v8, v17, v8, s[18:19]1712; GFX7-NEXT:    v_cndmask_b32_e64 v9, v17, v9, s[20:21]1713; GFX7-NEXT:    v_cndmask_b32_e64 v10, v17, v10, s[22:23]1714; GFX7-NEXT:    v_cndmask_b32_e64 v11, v17, v11, s[24:25]1715; GFX7-NEXT:    v_cndmask_b32_e64 v12, v17, v12, s[26:27]1716; GFX7-NEXT:    v_cndmask_b32_e64 v14, v17, v19, s[40:41]1717; GFX7-NEXT:    s_waitcnt vmcnt(0)1718; GFX7-NEXT:    v_min_f32_e32 v18, v15, v161719; GFX7-NEXT:    v_cmp_o_f32_e32 vcc, v15, v161720; GFX7-NEXT:    v_cndmask_b32_e32 v15, v17, v18, vcc1721; GFX7-NEXT:    s_setpc_b64 s[30:31]1722;1723; GFX8-LABEL: v_minimum_v16f32:1724; GFX8:       ; %bb.0:1725; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1726; GFX8-NEXT:    v_cmp_o_f32_e32 vcc, v0, v161727; GFX8-NEXT:    v_min_f32_e32 v0, v0, v161728; GFX8-NEXT:    buffer_load_dword v16, off, s[0:3], s321729; GFX8-NEXT:    v_cmp_o_f32_e64 s[4:5], v1, v171730; GFX8-NEXT:    v_min_f32_e32 v1, v1, v171731; GFX8-NEXT:    v_cmp_o_f32_e64 s[6:7], v2, v181732; GFX8-NEXT:    v_min_f32_e32 v2, v2, v181733; GFX8-NEXT:    v_mov_b32_e32 v17, 0x7fc000001734; GFX8-NEXT:    v_min_f32_e32 v18, v13, v291735; GFX8-NEXT:    v_cmp_o_f32_e64 s[28:29], v13, v291736; GFX8-NEXT:    v_cmp_o_f32_e64 s[8:9], v3, v191737; GFX8-NEXT:    v_min_f32_e32 v3, v3, v191738; GFX8-NEXT:    v_cmp_o_f32_e64 s[10:11], v4, v201739; GFX8-NEXT:    v_min_f32_e32 v4, v4, v201740; GFX8-NEXT:    v_cmp_o_f32_e64 s[12:13], v5, v211741; GFX8-NEXT:    v_min_f32_e32 v5, v5, v211742; GFX8-NEXT:    v_cmp_o_f32_e64 s[14:15], v6, v221743; GFX8-NEXT:    v_min_f32_e32 v6, v6, v221744; GFX8-NEXT:    v_cmp_o_f32_e64 s[16:17], v7, v231745; GFX8-NEXT:    v_min_f32_e32 v7, v7, v231746; GFX8-NEXT:    v_cmp_o_f32_e64 s[18:19], v8, v241747; GFX8-NEXT:    v_min_f32_e32 v8, v8, v241748; GFX8-NEXT:    v_cmp_o_f32_e64 s[20:21], v9, v251749; GFX8-NEXT:    v_min_f32_e32 v9, v9, v251750; GFX8-NEXT:    v_cmp_o_f32_e64 s[22:23], v10, v261751; GFX8-NEXT:    v_min_f32_e32 v10, v10, v261752; GFX8-NEXT:    v_cmp_o_f32_e64 s[24:25], v11, v271753; GFX8-NEXT:    v_min_f32_e32 v11, v11, v271754; GFX8-NEXT:    v_cmp_o_f32_e64 s[26:27], v12, v281755; GFX8-NEXT:    v_min_f32_e32 v12, v12, v281756; GFX8-NEXT:    v_min_f32_e32 v19, v14, v301757; GFX8-NEXT:    v_cmp_o_f32_e64 s[40:41], v14, v301758; GFX8-NEXT:    v_cndmask_b32_e32 v0, v17, v0, vcc1759; GFX8-NEXT:    v_cndmask_b32_e64 v13, v17, v18, s[28:29]1760; GFX8-NEXT:    v_cndmask_b32_e64 v1, v17, v1, s[4:5]1761; GFX8-NEXT:    v_cndmask_b32_e64 v2, v17, v2, s[6:7]1762; GFX8-NEXT:    v_cndmask_b32_e64 v3, v17, v3, s[8:9]1763; GFX8-NEXT:    v_cndmask_b32_e64 v4, v17, v4, s[10:11]1764; GFX8-NEXT:    v_cndmask_b32_e64 v5, v17, v5, s[12:13]1765; GFX8-NEXT:    v_cndmask_b32_e64 v6, v17, v6, s[14:15]1766; GFX8-NEXT:    v_cndmask_b32_e64 v7, v17, v7, s[16:17]1767; GFX8-NEXT:    v_cndmask_b32_e64 v8, v17, v8, s[18:19]1768; GFX8-NEXT:    v_cndmask_b32_e64 v9, v17, v9, s[20:21]1769; GFX8-NEXT:    v_cndmask_b32_e64 v10, v17, v10, s[22:23]1770; GFX8-NEXT:    v_cndmask_b32_e64 v11, v17, v11, s[24:25]1771; GFX8-NEXT:    v_cndmask_b32_e64 v12, v17, v12, s[26:27]1772; GFX8-NEXT:    v_cndmask_b32_e64 v14, v17, v19, s[40:41]1773; GFX8-NEXT:    s_waitcnt vmcnt(0)1774; GFX8-NEXT:    v_min_f32_e32 v18, v15, v161775; GFX8-NEXT:    v_cmp_o_f32_e32 vcc, v15, v161776; GFX8-NEXT:    v_cndmask_b32_e32 v15, v17, v18, vcc1777; GFX8-NEXT:    s_setpc_b64 s[30:31]1778;1779; GFX900-LABEL: v_minimum_v16f32:1780; GFX900:       ; %bb.0:1781; GFX900-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1782; GFX900-NEXT:    v_cmp_o_f32_e32 vcc, v0, v161783; GFX900-NEXT:    v_min_f32_e32 v0, v0, v161784; GFX900-NEXT:    buffer_load_dword v16, off, s[0:3], s321785; GFX900-NEXT:    v_cmp_o_f32_e64 s[4:5], v1, v171786; GFX900-NEXT:    v_min_f32_e32 v1, v1, v171787; GFX900-NEXT:    v_cmp_o_f32_e64 s[6:7], v2, v181788; GFX900-NEXT:    v_min_f32_e32 v2, v2, v181789; GFX900-NEXT:    v_mov_b32_e32 v17, 0x7fc000001790; GFX900-NEXT:    v_min_f32_e32 v18, v13, v291791; GFX900-NEXT:    v_cmp_o_f32_e64 s[28:29], v13, v291792; GFX900-NEXT:    v_cmp_o_f32_e64 s[8:9], v3, v191793; GFX900-NEXT:    v_min_f32_e32 v3, v3, v191794; GFX900-NEXT:    v_cmp_o_f32_e64 s[10:11], v4, v201795; GFX900-NEXT:    v_min_f32_e32 v4, v4, v201796; GFX900-NEXT:    v_cmp_o_f32_e64 s[12:13], v5, v211797; GFX900-NEXT:    v_min_f32_e32 v5, v5, v211798; GFX900-NEXT:    v_cmp_o_f32_e64 s[14:15], v6, v221799; GFX900-NEXT:    v_min_f32_e32 v6, v6, v221800; GFX900-NEXT:    v_cmp_o_f32_e64 s[16:17], v7, v231801; GFX900-NEXT:    v_min_f32_e32 v7, v7, v231802; GFX900-NEXT:    v_cmp_o_f32_e64 s[18:19], v8, v241803; GFX900-NEXT:    v_min_f32_e32 v8, v8, v241804; GFX900-NEXT:    v_cmp_o_f32_e64 s[20:21], v9, v251805; GFX900-NEXT:    v_min_f32_e32 v9, v9, v251806; GFX900-NEXT:    v_cmp_o_f32_e64 s[22:23], v10, v261807; GFX900-NEXT:    v_min_f32_e32 v10, v10, v261808; GFX900-NEXT:    v_cmp_o_f32_e64 s[24:25], v11, v271809; GFX900-NEXT:    v_min_f32_e32 v11, v11, v271810; GFX900-NEXT:    v_cmp_o_f32_e64 s[26:27], v12, v281811; GFX900-NEXT:    v_min_f32_e32 v12, v12, v281812; GFX900-NEXT:    v_min_f32_e32 v19, v14, v301813; GFX900-NEXT:    v_cmp_o_f32_e64 s[40:41], v14, v301814; GFX900-NEXT:    v_cndmask_b32_e32 v0, v17, v0, vcc1815; GFX900-NEXT:    v_cndmask_b32_e64 v13, v17, v18, s[28:29]1816; GFX900-NEXT:    v_cndmask_b32_e64 v1, v17, v1, s[4:5]1817; GFX900-NEXT:    v_cndmask_b32_e64 v2, v17, v2, s[6:7]1818; GFX900-NEXT:    v_cndmask_b32_e64 v3, v17, v3, s[8:9]1819; GFX900-NEXT:    v_cndmask_b32_e64 v4, v17, v4, s[10:11]1820; GFX900-NEXT:    v_cndmask_b32_e64 v5, v17, v5, s[12:13]1821; GFX900-NEXT:    v_cndmask_b32_e64 v6, v17, v6, s[14:15]1822; GFX900-NEXT:    v_cndmask_b32_e64 v7, v17, v7, s[16:17]1823; GFX900-NEXT:    v_cndmask_b32_e64 v8, v17, v8, s[18:19]1824; GFX900-NEXT:    v_cndmask_b32_e64 v9, v17, v9, s[20:21]1825; GFX900-NEXT:    v_cndmask_b32_e64 v10, v17, v10, s[22:23]1826; GFX900-NEXT:    v_cndmask_b32_e64 v11, v17, v11, s[24:25]1827; GFX900-NEXT:    v_cndmask_b32_e64 v12, v17, v12, s[26:27]1828; GFX900-NEXT:    v_cndmask_b32_e64 v14, v17, v19, s[40:41]1829; GFX900-NEXT:    s_waitcnt vmcnt(0)1830; GFX900-NEXT:    v_min_f32_e32 v18, v15, v161831; GFX900-NEXT:    v_cmp_o_f32_e32 vcc, v15, v161832; GFX900-NEXT:    v_cndmask_b32_e32 v15, v17, v18, vcc1833; GFX900-NEXT:    s_setpc_b64 s[30:31]1834;1835; GFX950-LABEL: v_minimum_v16f32:1836; GFX950:       ; %bb.0:1837; GFX950-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1838; GFX950-NEXT:    scratch_load_dword v31, off, s321839; GFX950-NEXT:    v_minimum3_f32 v0, v0, v16, v161840; GFX950-NEXT:    v_minimum3_f32 v1, v1, v17, v171841; GFX950-NEXT:    v_minimum3_f32 v2, v2, v18, v181842; GFX950-NEXT:    v_minimum3_f32 v3, v3, v19, v191843; GFX950-NEXT:    v_minimum3_f32 v4, v4, v20, v201844; GFX950-NEXT:    v_minimum3_f32 v5, v5, v21, v211845; GFX950-NEXT:    v_minimum3_f32 v6, v6, v22, v221846; GFX950-NEXT:    v_minimum3_f32 v7, v7, v23, v231847; GFX950-NEXT:    v_minimum3_f32 v8, v8, v24, v241848; GFX950-NEXT:    v_minimum3_f32 v9, v9, v25, v251849; GFX950-NEXT:    v_minimum3_f32 v10, v10, v26, v261850; GFX950-NEXT:    v_minimum3_f32 v11, v11, v27, v271851; GFX950-NEXT:    v_minimum3_f32 v12, v12, v28, v281852; GFX950-NEXT:    v_minimum3_f32 v13, v13, v29, v291853; GFX950-NEXT:    v_minimum3_f32 v14, v14, v30, v301854; GFX950-NEXT:    s_waitcnt vmcnt(0)1855; GFX950-NEXT:    v_minimum3_f32 v15, v15, v31, v311856; GFX950-NEXT:    s_setpc_b64 s[30:31]1857;1858; GFX10-LABEL: v_minimum_v16f32:1859; GFX10:       ; %bb.0:1860; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1861; GFX10-NEXT:    buffer_load_dword v31, off, s[0:3], s321862; GFX10-NEXT:    v_min_f32_e32 v32, v0, v161863; GFX10-NEXT:    v_cmp_o_f32_e32 vcc_lo, v0, v161864; GFX10-NEXT:    v_min_f32_e32 v33, v1, v171865; GFX10-NEXT:    v_min_f32_e32 v34, v2, v181866; GFX10-NEXT:    v_min_f32_e32 v35, v3, v191867; GFX10-NEXT:    v_min_f32_e32 v36, v4, v201868; GFX10-NEXT:    v_cndmask_b32_e32 v0, 0x7fc00000, v32, vcc_lo1869; GFX10-NEXT:    v_cmp_o_f32_e32 vcc_lo, v1, v171870; GFX10-NEXT:    v_min_f32_e32 v37, v5, v211871; GFX10-NEXT:    v_min_f32_e32 v38, v6, v221872; GFX10-NEXT:    v_min_f32_e32 v39, v7, v231873; GFX10-NEXT:    v_min_f32_e32 v48, v8, v241874; GFX10-NEXT:    v_cndmask_b32_e32 v1, 0x7fc00000, v33, vcc_lo1875; GFX10-NEXT:    v_cmp_o_f32_e32 vcc_lo, v2, v181876; GFX10-NEXT:    v_min_f32_e32 v49, v9, v251877; GFX10-NEXT:    v_min_f32_e32 v50, v10, v261878; GFX10-NEXT:    v_min_f32_e32 v51, v11, v271879; GFX10-NEXT:    v_min_f32_e32 v52, v12, v281880; GFX10-NEXT:    v_cndmask_b32_e32 v2, 0x7fc00000, v34, vcc_lo1881; GFX10-NEXT:    v_cmp_o_f32_e32 vcc_lo, v3, v191882; GFX10-NEXT:    v_min_f32_e32 v53, v13, v291883; GFX10-NEXT:    v_min_f32_e32 v54, v14, v301884; GFX10-NEXT:    v_cndmask_b32_e32 v3, 0x7fc00000, v35, vcc_lo1885; GFX10-NEXT:    v_cmp_o_f32_e32 vcc_lo, v4, v201886; GFX10-NEXT:    v_cndmask_b32_e32 v4, 0x7fc00000, v36, vcc_lo1887; GFX10-NEXT:    v_cmp_o_f32_e32 vcc_lo, v5, v211888; GFX10-NEXT:    v_cndmask_b32_e32 v5, 0x7fc00000, v37, vcc_lo1889; GFX10-NEXT:    v_cmp_o_f32_e32 vcc_lo, v6, v221890; GFX10-NEXT:    v_cndmask_b32_e32 v6, 0x7fc00000, v38, vcc_lo1891; GFX10-NEXT:    v_cmp_o_f32_e32 vcc_lo, v7, v231892; GFX10-NEXT:    v_cndmask_b32_e32 v7, 0x7fc00000, v39, vcc_lo1893; GFX10-NEXT:    v_cmp_o_f32_e32 vcc_lo, v8, v241894; GFX10-NEXT:    v_cndmask_b32_e32 v8, 0x7fc00000, v48, vcc_lo1895; GFX10-NEXT:    v_cmp_o_f32_e32 vcc_lo, v9, v251896; GFX10-NEXT:    v_cndmask_b32_e32 v9, 0x7fc00000, v49, vcc_lo1897; GFX10-NEXT:    v_cmp_o_f32_e32 vcc_lo, v10, v261898; GFX10-NEXT:    v_cndmask_b32_e32 v10, 0x7fc00000, v50, vcc_lo1899; GFX10-NEXT:    v_cmp_o_f32_e32 vcc_lo, v11, v271900; GFX10-NEXT:    v_cndmask_b32_e32 v11, 0x7fc00000, v51, vcc_lo1901; GFX10-NEXT:    v_cmp_o_f32_e32 vcc_lo, v12, v281902; GFX10-NEXT:    v_cndmask_b32_e32 v12, 0x7fc00000, v52, vcc_lo1903; GFX10-NEXT:    v_cmp_o_f32_e32 vcc_lo, v13, v291904; GFX10-NEXT:    v_cndmask_b32_e32 v13, 0x7fc00000, v53, vcc_lo1905; GFX10-NEXT:    v_cmp_o_f32_e32 vcc_lo, v14, v301906; GFX10-NEXT:    v_cndmask_b32_e32 v14, 0x7fc00000, v54, vcc_lo1907; GFX10-NEXT:    s_waitcnt vmcnt(0)1908; GFX10-NEXT:    v_min_f32_e32 v16, v15, v311909; GFX10-NEXT:    v_cmp_o_f32_e32 vcc_lo, v15, v311910; GFX10-NEXT:    v_cndmask_b32_e32 v15, 0x7fc00000, v16, vcc_lo1911; GFX10-NEXT:    s_setpc_b64 s[30:31]1912;1913; GFX11-LABEL: v_minimum_v16f32:1914; GFX11:       ; %bb.0:1915; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1916; GFX11-NEXT:    scratch_load_b32 v31, off, s321917; GFX11-NEXT:    v_dual_min_f32 v32, v0, v16 :: v_dual_min_f32 v33, v1, v171918; GFX11-NEXT:    v_cmp_o_f32_e32 vcc_lo, v0, v161919; GFX11-NEXT:    v_dual_min_f32 v34, v2, v18 :: v_dual_min_f32 v35, v3, v191920; GFX11-NEXT:    v_dual_min_f32 v36, v4, v20 :: v_dual_min_f32 v37, v5, v211921; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4)1922; GFX11-NEXT:    v_cndmask_b32_e32 v0, 0x7fc00000, v32, vcc_lo1923; GFX11-NEXT:    v_cmp_o_f32_e32 vcc_lo, v1, v171924; GFX11-NEXT:    v_min_f32_e32 v54, v14, v301925; GFX11-NEXT:    v_dual_min_f32 v38, v6, v22 :: v_dual_min_f32 v39, v7, v231926; GFX11-NEXT:    v_dual_min_f32 v48, v8, v24 :: v_dual_min_f32 v49, v9, v251927; GFX11-NEXT:    v_cndmask_b32_e32 v1, 0x7fc00000, v33, vcc_lo1928; GFX11-NEXT:    v_cmp_o_f32_e32 vcc_lo, v2, v181929; GFX11-NEXT:    v_dual_min_f32 v50, v10, v26 :: v_dual_min_f32 v51, v11, v271930; GFX11-NEXT:    v_dual_min_f32 v52, v12, v28 :: v_dual_min_f32 v53, v13, v291931; GFX11-NEXT:    v_cndmask_b32_e32 v2, 0x7fc00000, v34, vcc_lo1932; GFX11-NEXT:    v_cmp_o_f32_e32 vcc_lo, v3, v191933; GFX11-NEXT:    v_cndmask_b32_e32 v3, 0x7fc00000, v35, vcc_lo1934; GFX11-NEXT:    v_cmp_o_f32_e32 vcc_lo, v4, v201935; GFX11-NEXT:    v_cndmask_b32_e32 v4, 0x7fc00000, v36, vcc_lo1936; GFX11-NEXT:    v_cmp_o_f32_e32 vcc_lo, v5, v211937; GFX11-NEXT:    v_cndmask_b32_e32 v5, 0x7fc00000, v37, vcc_lo1938; GFX11-NEXT:    v_cmp_o_f32_e32 vcc_lo, v6, v221939; GFX11-NEXT:    v_cndmask_b32_e32 v6, 0x7fc00000, v38, vcc_lo1940; GFX11-NEXT:    v_cmp_o_f32_e32 vcc_lo, v7, v231941; GFX11-NEXT:    v_cndmask_b32_e32 v7, 0x7fc00000, v39, vcc_lo1942; GFX11-NEXT:    v_cmp_o_f32_e32 vcc_lo, v8, v241943; GFX11-NEXT:    v_cndmask_b32_e32 v8, 0x7fc00000, v48, vcc_lo1944; GFX11-NEXT:    v_cmp_o_f32_e32 vcc_lo, v9, v251945; GFX11-NEXT:    v_cndmask_b32_e32 v9, 0x7fc00000, v49, vcc_lo1946; GFX11-NEXT:    v_cmp_o_f32_e32 vcc_lo, v10, v261947; GFX11-NEXT:    v_cndmask_b32_e32 v10, 0x7fc00000, v50, vcc_lo1948; GFX11-NEXT:    v_cmp_o_f32_e32 vcc_lo, v11, v271949; GFX11-NEXT:    v_cndmask_b32_e32 v11, 0x7fc00000, v51, vcc_lo1950; GFX11-NEXT:    v_cmp_o_f32_e32 vcc_lo, v12, v281951; GFX11-NEXT:    v_cndmask_b32_e32 v12, 0x7fc00000, v52, vcc_lo1952; GFX11-NEXT:    v_cmp_o_f32_e32 vcc_lo, v13, v291953; GFX11-NEXT:    v_cndmask_b32_e32 v13, 0x7fc00000, v53, vcc_lo1954; GFX11-NEXT:    v_cmp_o_f32_e32 vcc_lo, v14, v301955; GFX11-NEXT:    v_cndmask_b32_e32 v14, 0x7fc00000, v54, vcc_lo1956; GFX11-NEXT:    s_waitcnt vmcnt(0)1957; GFX11-NEXT:    v_min_f32_e32 v16, v15, v311958; GFX11-NEXT:    v_cmp_o_f32_e32 vcc_lo, v15, v311959; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)1960; GFX11-NEXT:    v_cndmask_b32_e32 v15, 0x7fc00000, v16, vcc_lo1961; GFX11-NEXT:    s_setpc_b64 s[30:31]1962;1963; GFX12-LABEL: v_minimum_v16f32:1964; GFX12:       ; %bb.0:1965; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x01966; GFX12-NEXT:    s_wait_expcnt 0x01967; GFX12-NEXT:    s_wait_samplecnt 0x01968; GFX12-NEXT:    s_wait_bvhcnt 0x01969; GFX12-NEXT:    s_wait_kmcnt 0x01970; GFX12-NEXT:    scratch_load_b32 v31, off, s321971; GFX12-NEXT:    v_minimum_f32 v0, v0, v161972; GFX12-NEXT:    v_minimum_f32 v1, v1, v171973; GFX12-NEXT:    v_minimum_f32 v2, v2, v181974; GFX12-NEXT:    v_minimum_f32 v3, v3, v191975; GFX12-NEXT:    v_minimum_f32 v4, v4, v201976; GFX12-NEXT:    v_minimum_f32 v5, v5, v211977; GFX12-NEXT:    v_minimum_f32 v6, v6, v221978; GFX12-NEXT:    v_minimum_f32 v7, v7, v231979; GFX12-NEXT:    v_minimum_f32 v8, v8, v241980; GFX12-NEXT:    v_minimum_f32 v9, v9, v251981; GFX12-NEXT:    v_minimum_f32 v10, v10, v261982; GFX12-NEXT:    v_minimum_f32 v11, v11, v271983; GFX12-NEXT:    v_minimum_f32 v12, v12, v281984; GFX12-NEXT:    v_minimum_f32 v13, v13, v291985; GFX12-NEXT:    v_minimum_f32 v14, v14, v301986; GFX12-NEXT:    s_wait_loadcnt 0x01987; GFX12-NEXT:    v_minimum_f32 v15, v15, v311988; GFX12-NEXT:    s_setpc_b64 s[30:31]1989  %op = call <16 x float> @llvm.minimum.v16f32(<16 x float> %src0, <16 x float> %src1)1990  ret <16 x float> %op1991}1992;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:1993; GCN: {{.*}}1994