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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn < %s | FileCheck --check-prefix=SI %s3; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck --check-prefix=GFX9 %s4; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck --check-prefix=GFX10 %s5; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck --check-prefix=GFX11 %s6; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck --check-prefix=GFX12 %s7 8define { i64, i1 } @umulo_i64_v_v(i64 %x, i64 %y) {9; SI-LABEL: umulo_i64_v_v:10; SI: ; %bb.0: ; %bb11; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)12; SI-NEXT: v_mul_hi_u32 v4, v1, v213; SI-NEXT: v_mul_lo_u32 v5, v1, v214; SI-NEXT: v_mul_hi_u32 v6, v0, v315; SI-NEXT: v_mul_lo_u32 v7, v0, v316; SI-NEXT: v_mul_hi_u32 v8, v0, v217; SI-NEXT: v_mul_hi_u32 v9, v1, v318; SI-NEXT: v_mul_lo_u32 v3, v1, v319; SI-NEXT: v_mul_lo_u32 v0, v0, v220; SI-NEXT: v_add_i32_e32 v1, vcc, v8, v721; SI-NEXT: v_addc_u32_e32 v2, vcc, 0, v6, vcc22; SI-NEXT: v_add_i32_e32 v6, vcc, v1, v523; SI-NEXT: v_add_i32_e64 v1, s[4:5], v1, v524; SI-NEXT: v_addc_u32_e32 v2, vcc, v2, v4, vcc25; SI-NEXT: v_addc_u32_e32 v4, vcc, 0, v9, vcc26; SI-NEXT: v_add_i32_e32 v2, vcc, v2, v327; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc28; SI-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[2:3]29; SI-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc30; SI-NEXT: s_setpc_b64 s[30:31]31;32; GFX9-LABEL: umulo_i64_v_v:33; GFX9: ; %bb.0: ; %bb34; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)35; GFX9-NEXT: v_mov_b32_e32 v4, v136; GFX9-NEXT: v_mad_u64_u32 v[5:6], s[4:5], v0, v3, 037; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v0, v2, 038; GFX9-NEXT: v_mad_u64_u32 v[7:8], s[4:5], v4, v2, 039; GFX9-NEXT: v_add_co_u32_e32 v9, vcc, v1, v540; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v4, v3, 041; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, 0, v6, vcc42; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v9, v743; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v6, v8, vcc44; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc45; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v4, v246; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc47; GFX9-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[2:3]48; GFX9-NEXT: v_add3_u32 v1, v1, v5, v749; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc50; GFX9-NEXT: s_setpc_b64 s[30:31]51;52; GFX10-LABEL: umulo_i64_v_v:53; GFX10: ; %bb.0: ; %bb54; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)55; GFX10-NEXT: v_mov_b32_e32 v4, v156; GFX10-NEXT: v_mad_u64_u32 v[5:6], s4, v0, v3, 057; GFX10-NEXT: v_mad_u64_u32 v[0:1], s4, v0, v2, 058; GFX10-NEXT: v_mad_u64_u32 v[7:8], s4, v4, v2, 059; GFX10-NEXT: v_mad_u64_u32 v[2:3], s4, v4, v3, 060; GFX10-NEXT: v_add_co_u32 v4, vcc_lo, v1, v561; GFX10-NEXT: v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo62; GFX10-NEXT: v_add3_u32 v1, v1, v5, v763; GFX10-NEXT: v_add_co_u32 v4, vcc_lo, v4, v764; GFX10-NEXT: v_add_co_ci_u32_e32 v4, vcc_lo, v6, v8, vcc_lo65; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo66; GFX10-NEXT: v_add_co_u32 v2, vcc_lo, v4, v267; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo68; GFX10-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[2:3]69; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo70; GFX10-NEXT: s_setpc_b64 s[30:31]71;72; GFX11-LABEL: umulo_i64_v_v:73; GFX11: ; %bb.0: ; %bb74; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)75; GFX11-NEXT: v_dual_mov_b32 v4, v0 :: v_dual_mov_b32 v5, v176; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)77; GFX11-NEXT: v_mad_u64_u32 v[6:7], null, v4, v3, 078; GFX11-NEXT: v_mad_u64_u32 v[0:1], null, v4, v2, 079; GFX11-NEXT: v_mad_u64_u32 v[8:9], null, v5, v2, 080; GFX11-NEXT: v_mad_u64_u32 v[10:11], null, v5, v3, 081; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)82; GFX11-NEXT: v_add_co_u32 v2, vcc_lo, v1, v683; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v7, vcc_lo84; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)85; GFX11-NEXT: v_add3_u32 v1, v1, v6, v886; GFX11-NEXT: v_add_co_u32 v2, vcc_lo, v2, v887; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)88; GFX11-NEXT: v_add_co_ci_u32_e32 v2, vcc_lo, v3, v9, vcc_lo89; GFX11-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v11, vcc_lo90; GFX11-NEXT: v_add_co_u32 v2, vcc_lo, v2, v1091; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)92; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo93; GFX11-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[2:3]94; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo95; GFX11-NEXT: s_setpc_b64 s[30:31]96;97; GFX12-LABEL: umulo_i64_v_v:98; GFX12: ; %bb.0: ; %bb99; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0100; GFX12-NEXT: s_wait_expcnt 0x0101; GFX12-NEXT: s_wait_samplecnt 0x0102; GFX12-NEXT: s_wait_bvhcnt 0x0103; GFX12-NEXT: s_wait_kmcnt 0x0104; GFX12-NEXT: v_mov_b32_e32 v4, v1105; GFX12-NEXT: v_mad_co_u64_u32 v[5:6], null, v0, v3, 0106; GFX12-NEXT: v_mad_co_u64_u32 v[0:1], null, v0, v2, 0107; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)108; GFX12-NEXT: v_mad_co_u64_u32 v[7:8], null, v4, v2, 0109; GFX12-NEXT: v_mad_co_u64_u32 v[2:3], null, v4, v3, 0110; GFX12-NEXT: v_add_co_u32 v4, vcc_lo, v1, v5111; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)112; GFX12-NEXT: v_add_co_ci_u32_e64 v6, null, 0, v6, vcc_lo113; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)114; GFX12-NEXT: v_add3_u32 v1, v1, v5, v7115; GFX12-NEXT: v_add_co_u32 v4, vcc_lo, v4, v7116; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)117; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)118; GFX12-NEXT: v_add_co_ci_u32_e32 v4, vcc_lo, v6, v8, vcc_lo119; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)120; GFX12-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo121; GFX12-NEXT: v_add_co_u32 v2, vcc_lo, v4, v2122; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)123; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)124; GFX12-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo125; GFX12-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[2:3]126; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)127; GFX12-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo128; GFX12-NEXT: s_setpc_b64 s[30:31]129bb:130 %umulo = tail call { i64, i1 } @llvm.umul.with.overflow.i64(i64 %x, i64 %y)131 ret { i64, i1 } %umulo132}133 134define { i64, i1 } @smulo_i64_v_v(i64 %x, i64 %y) {135; SI-LABEL: smulo_i64_v_v:136; SI: ; %bb.0: ; %bb137; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)138; SI-NEXT: v_mul_hi_u32 v6, v1, v2139; SI-NEXT: v_mul_lo_u32 v5, v1, v2140; SI-NEXT: v_mul_hi_u32 v7, v0, v3141; SI-NEXT: v_mul_lo_u32 v8, v0, v3142; SI-NEXT: v_mul_hi_u32 v9, v0, v2143; SI-NEXT: v_mul_hi_i32 v10, v1, v3144; SI-NEXT: v_mul_lo_u32 v11, v1, v3145; SI-NEXT: v_mul_lo_u32 v4, v0, v2146; SI-NEXT: v_add_i32_e32 v8, vcc, v9, v8147; SI-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc148; SI-NEXT: v_add_i32_e32 v9, vcc, v8, v5149; SI-NEXT: v_add_i32_e64 v5, s[4:5], v8, v5150; SI-NEXT: v_addc_u32_e32 v8, vcc, v7, v6, vcc151; SI-NEXT: v_ashrrev_i32_e32 v6, 31, v5152; SI-NEXT: v_addc_u32_e32 v9, vcc, 0, v10, vcc153; SI-NEXT: v_mov_b32_e32 v7, v6154; SI-NEXT: v_add_i32_e32 v8, vcc, v8, v11155; SI-NEXT: v_addc_u32_e32 v9, vcc, 0, v9, vcc156; SI-NEXT: v_sub_i32_e32 v2, vcc, v8, v2157; SI-NEXT: v_subbrev_u32_e32 v10, vcc, 0, v9, vcc158; SI-NEXT: v_cmp_gt_i32_e32 vcc, 0, v1159; SI-NEXT: v_cndmask_b32_e32 v1, v9, v10, vcc160; SI-NEXT: v_cndmask_b32_e32 v2, v8, v2, vcc161; SI-NEXT: v_sub_i32_e32 v0, vcc, v2, v0162; SI-NEXT: v_subbrev_u32_e32 v8, vcc, 0, v1, vcc163; SI-NEXT: v_cmp_gt_i32_e32 vcc, 0, v3164; SI-NEXT: v_cndmask_b32_e32 v1, v1, v8, vcc165; SI-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc166; SI-NEXT: v_cmp_ne_u64_e32 vcc, v[0:1], v[6:7]167; SI-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc168; SI-NEXT: v_mov_b32_e32 v0, v4169; SI-NEXT: v_mov_b32_e32 v1, v5170; SI-NEXT: s_setpc_b64 s[30:31]171;172; GFX9-LABEL: smulo_i64_v_v:173; GFX9: ; %bb.0: ; %bb174; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)175; GFX9-NEXT: v_mov_b32_e32 v5, v0176; GFX9-NEXT: v_mov_b32_e32 v4, v1177; GFX9-NEXT: v_mad_u64_u32 v[6:7], s[4:5], v5, v3, 0178; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v5, v2, 0179; GFX9-NEXT: v_mad_u64_u32 v[8:9], s[4:5], v4, v2, 0180; GFX9-NEXT: v_add_co_u32_e32 v12, vcc, v1, v6181; GFX9-NEXT: v_mad_i64_i32 v[10:11], s[4:5], v4, v3, 0182; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v7, vcc183; GFX9-NEXT: v_add_co_u32_e32 v12, vcc, v12, v8184; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, v7, v9, vcc185; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v11, vcc186; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, v7, v10187; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v9, vcc188; GFX9-NEXT: v_sub_co_u32_e32 v2, vcc, v7, v2189; GFX9-NEXT: v_subbrev_co_u32_e32 v10, vcc, 0, v9, vcc190; GFX9-NEXT: v_cmp_gt_i32_e32 vcc, 0, v4191; GFX9-NEXT: v_cndmask_b32_e32 v2, v7, v2, vcc192; GFX9-NEXT: v_cndmask_b32_e32 v4, v9, v10, vcc193; GFX9-NEXT: v_sub_co_u32_e32 v5, vcc, v2, v5194; GFX9-NEXT: v_subbrev_co_u32_e32 v7, vcc, 0, v4, vcc195; GFX9-NEXT: v_cmp_gt_i32_e32 vcc, 0, v3196; GFX9-NEXT: v_add3_u32 v1, v1, v6, v8197; GFX9-NEXT: v_cndmask_b32_e32 v3, v4, v7, vcc198; GFX9-NEXT: v_ashrrev_i32_e32 v4, 31, v1199; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc200; GFX9-NEXT: v_mov_b32_e32 v5, v4201; GFX9-NEXT: v_cmp_ne_u64_e32 vcc, v[2:3], v[4:5]202; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc203; GFX9-NEXT: s_setpc_b64 s[30:31]204;205; GFX10-LABEL: smulo_i64_v_v:206; GFX10: ; %bb.0: ; %bb207; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)208; GFX10-NEXT: v_mov_b32_e32 v4, v0209; GFX10-NEXT: v_mov_b32_e32 v5, v1210; GFX10-NEXT: v_mad_u64_u32 v[6:7], s4, v4, v3, 0211; GFX10-NEXT: v_mad_u64_u32 v[0:1], s4, v4, v2, 0212; GFX10-NEXT: v_mad_u64_u32 v[8:9], s4, v5, v2, 0213; GFX10-NEXT: v_mad_i64_i32 v[10:11], s4, v5, v3, 0214; GFX10-NEXT: v_add_co_u32 v12, vcc_lo, v1, v6215; GFX10-NEXT: v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo216; GFX10-NEXT: v_add3_u32 v1, v1, v6, v8217; GFX10-NEXT: v_add_co_u32 v12, vcc_lo, v12, v8218; GFX10-NEXT: v_add_co_ci_u32_e32 v7, vcc_lo, v7, v9, vcc_lo219; GFX10-NEXT: v_add_co_ci_u32_e32 v9, vcc_lo, 0, v11, vcc_lo220; GFX10-NEXT: v_add_co_u32 v7, vcc_lo, v7, v10221; GFX10-NEXT: v_add_co_ci_u32_e32 v9, vcc_lo, 0, v9, vcc_lo222; GFX10-NEXT: v_sub_co_u32 v2, vcc_lo, v7, v2223; GFX10-NEXT: v_subrev_co_ci_u32_e32 v10, vcc_lo, 0, v9, vcc_lo224; GFX10-NEXT: v_cmp_gt_i32_e32 vcc_lo, 0, v5225; GFX10-NEXT: v_cndmask_b32_e32 v6, v7, v2, vcc_lo226; GFX10-NEXT: v_cndmask_b32_e32 v5, v9, v10, vcc_lo227; GFX10-NEXT: v_ashrrev_i32_e32 v2, 31, v1228; GFX10-NEXT: v_sub_co_u32 v4, vcc_lo, v6, v4229; GFX10-NEXT: v_subrev_co_ci_u32_e32 v7, vcc_lo, 0, v5, vcc_lo230; GFX10-NEXT: v_cmp_gt_i32_e32 vcc_lo, 0, v3231; GFX10-NEXT: v_mov_b32_e32 v3, v2232; GFX10-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc_lo233; GFX10-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc_lo234; GFX10-NEXT: v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[2:3]235; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo236; GFX10-NEXT: s_setpc_b64 s[30:31]237;238; GFX11-LABEL: smulo_i64_v_v:239; GFX11: ; %bb.0: ; %bb240; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)241; GFX11-NEXT: v_dual_mov_b32 v4, v0 :: v_dual_mov_b32 v5, v1242; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)243; GFX11-NEXT: v_mad_u64_u32 v[6:7], null, v4, v3, 0244; GFX11-NEXT: v_mad_u64_u32 v[0:1], null, v4, v2, 0245; GFX11-NEXT: v_mad_u64_u32 v[8:9], null, v5, v2, 0246; GFX11-NEXT: v_mad_i64_i32 v[10:11], null, v5, v3, 0247; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)248; GFX11-NEXT: v_add_co_u32 v12, vcc_lo, v1, v6249; GFX11-NEXT: v_add_co_ci_u32_e64 v7, null, 0, v7, vcc_lo250; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)251; GFX11-NEXT: v_add3_u32 v1, v1, v6, v8252; GFX11-NEXT: v_add_co_u32 v12, vcc_lo, v12, v8253; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)254; GFX11-NEXT: v_add_co_ci_u32_e32 v7, vcc_lo, v7, v9, vcc_lo255; GFX11-NEXT: v_add_co_ci_u32_e32 v9, vcc_lo, 0, v11, vcc_lo256; GFX11-NEXT: v_add_co_u32 v7, vcc_lo, v7, v10257; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)258; GFX11-NEXT: v_add_co_ci_u32_e64 v9, null, 0, v9, vcc_lo259; GFX11-NEXT: v_sub_co_u32 v2, vcc_lo, v7, v2260; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)261; GFX11-NEXT: v_subrev_co_ci_u32_e64 v10, null, 0, v9, vcc_lo262; GFX11-NEXT: v_cmp_gt_i32_e32 vcc_lo, 0, v5263; GFX11-NEXT: v_cndmask_b32_e32 v6, v7, v2, vcc_lo264; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)265; GFX11-NEXT: v_cndmask_b32_e32 v5, v9, v10, vcc_lo266; GFX11-NEXT: v_ashrrev_i32_e32 v2, 31, v1267; GFX11-NEXT: v_sub_co_u32 v4, vcc_lo, v6, v4268; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)269; GFX11-NEXT: v_subrev_co_ci_u32_e64 v7, null, 0, v5, vcc_lo270; GFX11-NEXT: v_cmp_gt_i32_e32 vcc_lo, 0, v3271; GFX11-NEXT: v_mov_b32_e32 v3, v2272; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)273; GFX11-NEXT: v_dual_cndmask_b32 v4, v6, v4 :: v_dual_cndmask_b32 v5, v5, v7274; GFX11-NEXT: v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[2:3]275; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo276; GFX11-NEXT: s_setpc_b64 s[30:31]277;278; GFX12-LABEL: smulo_i64_v_v:279; GFX12: ; %bb.0: ; %bb280; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0281; GFX12-NEXT: s_wait_expcnt 0x0282; GFX12-NEXT: s_wait_samplecnt 0x0283; GFX12-NEXT: s_wait_bvhcnt 0x0284; GFX12-NEXT: s_wait_kmcnt 0x0285; GFX12-NEXT: v_dual_mov_b32 v4, v0 :: v_dual_mov_b32 v5, v1286; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)287; GFX12-NEXT: v_mad_co_u64_u32 v[6:7], null, v4, v3, 0288; GFX12-NEXT: v_mad_co_u64_u32 v[0:1], null, v4, v2, 0289; GFX12-NEXT: v_mad_co_u64_u32 v[8:9], null, v5, v2, 0290; GFX12-NEXT: v_mad_co_i64_i32 v[10:11], null, v5, v3, 0291; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)292; GFX12-NEXT: v_add_co_u32 v12, vcc_lo, v1, v6293; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)294; GFX12-NEXT: v_add_co_ci_u32_e64 v7, null, 0, v7, vcc_lo295; GFX12-NEXT: v_add3_u32 v1, v1, v6, v8296; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)297; GFX12-NEXT: v_add_co_u32 v12, vcc_lo, v12, v8298; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)299; GFX12-NEXT: v_add_co_ci_u32_e32 v7, vcc_lo, v7, v9, vcc_lo300; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)301; GFX12-NEXT: v_add_co_ci_u32_e32 v9, vcc_lo, 0, v11, vcc_lo302; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)303; GFX12-NEXT: v_add_co_u32 v7, vcc_lo, v7, v10304; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)305; GFX12-NEXT: v_add_co_ci_u32_e64 v9, null, 0, v9, vcc_lo306; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)307; GFX12-NEXT: v_sub_co_u32 v2, vcc_lo, v7, v2308; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)309; GFX12-NEXT: v_subrev_co_ci_u32_e64 v10, null, 0, v9, vcc_lo310; GFX12-NEXT: v_cmp_gt_i32_e32 vcc_lo, 0, v5311; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)312; GFX12-NEXT: v_cndmask_b32_e32 v6, v7, v2, vcc_lo313; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)314; GFX12-NEXT: v_cndmask_b32_e32 v5, v9, v10, vcc_lo315; GFX12-NEXT: v_ashrrev_i32_e32 v2, 31, v1316; GFX12-NEXT: v_sub_co_u32 v4, vcc_lo, v6, v4317; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)318; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)319; GFX12-NEXT: v_subrev_co_ci_u32_e64 v7, null, 0, v5, vcc_lo320; GFX12-NEXT: v_cmp_gt_i32_e32 vcc_lo, 0, v3321; GFX12-NEXT: v_mov_b32_e32 v3, v2322; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)323; GFX12-NEXT: v_dual_cndmask_b32 v4, v6, v4 :: v_dual_cndmask_b32 v5, v5, v7324; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)325; GFX12-NEXT: v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[2:3]326; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)327; GFX12-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo328; GFX12-NEXT: s_setpc_b64 s[30:31]329bb:330 %smulo = tail call { i64, i1 } @llvm.smul.with.overflow.i64(i64 %x, i64 %y)331 ret { i64, i1 } %smulo332}333 334define amdgpu_kernel void @umulo_i64_s(i64 %x, i64 %y) {335; SI-LABEL: umulo_i64_s:336; SI: ; %bb.0: ; %bb337; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9338; SI-NEXT: s_mov_b32 s7, 0xf000339; SI-NEXT: s_waitcnt lgkmcnt(0)340; SI-NEXT: v_mov_b32_e32 v0, s2341; SI-NEXT: v_mul_hi_u32 v1, s1, v0342; SI-NEXT: s_mul_i32 s4, s1, s2343; SI-NEXT: v_mov_b32_e32 v2, s3344; SI-NEXT: v_mul_hi_u32 v3, s0, v2345; SI-NEXT: s_mul_i32 s5, s0, s3346; SI-NEXT: v_mul_hi_u32 v0, s0, v0347; SI-NEXT: v_mul_hi_u32 v2, s1, v2348; SI-NEXT: s_mul_i32 s1, s1, s3349; SI-NEXT: s_mul_i32 s2, s0, s2350; SI-NEXT: v_add_i32_e32 v4, vcc, s5, v0351; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc352; SI-NEXT: v_add_i32_e32 v4, vcc, s4, v4353; SI-NEXT: v_addc_u32_e32 v1, vcc, v3, v1, vcc354; SI-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc355; SI-NEXT: v_add_i32_e32 v3, vcc, s5, v0356; SI-NEXT: v_add_i32_e32 v0, vcc, s1, v1357; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v2, vcc358; SI-NEXT: v_add_i32_e32 v2, vcc, s4, v3359; SI-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1]360; SI-NEXT: v_cndmask_b32_e64 v1, v2, 0, vcc361; SI-NEXT: s_and_b64 s[0:1], vcc, exec362; SI-NEXT: s_cselect_b32 s0, 0, s2363; SI-NEXT: s_mov_b32 s6, -1364; SI-NEXT: v_mov_b32_e32 v0, s0365; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0366; SI-NEXT: s_endpgm367;368; GFX9-LABEL: umulo_i64_s:369; GFX9: ; %bb.0: ; %bb370; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24371; GFX9-NEXT: s_waitcnt lgkmcnt(0)372; GFX9-NEXT: s_mul_i32 s7, s0, s3373; GFX9-NEXT: s_mul_hi_u32 s8, s0, s2374; GFX9-NEXT: s_mul_hi_u32 s5, s0, s3375; GFX9-NEXT: s_add_u32 s9, s8, s7376; GFX9-NEXT: s_mul_i32 s6, s1, s2377; GFX9-NEXT: s_addc_u32 s5, 0, s5378; GFX9-NEXT: s_mul_hi_u32 s4, s1, s2379; GFX9-NEXT: s_add_u32 s9, s9, s6380; GFX9-NEXT: s_mul_hi_u32 s10, s1, s3381; GFX9-NEXT: s_addc_u32 s4, s5, s4382; GFX9-NEXT: s_addc_u32 s5, s10, 0383; GFX9-NEXT: s_mul_i32 s1, s1, s3384; GFX9-NEXT: s_add_u32 s4, s4, s1385; GFX9-NEXT: s_addc_u32 s5, 0, s5386; GFX9-NEXT: s_add_i32 s1, s8, s7387; GFX9-NEXT: s_add_i32 s1, s1, s6388; GFX9-NEXT: s_mul_i32 s0, s0, s2389; GFX9-NEXT: s_cmp_lg_u64 s[4:5], 0390; GFX9-NEXT: s_cselect_b32 s1, 0, s1391; GFX9-NEXT: s_cselect_b32 s0, 0, s0392; GFX9-NEXT: v_mov_b32_e32 v0, s0393; GFX9-NEXT: v_mov_b32_e32 v1, s1394; GFX9-NEXT: global_store_dwordx2 v[0:1], v[0:1], off395; GFX9-NEXT: s_endpgm396;397; GFX10-LABEL: umulo_i64_s:398; GFX10: ; %bb.0: ; %bb399; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24400; GFX10-NEXT: s_waitcnt lgkmcnt(0)401; GFX10-NEXT: s_mul_i32 s7, s0, s3402; GFX10-NEXT: s_mul_hi_u32 s8, s0, s2403; GFX10-NEXT: s_mul_hi_u32 s5, s0, s3404; GFX10-NEXT: s_mul_hi_u32 s4, s1, s2405; GFX10-NEXT: s_mul_i32 s6, s1, s2406; GFX10-NEXT: s_mul_hi_u32 s9, s1, s3407; GFX10-NEXT: s_mul_i32 s1, s1, s3408; GFX10-NEXT: s_add_u32 s3, s8, s7409; GFX10-NEXT: s_addc_u32 s5, 0, s5410; GFX10-NEXT: s_add_u32 s3, s3, s6411; GFX10-NEXT: s_addc_u32 s3, s5, s4412; GFX10-NEXT: s_addc_u32 s5, s9, 0413; GFX10-NEXT: s_add_u32 s4, s3, s1414; GFX10-NEXT: s_addc_u32 s5, 0, s5415; GFX10-NEXT: s_add_i32 s1, s8, s7416; GFX10-NEXT: s_mul_i32 s0, s0, s2417; GFX10-NEXT: s_add_i32 s1, s1, s6418; GFX10-NEXT: s_cmp_lg_u64 s[4:5], 0419; GFX10-NEXT: s_cselect_b32 s0, 0, s0420; GFX10-NEXT: s_cselect_b32 s1, 0, s1421; GFX10-NEXT: v_mov_b32_e32 v0, s0422; GFX10-NEXT: v_mov_b32_e32 v1, s1423; GFX10-NEXT: global_store_dwordx2 v[0:1], v[0:1], off424; GFX10-NEXT: s_endpgm425;426; GFX11-LABEL: umulo_i64_s:427; GFX11: ; %bb.0: ; %bb428; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24429; GFX11-NEXT: s_waitcnt lgkmcnt(0)430; GFX11-NEXT: s_mul_i32 s7, s0, s3431; GFX11-NEXT: s_mul_hi_u32 s8, s0, s2432; GFX11-NEXT: s_mul_hi_u32 s5, s0, s3433; GFX11-NEXT: s_mul_hi_u32 s4, s1, s2434; GFX11-NEXT: s_mul_i32 s6, s1, s2435; GFX11-NEXT: s_mul_hi_u32 s9, s1, s3436; GFX11-NEXT: s_mul_i32 s1, s1, s3437; GFX11-NEXT: s_add_u32 s3, s8, s7438; GFX11-NEXT: s_addc_u32 s5, 0, s5439; GFX11-NEXT: s_add_u32 s3, s3, s6440; GFX11-NEXT: s_addc_u32 s3, s5, s4441; GFX11-NEXT: s_addc_u32 s5, s9, 0442; GFX11-NEXT: s_add_u32 s4, s3, s1443; GFX11-NEXT: s_addc_u32 s5, 0, s5444; GFX11-NEXT: s_add_i32 s1, s8, s7445; GFX11-NEXT: s_mul_i32 s0, s0, s2446; GFX11-NEXT: s_add_i32 s1, s1, s6447; GFX11-NEXT: s_cmp_lg_u64 s[4:5], 0448; GFX11-NEXT: s_cselect_b32 s0, 0, s0449; GFX11-NEXT: s_cselect_b32 s1, 0, s1450; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)451; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1452; GFX11-NEXT: global_store_b64 v[0:1], v[0:1], off453; GFX11-NEXT: s_endpgm454;455; GFX12-LABEL: umulo_i64_s:456; GFX12: ; %bb.0: ; %bb457; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24458; GFX12-NEXT: s_mov_b32 s5, 0459; GFX12-NEXT: s_wait_kmcnt 0x0460; GFX12-NEXT: s_mul_hi_u32 s7, s0, s3461; GFX12-NEXT: s_mul_i32 s6, s0, s3462; GFX12-NEXT: s_mul_hi_u32 s4, s0, s2463; GFX12-NEXT: s_mul_i32 s10, s1, s2464; GFX12-NEXT: s_add_nc_u64 s[6:7], s[4:5], s[6:7]465; GFX12-NEXT: s_mul_hi_u32 s9, s1, s2466; GFX12-NEXT: s_mul_hi_u32 s11, s1, s3467; GFX12-NEXT: s_add_co_u32 s4, s6, s10468; GFX12-NEXT: s_add_co_ci_u32 s4, s7, s9469; GFX12-NEXT: s_mul_i32 s8, s1, s3470; GFX12-NEXT: s_add_co_ci_u32 s9, s11, 0471; GFX12-NEXT: s_mul_u64 s[0:1], s[0:1], s[2:3]472; GFX12-NEXT: s_add_nc_u64 s[4:5], s[4:5], s[8:9]473; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)474; GFX12-NEXT: s_cmp_lg_u64 s[4:5], 0475; GFX12-NEXT: s_cselect_b32 s0, 0, s0476; GFX12-NEXT: s_cselect_b32 s1, 0, s1477; GFX12-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1478; GFX12-NEXT: global_store_b64 v[0:1], v[0:1], off479; GFX12-NEXT: s_endpgm480bb:481 %umulo = tail call { i64, i1 } @llvm.umul.with.overflow.i64(i64 %x, i64 %y)482 %mul = extractvalue { i64, i1 } %umulo, 0483 %overflow = extractvalue { i64, i1 } %umulo, 1484 %res = select i1 %overflow, i64 0, i64 %mul485 store i64 %res, ptr addrspace(1) poison486 ret void487}488 489define amdgpu_kernel void @smulo_i64_s(i64 %x, i64 %y) {490; SI-LABEL: smulo_i64_s:491; SI: ; %bb.0: ; %bb492; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9493; SI-NEXT: s_mov_b32 s7, 0xf000494; SI-NEXT: s_waitcnt lgkmcnt(0)495; SI-NEXT: v_mov_b32_e32 v0, s2496; SI-NEXT: v_mul_hi_u32 v1, s1, v0497; SI-NEXT: s_mul_i32 s4, s1, s2498; SI-NEXT: v_mov_b32_e32 v2, s3499; SI-NEXT: v_mul_hi_u32 v3, s0, v2500; SI-NEXT: s_mul_i32 s5, s0, s3501; SI-NEXT: v_mul_hi_u32 v0, s0, v0502; SI-NEXT: v_mul_hi_i32 v2, s1, v2503; SI-NEXT: s_mul_i32 s6, s1, s3504; SI-NEXT: s_mul_i32 s8, s0, s2505; SI-NEXT: v_readfirstlane_b32 s9, v1506; SI-NEXT: v_readfirstlane_b32 s10, v3507; SI-NEXT: v_readfirstlane_b32 s11, v0508; SI-NEXT: v_readfirstlane_b32 s12, v2509; SI-NEXT: v_add_i32_e32 v0, vcc, s5, v0510; SI-NEXT: s_add_u32 s5, s11, s5511; SI-NEXT: v_add_i32_e32 v2, vcc, s4, v0512; SI-NEXT: s_addc_u32 s10, 0, s10513; SI-NEXT: v_ashrrev_i32_e32 v0, 31, v2514; SI-NEXT: s_add_u32 s4, s5, s4515; SI-NEXT: v_mov_b32_e32 v1, v0516; SI-NEXT: s_addc_u32 s4, s10, s9517; SI-NEXT: s_addc_u32 s5, s12, 0518; SI-NEXT: s_add_u32 s4, s4, s6519; SI-NEXT: s_addc_u32 s5, 0, s5520; SI-NEXT: s_sub_u32 s2, s4, s2521; SI-NEXT: s_subb_u32 s6, s5, 0522; SI-NEXT: s_cmp_lt_i32 s1, 0523; SI-NEXT: s_cselect_b32 s1, s6, s5524; SI-NEXT: s_cselect_b32 s2, s2, s4525; SI-NEXT: s_sub_u32 s0, s2, s0526; SI-NEXT: s_subb_u32 s4, s1, 0527; SI-NEXT: s_cmp_lt_i32 s3, 0528; SI-NEXT: s_cselect_b32 s1, s4, s1529; SI-NEXT: s_cselect_b32 s0, s0, s2530; SI-NEXT: v_cmp_ne_u64_e32 vcc, s[0:1], v[0:1]531; SI-NEXT: v_cndmask_b32_e64 v1, v2, 0, vcc532; SI-NEXT: s_and_b64 s[0:1], vcc, exec533; SI-NEXT: s_cselect_b32 s0, 0, s8534; SI-NEXT: s_mov_b32 s6, -1535; SI-NEXT: v_mov_b32_e32 v0, s0536; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0537; SI-NEXT: s_endpgm538;539; GFX9-LABEL: smulo_i64_s:540; GFX9: ; %bb.0: ; %bb541; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24542; GFX9-NEXT: s_waitcnt lgkmcnt(0)543; GFX9-NEXT: s_mul_i32 s7, s0, s3544; GFX9-NEXT: s_mul_hi_u32 s8, s0, s2545; GFX9-NEXT: s_mul_hi_u32 s5, s0, s3546; GFX9-NEXT: s_add_u32 s9, s8, s7547; GFX9-NEXT: s_mul_i32 s6, s1, s2548; GFX9-NEXT: s_addc_u32 s5, 0, s5549; GFX9-NEXT: s_mul_hi_u32 s4, s1, s2550; GFX9-NEXT: s_add_u32 s9, s9, s6551; GFX9-NEXT: s_mul_hi_i32 s10, s1, s3552; GFX9-NEXT: s_addc_u32 s4, s5, s4553; GFX9-NEXT: s_addc_u32 s5, s10, 0554; GFX9-NEXT: s_mul_i32 s9, s1, s3555; GFX9-NEXT: s_add_u32 s4, s4, s9556; GFX9-NEXT: s_addc_u32 s5, 0, s5557; GFX9-NEXT: s_sub_u32 s9, s4, s2558; GFX9-NEXT: s_subb_u32 s10, s5, 0559; GFX9-NEXT: s_cmp_lt_i32 s1, 0560; GFX9-NEXT: s_cselect_b32 s4, s9, s4561; GFX9-NEXT: s_cselect_b32 s1, s10, s5562; GFX9-NEXT: s_sub_u32 s9, s4, s0563; GFX9-NEXT: s_subb_u32 s5, s1, 0564; GFX9-NEXT: s_cmp_lt_i32 s3, 0565; GFX9-NEXT: s_cselect_b32 s5, s5, s1566; GFX9-NEXT: s_cselect_b32 s4, s9, s4567; GFX9-NEXT: s_add_i32 s1, s8, s7568; GFX9-NEXT: s_add_i32 s1, s1, s6569; GFX9-NEXT: s_ashr_i32 s6, s1, 31570; GFX9-NEXT: s_mov_b32 s7, s6571; GFX9-NEXT: s_mul_i32 s0, s0, s2572; GFX9-NEXT: s_cmp_lg_u64 s[4:5], s[6:7]573; GFX9-NEXT: s_cselect_b32 s1, 0, s1574; GFX9-NEXT: s_cselect_b32 s0, 0, s0575; GFX9-NEXT: v_mov_b32_e32 v0, s0576; GFX9-NEXT: v_mov_b32_e32 v1, s1577; GFX9-NEXT: global_store_dwordx2 v[0:1], v[0:1], off578; GFX9-NEXT: s_endpgm579;580; GFX10-LABEL: smulo_i64_s:581; GFX10: ; %bb.0: ; %bb582; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24583; GFX10-NEXT: s_waitcnt lgkmcnt(0)584; GFX10-NEXT: s_mul_i32 s7, s0, s3585; GFX10-NEXT: s_mul_hi_u32 s8, s0, s2586; GFX10-NEXT: s_mul_hi_u32 s5, s0, s3587; GFX10-NEXT: s_mul_i32 s6, s1, s2588; GFX10-NEXT: s_add_u32 s11, s8, s7589; GFX10-NEXT: s_mul_hi_u32 s4, s1, s2590; GFX10-NEXT: s_addc_u32 s5, 0, s5591; GFX10-NEXT: s_mul_hi_i32 s9, s1, s3592; GFX10-NEXT: s_add_u32 s11, s11, s6593; GFX10-NEXT: s_mul_i32 s10, s1, s3594; GFX10-NEXT: s_addc_u32 s4, s5, s4595; GFX10-NEXT: s_addc_u32 s5, s9, 0596; GFX10-NEXT: s_add_u32 s4, s4, s10597; GFX10-NEXT: s_addc_u32 s5, 0, s5598; GFX10-NEXT: s_sub_u32 s9, s4, s2599; GFX10-NEXT: s_subb_u32 s10, s5, 0600; GFX10-NEXT: s_cmp_lt_i32 s1, 0601; GFX10-NEXT: s_cselect_b32 s1, s9, s4602; GFX10-NEXT: s_cselect_b32 s4, s10, s5603; GFX10-NEXT: s_sub_u32 s9, s1, s0604; GFX10-NEXT: s_subb_u32 s5, s4, 0605; GFX10-NEXT: s_cmp_lt_i32 s3, 0606; GFX10-NEXT: s_mul_i32 s0, s0, s2607; GFX10-NEXT: s_cselect_b32 s5, s5, s4608; GFX10-NEXT: s_cselect_b32 s4, s9, s1609; GFX10-NEXT: s_add_i32 s1, s8, s7610; GFX10-NEXT: s_add_i32 s1, s1, s6611; GFX10-NEXT: s_ashr_i32 s6, s1, 31612; GFX10-NEXT: s_mov_b32 s7, s6613; GFX10-NEXT: s_cmp_lg_u64 s[4:5], s[6:7]614; GFX10-NEXT: s_cselect_b32 s0, 0, s0615; GFX10-NEXT: s_cselect_b32 s1, 0, s1616; GFX10-NEXT: v_mov_b32_e32 v0, s0617; GFX10-NEXT: v_mov_b32_e32 v1, s1618; GFX10-NEXT: global_store_dwordx2 v[0:1], v[0:1], off619; GFX10-NEXT: s_endpgm620;621; GFX11-LABEL: smulo_i64_s:622; GFX11: ; %bb.0: ; %bb623; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24624; GFX11-NEXT: s_waitcnt lgkmcnt(0)625; GFX11-NEXT: s_mul_i32 s7, s0, s3626; GFX11-NEXT: s_mul_hi_u32 s8, s0, s2627; GFX11-NEXT: s_mul_hi_u32 s5, s0, s3628; GFX11-NEXT: s_mul_i32 s6, s1, s2629; GFX11-NEXT: s_add_u32 s11, s8, s7630; GFX11-NEXT: s_mul_hi_u32 s4, s1, s2631; GFX11-NEXT: s_addc_u32 s5, 0, s5632; GFX11-NEXT: s_mul_hi_i32 s9, s1, s3633; GFX11-NEXT: s_add_u32 s11, s11, s6634; GFX11-NEXT: s_mul_i32 s10, s1, s3635; GFX11-NEXT: s_addc_u32 s4, s5, s4636; GFX11-NEXT: s_addc_u32 s5, s9, 0637; GFX11-NEXT: s_add_u32 s4, s4, s10638; GFX11-NEXT: s_addc_u32 s5, 0, s5639; GFX11-NEXT: s_sub_u32 s9, s4, s2640; GFX11-NEXT: s_subb_u32 s10, s5, 0641; GFX11-NEXT: s_cmp_lt_i32 s1, 0642; GFX11-NEXT: s_cselect_b32 s1, s9, s4643; GFX11-NEXT: s_cselect_b32 s4, s10, s5644; GFX11-NEXT: s_sub_u32 s9, s1, s0645; GFX11-NEXT: s_subb_u32 s5, s4, 0646; GFX11-NEXT: s_cmp_lt_i32 s3, 0647; GFX11-NEXT: s_mul_i32 s0, s0, s2648; GFX11-NEXT: s_cselect_b32 s5, s5, s4649; GFX11-NEXT: s_cselect_b32 s4, s9, s1650; GFX11-NEXT: s_add_i32 s1, s8, s7651; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)652; GFX11-NEXT: s_add_i32 s1, s1, s6653; GFX11-NEXT: s_ashr_i32 s6, s1, 31654; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)655; GFX11-NEXT: s_mov_b32 s7, s6656; GFX11-NEXT: s_cmp_lg_u64 s[4:5], s[6:7]657; GFX11-NEXT: s_cselect_b32 s0, 0, s0658; GFX11-NEXT: s_cselect_b32 s1, 0, s1659; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)660; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1661; GFX11-NEXT: global_store_b64 v[0:1], v[0:1], off662; GFX11-NEXT: s_endpgm663;664; GFX12-LABEL: smulo_i64_s:665; GFX12: ; %bb.0: ; %bb666; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24667; GFX12-NEXT: s_mov_b32 s5, 0668; GFX12-NEXT: s_wait_kmcnt 0x0669; GFX12-NEXT: s_mul_hi_u32 s7, s0, s3670; GFX12-NEXT: s_mul_i32 s6, s0, s3671; GFX12-NEXT: s_mul_hi_u32 s4, s0, s2672; GFX12-NEXT: s_mul_i32 s10, s1, s2673; GFX12-NEXT: s_add_nc_u64 s[6:7], s[4:5], s[6:7]674; GFX12-NEXT: s_mul_hi_u32 s9, s1, s2675; GFX12-NEXT: s_mul_hi_i32 s11, s1, s3676; GFX12-NEXT: s_add_co_u32 s4, s6, s10677; GFX12-NEXT: s_add_co_ci_u32 s4, s7, s9678; GFX12-NEXT: s_mul_i32 s8, s1, s3679; GFX12-NEXT: s_add_co_ci_u32 s9, s11, 0680; GFX12-NEXT: s_cmp_lt_i32 s1, 0681; GFX12-NEXT: s_add_nc_u64 s[6:7], s[4:5], s[8:9]682; GFX12-NEXT: s_mov_b32 s4, s2683; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)684; GFX12-NEXT: s_sub_nc_u64 s[8:9], s[6:7], s[4:5]685; GFX12-NEXT: s_mov_b32 s4, s0686; GFX12-NEXT: s_cselect_b32 s7, s9, s7687; GFX12-NEXT: s_cselect_b32 s6, s8, s6688; GFX12-NEXT: s_cmp_lt_i32 s3, 0689; GFX12-NEXT: s_sub_nc_u64 s[4:5], s[6:7], s[4:5]690; GFX12-NEXT: s_mul_u64 s[0:1], s[0:1], s[2:3]691; GFX12-NEXT: s_cselect_b32 s3, s5, s7692; GFX12-NEXT: s_cselect_b32 s2, s4, s6693; GFX12-NEXT: s_ashr_i32 s4, s1, 31694; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)695; GFX12-NEXT: s_mov_b32 s5, s4696; GFX12-NEXT: s_cmp_lg_u64 s[2:3], s[4:5]697; GFX12-NEXT: s_cselect_b32 s0, 0, s0698; GFX12-NEXT: s_cselect_b32 s1, 0, s1699; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)700; GFX12-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1701; GFX12-NEXT: global_store_b64 v[0:1], v[0:1], off702; GFX12-NEXT: s_endpgm703bb:704 %umulo = tail call { i64, i1 } @llvm.smul.with.overflow.i64(i64 %x, i64 %y)705 %mul = extractvalue { i64, i1 } %umulo, 0706 %overflow = extractvalue { i64, i1 } %umulo, 1707 %res = select i1 %overflow, i64 0, i64 %mul708 store i64 %res, ptr addrspace(1) poison709 ret void710}711 712define { i64, i1 } @smulo_i64_v_4(i64 %i) {713; SI-LABEL: smulo_i64_v_4:714; SI: ; %bb.0: ; %bb715; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)716; SI-NEXT: v_lshl_b64 v[5:6], v[0:1], 2717; SI-NEXT: v_alignbit_b32 v4, v1, v0, 30718; SI-NEXT: v_ashr_i64 v[2:3], v[5:6], 2719; SI-NEXT: v_cmp_ne_u64_e32 vcc, v[2:3], v[0:1]720; SI-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc721; SI-NEXT: v_mov_b32_e32 v0, v5722; SI-NEXT: v_mov_b32_e32 v1, v4723; SI-NEXT: s_setpc_b64 s[30:31]724;725; GFX9-LABEL: smulo_i64_v_4:726; GFX9: ; %bb.0: ; %bb727; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)728; GFX9-NEXT: v_lshlrev_b64 v[4:5], 2, v[0:1]729; GFX9-NEXT: v_alignbit_b32 v3, v1, v0, 30730; GFX9-NEXT: v_ashrrev_i64 v[5:6], 2, v[4:5]731; GFX9-NEXT: v_cmp_ne_u64_e32 vcc, v[5:6], v[0:1]732; GFX9-NEXT: v_mov_b32_e32 v0, v4733; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc734; GFX9-NEXT: v_mov_b32_e32 v1, v3735; GFX9-NEXT: s_setpc_b64 s[30:31]736;737; GFX10-LABEL: smulo_i64_v_4:738; GFX10: ; %bb.0: ; %bb739; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)740; GFX10-NEXT: v_lshlrev_b64 v[4:5], 2, v[0:1]741; GFX10-NEXT: v_alignbit_b32 v3, v1, v0, 30742; GFX10-NEXT: v_ashrrev_i64 v[5:6], 2, v[4:5]743; GFX10-NEXT: v_cmp_ne_u64_e32 vcc_lo, v[5:6], v[0:1]744; GFX10-NEXT: v_mov_b32_e32 v0, v4745; GFX10-NEXT: v_mov_b32_e32 v1, v3746; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo747; GFX10-NEXT: s_setpc_b64 s[30:31]748;749; GFX11-LABEL: smulo_i64_v_4:750; GFX11: ; %bb.0: ; %bb751; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)752; GFX11-NEXT: v_lshlrev_b64 v[4:5], 2, v[0:1]753; GFX11-NEXT: v_alignbit_b32 v3, v1, v0, 30754; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)755; GFX11-NEXT: v_ashrrev_i64 v[5:6], 2, v[4:5]756; GFX11-NEXT: v_cmp_ne_u64_e32 vcc_lo, v[5:6], v[0:1]757; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3)758; GFX11-NEXT: v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v3759; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo760; GFX11-NEXT: s_setpc_b64 s[30:31]761;762; GFX12-LABEL: smulo_i64_v_4:763; GFX12: ; %bb.0: ; %bb764; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0765; GFX12-NEXT: s_wait_expcnt 0x0766; GFX12-NEXT: s_wait_samplecnt 0x0767; GFX12-NEXT: s_wait_bvhcnt 0x0768; GFX12-NEXT: s_wait_kmcnt 0x0769; GFX12-NEXT: v_lshlrev_b64_e32 v[4:5], 2, v[0:1]770; GFX12-NEXT: v_alignbit_b32 v3, v1, v0, 30771; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)772; GFX12-NEXT: v_ashrrev_i64 v[5:6], 2, v[4:5]773; GFX12-NEXT: v_cmp_ne_u64_e32 vcc_lo, v[5:6], v[0:1]774; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3)775; GFX12-NEXT: v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v3776; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)777; GFX12-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo778; GFX12-NEXT: s_setpc_b64 s[30:31]779bb:780 %umulo = tail call { i64, i1 } @llvm.smul.with.overflow.i64(i64 %i, i64 4)781 ret { i64, i1 } %umulo782}783 784define { i64, i1 } @umulo_i64_v_4(i64 %i) {785; SI-LABEL: umulo_i64_v_4:786; SI: ; %bb.0: ; %bb787; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)788; SI-NEXT: v_and_b32_e32 v7, 0x3fffffff, v1789; SI-NEXT: v_mov_b32_e32 v6, v0790; SI-NEXT: v_lshl_b64 v[4:5], v[0:1], 2791; SI-NEXT: v_alignbit_b32 v3, v1, v0, 30792; SI-NEXT: v_cmp_ne_u64_e32 vcc, v[6:7], v[0:1]793; SI-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc794; SI-NEXT: v_mov_b32_e32 v0, v4795; SI-NEXT: v_mov_b32_e32 v1, v3796; SI-NEXT: s_setpc_b64 s[30:31]797;798; GFX9-LABEL: umulo_i64_v_4:799; GFX9: ; %bb.0: ; %bb800; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)801; GFX9-NEXT: v_and_b32_e32 v7, 0x3fffffff, v1802; GFX9-NEXT: v_mov_b32_e32 v6, v0803; GFX9-NEXT: v_lshlrev_b64 v[4:5], 2, v[0:1]804; GFX9-NEXT: v_cmp_ne_u64_e32 vcc, v[6:7], v[0:1]805; GFX9-NEXT: v_alignbit_b32 v3, v1, v0, 30806; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc807; GFX9-NEXT: v_mov_b32_e32 v0, v4808; GFX9-NEXT: v_mov_b32_e32 v1, v3809; GFX9-NEXT: s_setpc_b64 s[30:31]810;811; GFX10-LABEL: umulo_i64_v_4:812; GFX10: ; %bb.0: ; %bb813; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)814; GFX10-NEXT: v_and_b32_e32 v7, 0x3fffffff, v1815; GFX10-NEXT: v_mov_b32_e32 v6, v0816; GFX10-NEXT: v_lshlrev_b64 v[4:5], 2, v[0:1]817; GFX10-NEXT: v_alignbit_b32 v3, v1, v0, 30818; GFX10-NEXT: v_cmp_ne_u64_e32 vcc_lo, v[6:7], v[0:1]819; GFX10-NEXT: v_mov_b32_e32 v0, v4820; GFX10-NEXT: v_mov_b32_e32 v1, v3821; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo822; GFX10-NEXT: s_setpc_b64 s[30:31]823;824; GFX11-LABEL: umulo_i64_v_4:825; GFX11: ; %bb.0: ; %bb826; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)827; GFX11-NEXT: v_dual_mov_b32 v6, v0 :: v_dual_and_b32 v7, 0x3fffffff, v1828; GFX11-NEXT: v_lshlrev_b64 v[4:5], 2, v[0:1]829; GFX11-NEXT: v_alignbit_b32 v3, v1, v0, 30830; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)831; GFX11-NEXT: v_cmp_ne_u64_e32 vcc_lo, v[6:7], v[0:1]832; GFX11-NEXT: v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v3833; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo834; GFX11-NEXT: s_setpc_b64 s[30:31]835;836; GFX12-LABEL: umulo_i64_v_4:837; GFX12: ; %bb.0: ; %bb838; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0839; GFX12-NEXT: s_wait_expcnt 0x0840; GFX12-NEXT: s_wait_samplecnt 0x0841; GFX12-NEXT: s_wait_bvhcnt 0x0842; GFX12-NEXT: s_wait_kmcnt 0x0843; GFX12-NEXT: v_dual_mov_b32 v6, v0 :: v_dual_and_b32 v7, 0x3fffffff, v1844; GFX12-NEXT: v_lshlrev_b64_e32 v[4:5], 2, v[0:1]845; GFX12-NEXT: v_alignbit_b32 v3, v1, v0, 30846; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)847; GFX12-NEXT: v_cmp_ne_u64_e32 vcc_lo, v[6:7], v[0:1]848; GFX12-NEXT: v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v3849; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)850; GFX12-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo851; GFX12-NEXT: s_setpc_b64 s[30:31]852bb:853 %umulo = tail call { i64, i1 } @llvm.umul.with.overflow.i64(i64 %i, i64 4)854 ret { i64, i1 } %umulo855}856 857declare { i64, i1 } @llvm.umul.with.overflow.i64(i64, i64)858declare { i64, i1 } @llvm.smul.with.overflow.i64(i64, i64)859