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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=amdgcn < %s | FileCheck --check-prefixes=SI,GCN,FUNC %s3; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck --check-prefixes=VI,GCN,FUNC %s4; RUN: llc -mtriple=r600 -mcpu=redwood < %s | FileCheck --check-prefixes=R600,FUNC %s5 6define amdgpu_kernel void @local_size_x(ptr addrspace(1) %out) {7; SI-LABEL: local_size_x:8; SI: ; %bb.0: ; %entry9; SI-NEXT: s_load_dword s6, s[4:5], 0x610; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x911; SI-NEXT: s_mov_b32 s3, 0xf00012; SI-NEXT: s_mov_b32 s2, -113; SI-NEXT: s_waitcnt lgkmcnt(0)14; SI-NEXT: v_mov_b32_e32 v0, s615; SI-NEXT: buffer_store_dword v0, off, s[0:3], 016; SI-NEXT: s_endpgm17;18; VI-LABEL: local_size_x:19; VI: ; %bb.0: ; %entry20; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2421; VI-NEXT: s_load_dword s2, s[4:5], 0x1822; VI-NEXT: s_waitcnt lgkmcnt(0)23; VI-NEXT: v_mov_b32_e32 v0, s024; VI-NEXT: v_mov_b32_e32 v1, s125; VI-NEXT: v_mov_b32_e32 v2, s226; VI-NEXT: flat_store_dword v[0:1], v227; VI-NEXT: s_endpgm28;29; R600-LABEL: local_size_x:30; R600: ; %bb.0: ; %entry31; R600-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]32; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 133; R600-NEXT: CF_END34; R600-NEXT: PAD35; R600-NEXT: ALU clause starting at 4:36; R600-NEXT: LSHR T0.X, KC0[2].Y, literal.x,37; R600-NEXT: MOV * T1.X, KC0[1].Z,38; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)39entry:40 %0 = call i32 @llvm.r600.read.local.size.x() #041 store i32 %0, ptr addrspace(1) %out42 ret void43}44 45define amdgpu_kernel void @local_size_y(ptr addrspace(1) %out) {46; SI-LABEL: local_size_y:47; SI: ; %bb.0: ; %entry48; SI-NEXT: s_load_dword s6, s[4:5], 0x749; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x950; SI-NEXT: s_mov_b32 s3, 0xf00051; SI-NEXT: s_mov_b32 s2, -152; SI-NEXT: s_waitcnt lgkmcnt(0)53; SI-NEXT: v_mov_b32_e32 v0, s654; SI-NEXT: buffer_store_dword v0, off, s[0:3], 055; SI-NEXT: s_endpgm56;57; VI-LABEL: local_size_y:58; VI: ; %bb.0: ; %entry59; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2460; VI-NEXT: s_load_dword s2, s[4:5], 0x1c61; VI-NEXT: s_waitcnt lgkmcnt(0)62; VI-NEXT: v_mov_b32_e32 v0, s063; VI-NEXT: v_mov_b32_e32 v1, s164; VI-NEXT: v_mov_b32_e32 v2, s265; VI-NEXT: flat_store_dword v[0:1], v266; VI-NEXT: s_endpgm67;68; R600-LABEL: local_size_y:69; R600: ; %bb.0: ; %entry70; R600-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]71; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 172; R600-NEXT: CF_END73; R600-NEXT: PAD74; R600-NEXT: ALU clause starting at 4:75; R600-NEXT: LSHR T0.X, KC0[2].Y, literal.x,76; R600-NEXT: MOV * T1.X, KC0[1].W,77; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)78entry:79 %0 = call i32 @llvm.r600.read.local.size.y() #080 store i32 %0, ptr addrspace(1) %out81 ret void82}83 84define amdgpu_kernel void @local_size_z(ptr addrspace(1) %out) {85; SI-LABEL: local_size_z:86; SI: ; %bb.0: ; %entry87; SI-NEXT: s_load_dword s6, s[4:5], 0x888; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x989; SI-NEXT: s_mov_b32 s3, 0xf00090; SI-NEXT: s_mov_b32 s2, -191; SI-NEXT: s_waitcnt lgkmcnt(0)92; SI-NEXT: v_mov_b32_e32 v0, s693; SI-NEXT: buffer_store_dword v0, off, s[0:3], 094; SI-NEXT: s_endpgm95;96; VI-LABEL: local_size_z:97; VI: ; %bb.0: ; %entry98; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2499; VI-NEXT: s_load_dword s2, s[4:5], 0x20100; VI-NEXT: s_waitcnt lgkmcnt(0)101; VI-NEXT: v_mov_b32_e32 v0, s0102; VI-NEXT: v_mov_b32_e32 v1, s1103; VI-NEXT: v_mov_b32_e32 v2, s2104; VI-NEXT: flat_store_dword v[0:1], v2105; VI-NEXT: s_endpgm106;107; R600-LABEL: local_size_z:108; R600: ; %bb.0: ; %entry109; R600-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]110; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1111; R600-NEXT: CF_END112; R600-NEXT: PAD113; R600-NEXT: ALU clause starting at 4:114; R600-NEXT: LSHR T0.X, KC0[2].Y, literal.x,115; R600-NEXT: MOV * T1.X, KC0[2].X,116; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)117entry:118 %0 = call i32 @llvm.r600.read.local.size.z() #0119 store i32 %0, ptr addrspace(1) %out120 ret void121}122 123define amdgpu_kernel void @local_size_xy(ptr addrspace(1) %out) {124; SI-LABEL: local_size_xy:125; SI: ; %bb.0: ; %entry126; SI-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x6127; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9128; SI-NEXT: s_mov_b32 s3, 0xf000129; SI-NEXT: s_waitcnt lgkmcnt(0)130; SI-NEXT: s_mul_i32 s4, s6, s7131; SI-NEXT: s_mov_b32 s2, -1132; SI-NEXT: v_mov_b32_e32 v0, s4133; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0134; SI-NEXT: s_endpgm135;136; VI-LABEL: local_size_xy:137; VI: ; %bb.0: ; %entry138; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x18139; VI-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24140; VI-NEXT: s_waitcnt lgkmcnt(0)141; VI-NEXT: s_mul_i32 s0, s0, s1142; VI-NEXT: v_mov_b32_e32 v0, s2143; VI-NEXT: v_mov_b32_e32 v1, s3144; VI-NEXT: v_mov_b32_e32 v2, s0145; VI-NEXT: flat_store_dword v[0:1], v2146; VI-NEXT: s_endpgm147;148; R600-LABEL: local_size_xy:149; R600: ; %bb.0: ; %entry150; R600-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]151; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1152; R600-NEXT: CF_END153; R600-NEXT: PAD154; R600-NEXT: ALU clause starting at 4:155; R600-NEXT: LSHR T0.X, KC0[2].Y, literal.x,156; R600-NEXT: MULLO_INT * T1.X, KC0[1].Z, KC0[1].W,157; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)158entry:159 %x = call i32 @llvm.r600.read.local.size.x() #0160 %y = call i32 @llvm.r600.read.local.size.y() #0161 %val = mul i32 %x, %y162 store i32 %val, ptr addrspace(1) %out163 ret void164}165 166define amdgpu_kernel void @local_size_xz(ptr addrspace(1) %out) {167; SI-LABEL: local_size_xz:168; SI: ; %bb.0: ; %entry169; SI-NEXT: s_load_dword s2, s[4:5], 0x6170; SI-NEXT: s_load_dword s6, s[4:5], 0x8171; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9172; SI-NEXT: s_mov_b32 s3, 0xf000173; SI-NEXT: s_waitcnt lgkmcnt(0)174; SI-NEXT: s_mul_i32 s4, s2, s6175; SI-NEXT: s_mov_b32 s2, -1176; SI-NEXT: v_mov_b32_e32 v0, s4177; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0178; SI-NEXT: s_endpgm179;180; VI-LABEL: local_size_xz:181; VI: ; %bb.0: ; %entry182; VI-NEXT: s_load_dword s2, s[4:5], 0x18183; VI-NEXT: s_load_dword s3, s[4:5], 0x20184; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24185; VI-NEXT: s_waitcnt lgkmcnt(0)186; VI-NEXT: s_mul_i32 s2, s2, s3187; VI-NEXT: v_mov_b32_e32 v0, s0188; VI-NEXT: v_mov_b32_e32 v1, s1189; VI-NEXT: v_mov_b32_e32 v2, s2190; VI-NEXT: flat_store_dword v[0:1], v2191; VI-NEXT: s_endpgm192;193; R600-LABEL: local_size_xz:194; R600: ; %bb.0: ; %entry195; R600-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]196; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1197; R600-NEXT: CF_END198; R600-NEXT: PAD199; R600-NEXT: ALU clause starting at 4:200; R600-NEXT: LSHR T0.X, KC0[2].Y, literal.x,201; R600-NEXT: MULLO_INT * T1.X, KC0[1].Z, KC0[2].X,202; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)203entry:204 %x = call i32 @llvm.r600.read.local.size.x() #0205 %z = call i32 @llvm.r600.read.local.size.z() #0206 %val = mul i32 %x, %z207 store i32 %val, ptr addrspace(1) %out208 ret void209}210 211define amdgpu_kernel void @local_size_yz(ptr addrspace(1) %out) {212; SI-LABEL: local_size_yz:213; SI: ; %bb.0: ; %entry214; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x7215; SI-NEXT: s_mov_b32 s7, 0xf000216; SI-NEXT: s_waitcnt lgkmcnt(0)217; SI-NEXT: s_mul_i32 s0, s0, s1218; SI-NEXT: s_mov_b32 s6, -1219; SI-NEXT: s_mov_b32 s4, s2220; SI-NEXT: s_mov_b32 s5, s3221; SI-NEXT: v_mov_b32_e32 v0, s0222; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0223; SI-NEXT: s_endpgm224;225; VI-LABEL: local_size_yz:226; VI: ; %bb.0: ; %entry227; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x1c228; VI-NEXT: s_waitcnt lgkmcnt(0)229; VI-NEXT: s_mul_i32 s0, s0, s1230; VI-NEXT: v_mov_b32_e32 v0, s2231; VI-NEXT: v_mov_b32_e32 v1, s3232; VI-NEXT: v_mov_b32_e32 v2, s0233; VI-NEXT: flat_store_dword v[0:1], v2234; VI-NEXT: s_endpgm235;236; R600-LABEL: local_size_yz:237; R600: ; %bb.0: ; %entry238; R600-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]239; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1240; R600-NEXT: CF_END241; R600-NEXT: PAD242; R600-NEXT: ALU clause starting at 4:243; R600-NEXT: LSHR T0.X, KC0[2].Y, literal.x,244; R600-NEXT: MULLO_INT * T1.X, KC0[1].W, KC0[2].X,245; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)246entry:247 %y = call i32 @llvm.r600.read.local.size.y() #0248 %z = call i32 @llvm.r600.read.local.size.z() #0249 %val = mul i32 %y, %z250 store i32 %val, ptr addrspace(1) %out251 ret void252}253 254define amdgpu_kernel void @local_size_xyz(ptr addrspace(1) %out) {255; SI-LABEL: local_size_xyz:256; SI: ; %bb.0: ; %entry257; SI-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x6258; SI-NEXT: s_load_dword s2, s[4:5], 0x8259; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9260; SI-NEXT: s_mov_b32 s3, 0xf000261; SI-NEXT: s_waitcnt lgkmcnt(0)262; SI-NEXT: s_mul_i32 s4, s6, s7263; SI-NEXT: s_add_i32 s4, s4, s2264; SI-NEXT: s_mov_b32 s2, -1265; SI-NEXT: v_mov_b32_e32 v0, s4266; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0267; SI-NEXT: s_endpgm268;269; VI-LABEL: local_size_xyz:270; VI: ; %bb.0: ; %entry271; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x18272; VI-NEXT: s_load_dword s6, s[4:5], 0x20273; VI-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24274; VI-NEXT: s_waitcnt lgkmcnt(0)275; VI-NEXT: s_mul_i32 s0, s0, s1276; VI-NEXT: s_add_i32 s0, s0, s6277; VI-NEXT: v_mov_b32_e32 v0, s2278; VI-NEXT: v_mov_b32_e32 v1, s3279; VI-NEXT: v_mov_b32_e32 v2, s0280; VI-NEXT: flat_store_dword v[0:1], v2281; VI-NEXT: s_endpgm282;283; R600-LABEL: local_size_xyz:284; R600: ; %bb.0: ; %entry285; R600-NEXT: ALU 3, @4, KC0[CB0:0-32], KC1[]286; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1287; R600-NEXT: CF_END288; R600-NEXT: PAD289; R600-NEXT: ALU clause starting at 4:290; R600-NEXT: MULLO_INT * T0.X, KC0[1].Z, KC0[1].W,291; R600-NEXT: ADD_INT T0.X, PS, KC0[2].X,292; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,293; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)294entry:295 %x = call i32 @llvm.r600.read.local.size.x() #0296 %y = call i32 @llvm.r600.read.local.size.y() #0297 %z = call i32 @llvm.r600.read.local.size.z() #0298 %xy = mul i32 %x, %y299 %xyz = add i32 %xy, %z300 store i32 %xyz, ptr addrspace(1) %out301 ret void302}303 304define amdgpu_kernel void @local_size_x_known_bits(ptr addrspace(1) %out) {305; SI-LABEL: local_size_x_known_bits:306; SI: ; %bb.0: ; %entry307; SI-NEXT: s_load_dword s6, s[4:5], 0x6308; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9309; SI-NEXT: s_mov_b32 s3, 0xf000310; SI-NEXT: s_mov_b32 s2, -1311; SI-NEXT: s_waitcnt lgkmcnt(0)312; SI-NEXT: v_mov_b32_e32 v0, s6313; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0314; SI-NEXT: s_endpgm315;316; VI-LABEL: local_size_x_known_bits:317; VI: ; %bb.0: ; %entry318; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24319; VI-NEXT: s_load_dword s2, s[4:5], 0x18320; VI-NEXT: s_waitcnt lgkmcnt(0)321; VI-NEXT: v_mov_b32_e32 v0, s0322; VI-NEXT: v_mov_b32_e32 v1, s1323; VI-NEXT: v_mov_b32_e32 v2, s2324; VI-NEXT: flat_store_dword v[0:1], v2325; VI-NEXT: s_endpgm326;327; R600-LABEL: local_size_x_known_bits:328; R600: ; %bb.0: ; %entry329; R600-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]330; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1331; R600-NEXT: CF_END332; R600-NEXT: PAD333; R600-NEXT: ALU clause starting at 4:334; R600-NEXT: LSHR T0.X, KC0[2].Y, literal.x,335; R600-NEXT: AND_INT * T1.X, KC0[1].Z, literal.y,336; R600-NEXT: 2(2.802597e-45), 65535(9.183409e-41)337entry:338 %size = call i32 @llvm.r600.read.local.size.x() #0339 %shl = shl i32 %size, 16340 %shr = lshr i32 %shl, 16341 store i32 %shr, ptr addrspace(1) %out342 ret void343}344 345define amdgpu_kernel void @local_size_y_known_bits(ptr addrspace(1) %out) {346; SI-LABEL: local_size_y_known_bits:347; SI: ; %bb.0: ; %entry348; SI-NEXT: s_load_dword s6, s[4:5], 0x7349; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9350; SI-NEXT: s_mov_b32 s3, 0xf000351; SI-NEXT: s_mov_b32 s2, -1352; SI-NEXT: s_waitcnt lgkmcnt(0)353; SI-NEXT: v_mov_b32_e32 v0, s6354; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0355; SI-NEXT: s_endpgm356;357; VI-LABEL: local_size_y_known_bits:358; VI: ; %bb.0: ; %entry359; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24360; VI-NEXT: s_load_dword s2, s[4:5], 0x1c361; VI-NEXT: s_waitcnt lgkmcnt(0)362; VI-NEXT: v_mov_b32_e32 v0, s0363; VI-NEXT: v_mov_b32_e32 v1, s1364; VI-NEXT: v_mov_b32_e32 v2, s2365; VI-NEXT: flat_store_dword v[0:1], v2366; VI-NEXT: s_endpgm367;368; R600-LABEL: local_size_y_known_bits:369; R600: ; %bb.0: ; %entry370; R600-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]371; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1372; R600-NEXT: CF_END373; R600-NEXT: PAD374; R600-NEXT: ALU clause starting at 4:375; R600-NEXT: LSHR T0.X, KC0[2].Y, literal.x,376; R600-NEXT: AND_INT * T1.X, KC0[1].W, literal.y,377; R600-NEXT: 2(2.802597e-45), 65535(9.183409e-41)378entry:379 %size = call i32 @llvm.r600.read.local.size.y() #0380 %shl = shl i32 %size, 16381 %shr = lshr i32 %shl, 16382 store i32 %shr, ptr addrspace(1) %out383 ret void384}385 386define amdgpu_kernel void @local_size_z_known_bits(ptr addrspace(1) %out) {387; SI-LABEL: local_size_z_known_bits:388; SI: ; %bb.0: ; %entry389; SI-NEXT: s_load_dword s6, s[4:5], 0x8390; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9391; SI-NEXT: s_mov_b32 s3, 0xf000392; SI-NEXT: s_mov_b32 s2, -1393; SI-NEXT: s_waitcnt lgkmcnt(0)394; SI-NEXT: v_mov_b32_e32 v0, s6395; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0396; SI-NEXT: s_endpgm397;398; VI-LABEL: local_size_z_known_bits:399; VI: ; %bb.0: ; %entry400; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24401; VI-NEXT: s_load_dword s2, s[4:5], 0x20402; VI-NEXT: s_waitcnt lgkmcnt(0)403; VI-NEXT: v_mov_b32_e32 v0, s0404; VI-NEXT: v_mov_b32_e32 v1, s1405; VI-NEXT: v_mov_b32_e32 v2, s2406; VI-NEXT: flat_store_dword v[0:1], v2407; VI-NEXT: s_endpgm408;409; R600-LABEL: local_size_z_known_bits:410; R600: ; %bb.0: ; %entry411; R600-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]412; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1413; R600-NEXT: CF_END414; R600-NEXT: PAD415; R600-NEXT: ALU clause starting at 4:416; R600-NEXT: LSHR T0.X, KC0[2].Y, literal.x,417; R600-NEXT: AND_INT * T1.X, KC0[2].X, literal.y,418; R600-NEXT: 2(2.802597e-45), 65535(9.183409e-41)419entry:420 %size = call i32 @llvm.r600.read.local.size.z() #0421 %shl = shl i32 %size, 16422 %shr = lshr i32 %shl, 16423 store i32 %shr, ptr addrspace(1) %out424 ret void425}426 427declare i32 @llvm.r600.read.local.size.x() #0428declare i32 @llvm.r600.read.local.size.y() #0429declare i32 @llvm.r600.read.local.size.z() #0430 431attributes #0 = { nounwind readnone }432;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:433; FUNC: {{.*}}434; GCN: {{.*}}435