1739 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 22; RUN: llc -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefixes=GCN,GFX678,GFX6 %s3; RUN: llc -mtriple=amdgcn -mcpu=hawaii < %s | FileCheck -check-prefixes=GCN,GFX678,GFX7 %s4; RUN: llc -mtriple=amdgcn -mcpu=fiji < %s | FileCheck -check-prefixes=GCN,GFX678,GFX8 %s5; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9 %s6; RUN: llc -mtriple=amdgcn -mcpu=gfx1030 < %s | FileCheck -check-prefixes=GCN,GFX1011,GFX10 %s7; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GCN,GFX1011,GFX11 %s8 9declare void @llvm.set.rounding(i32)10declare i32 @llvm.get.rounding()11 12define amdgpu_gfx void @s_set_rounding(i32 inreg %rounding) {13; GFX678-LABEL: s_set_rounding:14; GFX678: ; %bb.0:15; GFX678-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)16; GFX678-NEXT: s_add_i32 s34, s4, -417; GFX678-NEXT: s_min_u32 s34, s4, s3418; GFX678-NEXT: s_lshl_b32 s36, s34, 219; GFX678-NEXT: s_mov_b32 s34, 0x1c84a50f20; GFX678-NEXT: s_mov_b32 s35, 0xb73e62d921; GFX678-NEXT: s_lshr_b64 s[34:35], s[34:35], s3622; GFX678-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s3423; GFX678-NEXT: s_setpc_b64 s[30:31]24;25; GFX9-LABEL: s_set_rounding:26; GFX9: ; %bb.0:27; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)28; GFX9-NEXT: s_add_i32 s34, s4, -429; GFX9-NEXT: s_min_u32 s34, s4, s3430; GFX9-NEXT: s_lshl_b32 s36, s34, 231; GFX9-NEXT: s_mov_b32 s34, 0x1c84a50f32; GFX9-NEXT: s_mov_b32 s35, 0xb73e62d933; GFX9-NEXT: s_lshr_b64 s[34:35], s[34:35], s3634; GFX9-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s3435; GFX9-NEXT: s_setpc_b64 s[30:31]36;37; GFX10-LABEL: s_set_rounding:38; GFX10: ; %bb.0:39; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)40; GFX10-NEXT: s_add_i32 s34, s4, -441; GFX10-NEXT: s_min_u32 s36, s4, s3442; GFX10-NEXT: s_mov_b32 s34, 0x1c84a50f43; GFX10-NEXT: s_mov_b32 s35, 0xb73e62d944; GFX10-NEXT: s_lshl_b32 s36, s36, 245; GFX10-NEXT: s_lshr_b64 s[34:35], s[34:35], s3646; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s3447; GFX10-NEXT: s_setpc_b64 s[30:31]48;49; GFX11-LABEL: s_set_rounding:50; GFX11: ; %bb.0:51; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)52; GFX11-NEXT: s_add_i32 s0, s4, -453; GFX11-NEXT: s_min_u32 s2, s4, s054; GFX11-NEXT: s_mov_b32 s0, 0x1c84a50f55; GFX11-NEXT: s_mov_b32 s1, 0xb73e62d956; GFX11-NEXT: s_lshl_b32 s2, s2, 257; GFX11-NEXT: s_lshr_b64 s[0:1], s[0:1], s258; GFX11-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s059; GFX11-NEXT: s_setpc_b64 s[30:31]60 call void @llvm.set.rounding(i32 %rounding)61 ret void62}63 64define amdgpu_kernel void @s_set_rounding_kernel(i32 inreg %rounding) {65; GFX6-LABEL: s_set_rounding_kernel:66; GFX6: ; %bb.0:67; GFX6-NEXT: s_load_dword s2, s[4:5], 0x968; GFX6-NEXT: s_mov_b32 s0, 0x1c84a50f69; GFX6-NEXT: s_mov_b32 s1, 0xb73e62d970; GFX6-NEXT: ;;#ASMSTART71; GFX6-NEXT: ;;#ASMEND72; GFX6-NEXT: s_waitcnt lgkmcnt(0)73; GFX6-NEXT: s_add_i32 s3, s2, -474; GFX6-NEXT: s_min_u32 s2, s2, s375; GFX6-NEXT: s_lshl_b32 s2, s2, 276; GFX6-NEXT: s_lshr_b64 s[0:1], s[0:1], s277; GFX6-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s078; GFX6-NEXT: s_endpgm79;80; GFX7-LABEL: s_set_rounding_kernel:81; GFX7: ; %bb.0:82; GFX7-NEXT: s_load_dword s2, s[4:5], 0x983; GFX7-NEXT: s_mov_b32 s0, 0x1c84a50f84; GFX7-NEXT: s_mov_b32 s1, 0xb73e62d985; GFX7-NEXT: ;;#ASMSTART86; GFX7-NEXT: ;;#ASMEND87; GFX7-NEXT: s_waitcnt lgkmcnt(0)88; GFX7-NEXT: s_add_i32 s3, s2, -489; GFX7-NEXT: s_min_u32 s2, s2, s390; GFX7-NEXT: s_lshl_b32 s2, s2, 291; GFX7-NEXT: s_lshr_b64 s[0:1], s[0:1], s292; GFX7-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s093; GFX7-NEXT: s_endpgm94;95; GFX8-LABEL: s_set_rounding_kernel:96; GFX8: ; %bb.0:97; GFX8-NEXT: s_load_dword s2, s[4:5], 0x2498; GFX8-NEXT: s_mov_b32 s0, 0x1c84a50f99; GFX8-NEXT: s_mov_b32 s1, 0xb73e62d9100; GFX8-NEXT: ;;#ASMSTART101; GFX8-NEXT: ;;#ASMEND102; GFX8-NEXT: s_waitcnt lgkmcnt(0)103; GFX8-NEXT: s_add_i32 s3, s2, -4104; GFX8-NEXT: s_min_u32 s2, s2, s3105; GFX8-NEXT: s_lshl_b32 s2, s2, 2106; GFX8-NEXT: s_lshr_b64 s[0:1], s[0:1], s2107; GFX8-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s0108; GFX8-NEXT: s_endpgm109;110; GFX9-LABEL: s_set_rounding_kernel:111; GFX9: ; %bb.0:112; GFX9-NEXT: s_load_dword s2, s[4:5], 0x24113; GFX9-NEXT: s_mov_b32 s0, 0x1c84a50f114; GFX9-NEXT: s_mov_b32 s1, 0xb73e62d9115; GFX9-NEXT: ;;#ASMSTART116; GFX9-NEXT: ;;#ASMEND117; GFX9-NEXT: s_waitcnt lgkmcnt(0)118; GFX9-NEXT: s_add_i32 s3, s2, -4119; GFX9-NEXT: s_min_u32 s2, s2, s3120; GFX9-NEXT: s_lshl_b32 s2, s2, 2121; GFX9-NEXT: s_lshr_b64 s[0:1], s[0:1], s2122; GFX9-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s0123; GFX9-NEXT: s_endpgm124;125; GFX10-LABEL: s_set_rounding_kernel:126; GFX10: ; %bb.0:127; GFX10-NEXT: s_load_dword s2, s[4:5], 0x24128; GFX10-NEXT: s_mov_b32 s0, 0x1c84a50f129; GFX10-NEXT: s_mov_b32 s1, 0xb73e62d9130; GFX10-NEXT: ;;#ASMSTART131; GFX10-NEXT: ;;#ASMEND132; GFX10-NEXT: s_waitcnt lgkmcnt(0)133; GFX10-NEXT: s_add_i32 s3, s2, -4134; GFX10-NEXT: s_min_u32 s2, s2, s3135; GFX10-NEXT: s_lshl_b32 s2, s2, 2136; GFX10-NEXT: s_lshr_b64 s[0:1], s[0:1], s2137; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s0138; GFX10-NEXT: s_endpgm139;140; GFX11-LABEL: s_set_rounding_kernel:141; GFX11: ; %bb.0:142; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x24143; GFX11-NEXT: s_mov_b32 s0, 0x1c84a50f144; GFX11-NEXT: s_mov_b32 s1, 0xb73e62d9145; GFX11-NEXT: ;;#ASMSTART146; GFX11-NEXT: ;;#ASMEND147; GFX11-NEXT: s_waitcnt lgkmcnt(0)148; GFX11-NEXT: s_add_i32 s3, s2, -4149; GFX11-NEXT: s_min_u32 s2, s2, s3150; GFX11-NEXT: s_lshl_b32 s2, s2, 2151; GFX11-NEXT: s_lshr_b64 s[0:1], s[0:1], s2152; GFX11-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s0153; GFX11-NEXT: s_endpgm154 call void @llvm.set.rounding(i32 %rounding)155 call void asm sideeffect "",""()156 ret void157}158 159define void @v_set_rounding(i32 %rounding) {160; GFX6-LABEL: v_set_rounding:161; GFX6: ; %bb.0:162; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)163; GFX6-NEXT: v_add_i32_e32 v1, vcc, -4, v0164; GFX6-NEXT: v_min_u32_e32 v0, v0, v1165; GFX6-NEXT: s_mov_b32 s4, 0x1c84a50f166; GFX6-NEXT: v_lshlrev_b32_e32 v0, 2, v0167; GFX6-NEXT: s_mov_b32 s5, 0xb73e62d9168; GFX6-NEXT: v_lshr_b64 v[0:1], s[4:5], v0169; GFX6-NEXT: v_readfirstlane_b32 s4, v0170; GFX6-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s4171; GFX6-NEXT: s_setpc_b64 s[30:31]172;173; GFX7-LABEL: v_set_rounding:174; GFX7: ; %bb.0:175; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)176; GFX7-NEXT: v_add_i32_e32 v1, vcc, -4, v0177; GFX7-NEXT: v_min_u32_e32 v0, v0, v1178; GFX7-NEXT: s_mov_b32 s4, 0x1c84a50f179; GFX7-NEXT: v_lshlrev_b32_e32 v0, 2, v0180; GFX7-NEXT: s_mov_b32 s5, 0xb73e62d9181; GFX7-NEXT: v_lshr_b64 v[0:1], s[4:5], v0182; GFX7-NEXT: v_readfirstlane_b32 s4, v0183; GFX7-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s4184; GFX7-NEXT: s_setpc_b64 s[30:31]185;186; GFX8-LABEL: v_set_rounding:187; GFX8: ; %bb.0:188; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)189; GFX8-NEXT: v_add_u32_e32 v1, vcc, -4, v0190; GFX8-NEXT: v_min_u32_e32 v0, v0, v1191; GFX8-NEXT: s_mov_b32 s4, 0x1c84a50f192; GFX8-NEXT: v_lshlrev_b32_e32 v0, 2, v0193; GFX8-NEXT: s_mov_b32 s5, 0xb73e62d9194; GFX8-NEXT: v_lshrrev_b64 v[0:1], v0, s[4:5]195; GFX8-NEXT: v_readfirstlane_b32 s4, v0196; GFX8-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s4197; GFX8-NEXT: s_setpc_b64 s[30:31]198;199; GFX9-LABEL: v_set_rounding:200; GFX9: ; %bb.0:201; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)202; GFX9-NEXT: v_add_u32_e32 v1, -4, v0203; GFX9-NEXT: v_min_u32_e32 v0, v0, v1204; GFX9-NEXT: s_mov_b32 s4, 0x1c84a50f205; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0206; GFX9-NEXT: s_mov_b32 s5, 0xb73e62d9207; GFX9-NEXT: v_lshrrev_b64 v[0:1], v0, s[4:5]208; GFX9-NEXT: v_readfirstlane_b32 s4, v0209; GFX9-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s4210; GFX9-NEXT: s_setpc_b64 s[30:31]211;212; GFX10-LABEL: v_set_rounding:213; GFX10: ; %bb.0:214; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)215; GFX10-NEXT: v_add_nc_u32_e32 v1, -4, v0216; GFX10-NEXT: s_mov_b32 s4, 0x1c84a50f217; GFX10-NEXT: s_mov_b32 s5, 0xb73e62d9218; GFX10-NEXT: v_min_u32_e32 v0, v0, v1219; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0220; GFX10-NEXT: v_lshrrev_b64 v[0:1], v0, s[4:5]221; GFX10-NEXT: v_readfirstlane_b32 s4, v0222; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s4223; GFX10-NEXT: s_setpc_b64 s[30:31]224;225; GFX11-LABEL: v_set_rounding:226; GFX11: ; %bb.0:227; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)228; GFX11-NEXT: v_add_nc_u32_e32 v1, -4, v0229; GFX11-NEXT: s_mov_b32 s0, 0x1c84a50f230; GFX11-NEXT: s_mov_b32 s1, 0xb73e62d9231; GFX11-NEXT: v_min_u32_e32 v0, v0, v1232; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0233; GFX11-NEXT: v_lshrrev_b64 v[0:1], v0, s[0:1]234; GFX11-NEXT: v_readfirstlane_b32 s0, v0235; GFX11-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s0236; GFX11-NEXT: s_setpc_b64 s[30:31]237 call void @llvm.set.rounding(i32 %rounding)238 ret void239}240 241define void @set_rounding_get_rounding() {242; GFX678-LABEL: set_rounding_get_rounding:243; GFX678: ; %bb.0:244; GFX678-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)245; GFX678-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 0, 4)246; GFX678-NEXT: s_lshl_b32 s6, s4, 2247; GFX678-NEXT: s_mov_b32 s4, 0xeb24da71248; GFX678-NEXT: s_mov_b32 s5, 0xc96f385249; GFX678-NEXT: s_lshr_b64 s[4:5], s[4:5], s6250; GFX678-NEXT: s_and_b32 s4, s4, 15251; GFX678-NEXT: s_add_i32 s5, s4, 4252; GFX678-NEXT: s_cmp_lt_u32 s4, 4253; GFX678-NEXT: s_cselect_b32 s4, s4, s5254; GFX678-NEXT: s_add_i32 s5, s4, -4255; GFX678-NEXT: s_min_u32 s4, s4, s5256; GFX678-NEXT: s_lshl_b32 s6, s4, 2257; GFX678-NEXT: s_mov_b32 s4, 0x1c84a50f258; GFX678-NEXT: s_mov_b32 s5, 0xb73e62d9259; GFX678-NEXT: s_lshr_b64 s[4:5], s[4:5], s6260; GFX678-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s4261; GFX678-NEXT: s_setpc_b64 s[30:31]262;263; GFX9-LABEL: set_rounding_get_rounding:264; GFX9: ; %bb.0:265; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)266; GFX9-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 0, 4)267; GFX9-NEXT: s_lshl_b32 s6, s4, 2268; GFX9-NEXT: s_mov_b32 s4, 0xeb24da71269; GFX9-NEXT: s_mov_b32 s5, 0xc96f385270; GFX9-NEXT: s_lshr_b64 s[4:5], s[4:5], s6271; GFX9-NEXT: s_and_b32 s4, s4, 15272; GFX9-NEXT: s_add_i32 s5, s4, 4273; GFX9-NEXT: s_cmp_lt_u32 s4, 4274; GFX9-NEXT: s_cselect_b32 s4, s4, s5275; GFX9-NEXT: s_add_i32 s5, s4, -4276; GFX9-NEXT: s_min_u32 s4, s4, s5277; GFX9-NEXT: s_lshl_b32 s6, s4, 2278; GFX9-NEXT: s_mov_b32 s4, 0x1c84a50f279; GFX9-NEXT: s_mov_b32 s5, 0xb73e62d9280; GFX9-NEXT: s_lshr_b64 s[4:5], s[4:5], s6281; GFX9-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s4282; GFX9-NEXT: s_setpc_b64 s[30:31]283;284; GFX10-LABEL: set_rounding_get_rounding:285; GFX10: ; %bb.0:286; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)287; GFX10-NEXT: s_getreg_b32 s6, hwreg(HW_REG_MODE, 0, 4)288; GFX10-NEXT: s_mov_b32 s4, 0xeb24da71289; GFX10-NEXT: s_mov_b32 s5, 0xc96f385290; GFX10-NEXT: s_lshl_b32 s6, s6, 2291; GFX10-NEXT: s_lshr_b64 s[4:5], s[4:5], s6292; GFX10-NEXT: s_and_b32 s4, s4, 15293; GFX10-NEXT: s_add_i32 s5, s4, 4294; GFX10-NEXT: s_cmp_lt_u32 s4, 4295; GFX10-NEXT: s_cselect_b32 s4, s4, s5296; GFX10-NEXT: s_add_i32 s5, s4, -4297; GFX10-NEXT: s_min_u32 s6, s4, s5298; GFX10-NEXT: s_mov_b32 s4, 0x1c84a50f299; GFX10-NEXT: s_mov_b32 s5, 0xb73e62d9300; GFX10-NEXT: s_lshl_b32 s6, s6, 2301; GFX10-NEXT: s_lshr_b64 s[4:5], s[4:5], s6302; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s4303; GFX10-NEXT: s_setpc_b64 s[30:31]304;305; GFX11-LABEL: set_rounding_get_rounding:306; GFX11: ; %bb.0:307; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)308; GFX11-NEXT: s_getreg_b32 s2, hwreg(HW_REG_MODE, 0, 4)309; GFX11-NEXT: s_mov_b32 s0, 0xeb24da71310; GFX11-NEXT: s_mov_b32 s1, 0xc96f385311; GFX11-NEXT: s_lshl_b32 s2, s2, 2312; GFX11-NEXT: s_lshr_b64 s[0:1], s[0:1], s2313; GFX11-NEXT: s_and_b32 s0, s0, 15314; GFX11-NEXT: s_add_i32 s1, s0, 4315; GFX11-NEXT: s_cmp_lt_u32 s0, 4316; GFX11-NEXT: s_cselect_b32 s0, s0, s1317; GFX11-NEXT: s_add_i32 s1, s0, -4318; GFX11-NEXT: s_min_u32 s2, s0, s1319; GFX11-NEXT: s_mov_b32 s0, 0x1c84a50f320; GFX11-NEXT: s_mov_b32 s1, 0xb73e62d9321; GFX11-NEXT: s_lshl_b32 s2, s2, 2322; GFX11-NEXT: s_lshr_b64 s[0:1], s[0:1], s2323; GFX11-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s0324; GFX11-NEXT: s_setpc_b64 s[30:31]325 %rounding = call i32 @llvm.get.rounding()326 call void @llvm.set.rounding(i32 %rounding)327 ret void328}329 330define void @s_set_rounding_0() {331; GFX678-LABEL: s_set_rounding_0:332; GFX678: ; %bb.0:333; GFX678-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)334; GFX678-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 15335; GFX678-NEXT: s_setpc_b64 s[30:31]336;337; GFX9-LABEL: s_set_rounding_0:338; GFX9: ; %bb.0:339; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)340; GFX9-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 15341; GFX9-NEXT: s_setpc_b64 s[30:31]342;343; GFX1011-LABEL: s_set_rounding_0:344; GFX1011: ; %bb.0:345; GFX1011-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)346; GFX1011-NEXT: s_round_mode 0xf347; GFX1011-NEXT: s_setpc_b64 s[30:31]348 call void @llvm.set.rounding(i32 0)349 ret void350}351 352define void @s_set_rounding_1() {353; GFX678-LABEL: s_set_rounding_1:354; GFX678: ; %bb.0:355; GFX678-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)356; GFX678-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 0357; GFX678-NEXT: s_setpc_b64 s[30:31]358;359; GFX9-LABEL: s_set_rounding_1:360; GFX9: ; %bb.0:361; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)362; GFX9-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 0363; GFX9-NEXT: s_setpc_b64 s[30:31]364;365; GFX1011-LABEL: s_set_rounding_1:366; GFX1011: ; %bb.0:367; GFX1011-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)368; GFX1011-NEXT: s_round_mode 0x0369; GFX1011-NEXT: s_setpc_b64 s[30:31]370 call void @llvm.set.rounding(i32 1)371 ret void372}373 374define void @s_set_rounding_2() {375; GFX678-LABEL: s_set_rounding_2:376; GFX678: ; %bb.0:377; GFX678-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)378; GFX678-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 5379; GFX678-NEXT: s_setpc_b64 s[30:31]380;381; GFX9-LABEL: s_set_rounding_2:382; GFX9: ; %bb.0:383; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)384; GFX9-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 5385; GFX9-NEXT: s_setpc_b64 s[30:31]386;387; GFX1011-LABEL: s_set_rounding_2:388; GFX1011: ; %bb.0:389; GFX1011-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)390; GFX1011-NEXT: s_round_mode 0x5391; GFX1011-NEXT: s_setpc_b64 s[30:31]392 call void @llvm.set.rounding(i32 2)393 ret void394}395 396define void @s_set_rounding_3() {397; GFX678-LABEL: s_set_rounding_3:398; GFX678: ; %bb.0:399; GFX678-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)400; GFX678-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 10401; GFX678-NEXT: s_setpc_b64 s[30:31]402;403; GFX9-LABEL: s_set_rounding_3:404; GFX9: ; %bb.0:405; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)406; GFX9-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 10407; GFX9-NEXT: s_setpc_b64 s[30:31]408;409; GFX1011-LABEL: s_set_rounding_3:410; GFX1011: ; %bb.0:411; GFX1011-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)412; GFX1011-NEXT: s_round_mode 0xa413; GFX1011-NEXT: s_setpc_b64 s[30:31]414 call void @llvm.set.rounding(i32 3)415 ret void416}417 418; Unsupported mode.419define void @s_set_rounding_4() {420; GFX678-LABEL: s_set_rounding_4:421; GFX678: ; %bb.0:422; GFX678-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)423; GFX678-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 15424; GFX678-NEXT: s_setpc_b64 s[30:31]425;426; GFX9-LABEL: s_set_rounding_4:427; GFX9: ; %bb.0:428; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)429; GFX9-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 15430; GFX9-NEXT: s_setpc_b64 s[30:31]431;432; GFX1011-LABEL: s_set_rounding_4:433; GFX1011: ; %bb.0:434; GFX1011-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)435; GFX1011-NEXT: s_round_mode 0xf436; GFX1011-NEXT: s_setpc_b64 s[30:31]437 call void @llvm.set.rounding(i32 4)438 ret void439}440 441; undefined442define void @s_set_rounding_5() {443; GFX678-LABEL: s_set_rounding_5:444; GFX678: ; %bb.0:445; GFX678-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)446; GFX678-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 0447; GFX678-NEXT: s_setpc_b64 s[30:31]448;449; GFX9-LABEL: s_set_rounding_5:450; GFX9: ; %bb.0:451; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)452; GFX9-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 0453; GFX9-NEXT: s_setpc_b64 s[30:31]454;455; GFX1011-LABEL: s_set_rounding_5:456; GFX1011: ; %bb.0:457; GFX1011-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)458; GFX1011-NEXT: s_round_mode 0x0459; GFX1011-NEXT: s_setpc_b64 s[30:31]460 call void @llvm.set.rounding(i32 5)461 ret void462}463 464; undefined465define void @s_set_rounding_6() {466; GFX678-LABEL: s_set_rounding_6:467; GFX678: ; %bb.0:468; GFX678-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)469; GFX678-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 5470; GFX678-NEXT: s_setpc_b64 s[30:31]471;472; GFX9-LABEL: s_set_rounding_6:473; GFX9: ; %bb.0:474; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)475; GFX9-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 5476; GFX9-NEXT: s_setpc_b64 s[30:31]477;478; GFX1011-LABEL: s_set_rounding_6:479; GFX1011: ; %bb.0:480; GFX1011-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)481; GFX1011-NEXT: s_round_mode 0x5482; GFX1011-NEXT: s_setpc_b64 s[30:31]483 call void @llvm.set.rounding(i32 6)484 ret void485}486 487; "Dynamic"488define void @s_set_rounding_7() {489; GFX678-LABEL: s_set_rounding_7:490; GFX678: ; %bb.0:491; GFX678-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)492; GFX678-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 10493; GFX678-NEXT: s_setpc_b64 s[30:31]494;495; GFX9-LABEL: s_set_rounding_7:496; GFX9: ; %bb.0:497; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)498; GFX9-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 10499; GFX9-NEXT: s_setpc_b64 s[30:31]500;501; GFX1011-LABEL: s_set_rounding_7:502; GFX1011: ; %bb.0:503; GFX1011-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)504; GFX1011-NEXT: s_round_mode 0xa505; GFX1011-NEXT: s_setpc_b64 s[30:31]506 call void @llvm.set.rounding(i32 7)507 ret void508}509 510; Invalid511define void @s_set_rounding_neg1() {512; GFX678-LABEL: s_set_rounding_neg1:513; GFX678: ; %bb.0:514; GFX678-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)515; GFX678-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 11516; GFX678-NEXT: s_setpc_b64 s[30:31]517;518; GFX9-LABEL: s_set_rounding_neg1:519; GFX9: ; %bb.0:520; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)521; GFX9-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 11522; GFX9-NEXT: s_setpc_b64 s[30:31]523;524; GFX1011-LABEL: s_set_rounding_neg1:525; GFX1011: ; %bb.0:526; GFX1011-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)527; GFX1011-NEXT: s_round_mode 0xb528; GFX1011-NEXT: s_setpc_b64 s[30:31]529 call void @llvm.set.rounding(i32 -1)530 ret void531}532 533; --------------------------------------------------------------------534; Test extended values535; --------------------------------------------------------------------536 537; NearestTiesToEvenF32_TowardPositiveF64 = 8538define void @s_set_rounding_8() {539; GFX678-LABEL: s_set_rounding_8:540; GFX678: ; %bb.0:541; GFX678-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)542; GFX678-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 4543; GFX678-NEXT: s_setpc_b64 s[30:31]544;545; GFX9-LABEL: s_set_rounding_8:546; GFX9: ; %bb.0:547; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)548; GFX9-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 4549; GFX9-NEXT: s_setpc_b64 s[30:31]550;551; GFX1011-LABEL: s_set_rounding_8:552; GFX1011: ; %bb.0:553; GFX1011-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)554; GFX1011-NEXT: s_round_mode 0x4555; GFX1011-NEXT: s_setpc_b64 s[30:31]556 call void @llvm.set.rounding(i32 8)557 ret void558}559 560; NearestTiesToEvenF32_TowardNegativeF64 = 9561define void @s_set_rounding_9() {562; GFX678-LABEL: s_set_rounding_9:563; GFX678: ; %bb.0:564; GFX678-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)565; GFX678-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 8566; GFX678-NEXT: s_setpc_b64 s[30:31]567;568; GFX9-LABEL: s_set_rounding_9:569; GFX9: ; %bb.0:570; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)571; GFX9-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 8572; GFX9-NEXT: s_setpc_b64 s[30:31]573;574; GFX1011-LABEL: s_set_rounding_9:575; GFX1011: ; %bb.0:576; GFX1011-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)577; GFX1011-NEXT: s_round_mode 0x8578; GFX1011-NEXT: s_setpc_b64 s[30:31]579 call void @llvm.set.rounding(i32 9)580 ret void581}582 583; NearestTiesToEvenF32_TowardZeroF64 = 10584define void @s_set_rounding_10() {585; GFX678-LABEL: s_set_rounding_10:586; GFX678: ; %bb.0:587; GFX678-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)588; GFX678-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 12589; GFX678-NEXT: s_setpc_b64 s[30:31]590;591; GFX9-LABEL: s_set_rounding_10:592; GFX9: ; %bb.0:593; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)594; GFX9-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 12595; GFX9-NEXT: s_setpc_b64 s[30:31]596;597; GFX1011-LABEL: s_set_rounding_10:598; GFX1011: ; %bb.0:599; GFX1011-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)600; GFX1011-NEXT: s_round_mode 0xc601; GFX1011-NEXT: s_setpc_b64 s[30:31]602 call void @llvm.set.rounding(i32 10)603 ret void604}605 606; TowardPositiveF32_NearestTiesToEvenF64 = 11607define void @s_set_rounding_11() {608; GFX678-LABEL: s_set_rounding_11:609; GFX678: ; %bb.0:610; GFX678-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)611; GFX678-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 1612; GFX678-NEXT: s_setpc_b64 s[30:31]613;614; GFX9-LABEL: s_set_rounding_11:615; GFX9: ; %bb.0:616; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)617; GFX9-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 1618; GFX9-NEXT: s_setpc_b64 s[30:31]619;620; GFX1011-LABEL: s_set_rounding_11:621; GFX1011: ; %bb.0:622; GFX1011-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)623; GFX1011-NEXT: s_round_mode 0x1624; GFX1011-NEXT: s_setpc_b64 s[30:31]625 call void @llvm.set.rounding(i32 11)626 ret void627}628 629; TowardPositiveF32_TowardNegativeF64 = 12630define void @s_set_rounding_12() {631; GFX678-LABEL: s_set_rounding_12:632; GFX678: ; %bb.0:633; GFX678-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)634; GFX678-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 9635; GFX678-NEXT: s_setpc_b64 s[30:31]636;637; GFX9-LABEL: s_set_rounding_12:638; GFX9: ; %bb.0:639; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)640; GFX9-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 9641; GFX9-NEXT: s_setpc_b64 s[30:31]642;643; GFX1011-LABEL: s_set_rounding_12:644; GFX1011: ; %bb.0:645; GFX1011-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)646; GFX1011-NEXT: s_round_mode 0x9647; GFX1011-NEXT: s_setpc_b64 s[30:31]648 call void @llvm.set.rounding(i32 12)649 ret void650}651 652; TowardPositiveF32_TowardZeroF64 = 13653define void @s_set_rounding_13() {654; GFX678-LABEL: s_set_rounding_13:655; GFX678: ; %bb.0:656; GFX678-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)657; GFX678-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 13658; GFX678-NEXT: s_setpc_b64 s[30:31]659;660; GFX9-LABEL: s_set_rounding_13:661; GFX9: ; %bb.0:662; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)663; GFX9-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 13664; GFX9-NEXT: s_setpc_b64 s[30:31]665;666; GFX1011-LABEL: s_set_rounding_13:667; GFX1011: ; %bb.0:668; GFX1011-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)669; GFX1011-NEXT: s_round_mode 0xd670; GFX1011-NEXT: s_setpc_b64 s[30:31]671 call void @llvm.set.rounding(i32 13)672 ret void673}674 675; TowardNegativeF32_NearestTiesToEvenF64 = 14676define void @s_set_rounding_14() {677; GFX678-LABEL: s_set_rounding_14:678; GFX678: ; %bb.0:679; GFX678-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)680; GFX678-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 2681; GFX678-NEXT: s_setpc_b64 s[30:31]682;683; GFX9-LABEL: s_set_rounding_14:684; GFX9: ; %bb.0:685; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)686; GFX9-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 2687; GFX9-NEXT: s_setpc_b64 s[30:31]688;689; GFX1011-LABEL: s_set_rounding_14:690; GFX1011: ; %bb.0:691; GFX1011-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)692; GFX1011-NEXT: s_round_mode 0x2693; GFX1011-NEXT: s_setpc_b64 s[30:31]694 call void @llvm.set.rounding(i32 14)695 ret void696}697 698; TowardNegativeF32_TowardPositiveF64 = 15699define void @s_set_rounding_15() {700; GFX678-LABEL: s_set_rounding_15:701; GFX678: ; %bb.0:702; GFX678-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)703; GFX678-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 6704; GFX678-NEXT: s_setpc_b64 s[30:31]705;706; GFX9-LABEL: s_set_rounding_15:707; GFX9: ; %bb.0:708; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)709; GFX9-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 6710; GFX9-NEXT: s_setpc_b64 s[30:31]711;712; GFX1011-LABEL: s_set_rounding_15:713; GFX1011: ; %bb.0:714; GFX1011-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)715; GFX1011-NEXT: s_round_mode 0x6716; GFX1011-NEXT: s_setpc_b64 s[30:31]717 call void @llvm.set.rounding(i32 15)718 ret void719}720 721 722; TowardNegativeF32_TowardZeroF64 = 16723define void @s_set_rounding_16() {724; GFX678-LABEL: s_set_rounding_16:725; GFX678: ; %bb.0:726; GFX678-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)727; GFX678-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 14728; GFX678-NEXT: s_setpc_b64 s[30:31]729;730; GFX9-LABEL: s_set_rounding_16:731; GFX9: ; %bb.0:732; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)733; GFX9-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 14734; GFX9-NEXT: s_setpc_b64 s[30:31]735;736; GFX1011-LABEL: s_set_rounding_16:737; GFX1011: ; %bb.0:738; GFX1011-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)739; GFX1011-NEXT: s_round_mode 0xe740; GFX1011-NEXT: s_setpc_b64 s[30:31]741 call void @llvm.set.rounding(i32 16)742 ret void743}744 745; TowardZeroF32_NearestTiesToEvenF64 = 17746define void @s_set_rounding_17() {747; GFX678-LABEL: s_set_rounding_17:748; GFX678: ; %bb.0:749; GFX678-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)750; GFX678-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 3751; GFX678-NEXT: s_setpc_b64 s[30:31]752;753; GFX9-LABEL: s_set_rounding_17:754; GFX9: ; %bb.0:755; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)756; GFX9-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 3757; GFX9-NEXT: s_setpc_b64 s[30:31]758;759; GFX1011-LABEL: s_set_rounding_17:760; GFX1011: ; %bb.0:761; GFX1011-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)762; GFX1011-NEXT: s_round_mode 0x3763; GFX1011-NEXT: s_setpc_b64 s[30:31]764 call void @llvm.set.rounding(i32 17)765 ret void766}767 768; TowardZeroF32_TowardPositiveF64 = 18769define void @s_set_rounding_18() {770; GFX678-LABEL: s_set_rounding_18:771; GFX678: ; %bb.0:772; GFX678-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)773; GFX678-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 7774; GFX678-NEXT: s_setpc_b64 s[30:31]775;776; GFX9-LABEL: s_set_rounding_18:777; GFX9: ; %bb.0:778; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)779; GFX9-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 7780; GFX9-NEXT: s_setpc_b64 s[30:31]781;782; GFX1011-LABEL: s_set_rounding_18:783; GFX1011: ; %bb.0:784; GFX1011-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)785; GFX1011-NEXT: s_round_mode 0x7786; GFX1011-NEXT: s_setpc_b64 s[30:31]787 call void @llvm.set.rounding(i32 18)788 ret void789}790 791; TowardZeroF32_TowardNegativeF64 = 19,792define void @s_set_rounding_19() {793; GFX678-LABEL: s_set_rounding_19:794; GFX678: ; %bb.0:795; GFX678-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)796; GFX678-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 11797; GFX678-NEXT: s_setpc_b64 s[30:31]798;799; GFX9-LABEL: s_set_rounding_19:800; GFX9: ; %bb.0:801; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)802; GFX9-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 11803; GFX9-NEXT: s_setpc_b64 s[30:31]804;805; GFX1011-LABEL: s_set_rounding_19:806; GFX1011: ; %bb.0:807; GFX1011-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)808; GFX1011-NEXT: s_round_mode 0xb809; GFX1011-NEXT: s_setpc_b64 s[30:31]810 call void @llvm.set.rounding(i32 19)811 ret void812}813 814; Invalid, out of bounds815define void @s_set_rounding_20() {816; GFX678-LABEL: s_set_rounding_20:817; GFX678: ; %bb.0:818; GFX678-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)819; GFX678-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 11820; GFX678-NEXT: s_setpc_b64 s[30:31]821;822; GFX9-LABEL: s_set_rounding_20:823; GFX9: ; %bb.0:824; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)825; GFX9-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 11826; GFX9-NEXT: s_setpc_b64 s[30:31]827;828; GFX1011-LABEL: s_set_rounding_20:829; GFX1011: ; %bb.0:830; GFX1011-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)831; GFX1011-NEXT: s_round_mode 0xb832; GFX1011-NEXT: s_setpc_b64 s[30:31]833 call void @llvm.set.rounding(i32 20)834 ret void835}836 837define void @s_set_rounding_0xffff() {838; GFX678-LABEL: s_set_rounding_0xffff:839; GFX678: ; %bb.0:840; GFX678-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)841; GFX678-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 11842; GFX678-NEXT: s_setpc_b64 s[30:31]843;844; GFX9-LABEL: s_set_rounding_0xffff:845; GFX9: ; %bb.0:846; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)847; GFX9-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 11848; GFX9-NEXT: s_setpc_b64 s[30:31]849;850; GFX1011-LABEL: s_set_rounding_0xffff:851; GFX1011: ; %bb.0:852; GFX1011-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)853; GFX1011-NEXT: s_round_mode 0xb854; GFX1011-NEXT: s_setpc_b64 s[30:31]855 call void @llvm.set.rounding(i32 65535)856 ret void857}858 859; --------------------------------------------------------------------860; Test optimization knowing the value can only be in the standard861; range862; --------------------------------------------------------------------863 864define amdgpu_gfx void @s_set_rounding_i2_zeroext(i2 zeroext inreg %rounding) {865; GFX6-LABEL: s_set_rounding_i2_zeroext:866; GFX6: ; %bb.0:867; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)868; GFX6-NEXT: s_lshl_b32 s34, s4, 2869; GFX6-NEXT: s_lshr_b32 s34, 0xa50f, s34870; GFX6-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s34871; GFX6-NEXT: s_setpc_b64 s[30:31]872;873; GFX7-LABEL: s_set_rounding_i2_zeroext:874; GFX7: ; %bb.0:875; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)876; GFX7-NEXT: s_lshl_b32 s34, s4, 2877; GFX7-NEXT: s_lshr_b32 s34, 0xa50f, s34878; GFX7-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s34879; GFX7-NEXT: s_setpc_b64 s[30:31]880;881; GFX8-LABEL: s_set_rounding_i2_zeroext:882; GFX8: ; %bb.0:883; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)884; GFX8-NEXT: s_and_b32 s34, 0xffff, s4885; GFX8-NEXT: s_lshl_b32 s34, s34, 2886; GFX8-NEXT: s_lshr_b32 s34, 0xa50f, s34887; GFX8-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s34888; GFX8-NEXT: s_setpc_b64 s[30:31]889;890; GFX9-LABEL: s_set_rounding_i2_zeroext:891; GFX9: ; %bb.0:892; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)893; GFX9-NEXT: s_and_b32 s34, 0xffff, s4894; GFX9-NEXT: s_lshl_b32 s34, s34, 2895; GFX9-NEXT: s_lshr_b32 s34, 0xa50f, s34896; GFX9-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s34897; GFX9-NEXT: s_setpc_b64 s[30:31]898;899; GFX10-LABEL: s_set_rounding_i2_zeroext:900; GFX10: ; %bb.0:901; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)902; GFX10-NEXT: s_and_b32 s34, 0xffff, s4903; GFX10-NEXT: s_lshl_b32 s34, s34, 2904; GFX10-NEXT: s_lshr_b32 s34, 0xa50f, s34905; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s34906; GFX10-NEXT: s_setpc_b64 s[30:31]907;908; GFX11-LABEL: s_set_rounding_i2_zeroext:909; GFX11: ; %bb.0:910; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)911; GFX11-NEXT: s_and_b32 s0, 0xffff, s4912; GFX11-NEXT: s_lshl_b32 s0, s0, 2913; GFX11-NEXT: s_lshr_b32 s0, 0xa50f, s0914; GFX11-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s0915; GFX11-NEXT: s_setpc_b64 s[30:31]916 %zext.rounding = zext i2 %rounding to i32917 call void @llvm.set.rounding(i32 %zext.rounding)918 ret void919}920 921define amdgpu_gfx void @s_set_rounding_i2_signext(i2 signext inreg %rounding) {922; GFX6-LABEL: s_set_rounding_i2_signext:923; GFX6: ; %bb.0:924; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)925; GFX6-NEXT: s_add_i32 s34, s4, -4926; GFX6-NEXT: s_min_u32 s34, s4, s34927; GFX6-NEXT: s_lshl_b32 s36, s34, 2928; GFX6-NEXT: s_mov_b32 s34, 0x1c84a50f929; GFX6-NEXT: s_mov_b32 s35, 0xb73e62d9930; GFX6-NEXT: s_lshr_b64 s[34:35], s[34:35], s36931; GFX6-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s34932; GFX6-NEXT: s_setpc_b64 s[30:31]933;934; GFX7-LABEL: s_set_rounding_i2_signext:935; GFX7: ; %bb.0:936; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)937; GFX7-NEXT: s_add_i32 s34, s4, -4938; GFX7-NEXT: s_min_u32 s34, s4, s34939; GFX7-NEXT: s_lshl_b32 s36, s34, 2940; GFX7-NEXT: s_mov_b32 s34, 0x1c84a50f941; GFX7-NEXT: s_mov_b32 s35, 0xb73e62d9942; GFX7-NEXT: s_lshr_b64 s[34:35], s[34:35], s36943; GFX7-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s34944; GFX7-NEXT: s_setpc_b64 s[30:31]945;946; GFX8-LABEL: s_set_rounding_i2_signext:947; GFX8: ; %bb.0:948; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)949; GFX8-NEXT: s_sext_i32_i16 s34, s4950; GFX8-NEXT: s_add_i32 s35, s34, -4951; GFX8-NEXT: s_min_u32 s34, s34, s35952; GFX8-NEXT: s_lshl_b32 s36, s34, 2953; GFX8-NEXT: s_mov_b32 s34, 0x1c84a50f954; GFX8-NEXT: s_mov_b32 s35, 0xb73e62d9955; GFX8-NEXT: s_lshr_b64 s[34:35], s[34:35], s36956; GFX8-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s34957; GFX8-NEXT: s_setpc_b64 s[30:31]958;959; GFX9-LABEL: s_set_rounding_i2_signext:960; GFX9: ; %bb.0:961; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)962; GFX9-NEXT: s_sext_i32_i16 s34, s4963; GFX9-NEXT: s_add_i32 s35, s34, -4964; GFX9-NEXT: s_min_u32 s34, s34, s35965; GFX9-NEXT: s_lshl_b32 s36, s34, 2966; GFX9-NEXT: s_mov_b32 s34, 0x1c84a50f967; GFX9-NEXT: s_mov_b32 s35, 0xb73e62d9968; GFX9-NEXT: s_lshr_b64 s[34:35], s[34:35], s36969; GFX9-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s34970; GFX9-NEXT: s_setpc_b64 s[30:31]971;972; GFX10-LABEL: s_set_rounding_i2_signext:973; GFX10: ; %bb.0:974; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)975; GFX10-NEXT: s_sext_i32_i16 s34, s4976; GFX10-NEXT: s_add_i32 s35, s34, -4977; GFX10-NEXT: s_min_u32 s36, s34, s35978; GFX10-NEXT: s_mov_b32 s34, 0x1c84a50f979; GFX10-NEXT: s_mov_b32 s35, 0xb73e62d9980; GFX10-NEXT: s_lshl_b32 s36, s36, 2981; GFX10-NEXT: s_lshr_b64 s[34:35], s[34:35], s36982; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s34983; GFX10-NEXT: s_setpc_b64 s[30:31]984;985; GFX11-LABEL: s_set_rounding_i2_signext:986; GFX11: ; %bb.0:987; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)988; GFX11-NEXT: s_sext_i32_i16 s0, s4989; GFX11-NEXT: s_add_i32 s1, s0, -4990; GFX11-NEXT: s_min_u32 s2, s0, s1991; GFX11-NEXT: s_mov_b32 s0, 0x1c84a50f992; GFX11-NEXT: s_mov_b32 s1, 0xb73e62d9993; GFX11-NEXT: s_lshl_b32 s2, s2, 2994; GFX11-NEXT: s_lshr_b64 s[0:1], s[0:1], s2995; GFX11-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s0996; GFX11-NEXT: s_setpc_b64 s[30:31]997 %sext.rounding = sext i2 %rounding to i32998 call void @llvm.set.rounding(i32 %sext.rounding)999 ret void1000}1001 1002define amdgpu_gfx void @s_set_rounding_i3_signext(i3 signext inreg %rounding) {1003; GFX6-LABEL: s_set_rounding_i3_signext:1004; GFX6: ; %bb.0:1005; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1006; GFX6-NEXT: s_add_i32 s34, s4, -41007; GFX6-NEXT: s_min_u32 s34, s4, s341008; GFX6-NEXT: s_lshl_b32 s36, s34, 21009; GFX6-NEXT: s_mov_b32 s34, 0x1c84a50f1010; GFX6-NEXT: s_mov_b32 s35, 0xb73e62d91011; GFX6-NEXT: s_lshr_b64 s[34:35], s[34:35], s361012; GFX6-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s341013; GFX6-NEXT: s_setpc_b64 s[30:31]1014;1015; GFX7-LABEL: s_set_rounding_i3_signext:1016; GFX7: ; %bb.0:1017; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1018; GFX7-NEXT: s_add_i32 s34, s4, -41019; GFX7-NEXT: s_min_u32 s34, s4, s341020; GFX7-NEXT: s_lshl_b32 s36, s34, 21021; GFX7-NEXT: s_mov_b32 s34, 0x1c84a50f1022; GFX7-NEXT: s_mov_b32 s35, 0xb73e62d91023; GFX7-NEXT: s_lshr_b64 s[34:35], s[34:35], s361024; GFX7-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s341025; GFX7-NEXT: s_setpc_b64 s[30:31]1026;1027; GFX8-LABEL: s_set_rounding_i3_signext:1028; GFX8: ; %bb.0:1029; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1030; GFX8-NEXT: s_sext_i32_i16 s34, s41031; GFX8-NEXT: s_add_i32 s35, s34, -41032; GFX8-NEXT: s_min_u32 s34, s34, s351033; GFX8-NEXT: s_lshl_b32 s36, s34, 21034; GFX8-NEXT: s_mov_b32 s34, 0x1c84a50f1035; GFX8-NEXT: s_mov_b32 s35, 0xb73e62d91036; GFX8-NEXT: s_lshr_b64 s[34:35], s[34:35], s361037; GFX8-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s341038; GFX8-NEXT: s_setpc_b64 s[30:31]1039;1040; GFX9-LABEL: s_set_rounding_i3_signext:1041; GFX9: ; %bb.0:1042; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1043; GFX9-NEXT: s_sext_i32_i16 s34, s41044; GFX9-NEXT: s_add_i32 s35, s34, -41045; GFX9-NEXT: s_min_u32 s34, s34, s351046; GFX9-NEXT: s_lshl_b32 s36, s34, 21047; GFX9-NEXT: s_mov_b32 s34, 0x1c84a50f1048; GFX9-NEXT: s_mov_b32 s35, 0xb73e62d91049; GFX9-NEXT: s_lshr_b64 s[34:35], s[34:35], s361050; GFX9-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s341051; GFX9-NEXT: s_setpc_b64 s[30:31]1052;1053; GFX10-LABEL: s_set_rounding_i3_signext:1054; GFX10: ; %bb.0:1055; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1056; GFX10-NEXT: s_sext_i32_i16 s34, s41057; GFX10-NEXT: s_add_i32 s35, s34, -41058; GFX10-NEXT: s_min_u32 s36, s34, s351059; GFX10-NEXT: s_mov_b32 s34, 0x1c84a50f1060; GFX10-NEXT: s_mov_b32 s35, 0xb73e62d91061; GFX10-NEXT: s_lshl_b32 s36, s36, 21062; GFX10-NEXT: s_lshr_b64 s[34:35], s[34:35], s361063; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s341064; GFX10-NEXT: s_setpc_b64 s[30:31]1065;1066; GFX11-LABEL: s_set_rounding_i3_signext:1067; GFX11: ; %bb.0:1068; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1069; GFX11-NEXT: s_sext_i32_i16 s0, s41070; GFX11-NEXT: s_add_i32 s1, s0, -41071; GFX11-NEXT: s_min_u32 s2, s0, s11072; GFX11-NEXT: s_mov_b32 s0, 0x1c84a50f1073; GFX11-NEXT: s_mov_b32 s1, 0xb73e62d91074; GFX11-NEXT: s_lshl_b32 s2, s2, 21075; GFX11-NEXT: s_lshr_b64 s[0:1], s[0:1], s21076; GFX11-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s01077; GFX11-NEXT: s_setpc_b64 s[30:31]1078 %sext.rounding = sext i3 %rounding to i321079 call void @llvm.set.rounding(i32 %sext.rounding)1080 ret void1081}1082 1083define amdgpu_gfx void @s_set_rounding_i3_zeroext(i3 zeroext inreg %rounding) {1084; GFX6-LABEL: s_set_rounding_i3_zeroext:1085; GFX6: ; %bb.0:1086; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1087; GFX6-NEXT: s_add_i32 s34, s4, -41088; GFX6-NEXT: s_min_u32 s34, s4, s341089; GFX6-NEXT: s_lshl_b32 s36, s34, 21090; GFX6-NEXT: s_mov_b32 s34, 0x1c84a50f1091; GFX6-NEXT: s_mov_b32 s35, 0xb73e62d91092; GFX6-NEXT: s_lshr_b64 s[34:35], s[34:35], s361093; GFX6-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s341094; GFX6-NEXT: s_setpc_b64 s[30:31]1095;1096; GFX7-LABEL: s_set_rounding_i3_zeroext:1097; GFX7: ; %bb.0:1098; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1099; GFX7-NEXT: s_add_i32 s34, s4, -41100; GFX7-NEXT: s_min_u32 s34, s4, s341101; GFX7-NEXT: s_lshl_b32 s36, s34, 21102; GFX7-NEXT: s_mov_b32 s34, 0x1c84a50f1103; GFX7-NEXT: s_mov_b32 s35, 0xb73e62d91104; GFX7-NEXT: s_lshr_b64 s[34:35], s[34:35], s361105; GFX7-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s341106; GFX7-NEXT: s_setpc_b64 s[30:31]1107;1108; GFX8-LABEL: s_set_rounding_i3_zeroext:1109; GFX8: ; %bb.0:1110; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1111; GFX8-NEXT: s_and_b32 s34, 0xffff, s41112; GFX8-NEXT: s_add_i32 s35, s34, -41113; GFX8-NEXT: s_min_u32 s34, s34, s351114; GFX8-NEXT: s_lshl_b32 s36, s34, 21115; GFX8-NEXT: s_mov_b32 s34, 0x1c84a50f1116; GFX8-NEXT: s_mov_b32 s35, 0xb73e62d91117; GFX8-NEXT: s_lshr_b64 s[34:35], s[34:35], s361118; GFX8-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s341119; GFX8-NEXT: s_setpc_b64 s[30:31]1120;1121; GFX9-LABEL: s_set_rounding_i3_zeroext:1122; GFX9: ; %bb.0:1123; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1124; GFX9-NEXT: s_and_b32 s34, 0xffff, s41125; GFX9-NEXT: s_add_i32 s35, s34, -41126; GFX9-NEXT: s_min_u32 s34, s34, s351127; GFX9-NEXT: s_lshl_b32 s36, s34, 21128; GFX9-NEXT: s_mov_b32 s34, 0x1c84a50f1129; GFX9-NEXT: s_mov_b32 s35, 0xb73e62d91130; GFX9-NEXT: s_lshr_b64 s[34:35], s[34:35], s361131; GFX9-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s341132; GFX9-NEXT: s_setpc_b64 s[30:31]1133;1134; GFX10-LABEL: s_set_rounding_i3_zeroext:1135; GFX10: ; %bb.0:1136; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1137; GFX10-NEXT: s_and_b32 s34, 0xffff, s41138; GFX10-NEXT: s_add_i32 s35, s34, -41139; GFX10-NEXT: s_min_u32 s36, s34, s351140; GFX10-NEXT: s_mov_b32 s34, 0x1c84a50f1141; GFX10-NEXT: s_mov_b32 s35, 0xb73e62d91142; GFX10-NEXT: s_lshl_b32 s36, s36, 21143; GFX10-NEXT: s_lshr_b64 s[34:35], s[34:35], s361144; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s341145; GFX10-NEXT: s_setpc_b64 s[30:31]1146;1147; GFX11-LABEL: s_set_rounding_i3_zeroext:1148; GFX11: ; %bb.0:1149; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1150; GFX11-NEXT: s_and_b32 s0, 0xffff, s41151; GFX11-NEXT: s_add_i32 s1, s0, -41152; GFX11-NEXT: s_min_u32 s2, s0, s11153; GFX11-NEXT: s_mov_b32 s0, 0x1c84a50f1154; GFX11-NEXT: s_mov_b32 s1, 0xb73e62d91155; GFX11-NEXT: s_lshl_b32 s2, s2, 21156; GFX11-NEXT: s_lshr_b64 s[0:1], s[0:1], s21157; GFX11-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s01158; GFX11-NEXT: s_setpc_b64 s[30:31]1159 %sext.rounding = zext i3 %rounding to i321160 call void @llvm.set.rounding(i32 %sext.rounding)1161 ret void1162}1163 1164define amdgpu_gfx void @s_set_rounding_select_0_1(i32 inreg %cond) {1165; GFX6-LABEL: s_set_rounding_select_0_1:1166; GFX6: ; %bb.0:1167; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1168; GFX6-NEXT: s_cmp_lg_u32 s4, 01169; GFX6-NEXT: s_cselect_b64 s[34:35], -1, 01170; GFX6-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[34:35]1171; GFX6-NEXT: v_lshlrev_b32_e32 v0, 2, v01172; GFX6-NEXT: v_lshr_b32_e32 v0, 0xa50f, v01173; GFX6-NEXT: v_readfirstlane_b32 s34, v01174; GFX6-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s341175; GFX6-NEXT: s_setpc_b64 s[30:31]1176;1177; GFX7-LABEL: s_set_rounding_select_0_1:1178; GFX7: ; %bb.0:1179; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1180; GFX7-NEXT: s_cmp_lg_u32 s4, 01181; GFX7-NEXT: s_cselect_b64 s[34:35], -1, 01182; GFX7-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[34:35]1183; GFX7-NEXT: v_lshlrev_b32_e32 v0, 2, v01184; GFX7-NEXT: v_lshr_b32_e32 v0, 0xa50f, v01185; GFX7-NEXT: v_readfirstlane_b32 s34, v01186; GFX7-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s341187; GFX7-NEXT: s_setpc_b64 s[30:31]1188;1189; GFX8-LABEL: s_set_rounding_select_0_1:1190; GFX8: ; %bb.0:1191; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1192; GFX8-NEXT: s_cmp_lg_u32 s4, 01193; GFX8-NEXT: s_cselect_b64 s[34:35], -1, 01194; GFX8-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[34:35]1195; GFX8-NEXT: v_lshlrev_b32_e32 v0, 2, v01196; GFX8-NEXT: s_mov_b32 s34, 0xa50f1197; GFX8-NEXT: v_lshrrev_b32_e64 v0, v0, s341198; GFX8-NEXT: v_readfirstlane_b32 s34, v01199; GFX8-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s341200; GFX8-NEXT: s_setpc_b64 s[30:31]1201;1202; GFX9-LABEL: s_set_rounding_select_0_1:1203; GFX9: ; %bb.0:1204; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1205; GFX9-NEXT: s_cmp_lg_u32 s4, 01206; GFX9-NEXT: s_cselect_b64 s[34:35], -1, 01207; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[34:35]1208; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v01209; GFX9-NEXT: s_mov_b32 s34, 0xa50f1210; GFX9-NEXT: v_lshrrev_b32_e64 v0, v0, s341211; GFX9-NEXT: v_readfirstlane_b32 s34, v01212; GFX9-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s341213; GFX9-NEXT: s_setpc_b64 s[30:31]1214;1215; GFX10-LABEL: s_set_rounding_select_0_1:1216; GFX10: ; %bb.0:1217; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1218; GFX10-NEXT: s_cmp_lg_u32 s4, 01219; GFX10-NEXT: s_cselect_b32 s34, -1, 01220; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, s341221; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v01222; GFX10-NEXT: v_lshrrev_b32_e64 v0, v0, 0xa50f1223; GFX10-NEXT: v_readfirstlane_b32 s34, v01224; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s341225; GFX10-NEXT: s_setpc_b64 s[30:31]1226;1227; GFX11-LABEL: s_set_rounding_select_0_1:1228; GFX11: ; %bb.0:1229; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1230; GFX11-NEXT: s_cmp_lg_u32 s4, 01231; GFX11-NEXT: s_cselect_b32 s0, -1, 01232; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s01233; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v01234; GFX11-NEXT: v_lshrrev_b32_e64 v0, v0, 0xa50f1235; GFX11-NEXT: v_readfirstlane_b32 s0, v01236; GFX11-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s01237; GFX11-NEXT: s_setpc_b64 s[30:31]1238 %cmp = icmp eq i32 %cond, 01239 %rounding = select i1 %cmp, i32 0, i32 11240 call void @llvm.set.rounding(i32 %rounding)1241 ret void1242}1243 1244define amdgpu_gfx void @s_set_rounding_select_1_3(i32 inreg %cond) {1245; GFX678-LABEL: s_set_rounding_select_1_3:1246; GFX678: ; %bb.0:1247; GFX678-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1248; GFX678-NEXT: s_cmp_eq_u32 s4, 01249; GFX678-NEXT: s_cselect_b32 s34, 0xa50, 101250; GFX678-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s341251; GFX678-NEXT: s_setpc_b64 s[30:31]1252;1253; GFX9-LABEL: s_set_rounding_select_1_3:1254; GFX9: ; %bb.0:1255; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1256; GFX9-NEXT: s_cmp_eq_u32 s4, 01257; GFX9-NEXT: s_cselect_b32 s34, 0xa50, 101258; GFX9-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s341259; GFX9-NEXT: s_setpc_b64 s[30:31]1260;1261; GFX10-LABEL: s_set_rounding_select_1_3:1262; GFX10: ; %bb.0:1263; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1264; GFX10-NEXT: s_cmp_eq_u32 s4, 01265; GFX10-NEXT: s_cselect_b32 s34, 0xa50, 101266; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s341267; GFX10-NEXT: s_setpc_b64 s[30:31]1268;1269; GFX11-LABEL: s_set_rounding_select_1_3:1270; GFX11: ; %bb.0:1271; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1272; GFX11-NEXT: s_cmp_eq_u32 s4, 01273; GFX11-NEXT: s_cselect_b32 s0, 0xa50, 101274; GFX11-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s01275; GFX11-NEXT: s_setpc_b64 s[30:31]1276 %cmp = icmp eq i32 %cond, 01277 %rounding = select i1 %cmp, i32 1, i32 31278 call void @llvm.set.rounding(i32 %rounding)1279 ret void1280}1281 1282define void @v_set_rounding_select_1_3(i32 %cond) {1283; GFX678-LABEL: v_set_rounding_select_1_3:1284; GFX678: ; %bb.0:1285; GFX678-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1286; GFX678-NEXT: v_mov_b32_e32 v1, 0xa501287; GFX678-NEXT: v_cmp_eq_u32_e32 vcc, 0, v01288; GFX678-NEXT: v_cndmask_b32_e32 v0, 10, v1, vcc1289; GFX678-NEXT: v_readfirstlane_b32 s4, v01290; GFX678-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s41291; GFX678-NEXT: s_setpc_b64 s[30:31]1292;1293; GFX9-LABEL: v_set_rounding_select_1_3:1294; GFX9: ; %bb.0:1295; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1296; GFX9-NEXT: v_mov_b32_e32 v1, 0xa501297; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v01298; GFX9-NEXT: v_cndmask_b32_e32 v0, 10, v1, vcc1299; GFX9-NEXT: v_readfirstlane_b32 s4, v01300; GFX9-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s41301; GFX9-NEXT: s_setpc_b64 s[30:31]1302;1303; GFX10-LABEL: v_set_rounding_select_1_3:1304; GFX10: ; %bb.0:1305; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1306; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v01307; GFX10-NEXT: v_cndmask_b32_e64 v0, 10, 0xa50, vcc_lo1308; GFX10-NEXT: v_readfirstlane_b32 s4, v01309; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s41310; GFX10-NEXT: s_setpc_b64 s[30:31]1311;1312; GFX11-LABEL: v_set_rounding_select_1_3:1313; GFX11: ; %bb.0:1314; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1315; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v01316; GFX11-NEXT: v_cndmask_b32_e64 v0, 10, 0xa50, vcc_lo1317; GFX11-NEXT: v_readfirstlane_b32 s0, v01318; GFX11-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s01319; GFX11-NEXT: s_setpc_b64 s[30:31]1320 %cmp = icmp eq i32 %cond, 01321 %rounding = select i1 %cmp, i32 1, i32 31322 call void @llvm.set.rounding(i32 %rounding)1323 ret void1324}1325 1326define amdgpu_gfx void @s_set_rounding_select_2_0(i32 inreg %cond) {1327; GFX678-LABEL: s_set_rounding_select_2_0:1328; GFX678: ; %bb.0:1329; GFX678-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1330; GFX678-NEXT: s_cmp_eq_u32 s4, 01331; GFX678-NEXT: s_movk_i32 s34, 0xa51332; GFX678-NEXT: s_cselect_b32 s34, s34, 0xa50f1333; GFX678-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s341334; GFX678-NEXT: s_setpc_b64 s[30:31]1335;1336; GFX9-LABEL: s_set_rounding_select_2_0:1337; GFX9: ; %bb.0:1338; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1339; GFX9-NEXT: s_cmp_eq_u32 s4, 01340; GFX9-NEXT: s_movk_i32 s34, 0xa51341; GFX9-NEXT: s_cselect_b32 s34, s34, 0xa50f1342; GFX9-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s341343; GFX9-NEXT: s_setpc_b64 s[30:31]1344;1345; GFX10-LABEL: s_set_rounding_select_2_0:1346; GFX10: ; %bb.0:1347; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1348; GFX10-NEXT: s_cmp_eq_u32 s4, 01349; GFX10-NEXT: s_movk_i32 s34, 0xa51350; GFX10-NEXT: s_cselect_b32 s34, s34, 0xa50f1351; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s341352; GFX10-NEXT: s_setpc_b64 s[30:31]1353;1354; GFX11-LABEL: s_set_rounding_select_2_0:1355; GFX11: ; %bb.0:1356; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1357; GFX11-NEXT: s_cmp_eq_u32 s4, 01358; GFX11-NEXT: s_movk_i32 s0, 0xa51359; GFX11-NEXT: s_cselect_b32 s0, s0, 0xa50f1360; GFX11-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s01361; GFX11-NEXT: s_setpc_b64 s[30:31]1362 %cmp = icmp eq i32 %cond, 01363 %rounding = select i1 %cmp, i32 2, i32 01364 call void @llvm.set.rounding(i32 %rounding)1365 ret void1366}1367 1368define amdgpu_gfx void @s_set_rounding_select_2_1(i32 inreg %cond) {1369; GFX678-LABEL: s_set_rounding_select_2_1:1370; GFX678: ; %bb.0:1371; GFX678-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1372; GFX678-NEXT: s_cmp_eq_u32 s4, 01373; GFX678-NEXT: s_movk_i32 s34, 0xa51374; GFX678-NEXT: s_cselect_b32 s34, s34, 0xa501375; GFX678-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s341376; GFX678-NEXT: s_setpc_b64 s[30:31]1377;1378; GFX9-LABEL: s_set_rounding_select_2_1:1379; GFX9: ; %bb.0:1380; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1381; GFX9-NEXT: s_cmp_eq_u32 s4, 01382; GFX9-NEXT: s_movk_i32 s34, 0xa51383; GFX9-NEXT: s_cselect_b32 s34, s34, 0xa501384; GFX9-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s341385; GFX9-NEXT: s_setpc_b64 s[30:31]1386;1387; GFX10-LABEL: s_set_rounding_select_2_1:1388; GFX10: ; %bb.0:1389; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1390; GFX10-NEXT: s_cmp_eq_u32 s4, 01391; GFX10-NEXT: s_movk_i32 s34, 0xa51392; GFX10-NEXT: s_cselect_b32 s34, s34, 0xa501393; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s341394; GFX10-NEXT: s_setpc_b64 s[30:31]1395;1396; GFX11-LABEL: s_set_rounding_select_2_1:1397; GFX11: ; %bb.0:1398; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1399; GFX11-NEXT: s_cmp_eq_u32 s4, 01400; GFX11-NEXT: s_movk_i32 s0, 0xa51401; GFX11-NEXT: s_cselect_b32 s0, s0, 0xa501402; GFX11-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s01403; GFX11-NEXT: s_setpc_b64 s[30:31]1404 %cmp = icmp eq i32 %cond, 01405 %rounding = select i1 %cmp, i32 2, i32 11406 call void @llvm.set.rounding(i32 %rounding)1407 ret void1408}1409 1410define amdgpu_gfx void @s_set_rounding_select_1_2(i32 inreg %cond) {1411; GFX678-LABEL: s_set_rounding_select_1_2:1412; GFX678: ; %bb.0:1413; GFX678-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1414; GFX678-NEXT: s_cmp_eq_u32 s4, 01415; GFX678-NEXT: s_movk_i32 s34, 0xa501416; GFX678-NEXT: s_cselect_b32 s34, s34, 0xa51417; GFX678-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s341418; GFX678-NEXT: s_setpc_b64 s[30:31]1419;1420; GFX9-LABEL: s_set_rounding_select_1_2:1421; GFX9: ; %bb.0:1422; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1423; GFX9-NEXT: s_cmp_eq_u32 s4, 01424; GFX9-NEXT: s_movk_i32 s34, 0xa501425; GFX9-NEXT: s_cselect_b32 s34, s34, 0xa51426; GFX9-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s341427; GFX9-NEXT: s_setpc_b64 s[30:31]1428;1429; GFX10-LABEL: s_set_rounding_select_1_2:1430; GFX10: ; %bb.0:1431; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1432; GFX10-NEXT: s_cmp_eq_u32 s4, 01433; GFX10-NEXT: s_movk_i32 s34, 0xa501434; GFX10-NEXT: s_cselect_b32 s34, s34, 0xa51435; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s341436; GFX10-NEXT: s_setpc_b64 s[30:31]1437;1438; GFX11-LABEL: s_set_rounding_select_1_2:1439; GFX11: ; %bb.0:1440; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1441; GFX11-NEXT: s_cmp_eq_u32 s4, 01442; GFX11-NEXT: s_movk_i32 s0, 0xa501443; GFX11-NEXT: s_cselect_b32 s0, s0, 0xa51444; GFX11-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s01445; GFX11-NEXT: s_setpc_b64 s[30:31]1446 %cmp = icmp eq i32 %cond, 01447 %rounding = select i1 %cmp, i32 1, i32 21448 call void @llvm.set.rounding(i32 %rounding)1449 ret void1450}1451 1452define amdgpu_gfx void @s_set_rounding_select_3_0(i32 inreg %cond) {1453; GFX678-LABEL: s_set_rounding_select_3_0:1454; GFX678: ; %bb.0:1455; GFX678-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1456; GFX678-NEXT: s_cmp_eq_u32 s4, 01457; GFX678-NEXT: s_cselect_b32 s34, 10, 0xa50f1458; GFX678-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s341459; GFX678-NEXT: s_setpc_b64 s[30:31]1460;1461; GFX9-LABEL: s_set_rounding_select_3_0:1462; GFX9: ; %bb.0:1463; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1464; GFX9-NEXT: s_cmp_eq_u32 s4, 01465; GFX9-NEXT: s_cselect_b32 s34, 10, 0xa50f1466; GFX9-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s341467; GFX9-NEXT: s_setpc_b64 s[30:31]1468;1469; GFX10-LABEL: s_set_rounding_select_3_0:1470; GFX10: ; %bb.0:1471; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1472; GFX10-NEXT: s_cmp_eq_u32 s4, 01473; GFX10-NEXT: s_cselect_b32 s34, 10, 0xa50f1474; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s341475; GFX10-NEXT: s_setpc_b64 s[30:31]1476;1477; GFX11-LABEL: s_set_rounding_select_3_0:1478; GFX11: ; %bb.0:1479; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1480; GFX11-NEXT: s_cmp_eq_u32 s4, 01481; GFX11-NEXT: s_cselect_b32 s0, 10, 0xa50f1482; GFX11-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s01483; GFX11-NEXT: s_setpc_b64 s[30:31]1484 %cmp = icmp eq i32 %cond, 01485 %rounding = select i1 %cmp, i32 3, i32 01486 call void @llvm.set.rounding(i32 %rounding)1487 ret void1488}1489 1490define amdgpu_gfx void @s_set_rounding_select_4_0(i32 inreg %cond) {1491; GFX678-LABEL: s_set_rounding_select_4_0:1492; GFX678: ; %bb.0:1493; GFX678-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1494; GFX678-NEXT: s_cmp_eq_u32 s4, 01495; GFX678-NEXT: s_cselect_b32 s34, 4, 01496; GFX678-NEXT: s_add_i32 s35, s34, -41497; GFX678-NEXT: s_min_u32 s34, s34, s351498; GFX678-NEXT: s_lshl_b32 s36, s34, 21499; GFX678-NEXT: s_mov_b32 s34, 0x1c84a50f1500; GFX678-NEXT: s_mov_b32 s35, 0xb73e62d91501; GFX678-NEXT: s_lshr_b64 s[34:35], s[34:35], s361502; GFX678-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s341503; GFX678-NEXT: s_setpc_b64 s[30:31]1504;1505; GFX9-LABEL: s_set_rounding_select_4_0:1506; GFX9: ; %bb.0:1507; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1508; GFX9-NEXT: s_cmp_eq_u32 s4, 01509; GFX9-NEXT: s_cselect_b32 s34, 4, 01510; GFX9-NEXT: s_add_i32 s35, s34, -41511; GFX9-NEXT: s_min_u32 s34, s34, s351512; GFX9-NEXT: s_lshl_b32 s36, s34, 21513; GFX9-NEXT: s_mov_b32 s34, 0x1c84a50f1514; GFX9-NEXT: s_mov_b32 s35, 0xb73e62d91515; GFX9-NEXT: s_lshr_b64 s[34:35], s[34:35], s361516; GFX9-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s341517; GFX9-NEXT: s_setpc_b64 s[30:31]1518;1519; GFX10-LABEL: s_set_rounding_select_4_0:1520; GFX10: ; %bb.0:1521; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1522; GFX10-NEXT: s_cmp_eq_u32 s4, 01523; GFX10-NEXT: s_cselect_b32 s34, 4, 01524; GFX10-NEXT: s_add_i32 s35, s34, -41525; GFX10-NEXT: s_min_u32 s36, s34, s351526; GFX10-NEXT: s_mov_b32 s34, 0x1c84a50f1527; GFX10-NEXT: s_mov_b32 s35, 0xb73e62d91528; GFX10-NEXT: s_lshl_b32 s36, s36, 21529; GFX10-NEXT: s_lshr_b64 s[34:35], s[34:35], s361530; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s341531; GFX10-NEXT: s_setpc_b64 s[30:31]1532;1533; GFX11-LABEL: s_set_rounding_select_4_0:1534; GFX11: ; %bb.0:1535; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1536; GFX11-NEXT: s_cmp_eq_u32 s4, 01537; GFX11-NEXT: s_cselect_b32 s0, 4, 01538; GFX11-NEXT: s_add_i32 s1, s0, -41539; GFX11-NEXT: s_min_u32 s2, s0, s11540; GFX11-NEXT: s_mov_b32 s0, 0x1c84a50f1541; GFX11-NEXT: s_mov_b32 s1, 0xb73e62d91542; GFX11-NEXT: s_lshl_b32 s2, s2, 21543; GFX11-NEXT: s_lshr_b64 s[0:1], s[0:1], s21544; GFX11-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s01545; GFX11-NEXT: s_setpc_b64 s[30:31]1546 %cmp = icmp eq i32 %cond, 01547 %rounding = select i1 %cmp, i32 4, i32 01548 call void @llvm.set.rounding(i32 %rounding)1549 ret void1550}1551 1552define amdgpu_gfx void @s_set_rounding_select_3_5(i32 inreg %cond) {1553; GFX678-LABEL: s_set_rounding_select_3_5:1554; GFX678: ; %bb.0:1555; GFX678-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1556; GFX678-NEXT: s_cmp_eq_u32 s4, 01557; GFX678-NEXT: s_cselect_b32 s34, 3, 51558; GFX678-NEXT: s_add_i32 s35, s34, -41559; GFX678-NEXT: s_min_u32 s34, s34, s351560; GFX678-NEXT: s_lshl_b32 s36, s34, 21561; GFX678-NEXT: s_mov_b32 s34, 0x1c84a50f1562; GFX678-NEXT: s_mov_b32 s35, 0xb73e62d91563; GFX678-NEXT: s_lshr_b64 s[34:35], s[34:35], s361564; GFX678-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s341565; GFX678-NEXT: s_setpc_b64 s[30:31]1566;1567; GFX9-LABEL: s_set_rounding_select_3_5:1568; GFX9: ; %bb.0:1569; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1570; GFX9-NEXT: s_cmp_eq_u32 s4, 01571; GFX9-NEXT: s_cselect_b32 s34, 3, 51572; GFX9-NEXT: s_add_i32 s35, s34, -41573; GFX9-NEXT: s_min_u32 s34, s34, s351574; GFX9-NEXT: s_lshl_b32 s36, s34, 21575; GFX9-NEXT: s_mov_b32 s34, 0x1c84a50f1576; GFX9-NEXT: s_mov_b32 s35, 0xb73e62d91577; GFX9-NEXT: s_lshr_b64 s[34:35], s[34:35], s361578; GFX9-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s341579; GFX9-NEXT: s_setpc_b64 s[30:31]1580;1581; GFX10-LABEL: s_set_rounding_select_3_5:1582; GFX10: ; %bb.0:1583; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1584; GFX10-NEXT: s_cmp_eq_u32 s4, 01585; GFX10-NEXT: s_cselect_b32 s34, 3, 51586; GFX10-NEXT: s_add_i32 s35, s34, -41587; GFX10-NEXT: s_min_u32 s36, s34, s351588; GFX10-NEXT: s_mov_b32 s34, 0x1c84a50f1589; GFX10-NEXT: s_mov_b32 s35, 0xb73e62d91590; GFX10-NEXT: s_lshl_b32 s36, s36, 21591; GFX10-NEXT: s_lshr_b64 s[34:35], s[34:35], s361592; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s341593; GFX10-NEXT: s_setpc_b64 s[30:31]1594;1595; GFX11-LABEL: s_set_rounding_select_3_5:1596; GFX11: ; %bb.0:1597; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1598; GFX11-NEXT: s_cmp_eq_u32 s4, 01599; GFX11-NEXT: s_cselect_b32 s0, 3, 51600; GFX11-NEXT: s_add_i32 s1, s0, -41601; GFX11-NEXT: s_min_u32 s2, s0, s11602; GFX11-NEXT: s_mov_b32 s0, 0x1c84a50f1603; GFX11-NEXT: s_mov_b32 s1, 0xb73e62d91604; GFX11-NEXT: s_lshl_b32 s2, s2, 21605; GFX11-NEXT: s_lshr_b64 s[0:1], s[0:1], s21606; GFX11-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s01607; GFX11-NEXT: s_setpc_b64 s[30:31]1608 %cmp = icmp eq i32 %cond, 01609 %rounding = select i1 %cmp, i32 3, i32 51610 call void @llvm.set.rounding(i32 %rounding)1611 ret void1612}1613 1614define amdgpu_kernel void @get_rounding_after_set_rounding_1() {1615; GFX6-LABEL: get_rounding_after_set_rounding_1:1616; GFX6: ; %bb.0:1617; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 01618; GFX6-NEXT: s_mov_b32 s3, 0xf0001619; GFX6-NEXT: s_nop 01620; GFX6-NEXT: s_getreg_b32 s0, hwreg(HW_REG_MODE, 0, 4)1621; GFX6-NEXT: s_lshl_b32 s2, s0, 21622; GFX6-NEXT: s_mov_b32 s0, 0xeb24da711623; GFX6-NEXT: s_mov_b32 s1, 0xc96f3851624; GFX6-NEXT: s_lshr_b64 s[0:1], s[0:1], s21625; GFX6-NEXT: s_and_b32 s0, s0, 151626; GFX6-NEXT: s_add_i32 s1, s0, 41627; GFX6-NEXT: s_cmp_lt_u32 s0, 41628; GFX6-NEXT: s_cselect_b32 s4, s0, s11629; GFX6-NEXT: s_mov_b64 s[0:1], 01630; GFX6-NEXT: s_mov_b32 s2, -11631; GFX6-NEXT: v_mov_b32_e32 v0, s41632; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 01633; GFX6-NEXT: s_waitcnt vmcnt(0)1634; GFX6-NEXT: s_endpgm1635;1636; GFX7-LABEL: get_rounding_after_set_rounding_1:1637; GFX7: ; %bb.0:1638; GFX7-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 01639; GFX7-NEXT: s_mov_b32 s3, 0xf0001640; GFX7-NEXT: s_nop 01641; GFX7-NEXT: s_getreg_b32 s0, hwreg(HW_REG_MODE, 0, 4)1642; GFX7-NEXT: s_lshl_b32 s2, s0, 21643; GFX7-NEXT: s_mov_b32 s0, 0xeb24da711644; GFX7-NEXT: s_mov_b32 s1, 0xc96f3851645; GFX7-NEXT: s_lshr_b64 s[0:1], s[0:1], s21646; GFX7-NEXT: s_and_b32 s0, s0, 151647; GFX7-NEXT: s_add_i32 s1, s0, 41648; GFX7-NEXT: s_cmp_lt_u32 s0, 41649; GFX7-NEXT: s_cselect_b32 s4, s0, s11650; GFX7-NEXT: s_mov_b64 s[0:1], 01651; GFX7-NEXT: s_mov_b32 s2, -11652; GFX7-NEXT: v_mov_b32_e32 v0, s41653; GFX7-NEXT: buffer_store_dword v0, off, s[0:3], 01654; GFX7-NEXT: s_waitcnt vmcnt(0)1655; GFX7-NEXT: s_endpgm1656;1657; GFX8-LABEL: get_rounding_after_set_rounding_1:1658; GFX8: ; %bb.0:1659; GFX8-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 01660; GFX8-NEXT: v_mov_b32_e32 v0, 01661; GFX8-NEXT: v_mov_b32_e32 v1, 01662; GFX8-NEXT: s_getreg_b32 s0, hwreg(HW_REG_MODE, 0, 4)1663; GFX8-NEXT: s_lshl_b32 s2, s0, 21664; GFX8-NEXT: s_mov_b32 s0, 0xeb24da711665; GFX8-NEXT: s_mov_b32 s1, 0xc96f3851666; GFX8-NEXT: s_lshr_b64 s[0:1], s[0:1], s21667; GFX8-NEXT: s_and_b32 s0, s0, 151668; GFX8-NEXT: s_add_i32 s1, s0, 41669; GFX8-NEXT: s_cmp_lt_u32 s0, 41670; GFX8-NEXT: s_cselect_b32 s0, s0, s11671; GFX8-NEXT: v_mov_b32_e32 v2, s01672; GFX8-NEXT: flat_store_dword v[0:1], v21673; GFX8-NEXT: s_waitcnt vmcnt(0)1674; GFX8-NEXT: s_endpgm1675;1676; GFX9-LABEL: get_rounding_after_set_rounding_1:1677; GFX9: ; %bb.0:1678; GFX9-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 01679; GFX9-NEXT: v_mov_b32_e32 v0, 01680; GFX9-NEXT: v_mov_b32_e32 v1, 01681; GFX9-NEXT: s_getreg_b32 s0, hwreg(HW_REG_MODE, 0, 4)1682; GFX9-NEXT: s_lshl_b32 s2, s0, 21683; GFX9-NEXT: s_mov_b32 s0, 0xeb24da711684; GFX9-NEXT: s_mov_b32 s1, 0xc96f3851685; GFX9-NEXT: s_lshr_b64 s[0:1], s[0:1], s21686; GFX9-NEXT: s_and_b32 s0, s0, 151687; GFX9-NEXT: s_add_i32 s1, s0, 41688; GFX9-NEXT: s_cmp_lt_u32 s0, 41689; GFX9-NEXT: s_cselect_b32 s0, s0, s11690; GFX9-NEXT: v_mov_b32_e32 v2, s01691; GFX9-NEXT: global_store_dword v[0:1], v2, off1692; GFX9-NEXT: s_waitcnt vmcnt(0)1693; GFX9-NEXT: s_endpgm1694;1695; GFX10-LABEL: get_rounding_after_set_rounding_1:1696; GFX10: ; %bb.0:1697; GFX10-NEXT: s_round_mode 0x01698; GFX10-NEXT: s_mov_b32 s0, 0xeb24da711699; GFX10-NEXT: s_getreg_b32 s2, hwreg(HW_REG_MODE, 0, 4)1700; GFX10-NEXT: s_mov_b32 s1, 0xc96f3851701; GFX10-NEXT: s_lshl_b32 s2, s2, 21702; GFX10-NEXT: v_mov_b32_e32 v0, 01703; GFX10-NEXT: s_lshr_b64 s[0:1], s[0:1], s21704; GFX10-NEXT: v_mov_b32_e32 v1, 01705; GFX10-NEXT: s_and_b32 s0, s0, 151706; GFX10-NEXT: s_add_i32 s1, s0, 41707; GFX10-NEXT: s_cmp_lt_u32 s0, 41708; GFX10-NEXT: s_cselect_b32 s0, s0, s11709; GFX10-NEXT: v_mov_b32_e32 v2, s01710; GFX10-NEXT: global_store_dword v[0:1], v2, off1711; GFX10-NEXT: s_waitcnt_vscnt null, 0x01712; GFX10-NEXT: s_endpgm1713;1714; GFX11-LABEL: get_rounding_after_set_rounding_1:1715; GFX11: ; %bb.0:1716; GFX11-NEXT: s_round_mode 0x01717; GFX11-NEXT: s_mov_b32 s0, 0xeb24da711718; GFX11-NEXT: s_getreg_b32 s2, hwreg(HW_REG_MODE, 0, 4)1719; GFX11-NEXT: s_mov_b32 s1, 0xc96f3851720; GFX11-NEXT: s_lshl_b32 s2, s2, 21721; GFX11-NEXT: v_mov_b32_e32 v0, 01722; GFX11-NEXT: s_lshr_b64 s[0:1], s[0:1], s21723; GFX11-NEXT: s_and_b32 s0, s0, 151724; GFX11-NEXT: s_add_i32 s1, s0, 41725; GFX11-NEXT: s_cmp_lt_u32 s0, 41726; GFX11-NEXT: s_cselect_b32 s0, s0, s11727; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, s01728; GFX11-NEXT: global_store_b32 v[0:1], v2, off dlc1729; GFX11-NEXT: s_waitcnt_vscnt null, 0x01730; GFX11-NEXT: s_endpgm1731 tail call void @llvm.set.rounding(i32 1)1732 %set.mode = tail call i32 @llvm.get.rounding()1733 store volatile i32 %set.mode, ptr addrspace(1) null1734 ret void1735}1736 1737;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:1738; GCN: {{.*}}1739